RT7304 - Richtek

®
RT7304
Primary-Side-Regulation LED Driver Controller
with Active PFC
General Description
Features
The RT7304 is a constant current LED driver with active
power factor correction. It supports high power factor
across a wide range of line voltages, and it drives the
converter in the Quasi-Resonant (QR) mode to achieve
higher efficiency. By using Primary Side Regulation (PSR),
the RT7304 controls the output current accurately without
a shunt regulator and an opto-coupler at the secondary
side, reducing the external component count, the cost,
and the volume of the driver board.








The RT7304 embeds comprehensive protection functions
for robust designs, including LED open-circuit protection,
LED short-circuit protection, output diode short-circuit
protection, VDD Under-Voltage lockout (UVLO), VDD OverVoltage Protection (VDD OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.

Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Quasi-Resonant
Maximum/Minimum Switching Frequency
Clamping
Maximum/Minimum On-Time Limitation
Wide VDD Voltage Range (up to 25V)
Multiple Protection Features
 LED Open-Circuit Protection
 LED Short-Circuit Protection
 Output Diode Short-Circuit Protection
 VDD Under-Voltage Lockout
 VDD Over-Voltage Protection
 Over-Temperature Protection
 Cycle-by-Cycle Current Limit
RoHS Compliant and Halogen Free
Marking Information
0H= : Product Code
0H=DNN
Applications
DNN : Date Code

AC/DC LED Lighting driver
Simplified Application Circuit
Flyback Converter
Line
Buck-Boost Converter
TX1
BD
CSIN
DOUT
VOUT+
Line
COUT
RST
RT7304
RG
GD
Neutral
VDD
CS
CSIN
VOUTQ1
RPC
TX1
BD
RST
RT7304
RG
GD
Neutral
VDD
CS
CCOMP
COMP
GND
ZCD
DAUX
CVDD
CCOMP
RZCD2
RZCD1
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
COUT
VOUT+
Q1
RPC
RCS
RCS
CVDD
VOUTDOUT
COMP
GND
ZCD
DAUX
RZCD2
RZCD1
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RT7304
Ordering Information
Pin Configurations
RT7304
(TOP VIEW)
Package Type
E : SOT-23-6
COMP ZCD CS
6
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
4
2
3
GND VDD GD
Richtek products are :

5
SOT-23-6
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
GND
Ground of the Controller.
2
VDD
Supply Voltage (VDD) Input. The controller will be enabled when V DD exceeds VTH_ON
and disabled when VDD is lower than VTH_OFF.
3
GD
Gate Driver Output for External Power MOSFET.
4
CS
Current Sense Input. Connect this pin to the current sense resistor.
5
ZCD
Zero Current Detection Input. This pin is used to sense the voltage at auxiliary winding of
the transformer.
6
COMP
Compensation Node. Output of the internal trans-conductance amplifier.
Function Block Diagram
Valley
Detector
ZCD
Clamping
Circuit
Ramp
Generator
Under
Voltage
Lockout
(16V/9V)
Starter
Circuit
+
Constant Current Control
Constant On-Time
Comparator
ICS
Output Over
Voltage
Protection
CS
PWM
Control
Logic
VDD OVP
VDD
VDD Over
Voltage
Protection
VCLAMP 13V
PWM
+
VCS_CL
1V
Current Limit
Comparator
GD
Gate
Driver
RGD
GND
Output Diode
Short Circuit
Protection
Leading
Edge
Blanking
Over
Temperature
Protection
OTP
Output OVP
COMP
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is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
Operation
Critical-Conduction Mode (CRM) with Constant
On-Time Control.
Figure 1 shows a typical flyback converter with input
voltage (VIN). When main switch Q1 is turned on with a
fixed on-time (tON), the peak current (IL_PK) of the magnetic
inductor (Lm) can be calculated by the following equation :
V
IL_PK = IN  tON
Lm
TX1
DOUT
+
IL
VIN
+
COUT
Lm
VOUT
IOUT
ROUT
Q1
Primary-Side Constant-Current Regulation
The RT7304 needs no shunt regulator and opto-coupler
at the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
conventional flyback converter in Quasi-Resonant (QR)
mode, in which VAUX is the voltage on the auxiliary winding
of the transformer.
VDS
VIN
0
GD
(VGS)
VAUX
0
Figure 1. Typical Flyback Converter
If the input voltage is the output voltage of the full-bridge
rectifier with sinusoidal input voltage (VIN_PK x sin(θ)), the
inductor peak current (IL_PK) can be expressed as the
following equation :
VIN_PK  sin(θ)  tON
Lm
When the converter operates in CRM with constant ontime control, the envelope of the peak inductor current
will follow the input voltage waveform with in-phase. Thus,
high power factor can be achieved, as shown in Figure 2.
IL_PK =
VIN
Input Voltage
Iin_avg
Average Input Current
IL_PK
Peak Inductor Current
IDOUT
Output Diode Current
IQ1_DS MOSFET Current
(VOUT + Vf) x NA / NS
VIN x NA / NP
Clamped by
controller
IQ1
IDOUT
Figure 3. Key Waveforms of a Flyback Converter
Voltage Clamping Circuit
The RT7304 provides a voltage clamping circuit at ZCD
pin since the voltage on the auxiliary winding is negative
when the main switch is turned on. The lowest voltage on
ZCD pin is clamped near zero to prevent the IC from being
damaged by the negative voltage. Meanwhile, the sourcing
ZCD current (IZCD_SH), flowing through the upper resistor
(RZCD1), is sampled and held to be a line-voltage-related
signal for propagation delay compensation. The RT7304
embeds the programmable propagation delay
compensation through CS pin. A sourcing current ICS
(equal to IZCD_SH x KPC) applies a voltage offset (ICS x
RPC) which is proportional to line voltage on CS to
compensate the propagation delay effect. Thus, the output
current can be equal at high and low line voltage.
VQ1_GS MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
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3
RT7304
Valley
Signal
～
～
For improving converter's efficiency, the RT7304 detects
valleys of the Drain-to-Source voltage (VDS) of main switch
and turns on it near the selected valley. For the valley
detections, a pulse of the “valley signal” is generated
after a 500ns(typ.) delay time which starts at which the
voltage (VZCD) on ZCD pin goes down and reaches the
voltage threshold (VZCDT, 0.4V typ.). During the rising of
the VZCD, the VZCD must reach the voltage threshold
(VZCDA, 0.5V typ.). Otherwise, no pulse of the “valley
signal” is generated. Moreover, if the timing when the
falling VZCD reaches VZCDT is not later than a mask time
(tMASK, 2μs typ.) then the valley signal will be masked and
regards as no valley, as shown in Figure 4.
PWM
～
～
Quasi-Resonant Operation
tSTART
Valley
Signal
PWM
tS(MIN)
Valley
Signal
……
PWM
～
～
PWM
tS(MIN)
VZCD
～
～
VZCDA
VZCDT
Valley
Signal
Valley
Signal
……
PWM
5µs
tS(MIN)
500ns
tMASK
Figure 4. Valley Signal Generating Method
Figure 5 illustrates how valley signal triggers PWM. If no
valley signal is detected for a long time, the next PWM is
triggered by a starter circuit at the end of the interval (tSTART,
130μs typ.) which starts at the rising edge of the previous
PWM signal. A blanking time (tS(MIN), 8.5μs typ.), which
starts at the rising edge of the previous PWM signal, limits
minimum switching period. When the tS(MIN) interval is
on-going, all of valley signals are not allowed to trigger
the next PWM signal. After the end of the tS(MIN) interval,
the coming valley will trigger the next PWM signal. If one
or more valley signals are detected during the tS(MIN)
interval and no valley is detected after the end of the tS(MIN)
interval, the next PWM signal will be triggered
automatically at the end of the tS(MIN) + 5μs (typ.).
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Figure 5. PWM Triggered Method
Protections
LED Open-Circuit Protection
In an event of output open circuit, the converter will be
shut down to prevent being damaged, and it will be autorestarted when the output is recovered. Once the LED is
open, the output voltage and VZCD will rise. When the
sample-and-hold ZCD voltage (VZCD_SH) exceeds its OV
threshold (V ZCD_OVP, 3.1V typ.), output OVP will be
activated and the PWM output (GD pin) will be forced low
to turn off the main switch. If the output is still open-circuit
when the converter restarts, the converter will be shut
down again.
is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
LED Short-Circuit Protection
LED short-circuit protection can be achieved by VDD UVLO
and cycle-by-cycle current limitation. Once LED shortcircuit failure occurs, VDD drops related to the output
voltage. When the VDD is lower than falling UVLO threshold
(VTH_OFF, 9V typ.), the converter will be shut down and it
will be auto-restarted when the output is recovered.
Output Diode Short-Circuit Protection
When the output diode is damaged as short-circuit, the
transformer will be led to magnetic saturation and the main
switch will suffer from a high current stress. To avoid the
above situation, an output diode short-circuit protection
is built-in. When CS voltage VCS exceeds the threshold
(VCS_SD 1.5 typ.) of the output diode short-circuit protection,
the RT7304 will shut down the PWM output (GD pin) in
few cycles to prevent the converter from damage. It will
be auto-restarted when the failure condition is recovered.
VDD Under-Voltage Lockout (UVLO) and
Over-Voltage Protection(VDD OVP)
The RT7304 will be enabled when VDD voltage (VDD)
exceeds rising UVLO threshold (VTH_ON, 16V typ.) and
disabled when VDD is lower than falling UVLO threshold
(VTH_OFF, 9V typ.).
When VDD exceeds its over-voltage threshold (VOVP, 27V
typ.), the PWM output of the RT7304 is shut down. It will
be auto-restarted when the VDD is recovered to a normal
level.
Over-Temperature Protection (OTP)
The RT7304 provides an internal OTP function to protect
the controller itself from suffering thermal stress and
permanent damage. It's not suggested to use the function
as precise control of over temperature. Once the junction
temperature is higher than the OTP threshold (TSD, 150°C
typ.), the controller will shut down until the temperature
cools down by 30°C (typ.). Meanwhile, if VDD reaches falling
UVLO threshold voltage (VTH_OFF), the controller will
hiccup till the over-temperature condition is removed.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
is a registered trademark of Richtek Technology Corporation.
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5
RT7304
Absolute Maximum Ratings









(Note 1)
VDD to GND ----------------------------------------------------------------------------------------------------------------GD to GND ------------------------------------------------------------------------------------------------------------------CS, ZCD, COMP to GND ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOT-23-6 --------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOT-23-6, θJA ---------------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions



−0.3V to 30V
−0.3V to 20V
−0.3V to 6V
0.42W
235.6°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V
COMP Voltage, VCOMP ---------------------------------------------------------------------------------------------------- 0.7V to 4.3V
Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specification)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
25.5
27
28.5
V
--
10
--
s
Rising UVLO Threshold Voltage VTH_ON
15
16
17
V
Falling UVLO Threshold Voltage VTH_OFF
8
9
10
V
IZCD = 0, GD Open
--
--
3.5
mA
VDD = VTH_ON  1V
--
--
30
A
IZCD = 0 to 2.5mA
--
0
0.3
V
2.8
3.1
3.4
V
246.25
250
253.75
mV
4.5
--
--
V
--
62.5
--
A
VDD Supply Current and Protections Section
VDD OVP Threshold Voltage
VOVP
VDD OVP De-bounce Time
Operating Supply Current
(Note 5)
IDD_OP
Start-up Current
ZCD Section
Lower Clamp Voltage
ZCD OVP Threshold Voltage
VZCD_OVP
At the Knee Point
(Note 5)
Constant Current Control Section
Regulated factor for
Constant-Current Control
Maximum COMP Voltage
Maximum COMP Sourcing
Current
KCC
ICOMP < 30A
ICOMP(MAX) VCOMP < 3.5V
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is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
228
270
312
mV/s
2.2
2.7
3.2
s
Timing Control Section
Voltage Ramp Slope of the
Ramp Generator Output
Sramp
Minimum On-Time
tON(MIN)
Maximum On-Time
tON(MAX)
29
47
65
s
Minimum Switching Period
tS(MIN)
7
8.5
10
s
Duration of Starter
tSTART
At No Valley Detected
75
130
300
s
Blanking Time
tLEB
LEB + Propagation Delay
240
400
570
ns
Output Diode Short-Circuit
Protection Voltage Threshold
at CS
VCS_SD
Shutdown when VCS > VCS_SD in 7
cycles.
--
1.5
--
V
CS Voltage Threshold for
Peak Current Limitation
VCS_CL
0.93
1.03
1.13
V
Propagation Delay
Compensation factor
KPC
Sourcing I CS = I ZCD x KPC ,
IZCD = 150A
--
0.02
--
A/A
GD Voltage Rising Time
tR
CL = 1nF
--
60
80
ns
GD Voltage Falling Time
tF
CL = 1nF
--
40
70
ns
GD Output Clamping Voltage
VCLAMP
CL = 1nF
--
13
--
V
--
40
--
k
IZCD = 150A
Current Sense Section
(Note 5)
Gate Driver Section
Internal GD Pull Low Resistor RGD
Over-Temperature Protection Section
Over-Temperature Threshold
TSD
(Note 5)
--
150
--
C
Over-Temperature Threshold
Hysteresis
TSD_HYS
(Note 5)
--
30
--
C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity two-layer test board per JEDEC 51-3.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
is a registered trademark of Richtek Technology Corporation.
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RT7304
Typical Application Circuit
Flyback Application Circuit
RSN3 CSN2
Line
F1
TX1
BD
DOUT
+
RSN1
RST
CSN1
RSN2 DSN
RT7304
Neutral
COUT
…
CSIN
6
COMP
CCOMP
2
GD
-
RG
3
VOUT
Q1
RGP
VDD
CS
RPC
4
CCS
RCS
CVDD
GND
1
ZCD
5
RZCD2
CZCD
RZCD1
DAUX
RAUX
Buck-Boost Application Circuit
F1
BD
CSIN
TX1
RST
6
Neutral
CCOMP
2
RT7304
COMP
GD
3
RG
DOUT
COUT
…
Line
VOUT
+
Q1
RGP
VDD
CS
4
RPC
CCS
RCS
CVDD
GND
1
ZCD
5
RZCD2
CZCD
RAUX
RZCD1
DAUX
Table 1. Suggested Component Values
CVDD (F)
CCOMP (F)
CZCD (pF)
CCS (pF)
RST (M)
RGP (k)
RG ()
RAUX ()
22
1
22
4.7
(Optional)
1
10
47
10
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is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
Typical Operating Characteristics
VTH_ON vs. Temperature
VOVP vs. Temperature
28.0
18.0
27.8
17.5
27.6
17.0
VTH_ON (V)
VOVP (V)
27.4
27.2
27.0
26.8
26.6
16.5
16.0
15.5
15.0
26.4
14.5
26.2
14.0
26.0
-50
-25
0
25
50
75
100
-50
125
-25
0
Temperature (°C)
50
75
100
125
100
125
IDD_OP vs. Temperature
11.0
3.00
10.5
2.75
10.0
2.50
I DD_OP (mA)
VTH_OFF (V)
VTH_OFF vs. Temperature
9.5
9.0
8.5
2.25
2.00
1.75
8.0
1.50
7.5
1.25
7.0
1.00
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
Temperature (°C)
KCC vs. Temperature
ICOMP(max) vs. Temperature
0.270
100
0.265
90
I COMP(max) (μA)
0.260
KCC (V)
25
Temperature (°C)
0.255
0.250
0.245
80
70
60
0.240
50
0.235
40
0.230
30
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT7304
Sramp vs. Temperature
tON(min) vs. Temperature
3.0
0.32
2.8
0.28
tON(min) (μs)
Sramp (V/μs)
0.30
0.26
0.24
2.6
2.4
2.2
0.22
2.0
0.20
-50
-25
0
25
50
75
100
-50
125
-25
0
Temperature (°C)
50
75
100
125
100
125
100
125
Temperature (°C)
tSTART vs. Temperature
VCS_SD vs. Temperature
150
1.8
140
1.7
130
1.6
VCS_SD (V)
tSTART (μs)
25
120
110
100
1.5
1.4
1.3
90
-50
-25
0
25
50
75
100
1.2
125
-50
-25
0
Temperature (°C)
25
50
75
Temperature (°C)
VCS_CL vs. Temperature
KPC vs. Temperature
0.022
1.20
1.15
0.021
0.020
1.05
KPC (A/A)
VCS_CL (V)
1.10
1.00
0.95
0.019
0.018
0.90
0.017
0.85
0.016
0.80
-50
-25
0
25
50
75
100
Temperature (°C)
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10
125
-50
-25
0
25
50
75
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
Application Information
Output Current Setting
Minimum On-Time Setting
Considering the conversion efficiency, the programmed
DC level of the average output current (IOUT (t)) can be
The RT7304 limits a minimum on-time (tON(MIN)) for each
switching cycle. The tON(MIN) is a function of the sampleand-hold ZCD current (IZCD_SH) as following :
derived as :
K
N
IOUT_CC = 1  P  CC  CTRTX1
2 NS RCS
ISEC_PK NS

CTRTX1 =
IPRI_PK NP
tON(MIN)  IZCD_SH  375p  sec  A (typ.)
IZCD_SH can be expressed as :
IZCD_SH =
VIN  NA
R ZCD1  NP
in which CTRTX1 is the current transfer ratio of the
transformer TX1, ISEC_PK is the peak current of secondary
side, and IPRI_PK is the peak current of the primary side.
CTRTX1 can be estimated to be 0.9.
Thus, RZCD1 can be determined by :
According to the above parameters, current sense resistor
RCS can be determined as the following equation :
K CC
N
RCS = 1  P 
 CTRTX1
2 NS IOUT_CC
In addition, the current flowing out of ZCD pin must be
lower than 2.5mA (typ.). Thus, the R ZCD1 is also
determined by :
Propagation Delay Compensation Design
The VCS deviation (ΔVCS) caused by propagation delay
effect can be derived as :
VCS =
VIN  tD  RCS
Lm
in which t D is the delay period which includes the
propagation delay of the RT7304 and the turn-off transition
of the main MOSFET. The sourcing current from CS pin
of the RT7304 (ICS) can be expressed as :
ICS = KPC  VIN 
NA
 1
NP R ZCD1
where NA is the turns number of auxiliary winding.
RPC can be designed by :
RPC =
VCS
t  RCS  R ZCD1 NP
= D

ICS
Lm  KPC
NA
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
R ZCD1=
t ON(MIN)  VIN NA

(typ.)
375p
NP
RZCD1 >
2  VAC(MAX) NA

2.5m
NP
where the VAC(MAX) is maximum input AC voltage.
Output Over-Voltage Protection Setting
Output OVP is achieved by sensing the knee voltage on
the auxiliary winging. It is recommended that output OV
level (VOUT_OVP) is set at 120% of nominal output voltage
(VOUT). Thus, RZCD1 and RZCD2 can be determined by the
equation as :
VOUT 
R ZCD2
NA

 120% = 3.1V (typ.)
NS R ZCD1  R ZCD2
Table 2. Suggested Component Values Range
Component
Range of Typical Value
CVDD
10F to 33F
CCOMP
1F to 4.7F
CZCD
10pF to 22pF
CCS
NC to 22pF
RST
0.68M to 2M
RGP
10k to 22k
RG
10 to 47
RAUX
10 to 100
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RT7304
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when designing a PCB layout for
switching power supply.

The current path(1) from input capacitor, transformer,
MOSFET, R CS return to input capacitor is a high
frequency current loop. The path(2) from GD pin,
MOSFET, RCS return to input capacitor is also a high
frequency current loop. They must be as short as
possible to decrease noise coupling and kept a space
to other low voltage traces, such as IC control circuit
paths, especially. Besides, the path(3) between
MOSFET ground(b) and IC ground(d) is recommended
to be as short as possible, too.

The path(4) from RCD snubber circuit to MOSFET is a
high switching loop. Keep it as small as possible.

It is good for reducing noise, output ripple and EMI issue
to separate ground traces of input capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit(d).
Finally, connect them together on input capacitor
ground(a). The areas of these ground traces should be
kept large.

Placing bypass capacitor for abating noise on IC is highly
recommended. The capacitors CCOMP,CZCD and CCS
should be placed as close to controller as possible.

To minimize parasitic trace inductance and EMI,
minimize the area of the loop connecting the secondary
winding, the output diode, and the output filter capacitor.
In addition, apply sufficient copper area at the anode
and cathode terminal of the diode for heat-sinking. It is
recommended to apply a larger area at the quiet cathode
terminal. A large anode area will induce high-frequency
radiated EMI.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOT-23-6 package, the thermal resistance, θ JA, is
235.6°C/W on a standard JEDEC 51-3 two-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (235.6°C/W) = 0.42W for
SOT-23-6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
0.6
Two-Layer PCB
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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12
is a registered trademark of Richtek Technology Corporation.
DS7304-04 February 2015
RT7304
…
Line
(4)
Neutral
(a)
CCOMP
RT7304
COMP
GD
VDD
CS
CCS (2)
(3)
(1)
Input capacitor
Ground (a)
(b)
GND
ZCD
(d)
(c)
Trace
Trace
Trace
IC
Auxiliary
MOSFET
Ground (d) Ground (c) Ground (b)
CZCD
Figure 7. PCB Layout Guide
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7304-04 February 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT7304
Outline Dimension
H
D
L
C
B
b
A
A1
e
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
14
DS7304-04 February 2015