RT8105 5V/12V Synchronous Buck PWM DC/DC Controller General Description Features The RT8105 is a high efficiency synchronous buck PWM controllers that generate logic-supply voltages in PC based systems. These high performance , single output devices include internal soft-start, frequency compensation networks and integrates all of the control, output adjustment, monitoring and protection functions into a single package. z Operating with 5V or 12V Supply Voltage z Drives All Low Cost N-MOSFETs Voltage Mode PWM Control 300kHz Fixed Frequency Oscillator Fast Transient Response : ` High-Speed GM Amplifier ` Full 0 to 100% Duty Ratio Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on MOSFET, No Current Sense Resistor Required Full-Time Over Voltage Protection RoHS Compliant and Halogen Free The device operating at fixed 300kHz frequency provides an optimum compromise between efficiency, external component size, and cost. Adjustable over-current protection (OCP) monitors the voltage drop across the RDS(ON) of the lower MOSFET for synchronous buck PWM DC/DC controller. The overcurrent function cycles the soft-start in 4-times hiccup mode to provide fault protection, and in an always hiccup mode for under-voltage protection. z z z z z z z z Applications z z z Ordering Information RT8105 z z Package Type S : SOP-8 Graphic Card Motherboard, Desktop Servers IA Equipments Telecomm Equipments High Power DC/DC Regulators Pin Configurations (TOP VIEW) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) BOOT Note : 8 PHASE UGATE 2 7 OPS GND 3 6 FB LGATE 4 5 VCC Richtek products are : ` ments of IPC/JEDEC J-STD-020. ` SOP-8 RoHS compliant and compatible with the current requireSuitable for use in SnPb or Pb-free soldering processes. Marking Information RT8105GS RT8105GS : Product Number RT8105 GSYMDNN YMDNN : Date Code RT8105ZS RT8105ZS : Product Number RT8105 ZSYMDNN DS8105-03 April 2011 YMDNN : Date Code www.richtek.com 1 RT8105 Typical Application Circuit +5V to +12V D1 BAT54 VIN +3.3V/+5V/+12V RBOOT 0 C2 0.1µF R1 10 1 5 C1 1µF 6 3 BOOT VCC UGATE PHASE RT8105 OPS FB GND LGATE Disable > R2 32 2 RUGATE 0 8 7 C3 1µF Q1 MU L1 3µH ROCSET Q2 ML 4 Q3 3904 C4 470µF R C C6 to C8 1000µFx3 R3 68 R4 200 to 1k VOUT VOUT = VREF × (1 + R3 ) R2 VREF : Internal reference voltage (0.8V ± 2%) C5 0.1 to 0.33µF Functional Pin Description BOOT (Pin 1) VCC (Pin 5) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. Connect this pin to a well-decoupled 5V or 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. FB (Pin 6) UGATE (Pin 2) Upper gate driver output. Connect to the gate of high side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. GND (Pin 3) Both signal and power ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to the low side MOSFET source and ground plane with the lowest impedance. LGATE (Pin 4) Lower gate drive output. Connect to the gate of low side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. www.richtek.com 2 Switcher feedback voltage. This pin is the inverting input of the error amplifier. FB senses the switcher output through an external resistor divider network. OPS (OCSET, POR and Shut-Down) (Pin 7) This pin provides multi-function of the over-current setting, UGATE turn-on POR sensing, and shut-down features. Connecting a resistor (ROCSET) between OPS and PHASE pins sets the over-current trip point. Pulling the pin to ground resets the device and all external MOSFETs are turned off allowing the output voltage power rails to float. This pin is also used to detect VIN in power on stage and issues an internal POR signal. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. DS8105-03 April 2011 RT8105 Function Block Diagram VCC + EN PH_M - Reference 0.1V + Bias & Regulators (3V_Logic & 3VDD_Analog) Power On Reset 0.8VREF 1.5V 3V + 0.6V UV_S IOC Soft-Start & Fault Logic - OC + OVP 1V 1.3V 40uA OPS 0.4V + - VOC BOOT UGATE PHASE EO + + - - FB GM Gate Control Logic VCC LGATE Oscillator (300kHz) GND DS8105-03 April 2011 www.richtek.com 3 RT8105 Absolute Maximum Ratings z z z z z z z z z z z z (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 16V BOOT to PHASE ------------------------------------------------------------------------------------------ 15V UGATE to PHASE DC ------------------------------------------------------------------------------------------------------------- −0.3V to (VBOOT-PHASE + 0.3V) <20ns -------------------------------------------------------------------------------------------------------- −5V to (VBOOT-PHASE + 5V) PHASE to GND DC ------------------------------------------------------------------------------------------------------------- −0.5V to 15V <20ns -------------------------------------------------------------------------------------------------------- −5V to 25V LGATE to GND DC ------------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) <20ns -------------------------------------------------------------------------------------------------------- −5V to (VCC + 5V) Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND-0.3V to 7V Power Dissipation, PD @ TA = 25°C (Note 2) SOP-8 -------------------------------------------------------------------------------------------------------- 0.625W Package Thermal Resistance SOP-8, θJA -------------------------------------------------------------------------------------------------- 160°C/W Junction Temperature ------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------------- 5V ± 5%,12V ± 10% Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------- −20°C to 85°C Electrical Characteristics (VCC = 5V/12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions IC Supply Voltage VCC Nominal Supply Current ICC UGATE and LGATE Open POR Threshold VCCRTH VCC Rising Hysteresis VCCHYS Min Typ Max Unit 4.75 -- 13.2 V -- 6 15 mA 3.8 4.1 4.35 V 0.35 0.5 -- V Power-On Reset Switcher Reference Reference Voltage VREF VCC = 12V 0.784 0.8 0.816 V f OSC VCC = 12V 250 300 350 kHz ΔVOSC VCC = 12V -- 1.5 -- VP-P Oscillator Free Running Frequency Ramp Amplitude To be continued www.richtek.com 4 DS8105-03 April 2011 RT8105 Parameter Symbol Test Conditions Min Typ Max Unit Error Amplifier (GM) E/A Transconductance gm -- 0.2 -- ms Open Loop DC Gain AO -- 90 -- dB 0.6 1 -- A -- 4 8 Ω PWM Controller Gate Drivers (VCC = 12V) Upper Gate Source IUGATE VBOOT − VPHASE = 12V, VUGATE − VPHASE = 6V VBOOT − VPHASE = 12V, VUGATE − VPHASE = 1V Upper Gate Sink RUGATE Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V 0.6 1 -- A Lower Gate Sink RLGATE VCC = 12V, VLGATE = 1V -- 3 5 Ω FB Under-Voltage Trip Δ FBUVT FB Falling 70 75 80 % OC Current Source IOC VPHASE = 0V 35 40 45 μA Pre-OVP Threshold (Before POR) VOVP1 VCC = 3V, Sweep VFB -- 1.1 1.3 V OVP Threshold (After POR) VOVP2 VCC = 5V, Sweep VFB 1 1.3 1.5 V Soft-Start Interval TSS -- 3.5 -- ms Protection Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8105-03 April 2011 www.richtek.com 5 RT8105 Typical Operating Characteristics Power On from VIN V CC (10V/Div) VIN (5V/Div) VIN (5V/Div) VOUT (1V/Div) UGATE (20V/Div) LGATE (20V/Div) VIN and VCC Power Sequence UGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 20A VOUT (1V/Div) VIN comes after VCC VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 20A Time (2ms/Div) Time (2ms/Div) Enable from OPS Disable from OPS OPS (2V/Div) OPS (2V/Div) VOUT (1V/Div) VOUT (1V/Div) UGATE (20V/Div) LGATE (20V/Div) UGATE (20V/Div) LGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 5A VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 5A Time (2ms/Div) Time (40μs/Div) Under Voltage Protection Over Voltage Protection VIN = 5V, VCC = 12V, VOUT = 1.5V, No Load FB (500mV/Div) FB (500mV/Div) UGATE (10V/Div) UGATE (10V/Div) LGATE (10V/Div) LGATE (10V/Div) Time (20μs/Div) www.richtek.com 6 VIN = 5V, VCC = 12V, VOUT = 1.5V, No Load Time (20μs/Div) DS8105-03 April 2011 RT8105 Over Current Protection Short Circuit Over Current Protection Low side MOSFET RDS(ON) = 9MΩ VIN = VCC = 12V, Low side MOSFET RDS(ON) = 6MΩ ROCSET = 15kΩ Inductor Current (20A/Div) VOUT (2V/Div) Inductor Current (20A/Div) VOUT (1V/Div) UGATE (20V/Div) UGATE (50V/Div) LGATE (20V/Div) LGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ROCSET = 15.4kΩ short circuit output terminal than power up Time (20μs/Div) Time (2ms/Div) Switching Frequency vs. Temperature 400 0.812 380 Switching Frequency (kHz)1 Reference Voltage (V) Reference Voltage vs. Temperature 0.816 0.808 0.804 0.800 0.796 0.792 0.788 VIN = VCC = 5V, No Load 0.784 -40 -25 -10 5 20 35 50 65 Temperature (°C) DS8105-03 April 2011 80 95 110 125 360 340 320 300 280 260 240 220 VIN = VCC = 5V, No Load 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 7 RT8105 Application Information RT8105 is a voltage-mode single phase synchronous buck controller with embedded MOSFET drivers. This part provides complete protection functions such as over voltage protection, under voltage protection and over current protection. Inductor current information is sensed by the RDS(ON) of the low side MOSFET. The over current protection threshold can be simply programmed by a resistor. In addition, the compensation circuit is implemented internally to minimize the external component count. soft start operation. RT8105 provides soft start function internally. The soft start function is used to prevent the large inrush current while converter is powered up. The FB signal will track the internal soft start signal, which is controlled by an internal digital counter and ramps up from zero in a monotone during soft start period. Therefore the duty cycle of UGATE signal will increase gradually and so does the input current. The typical soft-start duration is 3ms. Over Current Protection (OCP) VCC Power on Reset and VIN Detection Once VCC exceeds its power on reset rising threshold VCCRTH, UGATE will output continuous pulses (~10kHz, 1% duty cycle) for converter input voltage VIN detection. Figure 1 and figure 2 illustrate the operation of VIN detection for RT8105. VIN is recognized ready by detecting the voltage pulses at VOS pin exceed 1.5V for four times (both rising edge + falling edge for counter increment = 1). Once VIN is recognized ready, controller will initiates the soft start operation. Since a 40μA current will continuously flow through ROCSET, ROCSET must be lower than 37.5kΩ for the correct VIN detection function. Controller will not initiate soft start if ROCSET is higher than this value because VIN will not be recognized ready. 3V - 10pF + VOC VIN Detection Counter + - the following Equation : IOCSET ≈ ROCSET OPS PHASE 40uA × ROCSET − 0.4 RDS(ON) of the low side MOSFET Because the R DS(ON) of MOSFET increases with temperature, it is necessary to take this thermal effect into consideration in calculating OCP point. 3V V IN IOC OC Comparator IOC OC Figure 2 shows the over current protection (OCP) scheme of RT8105. A resistor ROCSET connected from PHASE pin to OPS pin sets the threshold. An internal current source, IOC (40μA typically), flowing through ROCSET determines the OCP trip point IOCSET, which can be calculated using - OPS + R OCSET + 0.4V Q1 + IOC x R OCSET - PHASE L ID x R DS(ON) Q2 Cparasitic DISABLE Q2 + Figure 2. Over Current Protection Scheme + - UGATE 1.5V Internal Counter will count (VOPS > 1.5V) four times (rising & falling) to recognize VIN is ready. Figure 1. VIN Detection Function Soft Start Once VIN is recognized ready, LGATE will go high for a short period of time to discharge the pre-biased voltage at the output capacitor. After that, controller will initiate the www.richtek.com 8 In addition, note that the OCP threshold is very sensitive to the parasitic capacitance at OPS pin. Parasitic capacitance or the drain-to-source capacitance of the small MOSFET (for shutdown function) will have influence on the OCP threshold. It is recommended to use small signal BJT for shutdown function. In addition, it is also recommended to place ROCSET close to IC to minimize the trace parasitic. When OCP is tripped, both UGATE and LGATE will go low to stop the energy transfer to the load. Controller will DS8105-03 April 2011 RT8105 try to restart in a hiccupped way. Figure 3 shows the hiccupped over current protection. Only four times of hiccup is allowed in over current protection. If over current condition still exist after four times of hiccup, controller will be latched. COUNT = 2 COUNT = 3 Output Inductor Selection 2V The selection of output inductor depends on the efficiency, output current and operating frequency. Low inductance value can have fast transient response, but the associated large current ripple will cause large output ripple voltage and decrease the efficiency. 0V OVERLOAD Inductor Current The controller can be disabled by pulling OPS pin to ground. The enable/disable function can be implemented by connecting a MOSFET or BJT to OPS pin. It is recommended to use small signal MOSFET/BJT to implement the enable/disable function. COUNT = 4 4V SS Internal COUNT = 1 Enable/Disable APPLIED 0A T0 T1 T2 T3 T4 TIME Figure 3. Hiccupped Over Current Protection Over Voltage Protection (OVP) The feedback voltage is continuously monitored for over voltage protection. When OVP is tripped, LGATE will go high and UGATE will go low to discharge the output capacitor. RT8105 provides full-time over voltage protection whenever soft start completes or not. Over voltage protection has two operating conditions: before soft start completes and after soft start completes. Each condition is described as follows. Before soft start completes, the typical OVP threshold is 137.5% of the internal reference voltage VREF. RT8105 provides non-latched OVP before soft start completes. The controller will return to normal operation if over voltage condition is removed. After soft start completes, however, the OVP threshold is typically 162.5% of VREF. RT8105 provides latched OVP after soft start completes. The controller can only be reset if VCC POR is exceeded again. Under Voltage Protection (UVP) The feedback voltage is also monitored for under voltage protection. The under voltage protection has 15us triggered delay. When UVP is tripped, both UGATE and LGATE will go low. Unlike OCP, UVP is not a latched protection; controller will always try to restart in a hiccupped way. DS8105-03 April 2011 In general, a 20% to 40% of inductor ripple current percentage (ΔIL / IOUT) is preferred in practical application. The minimum inductance can be determined as follows : VOUT L = (VIN − VOUT ) × VIN × fS × ΔIL Where : VIN = Input voltage VOUT = Output voltage ΔIL = Inductor current ripple fS = Switching frequency Output Capacitor Selection The selection of output capacitor depends on the inductor ripple current, the output ripple voltage and the amount of voltage under shoot during transient. The output ripple voltage is a function of both the capacitance and the equivalent series resistance (ESR) rC. The output ripple voltage can be expressed as follows : ΔVOUT = ΔVOR + ΔVOC 1 t2 ΔVOUT = ΔIL × rc + ∫ ic dt CO t1 1 VOUT 2 ΔVOUT = ΔIL × ΔIL × rc + (1− D)T S 8 COL where ΔVOR is caused by ESR, and ΔVOC is related to the capacitance value. For electrolytic capacitor application, major of the output voltage ripple is typically contributed by the ESR. Therefore, the output voltage ripple can be simplified as follows : ΔVOUT = ΔIL x rC www.richtek.com 9 RT8105 Therefore the ESR can be determined for a given output voltage ripple requirement. Input Capacitor Selection The selection of input capacitor depends on the maximum ripple current capability. Referred to Figure 1, the buck converter draws pulsed current from the input capacitor during S1 is turned on. RMS value of the ripple current flowing through the input capacitor can be expressed as follows : Irms = IOUT D(1 − D) (A) The input capacitor must be able to handle this RMS current. It is recommended to add ceramic capacitor and placed physically close to the drain of the high side MOSFET. This can effectively reduce the input ripple voltage. Control Loop Stability Figure 5 illustrates the system Bode plot. The close loop gain is the sum of the modulation gain and the compensation gain. The goal is to obtain the required crossover frequency with sufficient phase margin. The crossover frequency is preferred to be 1/10 to 1/5 of the switching frequency. The preferred phase margin is greater than 45°. Because RT8105 utilizes internal compensation, the location of FZ, FP and the gain at mid-frequency provided by the compensator are fixed. Therefore the inductance, output capacitance and especially the ESR of the output capacitor should be carefully selected to avoid stability issue. The ESR can not be too small, or the system will have stability problem. If the location of the zero contributed by ESR is far away from that of the LC double pole, the system will not have sufficient phase margin. It is recommended to choose output capacitor with proper ESR value to meet the stability requirement. Gain (dB) RT8105 utilizes operational transconductance amplifier (OTA) as the error amplifier and implements the compensation network internally. Figure 4 shows the internal Type II compensator, which provides two poles and one zero to the control loop. GM •R1• (voltage divider ration) Compensator V OUT GM C1 FZ C2 FP F CROSS R1 Freq. (log scale) Close Loop F LC F ESR Modulator Figure 4. Internal Type II Compensator One of the poles is located at low frequency to increase the low frequency gain to improve the DC regulation accuracy. The location of the other pole and the single zero can be calculated as follows : 1 1 FZ = ; FP = 2π × R1× C2 ⎛ C1× C2 ⎞ 2π × R1× ⎜ ⎟ ⎝ C1+ C2 ⎠ The transconductance and the internal compensation values are : GM = 0.2mA/V, R1 ≈ 75kΩ, C1 ≈ 2.5nF, C2 ≈ 10pF. The gain of the internal compensator at middle frequency can be calculated as follows : Gmid-freq. = GM x R1 www.richtek.com 10 Figure 5. System Bode Plot PCB Layout Considerations PCB layout is critical to high-current high-frequency switching converter design. A good layout can help the controller to function properly and obtain better performance. On the other hand, the circuit may have more power loss, pool performance and even malfunction if without a carefully layout. In order to obtain better performance, the general guidelines of PCB layout are listed as follows. ` Power stage components should be placed first. Place the input bulk capacitors close to the high side power MOSFETs, and then locate the output inductor then finally the output capacitors. DS8105-03 April 2011 RT8105 ` Placing the ceramic capacitors physically close to the drain of the high side MOSFET. This can reduce the input voltage drop when high side MOSFET is turned on. ` Keep the high-current loops as short as possible. The current transition between MOSFETs usually causes di/dt voltage spike due to the parasitic components on PCB trace and component lead. Therefore, making the trace length between power MOSFETs and inductors wide and short can reduce the voltage spike and also reduce EMI. ` Make MOSFET gate driver path as short as possible. Since the gate driver uses high-current pulses to switch on/off power MOSFET, the driver path must be short to reduce the trace inductance. This is especially important for low side MOSFET because this can reduce the possibility of shoot-through. Besides, also make the width of gate driving path as wide as possible to reduce the trace resistance. ` Provide enough copper area around power MOSFETs to help heat dissipation. Using thick copper also reduces the trace resistance and inductance to have better performance. ` The output capacitors should be placed physically close to the load. This can minimize the trace parasitic components and improve transient response. ` The feedback voltage divider resistor must be placed close to FB pin because it is noise-sensitive. ` ROCSET should be placed close to IC. ` The small signal MOSFET/BJT used to shutdown the controller should be placed close to IC to minimize the trace parasitic components. ` Voltage feedback path must away from switching nodes. The switching nodes, such as the interconnection between high side MOSFET, low side MOSFET and inductor, is extremely noisy. Feedback path must away from this kind of noisy node to avoid noise pick-up. ` A multi-layer PCB design is recommended. Use one single layer as the ground and have separate layers for power rail or signal. DS8105-03 April 2011 www.richtek.com 11 RT8105 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 12 DS8105-03 April 2011