RT7305 - Richtek

RT7305
Primary-Side Regulation LED Driver Controller
Active-PFC and Integrated Power MOSFET
General Description
with
Features
The RT7305 consists of a high voltage power MOSFET
and a high-performance constant current LED driver
with active power factor correction. It supports high
power factor across a wide range of line voltages, and
it drives the converter in the Quasi-Resonant (QR)
mode to achieve higher efficiency. By using Primary
Side Regulation (PSR), RT7305 controls the output
current accurately without a shunt regulator and an

opto-coupler at the secondary side, reducing the
external component count, the cost, and the volume of
the driver board.








Integrated 620V Power MOSFET
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Quasi-Resonant
Maximum/Minimum Switching Frequency
Clamping
Maximum/Minimum on-Time Limitation
Wide VDD Range (up to 25V)
Multiple Protection Features
 LED Open-Circuit Protection

RT7305 embeds comprehensive protection functions for
robust designs, including LED open circuit protection,
LED short circuit protection, output diode short-circuit
protection, VDD Under-Voltage Lockout (UVLO), VDD
Over-Voltage Protection (OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.

LED Short-Circuit Protection
Output Diode Short-Circuit Protection
VDD Under-Voltage Lockout
 VDD Over-Voltage Protection
 Over-Temperature Protection
 Cycle-by-Cycle Current Limitation
RoHS Compliant and Halogen Free


Applications

AC/DC LED Lighting Driver
Simplified Application Circuit
Flyback Application Circuit
Buck-Boost Application Circuit
TX1
BD1
CIN
VOUT+
VDD
Neutral
CVDD
COMP
CS
CCOMP
DOUT
VDD
Neutral
CVDD
DRAIN
RT7305
SOURCE
COMP
CS
CCOMP
COUT
VOUT+
RPC
RCS
ZCD
GND
DAUX
GND
DAUX
RZCD1
RZCD1
RZCD2
RZCD2
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
July 2014
RST
RPC
RCS
ZCD
DS7305-00
CIN
VOUT-
DRAIN
RT7305
SOURCE
VOUT-
Line
COUT
RST
TX1
BD1
DOUT
Line
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RT7305
Ordering Information
Marking Information
RT7305
RT7305GS : Product Number
YMDNN : Date Code
RT7305
GSYMDNN
Package Type
S : SOP-7
Lead Plating System
G : Green (Halogen Free and Pb Free)
Pin Configurations
(TOP VIEW)
Note :
Richtek products are :

VDD
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.

7
DRAIN
GND
2
ZCD
3
6
SOURCE
COMP
4
5
CS
Suitable for use in SnPb or Pb-free soldering processes.
SOP-7
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VDD
Supply Voltage (VDD) input. The controller will be enabled when VDD
exceeds VTH_ON and disabled when VDD is lower than VTH_OFF.
2
GND
Ground of the Controller.
3
ZCD
Zero Current Detection Input. This pin is used to sense the voltage at
auxiliary winding of the transformer.
4
COMP
Compensation Node. Output of the internal trans-conductance amplifier.
5
CS
Current Sense Input. Connect this pin to the current sense resistor.
6
SOURCE
Source terminal of the integrated power MOSFET.
7
DRAIN
Drain terminal of the integrated power MOSFET.
Function Block Diagram
Valley Signal
Valley
Detector
ZCD
Clamping
Circuit
Starter
Circuit
Ramp
Generator
UVLO
VDD OVP
+
Output
Over-Voltage
Protection
CS
Constant-Current
Comparator
Constant
Current
Control
ICS
VCS_CL
1V
PWM
Control
Logic
+
OverTemperature
Protection
VDD
VDD
Over-Voltage
Protection
DRAIN
VCLAMP 13V
PWM
Current-Limit
Comparator
Gate
Driver
Output Diode
Short-Circuit
Protection
Leading
Edge
Blanking
Under-Voltage
Lockout
(16V/9V)
Integrated
MOSFET
SOURCE
RGD
OTP
GND
Output OVP
COMP
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is a registered trademark of Richtek Technology Corporation
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July 2014
RT7305
Operation
Critical-Conduction Mode (CRM) with Constant
If the input voltage is the output voltage of the
On-Time Control
full-bridge rectifier with sinusoidal input voltage
(VIN_PKsin()), the inductor peak current (IL_PK) can be
expressed as the following equation :
Figure 1 shows a typical flyback converter with input
voltage (VIN). When main switch Q1 is turned on with
a fixed on-time (tON), the peak current (IL_PK) of the
magnetic inductor (Lm) can be calculated by the
following equation:
IL_PK 
VIN_PK  sin(θ)  tON
Lm
When the converter operates in CRM with constant
on-time control, the envelope of the peak inductor
V
IL_PK  IN  tON
Lm
current will follow the input voltage waveform with
in-phase. Thus, high power factor can be achieved, as
TX1
NP:NS DOUT
shown in Figure 2.
IL
IOUT
+
COUT
Lm
VIN
VOUT
-
ROUT
Q1
Figure 1. Typical Flyback Converter
Primary-Side Constant-Current Regulation
RT7305 needs no shunt regulator and opto-coupler at
the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
conventional flyback converter in Quasi-Resonant (QR)
mode, in which VAUX is the voltage on the auxiliary
winding of the transformer.
VDS
VIN
0
GD
(VGS)
VAUX
(VOUT + Vf) x NA / NS
0
VIN x NA / NP
Clamped by Controller
IQ1
VIN
Input Voltage
IL_PK
Peak Inductor Current
IQ1_DS
MOSFET Current
Iin_avg
Average Input Current
IDOUT
Output Diode Current
VQ1_GS
MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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July 2014
IDOUT
Figure 3. Key Waveforms of a Flyback Converter
Voltage Clamping Circuit
RT7305 provides a voltage clamping circuit at ZCD pin
since the voltage on the auxiliary winding is negative
when the main switch is turned on. The lowest voltage
on ZCD pin is clamped near zero to prevent the IC from
being damaged by the negative voltage. Meanwhile,
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RT7305
the sourcing ZCD current (IZCD_SH), flowing through
the upper resistor (RZCD1), is sampled and held to be a
line-voltage-related signal for propagation delay
will trigger the next PWM signal. If one or more valley
signals are detected during the tS(MIN) interval and no
valley is detected after the end of the tS(MIN) interval,
compensation. RT7305 embeds the programmable
propagation delay compensation through CS pin. A
sourcing current ICS (equal to IZCD_SH x KPC) applies a
voltage offset (ICS x RPC) which is proportional to line
voltage on CS to compensate the propagation delay
effect. Thus, the total power limit or output current can
be equal at high and low line voltage.
the next PWM signal will be triggered automatically at
end of the tS(MIN) + 5µs(typ.).
～
～
Valley
Signal
～
～
PWM
tSTART
Quasi-Resonant Operation
For improving converter’s efficiency, RT7305 detects
valleys of the Drain-to-Source voltage (VDS) of main
switch and turns it on near the selected valley. For the
valley detections, a pulse of the “valley signal” is
generated after a 500ns(typ.) delay time which starts at
which the voltage (VZCD) on ZCD pin goes down and
reaches the voltage threshold (VZCDT, 0.4V typ.).
During the rising of the VZCD, the VZCD must reach the
voltage threshold (VZCDA, 0.5V typ.). Otherwise, no
pulse of the “valley signal” is generated. Moreover, if
the timing when the falling VZCD reaches VZCDT is not
later than a mask time (tMASK, 2µs typ.) then the valley
signal will be masked and regards as no valley, as
shown in Figure 4.
PWM
Valley
Signal
PWM
tS(MIN)
Valley
Signal
PWM
tS(MIN)
Valley
Signal
PWM
tS(MIN)
5μs
～
～
Figure 5. PWM Triggered Method
VZCD
VZCDA
VZCDT
～
～
Protections
Valley
Signal
500ns
tMASK
Figure 4. Valley Signal Generating Method
Figure 5 illustrates how valley signal triggers PWM. If
no valley signal detected for a long time, the next PWM
is triggered by a starter circuit at end of the interval
(tSTART, 130µs typ.) which starts at the rising edge of
the previous PWM signal. A blanking time (tS(MIN),
8.5µs typ.), which starts at the rising edge of the
previous PWM signal, limits minimum switching period.
When the tS(MIN) interval is on-going, all of valley
signals are not allowed to trigger the next PWM signal.
After the end of the tS(MIN) interval, the coming valley
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LED Open-Circuit Protection
In an event of output open circuit, the converter will be
shut down to prevent being damaged, and it will be
auto-restarted when the output is recovered. Once the
LED is open-circuit, the output voltage and VZCD will
rise. When the sample-and-hold ZCD voltage (VZCD_SH)
exceeds its OV threshold (VZCD_OVP, 3.1V typ.), output
OVP will be activated and the PWM output (GD pin) will
be forced low to turn off the main switch. If the output is
still open-circuit when the converter restarts, the
converter will be shut down again.
LED Short-Circuit Protection
LED short-circuit protection can be achieved by VDD
UVLO and cycle-by-cycle current limitation. Once LED
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RT7305
short-circuit failure occurs, VDD drops related to the
output voltage. When the VDD is lower than falling
UVLO threshold (VTH_OFF, 9V typ.), the converter will
be shut down and it will be auto-restarted when the
output is recovered.
Output Diode Short-Circuit Protection
When the output diode is damaged as short-circuit, the
transformer will be led to magnetic saturation and the
main switch will suffer from a high current stress. To
avoid the above situation, an output diode short-circuit
protection is built-in. When CS voltage VCS exceeds
the threshold (VCS_SD 1.5 typ.) of the output diode
short-circuit protection, RT7305 will shut down the
Over-Temperature Protection (OTP)
The RT7305 provides an internal OTP function to
protect the controller itself from suffering thermal stress
and permanent damage. It is not suggested to use the
function as precise control of over temperature. Once
the junction temperature is higher than the OTP
threshold (TSD, 150C typ.), the controller will shut
down until the temperature cools down by 30C (typ.).
Meanwhile, if VDD reaches falling UVLO threshold
voltage (VTH_OFF), the controller will hiccup till the over
temperature condition is removed.
PWM output (GD pin) in few cycles to prevent the
converter from damage. It will be auto-restarted when
the failure condition is recovered.
VDD Under-Voltage Lockout (UVLO) and
Over-Voltage Protection (VDD OVP)
RT7305 will be enabled when VDD voltage (VDD)
exceeds rising UVLO threshold (VTH_ON, 16V typ.) and
disabled when VDD is lower than falling UVLO
threshold (VTH_OFF, 9V typ.). When VDD exceeds its
over-voltage threshold (VOVP, 27V typ.), the PWM
output of RT7305 is shut down. It will be auto-restarted
when the VDD is recovered to a normal level.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7305-00
July 2014
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RT7305
Absolute Maximum Ratings
(Note 1)

DRAIN to GND Voltage, VDRAIN ---------------------------------------------------------------------------------- 0.3V to 620V

VDD Supply Voltage, VDD------------------------------------------------------------------------------------------ 0.3V to 30V

SOURCE, CS, ZCD, COMP to GND Voltage ----------------------------------------------------------------- 0.3V to 6V

Power Dissipation, PD @ TA = 25C
SOP-7 -------------------------------------------------------------------------------------------------------------------- 1.246W

Package Thermal Resistance
(Note 2)
SOP-7, JA -------------------------------------------------------------------------------------------------------------- 80.25C/W

Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------------------ 150C

Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility
(Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)

Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 12V to 25V

COMP Voltage, VCOMP --------------------------------------------------------------------------------------------- 0.7V to 4.3V

Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
Electrical Characteristics
(VDD = 15V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
25.5
27
28.5
V
--
10
--
µs
VDD Supply Current and Protections Section
VDD OVP Threshold Voltage
VOVP
VDD OVP De-bounce Time
(Note 5)
Rising UVLO Threshold
Voltage
VTH_ON
15
16
17
V
Falling UVLO Threshold
Voltage
VTH_OFF
8
9
10
V
Operating Supply Current
IDD_OP
IZCD=0
--
--
3.5
mA
VDD = VTH_ON1V
--
--
30
µA
IZCD = 0 to 2.5mA
--
0
0.3
V
2.8
3.1
3.4
V
0.245
0.25
0.255
V
4.5
--
--
V
--
62.5
--
µA
Start-up Current
ZCD Section
Lower Clamp Voltage
ZCD OVP Threshold Voltage
VZCD_OVP
At the knee point
(Note 5)
Constant Current Control Section
Regulated factor for
Constant-Current Control
Maximum COMP Voltage
Maximum COMP Sourcing
Current
KCC
ICOMP < 30A
ICOMP(MAX) VCOMP < 3.5V
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RT7305
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
228
270
312
mV/µs
1.8
2.5
3.1
µs
Timing Control Section
Voltage Ramp Slope of the
Ramp Generator Output
Sramp
Minimum On-Time
tON(MIN)
Maximum On-Time
tON(MAX)
29
47
65
µs
Minimum Switching Period
tS(MIN)
7
8.5
10
µs
Duration of Starter
tSTART
At no valley detected
75
130
300
µs
Blanking Time
tLEB
LEB + Propagation Delay
--
470
--
ns
Output Diode Short-Circuit
Protection Voltage Threshold
at CS
VCS_SD
Shutdown when VCS > VCS_SD in 7
cycles.
--
1.5
--
V
CS Voltage Threshold for
Peak Current Limitation
VCS_CL
0.93
1.03
1.13
V
Propagation Delay
Compensation factor
KPC
Sourcing ICS = IZCD x KPC,
IZCD = 150A
--
0.02
--
A/A
IZCD = 150µA
Current Sense Section
(Note 5)
Over-Temperature Protection Section
Over-Temperature Threshold
TSD
(Note 5)
--
150
--
C
Over-Temperature Threshold
Hysteresis
TSD_HYS
(Note 5)
--
30
--
C
Drain-to-Source Leakage
Current
IDSS
VDS = 620V, VDD = 0V
--
--
1
µA
Static Drain-Source
On-Resistance
RDS(ON)
ID = 100mA
--
--
6.5

Power MOSFET Section
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal
measurement standard. Test condition : Device mounted on 2” x 2” FR-4 substrate PCB, 2oz copper, with minimum
recommended pad on top layer and thermal vias to bottom layer ground plane.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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July 2014
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RT7305
Typical Application Circuit
Flyback Application Circuit
C
RSN3 SN2
Line
DOUT
TX1
BD1
F1
+
COUT
VR1
CIN
RST
CSN1
Neutral
RSN2
1
VDD
CVDD
4
DSN
7
DRAIN
RT7305
6
SOURCE
COMP
CS
RPC
5
CCOMP
3
ROUT ～
～ VOUT
RSN1
CCS
ZCD
GND
RCS
2
CZCD
RAUX
DAUX
RZCD1
RZCD2
Buck-Boost Application Circuit
F1
Line
TX1
BD1
-
VR1
CIN
DOUT
RST
COUT
～ VOUT
ROUT ～
+
Neutral
1
VDD
CVDD
4
7
DRAIN
RT7305
6
SOURCE
COMP
CS
RPC
5
CCOMP
3
CCS
ZCD
GND
RCS
2
CZCD
RAUX
DAUX
RZCD1
RZCD2
Table 1. Suggested Component Values
CVDD (µF)
CCOMP (µF)
CZCD (pF)
CCS (pF)
RST (M)
RAUX ()
10
2.2
22
(optional)
10
(optional)
1
10
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RT7305
Typical Operating Characteristics
VTH_ON vs. Junction Temperature
VOVP vs. Junction Temperature
28.0
18.0
27.8
17.5
27.6
17.0
VTH_ON (V)
27.4
VOVP (V)
27.2
27.0
26.8
16.5
16.0
15.5
26.6
15.0
26.4
14.5
26.2
26.0
14.0
-50
-25
0
25
50
75
100
125
-50
-25
Junction Temperature (°C)
25
50
75
100
125
IDD_OP vs. Junction Temperature
11.0
3.00
10.5
2.75
10.0
2.50
I DD_OP (mA)
VTH_OFF (V)
VTH_OFF vs. Junction Temperature
9.5
9.0
8.5
2.25
2.00
1.75
8.0
1.50
7.5
1.25
7.0
1.00
-50
-25
0
25
50
75
100
125
-50
-25
Junction Temperature (°C)
0
25
50
75
100
125
Junction Temperature (°C)
ICOMP(max) vs. Junction Temperature
KCC vs. Junction Temperature
0.270
100
0.265
90
I COMP(max) (μA)
0.260
KCC (V)
0
Junction Temperature (°C)
0.255
0.250
0.245
0.240
80
70
60
50
40
0.235
0.230
30
-50
-25
0
25
50
75
100
Junction Temperature (°C)
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July 2014
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7305
tON(min) vs. Junction Temperature
Sramp vs. Junction Temperature
3.0
0.32
IZCD = -150µA
2.8
0.28
tON(min) (μs)
Sramp (V/μs)
0.30
0.26
0.24
2.6
2.4
2.2
0.22
2.0
0.20
-50
-25
0
25
50
75
100
-50
125
-25
25
50
75
100
125
VCS_SD vs. Junction Temperature
tSTART vs. Junction Temperature
150
1.8
140
1.7
130
1.6
VCS_SD (V)
tSTART (μs)
0
Junction Temperature (°C)
Junction Temperature (°C)
120
110
1.5
1.4
100
1.3
90
1.2
-50
-25
0
25
50
75
100
125
-50
-25
Junction Temperature (°C)
0
25
50
75
100
125
Junction Temperature (°C)
VCS_CL vs. Junction Temperature
KPC vs. Junction Temperature
0.022
1.20
1.15
0.021
1.10
KPC (A/A)
VCS_CL (V)
0.020
1.05
1.00
0.95
0.019
0.018
0.90
0.017
0.85
0.016
0.80
-50
-25
0
25
50
75
100
Junction Temperature (°C)
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10
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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July 2014
RT7305
Application Information
Output Current Setting
Minimum On-Time Setting
Considering the conversion efficiency, the programmed
DC level of the average output current (IOUT(t)) can be
derived as :
RT7305 limits a minimum on-time (tON(MIN)) for each
switching cycle. The tON(MIN) is a function of the
sample-and-hold ZCD current (IZCD_SH) as following :
IOUT_CC  1  K  NP  KCC  CTRTX1
2
NS RCS
CTRTX1 
ISEC_PK NS

,
IPRI_PK NP
tON(MIN)  IZCD_SH  375p  sec  A (typ.)
IZCD_SH can be expressed as :
IZCD_SH 
VIN  NA
RZCD1  NP
In which CTRTX1 is the current transfer ratio of the
transformer TX1, ISEC_PK is the peak current of
secondary side, and IPRI_PK is the peak current of the
primary side. CTRTX1 can be estimated to be 0.9.
According to the above parameters, current sense
resistor RCS can be determined as the following
equation :
Thus, RZCD1 can be determined by :
RCS  1  K  NP  KCC  CTRTX1
2
NS IOUT_CC
RZCD1 
RZCD1 
tON(MIN)  VIN NA

(typ.)
375p
NP
In addition, the current flowing out of ZCD pin must be
lower than 2.5mA (typ.). Thus, the RZCD1 is also
determined by :
2  VAC(MAX) NA

2.5m
NP
where the VAC(MAX) is maximum input AC voltage.
Propagation Delay Compensation Design
The VCS deviation (VCS) caused by propagation delay
effect can be derived as :
V  t R
VCS  IN D CS ,
Lm
In which tD is the delay period which includes the
propagation delay of RT7305 and the turn-off transition
of the main MOSFET. The sourcing current from CS
pin of RT7305 (ICS) can be expressed as :
N
ICS  KPC  VIN  A  1
NP RZCD1
where NA is the turns number of auxiliary winding.
RPC can be designed by :
VCS tD  RCS  RZCD1 NP
RPC 


ICS
Lm  KPC
NA
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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July 2014
Output Over-Voltage Protection Setting
Output OVP is achieved by sensing the knee voltage
on the auxiliary winging. It is recommended that output
OV level (VO_OVP) is set at 120% of nominal output
voltage (VOUT). Thus, RZCD1 and RZCD2 can be
determined by the equation as :
RZCD2
N
VOUT  A 
120%  3.1V(typ.)
NS RZCD1  RZCD2
Table 2. Suggested Component Values Range
Component
Range of Typical Value
CVDD
10µF to 33µF
CCOMP
1µF to 4.7µF
CZCD
NC to 22pF
CCS
NC to 10pF
RST
0.6M to 2M
RAUX
10 to 100
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RT7305
Thermal Considerations
Layout Consideration
For continuous operation, do not exceed absolute
A proper PCB layout can abate unknown noise
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
interference and EMI issue in the switching power
supply. Please refer to the guidelines when designing a
PCB layout for switching power supply :

PD(MAX) = (TJ(MAX)  TA) / JA
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction to
ambient thermal resistance.
as short as possible to decrease noise coupling and
kept a space to other low voltage traces, such as IC
control circuit paths, especially.

The path(2) for the RCD snubber circuit is a high
frequency switching loop. Keep it as small as
possible.

It is good for reducing noise, output ripple and EMI
issue to separate ground traces of input capacitor(a),
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For SOP-7 package, the thermal resistance,
The current path(1) from input capacitor, transformer,
RT7305, current sense resistor return to input
capacitor is a high frequency current loop. It must be
JA, is 80.25C/W on a standard JEDEC 51-3
single-layer thermal test board. The maximum power
current sense resistor(b), auxiliary winding(c) and IC
control circuit(d). Finally, connect them together on
dissipation at TA = 25C can be calculated by the
following formula :
input capacitor ground(a). The areas of these
ground traces should be kept large.
PD(MAX) = (125C  25C) / (80.25C/W) = 1.246W for
SOP-7 package

Placing bypass capacitor for abating noise on IC is
highly recommended. The capacitors CCOMP, CZCD,
and CCS should be placed as close to controller as
possible.

To minimize parasitic trace inductance and EMI,
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 6
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
2.0
Signal-Layer PCB
minimize the area of the loop connecting the
secondary winding, the output diode, and the output
filter capacitor. In addition, apply sufficient copper
area at the anode and cathode terminal of the diode
for heat-sinking. It is recommended to apply a larger
area at the quiet cathode terminal. A large anode
1.5
area will induce high-frequency radiated EMI.
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power
Dissipation
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is a registered trademark of Richtek Technology Corporation
DS7305-00
July 2014
RT7305
Line
～
～
CIN
Neutral
(2)
(a)
VDD
CVDD
DRAIN
RT7305
SOURCE
COMP
CS
CCOMP
CCS
ZCD
(1)
GND
CZCD
(d)
Input Capacitor
Ground (a)
(b)
Trace
Trace
IC
Ground (d)
Trace
Auxiliary Current Sense
Ground (c)
Ground (b)
(c)
Figure 7. PCB Layout Guide
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7305-00
July 2014
is a registered trademark of Richtek Technology Corporation
www.richtek.com
13
RT7305
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.310
0.510
0.012
0.020
F
1.194
1.346
0.047
0.053
F1
2.464
2.616
0.097
0.103
H
0.100
0.254
0.004
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
7-Lead SOP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation
DS7305-00
July 2014