® RT8812A Dual-Phase PWM Controller with PWM-VID Reference General Description Features The RT8812A is a 2/1 phase synchronous Buck PWM controller which is optimized for high performance graphic microprocessor and computer applications. The IC integrates a Constant-On-Time (COT) PWM controller, two MOSFET drivers with internal bootstrap diodes, as well as channel current balance and protection functions including Over Voltage Protection (OVP), Under Voltage Protection (UVP), current limit, and thermal shutdown into the WQFN-20L 3x3 package. Dual-Phase PWM Controller Two Embedded MOSFET Drivers and Embedded Switching Boot Diode External Reference Input Control PWM-VID Dynamic Voltage Control Dynamic Phase Number Control Lossless RDS(ON) Current Sensing for Current Balance Internal Fixed and External Adjustable Soft-Start Adjustable Current Limit Threshold Adjustable Switching Frequency UVP/OVP Protection Shoot Through Protection and Short Pulse Free Technology Support an Ultra-Low Output Voltage as Standby Voltage Thermal Shutdown Power Good Indicator RoHS Compliant and Halogen Free The RT8812A adopts RDS(ON) current sensing technique. Current limit is accomplished through continuous inductorcurrent-sense, while RDS(ON) current sensing is used for accurate channel current balance. Using the method of current sampling utilizes the best advantages of each technique. The RT8812A features external reference input and PWMVID dynamic output voltage control, in which the feedback voltage is regulated and tracks external input reference voltage. Other features include adjustable switching frequency, dynamic phase number control, internal/external soft-start, power good indicator, and enable functions. Applications CPU/GPU Core Power Supply Notebook PC Memory Power Supply Chipset/RAM Power Supply Generic DC/DC Power Regulator Simplified Application Circuit RT8812A VPVCC VIN PVCC TON BOOT1 UGATE1 VIN PHASE1 LGATE1 VOUT PGOOD PSI VID BOOT2 UGATE2 VIN PHASE2 LGATE2 EN GND Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 RGND VSNS VGND_SNS VOUT_SNS is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8812A Ordering Information Pin Configurations RT8812A (TOP VIEW) PHASE1 LGATE1 PVCC LGATE2 PHASE2 Package Type QW : WQFN-20L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current require- 20 19 18 17 16 BOOT1 UGATE1 EN PSI VID ments of IPC/JEDEC J-STD-020. 15 2 14 GND 3 4 21 5 13 12 11 6 7 8 BOOT2 UGATE2 PGOOD VSNS SS 9 10 REFADJ REFIN VREF TON RGND 1 Suitable for use in SnPb or Pb-free soldering processes. Marking Information WQFN-20L 3x3 0Z= : Product Code YMDNN : Date Code 0Z=YM DNN Function Pin Description Pin No. Pin Name Pin Function 1 BOOT1 Bootstrap Supply for PWM 1. This pin powers the high side MOSFET driver. 2 UGATE1 High Side Gate Driver of PWM 1. This pin provides the gate drive for the converter's high side MOSFET. Connect this pin to the Gate of high side MOSFET. 3 EN 4 PSI 5 VID 6 REFADJ Reference Adjustment Output. Refer to PWM-VID Dynamic Voltage Control. 7 REFIN External Reference Input. 8 VREF 9 TON Enable Control Input. Active high input. Power Saving Interface. When the voltage is pulled below 0.8V, the device will operate into 1 phase DEM. When the voltage is between 1.2V to 1.8V, the device will operate into 1 phase force CCM. When the voltage is between 2.4V to 5.5V, the device will operate into 2 phase force CCM. Programming Output Voltage Control Input. Refer to PWM-VID Dynamic Voltage Control. Reference Voltage Output. This is a high precision voltage reference (2V) from the VREF pin to RGND pin. ON-Time/Switching Frequency Adjustment Input. Connect a 100pF ceramic capacitor between CTON and ground is optional for noise immunity enhancement. Negative Remote Sense Input. Connect this pin to the ground of output load. 10 RGND 11 SS Soft-Start Time Setting. Connect an external capacitor to adjust soft-start time. When the external capacitor is removed, the internal soft-start function will be chose. 12 VSNS Positive Remote Sense Input. Connect this pin to the positive terminal of output load. 13 PGOOD Power Good Indicator Output. Active high open drain output. 14 UGATE2 High Side Gate Driver of PWM 2. This pin provides the gate drive for the converter's high side MOSFET. Connect this pin to the Gate of high side MOSFET. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Pin No. Pin Name Pin Function 15 BOOT2 Bootstrap Supply for PWM 2. This pin powers the high side MOSFET driver. 16 PHASE2 Switch Node for PWM2. This pin is return node of the high side driver of PWM 2. Connect this pin to the Source of high side MOSFET together with the Drain of low side MOSFET and the inductor. 17 LGATE2 Low Side Gate Driver of PWM 2. This pin provides the gate drive for the converter's low side MOSFET. Connect this pin to the Gate of low side MOSFET. 18 PVCC 19 LGATE1 20 PHASE1 Supply Voltage Input. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND. Low Side Gate Driver of PWM 1. This pin provides the gate drive for the converter's low side MOSFET. Connect this pin to the Gate of low side MOSFET. Switch Node for PWM1. This pin is return node of the high side driver of PWM 1. Connect this pin to the Source of high side MOSFET together with the Drain of low side MOSFET and the inductor. Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation. 21 (Exposed Pad) GND Function Block Diagram VREF Reference Output Gen. VID PVCC REFADJ PSI REFIN Power On Reset & Central Logic Mode Select OV Threshold Select PGOOD + Control & Protection Logic UV 40% REFIN + Boot-Phase Detection 1 - SS Soft-Start & Slew Rate Control VSNS RGND EN Boot-Phase Detection 2 PWM CMP + Enable Logic BOOT1 UGATE1 PHASE1 TON Gen 1 - PWM1 To Driver Logic To Power On Reset LGATE1 TON Gen 2 PWM2 Driver Logic BOOT2 UGATE2 PHASE2 LGATE2 To Power On Reset TON VIN Detection S/H GM + VB S/H GM + VB Current Balance PHASE1 ZCD To Driver Logic To Protection Logic Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 Current Limit is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8812A Operation The RT8812A is a 2/1 phase synchronous Buck PWM controller with integrated drivers which are optimized for high performance graphic microprocessor and computer applications. The IC integrates a COT (Constant-On-Time) PWM controller with two MOSFET drivers, as well as output current monitoring and protection functions. Referring to the function block diagram of TON Genx, the synchronous UGATE driver is turned on at the beginning of each cycle. After the internal one-shot timer expires, the UGATE driver will be turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range and output voltage. Another one-shot sets a minimum off-time. The RT8812A also features a PWM-VID dynamic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count and enables a wide dynamic voltage range. Soft-Start (SS) For internal soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. The output voltage will track the internal ramp voltage during soft-start interval. For external soft-start function, an additional capacitor connected from SS pin to the GND will be charged by a current source and determines the soft-start time. PGOOD The power good output is an open drain architecture. Current Balance The RT8812A implements internal current balance mechanism in the current loop. The RT8812A senses per phase current and compares it with the average current. If the sensed current of any particular phase is higher than average current, the on-time of this phase will be adjusted to be shorter. Current Limit The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. Thus, the current to the load exceeds average output inductor current, the output voltage falls and eventually crosses the under voltage protection threshold, inducing IC shutdown. Over Voltage Protection (OVP) & Under Voltage Protection (UVP) The output voltage is continuously monitored for over voltage and under voltage protection. When the output voltage exceeds its set voltage threshold (If VREFIN ≤ 1.33V, OV = 2V, or VREFIN > 1.33V, OV = 1.5 x VREFIN), UGATE goes low and LGATE is forced high; when it is less than 40% of its set voltage, under voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until PVCC is re-supplied and exceeds the POR rising threshold voltage or EN is reset. When the soft-start is finished, the PGOOD open drain output will be high impedance. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Absolute Maximum Ratings (Note 1) TON to GND -----------------------------------------------------------------------------------------------------------------RGND to GND -------------------------------------------------------------------------------------------------------------- BOOTx to PHASEx ------------------------------------------------------------------------------------------------------- PHASEx to GND DC -----------------------------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------------------------ UGATEx to PHASEx DC -----------------------------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------------------------ LGATEx to GND DC -----------------------------------------------------------------------------------------------------------------------------<20ns ------------------------------------------------------------------------------------------------------------------------ Other Pins ------------------------------------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25°C WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------ Package Thermal Resistance (Note 2) WQFN-20L 3x3, θJA -------------------------------------------------------------------------------------------------------WQFN-20L 3x3, θJC ------------------------------------------------------------------------------------------------------ Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- Junction Temperature ----------------------------------------------------------------------------------------------------- Storage Temperature Range -------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------- Recommended Operating Conditions −0.3V to 30V −0.7V to 0.7V −0.3V to 6V −0.3V to 30V −8V to 36V −0.3V to 6V −5V to 7.5V −0.3V to 6V −2.5V to 7.5V −0.3V to 6V 3.33W 30°C/W 7.5°C/W 260°C 150°C −65°C to 150°C 2kV (Note 4) Input Voltage, VIN ----------------------------------------------------------------------------------------------------------Supply Voltage, VPVCC ---------------------------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------- 7V to 26V 4.5V to 5.5V −40°C to 125°C −40°C to 85°C Electrical Characteristics (TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 -- 5.5 V PWM Controller PVCC Supply Voltage VPVCC PVCC Supply Current ISUPPLY EN = 3.3V, Not Switching -- 1.5 2 mA PVCC Shutdown Current ISHDN EN = 0V -- -- 10 A 3.8 4.1 4.4 V -- 0.3 -- V 270 300 330 kHz PVCC POR Threshold POR Hysteresis Switching Frequency fSW R TON = 500k Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 (Note 5) is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8812A Parameter Symbol Test Conditions Min Typ Max Unit Minimum On-Time tON(MIN) -- 70 -- ns Minimum Off-Time tOFF(MIN) -- 300 -- ns 1.6 -- -- -- -- 0.8 EN Input Voltage EN Input Voltage Logic-High VENH Logic-Low VENL V Mode Decision PSI High Threshold VPSIH Enables Two Phases with FCCM 2.4 -- -- V PSI Intermediate Threshold VPSIM Enables One Phases with FCCM 1.2 -- 1.8 V PSI Low Threshold VPSIL Enables One Phases with DEM -- -- 0.8 V High-Level VVIDH 2 -- -- Low-Level -- -- 1 Zero Current Crossing Threshold 8 -- 8 mV Current Limit Setting Current IOCSET 9 10 11 A Current Limit Setting Current IOCSET_TC Temperature Coefficient -- 6300 -- ppm/C ROCSET = 10k -- 60 -- mV VOVP, Absolute VREFIN 1.33V 1.9 2 2.1 V VOVP, Relative VREFIN > 1.33V 145 150 155 % FB forced above OV threshold -- 5 -- s UVP 35 40 45 % FB forced above UV threshold -- 3 -- s -- 150 -- C VID Input Voltage VVIDL V Protection Function Current Limit Threshold Absolute Over Voltage Protection Threshold Relative Over Voltage Protection Threshold OV Fault Delay Relative Under Voltage Protection Threshold VUVP UV Fault Delay Thermal Shutdown Threshold TSD PGOOD Blanking Time (Internal) From EN = high to PGOOD = high with VSNS within regulation point -- 2.5 -- ms VSNS Soft-Start (Internal) From first UGATE to VSNS regulation point, VREFIN = 1V and VSNS initial = 0V -- 0.7 -- ms -- 5 -- A VREFIN = 1V 17.5 12.5 7.5 mV Sourcing Current = 1mA, VID no Switching 1.98 2 2.02 V Soft-Start Current Source ISS Error Amplifier VSNS Error Comparator Threshold (Valley) Reference Reference Voltage VVREF Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Parameter Symbol Test Conditions Min Typ Max Unit Driver On-Resistance UGATE Driver Source RUGATEsr BOOTx PHASEx Forced to 5V -- 2 4 UGATE Driver Sink RUGATEsk BOOTx PHASEx Forced to 5V -- 1 2 LGATE Driver Source RLGATEsr LGATEx, High State -- 1.5 3 LGATE Driver Sink RLGATEsk LGATEx, Low State -- 0.7 1.5 From LGATE Falling to UGATE Rising -- 30 -- From UGATE Falling to LGATE Rising -- 20 -- PVCC to BOOTx, IBOOT = 10mA -- 40 80 Dead-Time Internal Boost Charging Switch On-Resistance RBOOT ns Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Not production tested. Test condition is VIN = 8V, VOUT = 1V, IOUT = 20A using application circuit. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8812A Typical Application Circuit 1 18 VPVCC PVCC 2.2µF RTON 500k 2.2 VIN 9 100k 13 PGOOD 4 PSI 5 VID SS 3 EN 8 VREF Enable BOOT2 UGATE2 0.1µF RREF1 PHASE2 20k RGND 20k RBOOT 6 CREFADJ RREFADJ 2.7nF 2k RGND RSTANDBY 5.1k VSTANDBY 0 470µF/50V 0.36µH/1.05m VOUT 22µF x 15 NC ROCSET 10k 11 CSS 47pF 0 15 330µF/2V x 4 NC VIN 0.1µF 10µF x 2 470µF/50V 0 14 0.36µH/1.05m 16 LGATE2 17 NC REFADJ NC RGND 7 REFIN CREFIN NC RREF2 18k 10µF x 2 0 Optional PGOOD PSI VID VIN 0.1µF PHASE1 20 LGATE1 19 TON CTON 1µF 0 BOOT1 1 RT8812A UGATE1 2 VSNS 10 10 10 VGND_SNS 12 VOUT_SNS GND 21 (Exposed pad) RGND RGND NC RGND Figure 1. 2 Active Phase Configuration 1 VPVCC 18 2.2µF RTON 500k 2.2 VIN PVCC 9 TON CTON 1µF Optional PGOOD 100k PSI 5 VID PSI 3 EN 8 VREF Enable 20k RGND 20k RBOOT 2k VSTANDBY 0 RREF2 18k RGND 6 CREFADJ RREFADJ 2.7nF RGND RSTANDBY 5.1k SS BOOT2 REFADJ 7 REFIN CREFIN NC VOUT 22µF x 15 NC NC 330µF/2V x 4 CSS 47pF 10 RGND UGATE2 PHASE2 470µF/50V 0.36µH/1.05m ROCSET 10k 11 VIN 10µF x 2 PHASE1 20 LGATE1 19 VSNS 0.1µF 0.1µF 0 PGOOD 4 VID RREF1 13 0 BOOT1 1 RT8812A UGATE1 2 10 10 VGND_SNS 12 VOUT_SNS 15 14 16 Floating LGATE2 17 GND 21 (Exposed pad) RGND NC RGND Figure 2. 1 Active Phase Configuration Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Typical Operating Characteristics Efficiency vs. Load Current 100% 100 90% 90 90% 90 80% 80 80% 80 70% 70 70% 70 Efficiency (%) Efficiency (%) Efficiency vs. Load Current 100% 100 60% 60 50% 50 40% 40 30% 30 20% 20 60% 60 50% 50 40% 40 30 30% 20% 20 10% 10 VOUT VIN = 19V, VPVCC = 5V, = 0.9V, 2 Phase Operation 0%0 0 5 10 15 20 25 30 35 40 45 50 VIN = 19V, VPVCC = 5V, VOUT = 0.9V, 1 Phase with DEM Operation 10 10% 0 0% 0.01 55 60 0.1 10 Load Current (A) Load Current (A) VREF vs. Temperature TON vs. Temperature 185.0 2.04 182.5 2.03 180.0 2.02 177.5 2.01 VREF (V) TON (ns) 1 175.0 172.5 170.0 2.00 1.99 1.98 167.5 1.97 VIN = 19V, VPVCC = 5V, No Load VIN = 19V, VPVCC = 5V, No Load 165.0 1.96 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 Temperature (°C) Temperature (°C) Inductor Current vs. Output Current Power On from EN 100 125 35 Inductor Current (A) 30 EN (5V/Div) 25 Phase 1 Phase 2 20 VOUT (1V/Div) 15 UGATE1 (50V/Div) 10 5 VIN = 19V, VPVCC = 5V UGATE2 (50V/Div) VIN = 19V, VPVCC = 5V, IOUT = 50A 0 0 10 20 30 40 50 60 Time (1ms/Div) Output Current (A) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8812A Power On from VCC Power Off from EN EN (5V/Div) PVCC (5V/Div) VOUT (1V/Div) VOUT (1V/Div) UGATE1 (50V/Div) UGATE2 (50V/Div) UGATE1 (50V/Div) VIN = 19V, VPVCC = 5V, IOUT = 50A UGATE2 (50V/Div) VIN = 19V, VPVCC = 5V, IOUT = 50A Time (1ms/Div) Time (1ms/Div) Power Off from VCC Dynamic Output Voltage Control VIN = 19V, VPVCC = 5V PVCC (5V/Div) DVID (2V/Div) VOUT (1V/Div) VOUT (1V/Div) UGATE1 (50V/Div) UGATE2 (50V/Div) UGATE1 (50V/Div) VIN = 19V, VPVCC = 5V, IOUT = 50A UGATE2 (50V/Div) IOUT = 50A, VREFIN = 0.6V to 1.2V Time (1ms/Div) Time (50μs/Div) Dynamic Output Voltage Control Load Transient Response VIN = 19V, VPVCC = 5V DVID (2V/Div) VOUT (100mV/Div) VOUT (1V/Div) IOUT (50A/Div) UGATE1 (50V/Div) UGATE2 (50V/Div) UGATE2 (50V/Div) UGATE1 (50V/Div) IOUT = 50A, VREFIN = 1.2V to 0.6V Time (50μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VIN = 19V, VPVCC = 5V Time (20μs/Div) is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Load Transient Response OVP VOUT (100mV/Div) VVSNS (1V/Div) IOUT (50A/Div) UGATE1 (20V/Div) UGATE2 (50V/Div) UGATE1 (50V/Div) VIN = 19V, VPVCC = 5V LGATE1 (5V/Div) VIN = 19V, VPVCC = 5V, No Load Time (20μs/Div) Time (100μs/Div) UVP OCP IL1 (20A/Div) VVSNS (1V/Div) IL2 (20A/Div) UGATE1 (20V/Div) LGATE1 (5V/Div) UGATE1 (50V/Div) VIN = 19V, VPVCC = 5V, IOUT = 40A Time (20μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 LGATE1 (10V/Div) VIN = 19V, VPVCC = 5V Time (20μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT8812A Application Information The RT8812A is a dual-phase synchronous Buck PWM controller with integrated drivers which is optimized for high performance graphic microprocessor and computer applications. A COT (Constant-On-Time) PWM controller and two MOSFET drivers with internal bootstrap diodes are integrated so that the external circuit can be easily designed and the number of component is reduced. The topology solves the poor load transient response timing problems of fixed-frequency mode PWM and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes. The IC supports dynamic mode transition function with various operating states, which include dual-phase with CCM operation and single phase with diode emulation mode. These different operating states make the system efficiency as high as possible. The RT8812A provides a PWM-VID dynamic control operation in which the feedback voltage is regulated and tracks external input reference voltage. It also features complete fault protection functions including over voltage, under voltage and current limit. Remote Sense The RT8812A uses the remote sense path (VSNS and RGND) to overcome voltage drops in the power lines by sensing the voltage directly at the end of GPU. Normally, to protect remote sense path disconnecting, there are two resistors (RLocal) connecting between local sense path and remote sense path. That is, in application with remote sense, the RLocal is recommended to be 10Ω to 100Ω. If no need of remote sense, the RLocal is recommended to be 0Ω. VIN BOOT UGATE Local Sense Path PHASE VOUT The RT8812A integrates a Constant-On-Time (COT) PWM controller, and the controller provides the PWM signal which relies on the output ripple voltage comparing with internal reference voltage as shown in Figure 4. Referring to the function block diagram of TON Genx, the synchronous UGATE driver is turned on at the beginning of each cycle. After the internal one-shot timer expires, the UGATE driver will be turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage and output voltage range. Another one-shot sets a minimum off-time. VOUT VPEAK VOUT VVALLEY VREF 0 t tON Figure 4. Constant On-Time PWM Control On-Time Control The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to output voltage and inversely proportional to input voltage. The implementation results in a nearly constant switching frequency without the need for a clock generator. 2 VOUT 3.2p TON = RTON VIN 0.5 And then the switching frequency FS is : FS = VOUT / VIN TON LGATE RLocal+ RLocal+ RGND GPU RTON is a resistor connected from the VIN to TON pin. The value of RTON can be selected according to Figure 5. - VSNS GPU Remote Sense Path Figure 3. Output Voltage Sensing Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 PWM Operation The recommend operation frequency range is 150kHz to 600kHz. is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Diode-Emulation Mode 800 In diode-emulation mode, the RT8812A automatically Frequency (kHz)1 700 600 500 400 300 200 150 250 350 450 550 650 750 RTON (kΩ) Figure 5. Frequency vs. RTON Active Phase Circuit setting The RT8812A operates as active phase being 2 phase, and 1 phase. When programming active phase being 1 phase, The UGATE2, BOOT2, PHASE2, and LGATE 2 pins are floating. As programming active phase being 1 phase, the voltage setting at PSI pin can't higher than 1.8V. reduces switching frequency at light-load conditions to maintain high efficiency. As the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial of negative current when the inductor freewheeling current reaches negative value. As the load current is further decreased, it takes a longer time to discharge the output capacitor to the level that requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction condition. The transition load point to the light load operation is shown in Figure 6 and can be calculated as follows : (V VOUT ) ILOAD(SKIP) IN t ON 2L where tON is on-time. Mode Selection The RT8812A can operate into 2 phases with force CCM, 1 phase with force CCM, and 1 phase with DEM according to PSI voltage setting. If PSI voltage is pulled below 0.8V, the controller will operate into 1 phase with DEM. In DEM operation, the RT8812A automatically reduces the operation frequency at light load conditions for saving power loss. If PSI voltage is pulled between 1.2V to 1.8V, the controller will switch operation into 1 phase with force CCM. If PSI voltage is pulled between 2.4V to 5.5V, the controller will switch operation into 2 phase with force CCM. The operation mode is summarized in Table 1. Moreover, the PSI pin is valid after POR of VR. Table 1 Operation Phase Number PSI Voltage Setting 1 phase with DEM 0V to 0.8V 1 phase with CCM 1.2V to 1.8V 2 phase with CCM 2.4V to 5.5V Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 IL Slope = (VIN - VOUT) / L IPEAK ILOAD = IPEAK/2 0 t tON Figure 6. Boundary condition of CCM/DEM The switching waveforms may be noisy and asynchronous in light loading diode-emulation operation condition, but this is a normal operating condition that results in high light-load efficiency. Trade-off in DEM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broad high efficiency range vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT8812A Forced-CCM Mode The low noise, forced-CCM mode disables the zerocrossing comparator, which controls the low side switch on-time. This causes the low side gate drive waveform to be the complement of the high side gate drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio VOUT/VIN. The benefit of forced-CCM mode is to keep the switching frequency fairly constant. signal as well as the input current at power up are limited. The soft-start process is finished until both the internal SSOK and external SSOK go high and protection is not triggered. Figure 7 shows the internal soft-start sequence. EN PVCC VOUT 4V Internal SS Enable and Disable The EN pin is a high impedance input that allows power sequencing between the controller bias voltage and another voltage rail. The RT8812A remains in shutdown if the EN pin is lower than 800mV. When the EN voltage rises above the 1.6V high level threshold, the RT8812A will begin a new initialization and soft-start cycle. Power On Reset (POR), UVLO Power On Reset (POR) occurs when VPVCC rises above to approximately 4.1V (typical), the RT8812A will reset the fault latch circuit and prepare for PWM operation. When the VPVCC is lower than 3.8V (typical), the Under Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. Soft-Start The RT8812A provides both internal soft-start function and external soft-start function. The soft-start function is used to prevent large inrush current and output voltage overshoot while the converter is being powered up. The soft-start function automatically begins once the chip is enabled. There is a delay time around 1.1ms from EN goes high to VOUT begins to ramp-up. 2V External SS Internal SSOK External SSOK LGATE UGATE PGOOD Soft-Start Current Limit Programming Normal Soft Discharged Figure 7. Internal Soft-Start Sequence The RT8812A also provides an external soft-start function, and the external soft-start sequence is shown in Figure 8. The external capacitor connected from SS pin to GND is charged by a 5μA current source to build a soft-start voltage ramp. If the external soft-start function is chosen, the external soft-start time should be set longer than internal soft-start time to avoid output voltage tracking the internal soft-start ramp. The recommend external soft-start slew rate is from 0.1V/ms to 0.4V/ms. If the external capacitor between the SS pin and ground is removed, the internal soft-start function will be chosen. An internal current source charges the internal soft-start capacitor so that the internal soft-start voltage ramps up linearly The output voltage will track the internal soft-start voltage during the soft-start interval. After the internal softstart voltage exceeds the REFIN voltage, the output voltage no longer tracks the internal soft-start voltage but follows the REFIN voltage. Therefore, the duty cycle of the UGATE Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Power Good Output (PGOOD) The PGOOD pin is an open drain output, and it requires a pull-up resistor. During soft-start, the PGOOD is held low and is allowed to be pulled high after VOUT achieved over UVP threshold and under OVP threshold. In additional, if any protection is triggered during operation, the PGOOD will be pulled low immediately. EN PVCC VOUT 4V Internal SS 2V External SS PWM VID and Dynamic Output Voltage Control Internal SSOK The RT8812A features a PWM VID input for dynamic output voltage control as shown in Figure 10, which reduces the number of device pin and enables a wide dynamic voltage range. The output voltage is determined by the applied voltage on the REFIN pin. The PWM duty cycle determines the variable output voltage at REFIN. External SSOK LGATE UGATE PGOOD Soft-Start PWM IN Soft Discharged Normal Current Limit Programming VID VREF RREF1 Figure 8. External Soft-Start Sequence RREFADJ REFADJ Buffer CREFADJ RGND RBOOT RGND VCC REFIN VREFIN ISS RREF2 RSTANDBY CREFIN SS CSS SS RGND Standby Mode Control VOUT tSS Figure 9. External Soft-Start Time Setting The soft-start time can be calculated as : (CSS VREFIN ) tSS = ISS Where ISS = 5μA (typ.), VREFIN is the voltage of REFIN pin, and CSS is the external capacitor placed from SS to GND. RGND Q1 RGND Figure 10. PWM VID Analog Circuit Diagram With the external circuit and VID control signal, the controller provides three operation modes shown as Figure 11. NORMAL MODE VREF BOOT MODE BOOT MODE STANDBY MODE REFIN PWM VID STANDBY CONTROL Figure 11. PWM VID Time Diagram Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT8812A Boot Mode VID is not driven, and the buffer output is tri-state. At this time, turn off the switch Q1 and connect a resistor divider as shown in Figure 11 that can set the REFIN voltage to be VBOOT as the following equation : RREF2 VBOOT = VVREF RREF1 RREF2 RBOOT Choose RREF2 to be approximately 10kΩ, and the RREF1 and RBOOT can be calculated by the following equations : RREF1 RBOOT RREF2 VVREF VBOOT VBOOT RREF2 VVREF VBOOT RBOOT VBOOT RBOOT RREF1 Standby Mode An external control can provide a very low voltage to meet VOUT operating in standby mode. If the VID pin is floating and switch Q1 is enabled as shown in Figure 11, the REFIN pin can be set for standby voltage according to the calculation below : VSTANDBY = VVREF RREF2 (RREF1 // RREFADJ ) RBOOT RREF2 RREFADJ RREF1 Vmin Vmax Vmin The relationship between VID duty and VREFIN is shown in RREF2 VVREF VBOOT VBOOT Vmax = VVREF By choosing RREF1, RREF2, and RBOOT, the RREFADJ can be calculated by the following equation : Where VVREF = 2V (typ.) RREF1 RREF2 RREF2 RBOOT RREFADJ // (RBOOT RREF2 ) RREF1 RREFADJ // (RBOOT RREF2 ) Vmin = VVREF Figure 12, and VOUT can be set according to the calculation below : VOUT = Vmin N VSTEP where VSTEP is the resolution of each voltage step 1 : (V Vmin ) VSTEP = max Nmax where Nmax is the number of total available voltage steps and N is the number of step at a specific VOUT. The dynamic voltage VID period (Tvid = Tu x Nmax) is determined by the unit pulse width (Tu) and the available step number (Nmax). The recommended Tu is 27ns. VREFIN N = Nmax Vmax RREF2 // RSTANDBY RREF1 RBOOT (RREF2 // RSTANDBY ) By choosing RREF1, RREF2, and RBOOT, the RSTANDBY can be calculated by the following equation : RSTANDBY RREF2 RREF1 RBOOT VSTANDBY N=2 N=1 Vmin 0.5 1 N=1 VID Input RREF2 VREF VSTANDBY RREF1 RREF2 RBOOT RREF1 VID Duty 0 Tu N=2 VID Input Tvid = Nmax x Tu Normal Mode If the VID pin is driven by a PWM signal and switch Q1 is disabled as shown in Figure 11, the VREFIN can be adjusted from Vmin to Vmax, where Vmin is the voltage at zero percent PWM duty cycle and Vmax is the voltage at one hundred percent PWM duty cycle. The Vmin and Vmax can be set by the following equations : Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 Figure 12. PWM VID Analog Output is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A VID Slew Rate Control Current Limit Setting In RT8812A, the VREFIN slew rate is proportional to PWM VID duty, the rising time and falling time are the same. In In normal mode, the VREFIN slew rate SR can be estimated by CREFADJ or CREFIN as the following equation : Current limit threshold can be set by a resistor (ROCSET) between LGATE1 and GND. Once PVCC exceeds the POR threshold and chip is enabled, an internal current source IOCSET flows through ROCSET. The voltage across ROCSET is stored as the current limit protection threshold VOCSET. The threshold range of VOCSET is 50mV to 400mV. After that, the current source is switched off. When choose CREFADJ : SR = RSR (VREFIN_Final VREFIN_initial ) 80% 2.2RSR CREFADJ = (RREF1 // RREFADJ ) // (RBOOT +RREF2 ) ROCSET = When choose CREFIN : SR = (VREFIN_Final VREFIN_initial ) 80% 2.2RSR CREFIN RSR = RREF1 // RREFADJ RBOOT // RREF2 The recommend SR is estimated by CREFADJ. Current Limit The RT8812A provides cycle-by-cycle current limit control by detecting the PHASE voltage drop across the low side MOSFET when it is turned on. The current limit circuit employs a unique “valley” current sensing algorithm as shown in Figure 13. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. In order to provide both good accuracy and a cost effective solution, the RT8812A supports temperature compensated MOSFET RDS(ON) sensing. IL IL,PEAK ILOAD IL,VALLEY t 0 Figure 13. “Valley” Current Limit In an over current condition, the current to the load exceeds the average output inductor current. Thus, the output voltage falls and eventually crosses the under voltage protection threshold, inducing IC shutdown. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 ROCSET can be determined using the following equation : IVALLEY RLGATEDS(ON) 40mV IOCSET where IVALLEY represents the desired inductor limit current (valley inductor current) and IOCSET is current limit setting current which has a temperature coefficient to compensate the temperature dependency of the RDS(ON). If ROCSET is not present, there is no current path for IOCSET to build the current limit threshold. In this situation, the current limit threshold is internally preset to 400mV. Negative Current Limit The RT8812A supports cycle-by-cycle negative current limiting. The absolute value of negative current limit threshold is the same with the positive current limit threshold. If negative inductor current is rising to trigger negative current limit, the low side MOSFET will be turned off and the current will flow to input side through the body diode of the high side MOSFET. At this time, output voltage tends to rise because this protection limits current to discharge the output capacitor. In order to prevent shutdown because of over voltage protection, the low side MOSFET is turned on again 400ns after it is turned off. If the device hits the negative over current threshold again before output voltage is discharged to the target level, the low side MOSFET is turned off and process repeats. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side MOSFET is turned off, the high side MOSFET is then turned on, and the device keeps normal operation. is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT8812A Current Balance The RT8812A implements current balance mechanism in the current loop. The RT8812A senses per phase current signal and compares it with the average current. If the sensed current of any particular phase is higher than the average current, the on-time of this phase will be decreased. The current balance accuracy is major related with onresistance of low side MOSFET (RLG,DS(ON)). That is, in practical application, using lower RLG,DS(ON) will reduce the current balance accuracy. Output Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage protection. If REFIN voltage is lower than 1.33V, the over voltage threshold follows to absolute over voltage 2V. If REFIN voltage is higher than 1.33V, the over voltage threshold follows relative over voltage 1.5 x VREFIN. When OVP is triggered, UGATE goes low and LGATE is forced high. The RT8812A is latched once OVP is triggered and can only be released by PVCC or EN power on reset. A 5μs delay is used in OVP detection circuit to prevent false trigger. Output Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 40% of its set voltage, under voltage protection is triggered and then all UGATE and LGATE gate drivers are forced low. There is a 3μs delay built in the UVP circuit to prevent false transitions. During soft-start, the UVP blanking time is equal to PGOOD blanking time. MOSFET Gate Driver The RT8812A integrates high current gate drivers for the MOSFETs to obtain high efficiency power conversion in synchronous Buck topology. A dead-time is used to prevent the crossover conduction for high side and low side MOSFETs. Because both the two gate signals are off during the dead-time, the inductor current freewheels through the body diode of the low side MOSFET. The freewheeling current and the forward voltage of the body diode contribute power losses to the converter. The Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 RT8812A employs adaptive dead time control scheme to ensure safe operation without sacrificing efficiency. Furthermore, elaborate logic circuit is implemented to prevent cross conduction. For high output current applications, two power MOSFETs are usually paralleled to reduce RDS(ON). The gate driver needs to provide more current to switch on/off these paralleled MOSFETs. Gate driver with lower source/sink current capability results in longer rising/falling time in gate signals and higher switching loss. The RT8812A embeds high current gate drivers to obtain high efficiency power conversion. Inductor Selection Inductor plays an importance role in step-down converters because the energy from the input power rail is stored in it and then released to the load. From the viewpoint of efficiency, the DC Resistance (DCR) of inductor should be as small as possible to minimize the copper loss. In additional, the inductor occupies most of the board space so the size of it is important. Low profile inductors can save board space especially when the height is limited. However, low DCR and low profile inductors are usually not cost effective. Additionally, higher inductance results in lower ripple current, which means the lower power loss. However, the inductor current rising time increases with inductance value. This means the transient response will be slower. Therefore, the inductor design is a trade-off between performance, size and cost. In general, inductance is designed to let the ripple current ranges between 20% to 40% of full load current. The inductance can be calculated using the following equation : Lmin = VIN VOUT V OUT fSW k IOUT_rated VIN where k is the ratio between inductor ripple current and rated output current. Input Capacitor Selection Voltage rating and current rating are the key parameters in selecting input capacitor. Generally, input capacitor has a voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A IRMS = IOUT VOUT VOUT 1 VIN VIN The next step is to select proper capacitor for RMS current rating. Use more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank is a good design. Besides, placing ceramic capacitor close to the drain of the high side MOSFET is helpful in reducing the input voltage ripple at heavy load. Output Capacitor Selection The output filter capacitor must have ESR low enough to meet output ripple and load transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capacitance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. Organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended. MOSFET Selection The majority of power loss in the step-down power conversion is due to the loss in the power MOSFETs. For low voltage high current applications, the duty cycle of the high side MOSFET is small. Therefore, the switching loss of the high side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such kind of application. However, the small duty cycle means the low side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, the MOSFETs with low RDS(ON) are preferred in the circuit design. In some cases, more than one MOSFET are connected in parallel to further decrease the on-state resistance. However, this depends on the low side MOSFET driver capability and the budget. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-20L 3x3 package, the thermal resistance, θJA, is 30°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : P D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for WQFN-20L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 14 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 4.0 Maximum Power Dissipation (W)1 The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : Four-Layer PCB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 14. Derating Curve of Maximum Power Dissipation Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS8812A-04 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT8812A Layout Considerations Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. Following layout guidelines must be considered before starting a layout for RT8812A. Place the RC filter as close as possible to the PVCC pin. Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high voltage switching node. Connections from the drivers to the respective gate of the high side or the low side MOSFET should be as short as possible to reduce stray inductance. All sensitive analog traces and components such as VSNS, RGND, EN, PSI, VID, PGOOD, VREF, TON VREFADJ, VREFIN and TSNS should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. Power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS8812A-04 November 2013 RT8812A Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 2.900 3.100 0.114 0.122 D2 1.650 1.750 0.065 0.069 E 2.900 3.100 0.114 0.122 E2 1.650 1.750 0.065 0.069 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 20L QFN 3x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS8812A-04 November 2013 www.richtek.com 21