STR-Y6735

Quasi-Resonant Controllers with Integrated Power MOSFET
STR-Y6700 Series
General Descriptions
Package
The STR-Y6700 series are power ICs for switching
power supplies, incorporating a MOSFET and a
quasi-resonant controller IC.
Including an auto standby function in the controller,
the product achieves the low standby power by the
automatic switching between the PWM operation in
normal operation, one bottom-skip operation under
medium to light load conditions and the burst-oscillation
under light load conditions.
The product achieves high cost-performance power
supply systems with few external components.
TO220F-7L
Features
Lineup
 Electrical Characteristics
 Multi-mode Control
The optimum operation depending on load conditions
is changed automatically and is achieved high
efficiency operation across the full range of loads.





Not to Scale
Operation Mode
Normal load ------------------------- Quasi-resonant mode
Medium to light load -------------One bottom-skip mode
Light load -------------------------- Burst oscillation mode
(Auto standby function)
No load power consumption
PIN < 30 mW (100VAC)
PIN < 50 mW (230VAC)
Leading Edge Blanking Function
Bias Assist Function
Built-in startup circuit reduces
Protections
Overcurrent Protection 1 (OCP1); Pulse-by-Pulse,
with Input Compensation Function
Overcurrent Protection 2 (OCP2)(1); latched shutdown
Overload Protection (OLP); latched shutdown
Overvoltage Protection (OVP); latched shutdown
Thermal Shutdown Protection (TSD); latched shutdown
(1)
Products with the last letter "A" don’t have the
OCP2 function.
Products
STR–Y6735
STR–Y6735A
STR–Y6753
BR1
L51
D51
T1
VOUT(+)
RDS(ON)(max.)
500 V
0.8 Ω
650 V
STR–Y6754
STR–Y6766
STR–Y6766A
STR–Y6765
STR–Y6763
STR–Y6763A
1.9 Ω
1.4 Ω
1.7 Ω
800 V
2.2 Ω
3.5 Ω
 Output Power, POUT(2)
Products
STR–Y6735
STR–Y6735A
STR–Y6753
STR–Y6754
STR–Y6766
STR–Y6766A
STR–Y6765
STR–Y6763
STR–Y6763A
(2)
Typical Application Circuit
VDSS(min.)
POUT (Open frame)
380VAC
85~265VAC
120 W(100VAC)
–
100 W
60 W
120 W
67 W
140 W
80 W
120 W
70 W
80 W
50 W
The output power is actual continues power that is measured at
50 °C ambient. The peak output power can be 120 to 140 % of
the value stated here. Core size, ON Duty, and thermal design
affect the output power. It may be less than the value stated here.
VAC
P
C1
PC1
R55
C51
S
R54
R51
R52
C53
U1
C52 R53
D2
STR-Y6700
C3
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
1
R2
U51
D
R56
VOUT(-)
Applications
 White goods
 Office automation equipment
 Industrial equipment
DZBD
2 3 4 5 6 7
RBD1
R3
ROCP
CBD
C4
C5
RBD2
PC1
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
CY
SANKEN ELECTRIC CO.,LTD.
http://www.sanken-ele.co.jp/en/
1
STR-Y6700 Series
CONTENTS
General Descriptions ------------------------------------------------------------------------------------------ 1
1. Absolute Maximum Ratings ----------------------------------------------------------------------------- 3
2. Electrical Characteristics -------------------------------------------------------------------------------- 4
3. Performance Curves -------------------------------------------------------------------------------------- 6
3.1 Derating Curves ------------------------------------------------------------------------------------ 6
3.2 Ambient Temperature versus Power Dissipation Curves ---------------------------------- 6
3.3 MOSFET Safe Operating Area Curves ------------------------------------------------------- 8
3.4 Transient Thermal Resistance Curves --------------------------------------------------------- 9
4. Functional Block Diagram----------------------------------------------------------------------------- 10
5. Pin Configuration Definitions ------------------------------------------------------------------------- 10
6. Typical Application Circuit --------------------------------------------------------------------------- 11
7. Package Outline ----------------------------------------------------------------------------------------- 12
8. Marking Diagram --------------------------------------------------------------------------------------- 12
9. Operational Description ------------------------------------------------------------------------------- 13
9.1 Startup Operation ------------------------------------------------------------------------------- 13
9.2 Undervoltage Lockout (UVLO) --------------------------------------------------------------- 13
9.3 Bias Assist Function ----------------------------------------------------------------------------- 13
9.4 Soft Start Function ------------------------------------------------------------------------------ 14
9.5 Constant Output Voltage Control ------------------------------------------------------------ 15
9.6 Leading Edge Blanking Function ------------------------------------------------------------- 15
9.7 Quasi-Resonant Operation and Bottom-On Timing Setup ------------------------------ 15
9.7.1 Quasi-Resonant Operation ------------------------------------------------------------ 15
9.7.2 Bottom-On Timing Setup ------------------------------------------------------------- 16
9.8 BD Pin Blanking Time -------------------------------------------------------------------------- 17
9.9 Multi-mode Control ----------------------------------------------------------------------------- 18
9.9.1 One Bottom-Skip Quasi-Resonant Operation ------------------------------------- 18
9.9.2 Automatic Standby Mode Function ------------------------------------------------- 19
9.10 Maximum On-Time Limitation Function --------------------------------------------------- 19
9.11 Overcurrent Protection (OCP) ---------------------------------------------------------------- 20
9.11.1 Overcurrent Protection 1 (OCP1) --------------------------------------------------- 20
9.11.2 Overcurrent Protection 2 (OCP2) --------------------------------------------------- 20
9.11.3 OCP1 Input Compensation Function ----------------------------------------------- 20
9.11.4 When Overcurrent Input Compensation is Not Required ---------------------- 23
9.12 Overload Protection (OLP) -------------------------------------------------------------------- 23
9.13 Overvoltage Protection (OVP) ---------------------------------------------------------------- 24
9.14 Thermal Shutdown (TSD) ---------------------------------------------------------------------- 24
10. Design Notes ---------------------------------------------------------------------------------------------- 25
10.1 External Components --------------------------------------------------------------------------- 25
10.2 Transformer Design ----------------------------------------------------------------------------- 27
10.3 PCB Trace Layout and Component Placement -------------------------------------------- 28
11. Pattern Layout Example ------------------------------------------------------------------------------- 30
12. Reference Design of Power Supply ------------------------------------------------------------------ 31
OPERATING PRECAUTIONS -------------------------------------------------------------------------- 33
IMPORTANT NOTES ------------------------------------------------------------------------------------- 34
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
2
STR-Y6700 Series
1.
Absolute Maximum Ratings
 The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
 Unless otherwise specified TA = 25 °C
Parameter
Drain Peak Current(1)
Maximum Switching Current(2)
Symbol
IDPEAK
IDMAX
Test Conditions
Single pulse
Single pulse
Ta= −20 to 125°C
Pins
1–2
1–2
ILPEAK=2.3A
ILPEAK=2.6A
Avalanche Energy(3)(4)
EAS
ILPEAK=2.9A
ILPEAK=3.2A
1–2
ILPEAK=4.1A
ILPEAK=3.5A
D/ST Pin Voltage
S/OCP Pin Voltage
VCC Pin Voltage
FB/OLP Pin Voltage
FB/OLP Pin Sink Current
BD Pin Voltage
Power Dissipation(5)
1−4
2–4
3–4
5–4
5–4
6–4
VSTARTUP
VOCP
VCC
VFB
IFB
VBD
PD1
With infinite
heatsink
1–2
Rating
6.7
8.9
9.2
10.5
11.0
14.6
6.7
8.9
9.2
10.5
11.0
14.6
60
77
99
116
198
152
Units
− 1.0 to VDSS
V
V
V
V
mA
V
− 2.0 to 6.0
35
− 0.3 to 7.0
10.0
− 6.0 to 6.0
19.9
21.8
20.2
23.6
STR–Y6763 / 63A
STR–Y6765
A
Control Part Power Dissipation
Internal Frame Temperature in
Operation
Operating Ambient Temperature
Storage Temperature
Junction Temperature
STR–Y6763 / 63A
STR–Y6765
A
STR–Y6753
STR–Y6766 / 66A
STR–Y6754
STR–Y6735 / 35A
STR–Y6763 / 63A
STR–Y6765
mJ
STR–Y6753
STR–Y6766 / 66A
STR–Y6754
STR–Y6735 / 35A
STR–Y6763 / 63A
STR–Y6765
W
STR–Y6753
STR–Y6766 / 66A
STR–Y6735 / 35A
STR–Y6754
1.8
0.8
W
W
TF
−
− 20 to 115
°C
TOP
Tstg
Tch
−
−
−
− 20 to 115
− 40 to 125
150
°C
°C
°C
VCC×ICC
STR–Y6766 / 66A
STR–Y6735 / 35A
1–2
3–4
PD2
STR–Y6753
STR–Y6754
21.5
Without heatsink
Notes
(1)
Refer to 3.3 MOSFET Safe Operating Area Curves
The maximum switching current is the drain current determined by the drive voltage of the IC and threshold voltage
(Vth) of the MOSFET.
(3)
Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve
(4)
Single pulse, VDD = 99 V, L = 20 mH
(5)
Refer to 3.2 TA-PD1curves.
(2)
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
3
STR-Y6700 Series
2.
Electrical Characteristics
 The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.
 Unless otherwise specified, TA = 25 °C, VCC = 20 V
Parameter
Symbol
Test
Conditions
Pins
Min.
Typ.
Max.
Units
VCC(ON)
3−4
13.8
15.1
17.3
V
VCC(OFF)
3−4
8.4
9.4
10.7
V
ICC(ON)
3−4
−
1.3
3.7
mA
3−4
−
4.5
50
µA
1−4
42
57
72
V
3−4
− 4.5
− 3.1
− 1.0
mA
VCC(BIAS)
3−4
9.5
11.0
12.5
V
fOSC
1−4
18.4
21.0
24.4
kHz
tSS
1−4
−
6.05
−
ms
VOCP(BS1)
2−4
0.487
0.572
0.665
V
VOCP(BS2)
2−4
0.200
0.289
0.380
V
VBD(TH1)
6−4
0.14
0.24
0.34
V
VBD(TH2)
6−4
0.07
0.17
0.27
V
Maximum Feedback Current
IFB(MAX)
5−4
−320
−205
−120
µA
Standby Operation
Standby Operation Threshold
Voltage
VFB(STBOP)
5−4
0.45
0.80
1.15
V
tON(MAX)
1−4
30.0
40.0
50.0
µs
−
455
−
Notes
Power Supply Startup Operation
Operation Start Voltage
Operation Stop Voltage
(1)
Circuit Current in Operation
Circuit Current in
Non-Operation
Startup Circuit Operation
Voltage
VSTART(ON)
Startup Current
ICC(STARTUP)
Startup Current Biasing
Threshold Voltage
PWM Switching Frequency
Soft Start Operation Duration
Normal Operation
Bottom-Skip Operation
Threshold Voltage 1
Bottom-Skip Operation
Threshold Voltage 2
Quasi-Resonant Operation
Threshold Voltage 1
Quasi-Resonant Operation
Threshold Voltage 2(2)
ICC(OFF)
VCC = 13 V
VCC = 13 V
Protected Operation
Maximum On-Time
Leading Edge Blanking Time
Overcurrent Detection 1
Threshold Voltage in Input
Compensation Operation
Overcurrent Detection 1
Threshold Voltage in Normal
Operation
Overcurrent Detection 2
Threshold Voltage
(1)
(2)
1−4
tON(LEB)
ns
−
470
−
VOCP(L)
VBD = –3V
2−4
0.560
0.660
0.760
V
VOCP(H)
VBD = 0V
2−4
0.820
0.910
1.000
V
VOCP(La.OFF)
2−4
1.65
1.83
2.01
V
STR–Y6735
/ 35A/ 65/
66/ 54
STR–Y6763
/ 63A/ 53
Products
without the
last letter
"A"
VCC(OFF) < VCC(BIAS) always.
VBD(TH2) < VBD(TH1) always.
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
4
STR-Y6700 Series
Parameter
Test
Conditions
Pins
Min.
Typ.
Max.
Units
IBD(O)
6−4
− 250
− 83
− 30
µA
OLP Bias Current
IFB(OLP)
5−4
− 15
− 10
−5
µA
OLP Threshold Voltage
VFB(OLP)
5−4
5.50
5.96
6.40
V
FB Pin Maximum Voltage in
Feedback Operation
VFB(MAX)
5−4
3.70
4.05
4.40
V
OVP Threshold Voltage
VCC(OVP)
3− 4
28.5
31.5
34.0
V
Tj(TSD)
−
135
−
−
°C
500
−
−
650
−
−
800
−
−
−
−
300
−
−
0.8
STR-Y6735
/ 35A
−
−
1.4
STR–Y6754
1.7
STR–Y6766
/ 66A
BD Pin Source Current
Thermal Shutdown Operating
Temperature
Symbol
Notes
MOSFET
Drain-to-Source Breakdown
Voltage
Drain Leakage Current
On Resistance
Switching Time
VDSS
IDSS
RDS(ON)
tf
IDS=300μA
VDS=VDSS
1–2
1–2
1–2
1–2
V
STR-Y6735 /
35A
STR-Y6753 /
54
STR-Y6763 /
63A / 65 /66
/66A
μA
Ω
1.9
STR–Y6753
2.2
STR–Y6765
STR–Y6763
/ 63A
STR–Y6753
/ 63 / 63A
STR-Y6735
/ 35A / 54 /
66 / 66A / 65
−
−
3.5
−
−
250
ns
−
−
300
ns
−
2.4
2.7
−
1.9
2.2
−
2.7
3.1
−
2.3
2.6
−
2.8
3.2
−
5.1
5.9
−
4.6
5.3
−
5.4
6.2
−
5.0
5.8
STR–Y6765
−
5.5
6.3
STR–Y6763
/ 63A
Thermal Resistance
Channel to Frame Thermal
Resistance(3)
Channel to Case Thermal
Resistance(4)
(3)
(4)
θch-F
θch-C
−
−
STR-Y6735
/ 35A / 54
STR–Y6766
/ 66A
°C/W
STR–Y6753
STR–Y6765
STR–Y6763
/ 63A
STR-Y6735
/ 35A / 54
STR–Y6766
/ 66A
°C/W
STR–Y6753
θch-F is thermal resistance between channel and internal frame.
θch-C is thermal resistance between channel and case. Case temperature is measured at the backside surface.
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
5
STR-Y6700 Series
3.
Performance Curves
3.1
Derating Curves
100
80
60
40
20
0
0
25
50
75
100
115
125
EAS Temperature Derating Coefficient (%)
Safe Operating Area
Temperature Derating Coefficient (%)
100
80
60
40
20
0
25
Internal frame temperature, TF (°C)
Figure 3-1 SOA Temperature Derating Coefficient Curve
3.2
75
100
125
150
Channel Temperature, Tch (°C)
Figure 3-2 Avalanche Energy Derating Coefficient Curve
Ambient Temperature versus Power Dissipation Curves
 STR–Y6735、STR–Y6735A
 STR–Y6753
30
30
25
25
Power Dissipation, PD1 (W)
Power Dissipation, PD1 (W)
50
21.5
20
With infinite heatsink
15
10
Without heatsink
5
With infinite heatsink
20.2
20
15
10
Without heatsink
5
1.8
1.8
0
0
0
25
50
75
100
115
125
150
0
25
Ambient Temperature, TA (°C )
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
50
75
100
115
125
150
Ambient Temperature, TA (°C )
6
STR-Y6700 Series
 STR–Y6754
 STR–Y6763、STR–Y6763A
30
30
25
21.5
Power Dissipation, PD1 (W)
Power Dissipation, PD1 (W)
25
With infinite heatsink
20
15
10
Without heatsink
5
1.8
With infinite heatsink
15
10
Without heatsink
5
1.8
0
0
19.9
20
25
50
75
100
115
0
125
0
150
25
Ambient Temperature, TA (°C )
75
100 115 125
150
Ambient Temperature, TA (°C )
 STR–Y6765
 STR–Y6766、STR–Y6766A
30
30
25
25
23.6
21.8
Power Dissipation, PD1 (W)
Power Dissipation, PD1 (W)
50
With infinite heatsink
20
15
10
Without heatsink
5
With infinite heatsink
20
15
10
Without heatsink
5
1.8
1.8
0
0
0
25
50
75
100 115 125
150
0
Ambient Temperature, TA (°C )
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
25
50
75
100 115 125
150
Ambient Temperature, TA (°C )
7
STR-Y6700 Series
3.3
MOSFET Safe Operating Area Curves
 When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1.
 The broken line in the safe operating area curve is the drain current curve limited by on-resistance.
 Unless otherwise specified, TA = 25 °C, Single pulse
 STR–Y6735, STR–Y6735A
 STR–Y6753
100
100
10
Drain Current, ID (A)
Drain Current, ID (A)
0.1ms
10
0.1ms
1ms
1
1
1ms
0.1
0.01
0.1
10
100
10
1000
100
Drain-to-Source Voltage (V)
1000
Drain-to-Source Voltage (V)
 STR–Y6754
 STR–Y6763, STR–Y6763A
100
10
0.1ms
10
Drain Current, ID (A)
Drain Current, ID (A)
0.1ms
1ms
1
1
1ms
0.1
0.01
0.1
10
100
10
1000
Drain-to-Source Voltage (V)
 STR–Y6765
1000
 STR–Y6766, STR–Y6766A
10
100
0.1ms
Drain Current, ID (A)
Drain Current, ID (A)
100
Drain-to-Source Voltage (V)
1ms
1
0.1
0.01
0.1ms
10
1ms
1
0.1
10
100
1000
Drain-to-Source Voltage (V)
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
10
100
1000
Drain-to-Source Voltage (V)
SANKEN ELECTRIC CO.,LTD.
8
STR-Y6700 Series
3.4
Transient Thermal Resistance Curves
 STR–Y6735, STR–Y6735A, STR–Y6754, STR–Y6765
Transient Thermal Resistance
θch-c (°C/W)
10
1
0.1
0.01
0.001
1µ
10µ
100µ
1m
10m
100m
1m
10m
100m
1m
10m
100m
Time (s)
 STR–Y6753, STR–Y6763, STR–Y6763A
Transient Thermal Resistance
θch-c (°C/W)
10
1
0.1
0.01
0.001
1µ
10µ
100µ
Time (s)
Transient Thermal Resistance
θch-c (°C/W)
 STR–Y6766, STR–Y6766A
10
1
0.1
0.01
0.001
1µ
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
10µ
100µ
Time (s)
SANKEN ELECTRIC CO.,LTD.
9
STR-Y6700 Series
4.
Functional Block Diagram
VCC
3
D/ST
1
STARTUP
UVLO
Reg / ICONST
DRV
LATCH
OCP/BS
S/OCP
2
FB/STB
OLP
FB/OLP
5
LOGIC
NF
7
OSC
GND
4
BD
6
BD
BD_STR-Y6700_R1
5.
Pin Configuration Definitions
1
D/ST
2
S/OCP
3
VCC
4
5
GND
FB/OLP
6
7
BD
NF
(LF3051)
Pin
Name
1
D/ST
2
S/OCP
3
VCC
4
GND
5
FB/OLP
6
BD
7
NF*
Descriptions
MOSFET drain and startup current input
MOSFET source and overcurrent protection
(OCP) signal input
Power supply voltage input for control part and
overvoltage protection (OVP) signal input
Ground
Constant voltage control signal input and over
load protection (OLP) signal input
Bottom Detection signal input, Input
Compensation detection signal input
(Non-function)
*For stable operation, NF pin should be connected to GND pin, using the shortest possible path.
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
10
STR-Y6700 Series
6.
Typical Application Circuit
 The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation.
 In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the
D/ST pin and the S/OCP pin.
 For stable operation, NF pin should be connected to GND pin, using the shortest possible path.
CRD clamp snubber
BR1
L51
D51
T1
VOUT(+)
VAC
R1 P
C2
C1
PC1
D1
R55
C51
S
R54
R51
R52
C53
U1
C52 R53
D2
STR-Y6700
R2
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
C3
U51
D
R56
VOUT(-)
DZBD
2 3 4 5 6 7
1
CV
RBD1
C(RC)
Damper snubber
R3
CBD
ROCP
C4
C5
RBD2
PC1
CY
Figure 6-1 Typical application circuit
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
SANKEN ELECTRIC CO.,LTD.
11
STR-Y6700 Series
7.
Package Outline
2.8 +0.2
 TO220F-7L
10 ±0.2
4.2 ±0.2
2.6±0.2
15 ±0.3
3.2±0.2
（5.6）
Gate burr
（1.1）
2.6 ±0.1
7-0.55 +0.2
-0.1
5×P1.17±0.15
＝5.85±0.15
2±0.15
（Measured at pin base）
5±0.5
7-0.62±0.15
5±0.5
10.4 ±0.5
（Measured at pin base）
R-end
R-end
+0.2
0.45 -0.1
2.54±0.6
（Measured at pin tip）
（Measured at pin base）
5.08±0.6
（Measured at pin tip）
0.5
0.5
Front view
1
0.5
0.5
Side view
2 3 4 5 6 7
NOTES :
1) Dimension is in millimeters.
2) Leadform: LF No.3051
3) Gate burr indicates protrusion of 0.3 mm (max.).
4) Pin treatment Pb-free. Device composition compliant with the RoHS directive.
8.
Marking Diagram
STR
Y67×××
Part Number
2
YMDDX
1
2
7
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
Lot Number
Y is the last digit of the year (0 to 9)
M is the month (1 to 9, O, N or D)
DD is a day (01 to 31)
X is the Sanken Control Symbol
SANKEN ELECTRIC CO.,LTD.
12
STR-Y6700 Series
9.
Operational Description
 All of the parameter values used in these descriptions
are typical values, unless they are specified as
minimum or maximum.
 With regard to current direction, "+" indicates sink
current (toward the IC) and "–" indicates source
current (from the IC).
9.1
winding so that VCC pin voltage becomes Equation (1)
within the specification of input and output voltage
variation of power supply.
VCC( BIAS) (max .)  VCC  VCC(OVP ) (min .)
⇒12.5 (V)  VCC  28.5 (V)
The startup time of IC is determined by C3 capacitor
value. The approximate startup time tSTART (shown in
Figure 9-2) is calculated as follows:
Startup Operation
Figure 9-1 shows the circuit around IC. Figure 9-2
shows the start up operation.
BR1
C1
U1
VCC
3
D2
P
VCC( ON )－VCC( INT )
(2)
I CC(STRATUP )
where,
tSTART : Startup time of IC (s)
VCC(INT) : Initial voltage on VCC pin (V)
R2
9.2
C3
GND
t START  C3 ×
T1
VAC
1
D/ST
(1)
D
VD
4
Figure 9-1 VCC pin peripheral circuit
Undervoltage Lockout (UVLO)
Figure 9-3 shows the relationship of VCC pin voltage
and circuit current ICC. When VCC pin voltage decreases
to VCC(OFF) = 9.4 V, the control circuit stops operation by
Undervoltage Lockout (UVLO) circuit, and reverts to
the state before startup.
Circuit current, ICC
VCC pin
voltage
VCC(ON)
ICC（ON）
Stop
Start
tSTART
Drain current,
ID
VCC（OFF）
VCC（ON） VCC pin
voltage
Figure 9-2 Startup operation
The IC incorporates the startup circuit. The circuit is
connected to D/ST pin. When D/ST pin voltage reaches
to Startup Circuit Operation Voltage V START(ON) = 57 V,
the startup circuit starts operation.
During the startup process, the constant current,
ICC(STARTUP) = − 3.1 mA, charges C3 at VCC pin. When
VCC pin voltage increases to VCC(ON) = 15.1 V, the
control circuit starts operation. During the IC operation,
the voltage rectified the auxiliary winding voltage, VD,
of Figure 9-1 becomes a power source to the VCC pin.
After switching operation begins, the startup circuit
turns off automatically so that its current consumption
becomes zero.
The approximate value of auxiliary winding voltage is
about 20 V, taking account of the winding turns of D
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
Figure 9-3 Relationship between
VCC pin voltage and ICC
9.3
Bias Assist Function
By the Bias Assist Function, the startup failure is
prevented and the latched state is kept.
The Bias Assist function is activated, when the VCC
voltage decreases to the Startup Current Biasing
Threshold Voltage, VCC(BIAS) = 11.0 V, in either of
following condition:
the FB pin voltage is the Standby Operation Threshold
Voltage, VFB(STBOP) = 0.80 V or less
or the IC is in the latched state due to activating the
protection function.
SANKEN ELECTRIC CO.,LTD.
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STR-Y6700 Series
When the Bias Assist Function is activated, the VCC
pin voltage is kept almost constant voltage, VCC(BIAS) by
providing the startup current, ISTARTUP, from the startup
circuit. Thus, the VCC pin voltage is kept more than
VCC(OFF).
Since the startup failure is prevented by the Bias
Assist Function, the value of C3 connected to VCC pin
can be small. Thus, the startup time and the response
time of the OVP become shorter.
The operation of the Bias Assist Function in startup is
as follows. It is necessary to check and adjust the startup
process based on actual operation in the application, so
that poor starting conditions may be avoided.
Figure 9-4 shows VCC pin voltage behavior during
the startup period.
After VCC pin voltage increases to VCC(ON) = 15.1 V
at startup, the IC starts the operation. Then circuit
current increases and VCC pin voltage decreases. At the
same time, the auxiliary winding voltage VD increases in
proportion to output voltage. These are all balanced to
produce VCC pin voltage.
When VCC pin voltage is decrease to VCC(OFF) = 9.4 V
in startup operation, the IC stops switching operation
and a startup failure occurs.
When the output load is light at startup, the output
voltage may become more than the target voltage due to
the delay of feedback circuit. In this case, the FB pin
voltage is decreased by the feedback control. When the
FB pin voltage decreases to the Standby Operation
Threshold Voltage, VFB(STBOP) = 0.80 V, or less, the IC
stops switching operation and VCC pin voltage
decreases. When VCC pin voltage decreases to VCC(BIAS),
the Bias Assist function is activated and the startup
failure is prevented.
VCC pin
voltage
step-wisely (4 steps). This function reduces the voltage
and the current stress of MOSFET and secondary side
rectifier diode.
During the soft start operation period, the operation is
in PWM operation, at an internally set operation
frequency, fOSC = 21.0 kHz.
Until BD pin voltage becomes the following condition
after the soft start time, the switching operation is PWM
control of fOSC = 21.0 kHz.
When BD pin voltage, VBD, becomes the following
condition, the IC starts quasi-resonant operation.
Quasi-resonant operation starting condition
 VBD ≥ VBD(TH1) = 0.24 V
 The effective pulse width of quasi-resonant signal
is 1.0 μs or more (refer to Figure 9-12)
After the soft start period, D/ST pin current, ID, is
limited by the overcurrent protection (OCP), until the
output voltage increases to the target operating voltage.
This period is given as tLIM.
When tLIM is longer than the OLP Delay Time, tOLP,
the output power is limited by the OLP operation (OLP).
Thus, the tOLP must be set longer than tLIM (refer to
Section 9.12).
Startup of IC Startup of SMPS
Normal operation
VCC pin voltage
tSTART
VCC(ON)
VCC(OFF)
tSS tLIM
Time
D/ST pin
current, ID
Startup success
IC starts operation
Target operating
voltage
Increase with rising of
output voltage
VCC(ON)
VCC(BIAS)
VCC(OFF)
PWM operation
Time
Quasi-resonant operation
BD pin voltage
VBD(TH1)
Bias assist period
Enlarged Waveform
Time
Startup failure
PWM operation
Time
Quasi-resonant operation
Figure 9-4 VCC pin voltage during startup period
The effective pulse width is
1.0µs or more
9.4
Soft Start Function
Figure 9-5 shows the behavior of VCC pin voltage,
drain current and BD pin voltage during the startup
period.
The IC activates the soft start circuitry during the
startup period. Soft start is fixed to tSS = 6.05 ms. During
the soft start period, over current threshold is increased
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
Figure 9-5 VCC and ID and VBD behavior during startup
SANKEN ELECTRIC CO.,LTD.
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STR-Y6700 Series
9.5
Constant Output Voltage Control
The IC achieves the constant voltage control of the
power supply output by using the current-mode control
method, which enhances the response speed and
provides the stable operation.
The IC compares the voltage, VROCP, of a current
detection resistor with the target voltage, VSC, by the
internal FB comparator, and controls the peak value of
VROCP so that it gets close to VSC, as shown in Figure 9-6
and Figure 9-7. VSC is generated by the FB/OLP pin
voltage.
 Light load conditions
When load conditions become lighter, the output
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, VSC decreases,
and the peak value of VROCP is controlled to be low,
and the peak drain current of I D decreases.
This control prevents the output voltage from
increasing.
 Heavy load conditions
When load conditions become greater, the IC
performs the inverse operation to that described above.
Thus, VSC increases and the peak drain current of ID
increases.
This control prevents the output voltage from
decreasing.
U1
S/OCP
2
GND FB/OLP
4
5
R3
VROCP
ROCP
C5
PC1
IFB
C4
Figure 9-6 FB/OLP pin peripheral circuit
Target voltage
+
9.6
Leading Edge Blanking Function
The IC uses the peak-current-mode control method
for the constant voltage control of output.
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of FB comparator or overcurrent protection
circuit (OCP) to the steep surge current in turning on a
power MOSFET.
In order to prevent this response to the surge voltage
in turning-on the power MOSFET, the Leading Edge
Blanking, tON(LEB) is built-in. During tON(LEB), the OCP
threshold voltage becomes VOCP(La.OFF) = 1.83 V in order
not to respond to the turn-on drain current surge (refer to
Section 9.11).
9.7
Quasi-Resonant Operation and
Bottom-On Timing Setup
9.7.1
Quasi-Resonant Operation
Using quasi-resonant operation, switching loss and
switching noise are reduced and it is possible to obtain
converters with high efficiency and low noise. This IC
performs quasi-resonant operation during one
bottom-skip operation.
Figure 9-8 shows the circuit of a flyback converter.
The meaning of symbols in Figure 9-8 is shown in Table
9-1. A flyback converter is a system that transfers the
energy stored in the transformer to the secondary side
when the primary side power MOSFET is turned off.
After the energy is completely transferred to the
secondary, when the power MOSFET keeps turning off,
the VDS begins free oscillation based on the LP and CV.
The quasi-resonant operation is the bottom-on operation that
the power MOSFET turns-on at the bottom point of free
oscillation of VDS.
Figure 9-9 shows an ideal VDS waveform during
bottom-on operation.
The delay time, tONDLY, is the time from starting free
oscillation of VDS to power MOSFET turn-on. The
tONDLY of an ideal bottom-on operation is half cycle of
the free oscillation, and is calculated using Equation (3).
t ONDLY ≒  L P  C V
(3)
VSC
VF
T1
VROCP
FB Comparator
Voltage on both
sides of ROCP
VFLY
C1 ID
P
Drain current,
ID
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
S
IOFF
VO
C51
VIN
NP
U1
Figure 9-7 Drain current, ID, and FB comparator
operation in steady operation
D51
LP
NS
CV
Figure 9-8 Basic flyback converter circuit
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STR-Y6700 Series
Table 9-1 The meaning of symbols in Figure 9-8
Symbol
VIN
VFLY
VDS
NP
NS
VO
VF
ID
IOFF
CV
LP
Descriptions
Input voltage
Flyback voltage
N
VFLY  P  VO  VF 
NS
The voltage between Drain and Source of
power MOSFET
Primary side number of turns
Secondary side number of turns
Output voltage
Forward voltage drop of the secondary
side rectifier
Drain current of power MOSFET
Current which flows through the
secondary side rectifier when power
MOSFET is off
Voltage resonant capacitor
Primary side inductance
The threshold voltage of quasi-resonant operation has
a hysteresis. VBD(TH1) is Quasi-Resonant Operation
Threshold Voltage 1, VBD(TH2) is Quasi-Resonant
Operation Threshold Voltage 2.
When the BD pin voltage, VREV2, increases to
VBD(TH1) = 0.24 V or more at the power MOSFET
turns-off, the power MOSFET keeps the off-state. After
that, the VDS decreases by the free oscillation. When the
VDS decreases to VBD(TH2) = 0.17 V, the power MOSFET
turns-on and the threshold voltage goes up to VBD(TH1)
automatically to prevent malfunction of the BD pin from
noise interference.
T1
VIN
P
C1
VIN
D2
CV
1
U1
DZBD
VFLY
BD
2 S/OCP GND
4
R
VDS 0
OCP
6
CBD
R2
VREV1
C3
3
VCC
D/ST
tONDLY
VIN
VFLY
D
VFW1
Forward voltage
Flyback voltage
RBD1
RBD2
VREV2
Bottom point
Figure 9-10 BD pin peripheral circuit
IOFF 0
Auxiliary
winding
voltage, VD
ID 0
tON
VREV1
0
Figure 9-9 Ideal bottom-on operation waveform
VFW1
9.7.2
Bottom-On Timing Setup
BD pin detects the signal of bottom-on timing and
input compensation of OCP1 (refer to Section 9.11.3).
Figure 9-10 shows the BD pin peripheral circuit, Figure
9-11 shows the waveform of auxiliary winding voltage.
The quasi-resonant signal, VREV2, is proportional to
auxiliary winding voltage, VD and is calculated as
follows:
VREV2 
R BD 2
 VREV1  VF 
R BD1  R BD 2
(4)
where,
VREV1: Flyback voltage of auxiliary winding D
VF : Forward voltage drop of ZBD
The BD pin detects the bottom point using the VREV2.
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
3.0 V recommended,
but less than 6.0 V acceptable
Quasi-resonant
Signal, VREV2
VBD(TH1)
tON
VBD(TH2)
0
Figure 9-11 The waveform of auxiliary winding voltage
 RBD1 and RBD2 Setup
RBD1 and RBD2 should be set so that VREV2 becomes
the following range:
Under the lowest condition of VCC pin voltage in
power supply specification, VREV2 ≥ VBD(TH1)= 0.34
V(max.).
Under the highest condition of VCC pin voltage in
SANKEN ELECTRIC CO.,LTD.
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STR-Y6700 Series
power supply specification, VREV2 < 6.0 V (Absolute
maximum rating of the BD pin) and the effective
pulse width of quasi-resonant signal is 1.0 μs or more
(refer to Figure 9-12).
The value of VREV2 is recommended about 3.0 V.
In the converse situation, if the turn-on point lags
behind the VDS bottom point (Figure 9-14), after
confirming the initial turn-on point, advance the
turn-on point by decreasing the CBD value gradually,
so that the turn-on will match the bottom point of VDS.
3.0 V recommended,
but less than 6.0 V acceptable
Quasi-resonant
signal, VREV2
Delayed turn-on point
0.34V
VDS
0.27V
0
Bottom point
Effective pulse width
(1.0μs or more)
Figure 9-12 The effective pulse width
of quasi-resonant signal
 CBD Setup
The delay time, tONDLY, until which the power
MOSFET turns on, is adjusted by the value of CBD, so
that the power MOSFET turns on at the bottom-on of
VDS (refer to Figure 9-9).
The initial value of CBD is set about 1000 pF. CBD is
adjusted while observing the actual operation
waveforms of VDS and ID under the maximum input
voltage and the maximum output power (If a voltage
probe is connected to BD pin, the bottom point may
misalign).
If the turn-on point precedes the bottom of the VDS
signal (see Figure 9-13), after confirming the initial
turn-on point, delay the turn-on point by increasing
the CBD value gradually, so that the turn-on will match
the bottom point of VDS.
Early turn-on point
VDS
0
IOFF
0
ID
0
ｔON
VBD(TH1)
VBD 0
Auxiliary
winding voltage
VD
Bottom point
VBD(TH2)
0
Figure 9-13 When the turn-on of a VDS waveform occurs
before a bottom point
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
IOFF
0
ID
0
ｔON
VBD(TH1)
VBD 0
Auxiliary
winding voltage
VD
VBD(TH2)
0
Figure 9-14 When the turn-on of a VDS waveform occurs
after a bottom point
9.8
BD Pin Blanking Time
Since the auxiliary winding voltage is input to the BD
pin, BD pin voltage may be affected from the surge
voltage ringing when the power MOSFET turns off. If
the IC detects the surge voltage as quasi-resonant signal,
the IC may repeatedly turn the power MOSFET on and
off at high frequency. This result in an increase of the
MOSFET power dissipation and temperature, and it can
be damaged.
The BD pin has a blanking period of 250 ns (max.) to
avoid detecting voltage during this period.
The poor coupling (the high leakage inductance) tends
to happen in a low output voltage transformer design
with high NP/ NS turns ratio (NP and NS indicate the
number of turns of the primary winding and secondary
winding, respectively), and the surge voltage ringing of
BD pin occurs easily (see Figure 9-15).
If the surge voltage continues longer than BD pin
blanking period and the high frequency operation of
power MOSFET occurs, the following adjustments are
required so that the surge period of BD pin is less than
250 ns.
In addition, the BD pin waveform during operation
should be measured by connecting test probes as short to
the BD pin and the GND pin as possible, in order to
measure any surge voltage correctly.
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STR-Y6700 Series
 CBD must be connected near the BD pin and the GND
pin.
 The circuit trace loop between the BD pin and the
GND pin must be separated from any traces carrying
high current
 The coupling of the primary winding and the auxiliary
winding must be good
 The clamping snubber circuit (refer to Figure 6-1)
must be adjusted properly.
and this enables the IC to switch in a stable operation.
Before the one bottom-skip point changed from heavy
to light load, or after that done from light to heavy load,
the switching frequency of the normal quasi-resonant
operation becomes higher and the switching loss of
power MOSFET increases. Thus, the temperature of the
power MOSFET should be checked at higher switching
frequency of the operation changing point in maximum
AC input voltage.
One bottom-skip quasi-resonant
VOCP(H)
VOCP(BS1)
VBD(TH1)
VBD(TH2)
VREV2
(a)Normal BD pin waveform (good coupling)
Normal quasi-resonant
VOCP(BS2)
VBD(TH1)
Load current
VBD(TH2)
VREV2
Figure 9-16 Hysteresis at the operational mode change
BD pin blanking time 250ns（max.）
(b)Inappropriate BD pin waveform (poor coupling)
Figure 9-15 The difference of BD pin voltage, VREV2,
waveform by the coupling condition of the transformer
9.9
Multi-mode Control
When the output power decreases, the usual
quasi-resonant control increases the switching frequency
and the switching loss.
Thus, The IC has the multi-mode control to achieve
high efficiency operation across the full range of loads.
The automatic multi-mode control changes among the
following three operational modes according to the
output loading state: normal quasi-resonant operation in
heavy load, one bottom-skip quasi-resonant operation in
medium to light load, and burst oscillation operation
(auto standby function) in light load.
9.9.1
 The mode is changed from one bottom-skip
quasi-resonant operation to normal quasi-resonant
operation (light load to heavy load).
When load is increased from one bottom-skip
operation, the MOSFET peak drain current value will
increase, and the positive pulse width will widen.
Also, the peak value of the S/OCP pin voltage
increases. When the load is increased further and the
S/OCP pin voltage rises to VOCP(BS1), the mode is
changed to normal quasi-resonant operation (see
Figure 9-17).
VDS
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
Normal
quasi-resonant
VOCP(H)
S/OCP
pin voltage
Light load
One Bottom-Skip Quasi-Resonant
Operation
The one bottom-skip function limits the rise of the
power MOSFET operation frequency in medium to light
load in order to reduce the switching loss.
Figure 9-17 shows the operation state transition
diagram of the output load from light load to heavy load.
Figure 9-18 shows the state transition diagram from
heavy load to light load.
As shown in Figure 9-16, in the process of the
increase and decrease of load current, hysteresis is
imposed at the time of each operational mode change.
For this reason, the switching waveform does not
become unstable near the threshold voltage of a change,
One bottom-skip
quasi-resonant
VOCP(BS1)
Heavy load
Figure 9-17 Operation state transition diagram from
light load to heavy load conditions

The mode is changed from normal quasi-resonant
operation to one bottom-skip quasi-resonant operation
(heavy load to light load).
When load is decreased from normal quasi-resonant
operation, the MOSFET peak drain current value will
decrease, and the positive pulse width will narrow.
Also, the peak value of the S/OCP pin voltage
decreases. When load is reduced further and the
S/OCP pin voltage falls to VOCP(BS2), the mode is
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STR-Y6700 Series
changed to one bottom-skip quasi-resonant operation
(see Figure 9-18).
VDS
One bottom-skip
quasi-resonant
Normal
quasi-resonant
VOCP(H)
S/OCP
pin
voltage
VOCP(BS2)
Heavy load
Light load
Figure 9-18 Operation state transition diagram from
heavy load to light load conditions
Figure 9-19 shows the effective pulse width of normal
quasi-resonant signal, and Figure 9-20 shows the
effective pulse width of one bottom-skip quasi-resonant
signal. In order to perform stable normal quasi-resonant
operation and one bottom-skip operation, it is necessary
to ensure that the pulse width of the quasi-resonant
signal is 1 μs or more under the conditions of minimum
input voltage and minimum output power.
The pulse width of the quasi-resonant signal, VREV2, is
defined as the period from the maximum specification of
VBD(TH1), 0.34 V, on the rising edge, to the maximum
specification of VBD(TH2), 0.27 V on the falling edge of
the pulse.
Quasi-resonant
signal, VREV2
9.9.2
Automatic Standby Mode Function
The S/OCP pin circuit monitors ID. Automatic
standby mode is activated automatically when ID reduces
under light load conditions at which the S/OCP pin
voltage falls to the standby state threshold voltage (about
9% compared to VOCP(H) = 0.910 V).
During standby mode, when the FB/OLP pin voltage
falls below VFB(STBOP), the IC stops switching operation,
and the burst oscillation mode will begin, as shown in
Figure 9-21.
Burst oscillation mode reduces switching losses and
improves power supply efficiency because of periodic
non-switching intervals.
Generally, to improve efficiency under light load
conditions, the frequency of the burst oscillation mode
becomes just a few kilohertz. Because the IC suppresses
the peak drain current well during burst oscillation mode,
audible noises can be reduced.
If the VCC pin voltage decreases to VCC(BIAS) = 11.0 V
during the transition to the burst oscillation mode, the
Bias Assist function is activated and stabilizes the
Standby mode operation, because ICC(STARTUP) is
provided to the VCC pin so that the VCC pin voltage
does not decrease to VCC(OFF).
However, if the Bias Assist function is always
activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
example, by adjusting the turns ratio of the auxiliary
winding and secondary winding and/or reducing the
value of R2 in Figure 10-2 (refer to Section 10.1
Peripheral Components for a detail of R2).
Output current,
IOUT
0.34V
Burst oscillation
0.27V
S/OCP pin
voltage
Effective pulse width
1.0µs or more
Below several kHz
Drain current,
ID
Figure 9-19 The effective pulse width of normal
quasi-resonant signal
Normal
operation
Standby
operation
Normal
operation
Figure 9-21 Auto Standby mode timing
Quasi-resonant
signal, VREV2
9.10 Maximum On-Time Limitation
Function
0.34V
0.27V
S/OCP pin
voltage
Effective pulse width
1.0µs or more
Figure 9-20 The effective pulse width of one
bottom-skip quasi-resonant signal
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
When the input voltage is low or in a transient state
such that the input voltage turns on or off, the on-time of
the incorporated power MOSFET is limited to the
maximum on-time, tON(MAX) = 40.0 μs in order to prevent
the decreasing of switching frequency. Thus, the peak
drain current is limited, and the audible noise of the
transformer is suppressed.
In designing a power supply, the on-time must be less
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STR-Y6700 Series
than tON(MAX) (see Figure 9-22).
If such a transformer is used that the on-time is
tON(MAX) or more, under the condition with the minimum
input voltage and the maximum output power, the output
power would become low. In that case, the transformer
should be redesigned taking into consideration the
following:
 Inductance, LP, of the transformer should be lowered
in order to raise the operation frequency.
In addition, if a C (RC) damper snubber of Figure
9-24 is used, reduce the capacitor value of damper
snubber. If the turn-on timing isn’t fitted to a VDS bottom
point, adjustments are required (refer to Section 9.7.2).
C（CR）
damper snubber
T1
D51
C1
C51
 Lower the primary and the secondary turns ratio, NP /
NS, to lower the duty cycle.
ID
1
D/ST
U1
On-time
S/OCP
2
time
C（CR）
damper snubber
ROCP
VDS
Figure 9-24 Damper snubber circuit
time
Figure 9-22 Confirmation of maximum on-time
9.11 Overcurrent Protection (OCP)
The IC has an Overcurrent Protection 1 (OCP1) and
an Overcurrent Protection 2 (OCP2).
OCP1 function: pulse-by-pulse, with Input Compensation Function. The OCP2 function: In case output
winding is shorted etc., the IC stops switching operation
at the latched state. The products with the last letter "A"
don’t have the OCP2 function.
9.11.2 Overcurrent Protection 2 (OCP2)
The products with the last letter "A" don’t have the
OCP2 function.
As the protection for an abnormal state, such as an
output winding being shorted or the withstand voltage of
secondary rectifier being out of specification, when the
S/OCP pin voltage reaches VOCP(La.OFF) = 1.83 V, the IC
stops switching operation immediately, in latch mode.
This overcurrent protection also operates during the
leading edge blanking.
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below VCC(OFF).
9.11.1 Overcurrent Protection 1 (OCP1)
OCP1 detects each drain peak current level of a power
MOSFET on pulse-by-pulse basis, and limits the output
power when the current level reaches to OCP threshold
voltage. During Leading Edge Blanking Time (tBW),
OCP1 is disabled. When power MOSFET turns on, the
surge voltage width of S/OCP pin should be less than
tON(LEB), as shown in Figure 9-23. In order to prevent
surge voltage, pay extra attention to ROCP trace layout
(refer to Section 10.3).
tON(LEB)
VOCP(H)’
Surge at MOSFET turn on
Figure 9-23 S/OCP pin voltage
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
9.11.3 OCP1 Input Compensation Function
The usual control ICs have some propagation delay
time. The steeper the slope of the actual drain current at
a high AC input voltage is, the larger the detection
voltage of actual drain peak current is, compared to
overcurrent detection threshold voltage. Thus, the peak
current has some variation depending on the AC input
voltage in OCP1 state.
When using a quasi-resonant converter with universal
input (85 to 265 VAC), if the output power is set
constant, then because higher input voltages have higher
frequency, the on-time is reduced. Thus, the peak
current in OCP1 state tends to be affected by
propagation delay in the higher input voltage.
If the IC does not have Input Compensation Function,
the output current at OCP1 point in the maximum input
voltage, IOUT(OCP), becomes about double of IOUT (Figure
9-25 “without input compensation”). IOUT is the target
output current considered with maximum output power
in the minimum input voltage.
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STR-Y6700 Series
Output Current at OCP1
IOUT(OCP) （A）
In order to suppress this variability, this IC has the
overcurrent input compensation function.
Without input
compensation
With optimal input
compensation
IOUT
Target output current
With excessive
input compensation
85V
265V
AC input voltage （V）
When VDZBD < VFW1 (Point B through Point D), the
input voltage is increased and VFW1 exceeds the Zener
voltage, VZ, of DZBD. VFW2 will be produced as a
negative voltage to compensate VOCP(H).
The value of VFW2 should be adjusted so that the
difference between IOUT and IOUT(OCP) is minimized as
shown in Figure 9-25 “With optimal input compensation”. If the excessive input compensation, IOUT(OCP)
may become less than IOUT (Figure 9-25 “With excessive
input compensation”). Thus, value of VFW2 must be
adjusted so that IOUT(OCP) remains more than IOUT, across
the input voltage range.
VAC
230
Figure 9-25 OCP1 input compensation
Figure 9-26 shows the OCP1 input compensation
circuit. The value of input compensation is set by BD
pin peripheral circuit.
By OCP1 Input Compensation Function, Overcurrent
Detection 1 Threshold Voltage in Normal Operation,
VOCP(H) = 0.910 V, is compensated depending on an AC
input voltage.
The forward voltage of auxiliary winding D, VFW1, is
proportional to AC input voltage. As shown in Figure
9-26, the voltage obtained by subtracting zener voltage,
VZ, of DZBD from VFW1 is biased by either end of RBD1
and RBD2, and thus the BD pin voltage is provided the
voltage on RDB2 divided by the divider of RBD1 and RBD2.
100
0
Auxiliary
winding
voltage
VREV1
0
VFW1
VDZBD
0
VZ
VFW2
0
A
B
C
D
At the input voltage where VFW1 reaches VZ
or more, VFW2 goes negative.
Flyback voltage, VREV1
D2
R2
T1
Figure 9-27 Each voltage waveform for the input voltage
in normal quasi-resonant operation
C3
3
VCC
D
DZBD
Forward voltage
VDZBD V
FW1
RBD1
BD
S/OCP GND
2
4
ROCP
6
CBD
RBD2
1) VIN(AC)C Setup
VIN(AC)C is the AC input voltage that starts input
compensation. In general specification, VIN(AC)C is
set 120 VAC to 170 VAC.
2) VZ Setup
VIN(AC)C is adjusted by the zener voltage, VZ, of
DZBD. The VFW1 at VIN(AC)C is calculated by using
Equation (5). VZ is set from the result.
VFW2
Figure 9-26 OCP input compensation circuit
Figure 9-27 shows the each voltage waveform for the
input voltage in normal quasi-resonant operation.
When VDZBD ≥ VFW1 (Point A), No input
compensation required, VFW2 remains zero, and the
detection voltage for an overcurrent event is the
Overcurrent 1 Detection Threshold Voltage in Normal
Operation, VOCP(H).
STR-Y6700 - DS Rev.4.0
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Setup of BD pin peripheral components (DZBD, RBD1
and RBD2) is as follows:
VFW1 
ND
 VIN( AC ) C  2  VZ
NP
(5)
where,
NP: Primary side number of turns
ND: Secondary side number of turns
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3) RBD1 and RBD2 Setup.
The recommended value of RBD2 is 1.0 kΩ.
In general specification, RBD1 is set by using result of
Equation (6) so that VFW2 = −3.0 V at maximum AC
input voltage.
R BD1
VREV2 
R
 BD 2
VFW 2
N
  D  VIN( AC ) MAX  2  VZ  VFW 2
 NP
(6)



where,
VFW2: BD pin voltage (−3.0 V)
NP: Primary side winding number of turns
ND: Auxiliary winding number of turns
VIN(AC)MAX: Maximum AC input voltage
VZ: Zener voltage of DZBD

R BD 2
  VFW1  VZ 
R BD1  R BD 2
R BD 2
R BD1  R BD 2
N

  D  VIN( AC ) MAX  2  VZ 
 N

 P

(7)
VOCP(H)
VOCP(H)' (V)
0.8
0.6
Max.
where,
VREV1: Flyback voltage of auxiliary wining
VF: Forward voltage drop of DZBD
< BD Pin Peripheral Components Value Selection
Reference Example >
Setting value:
Input voltage: VIN(AC) = 85VAC to 265VAC,
AC input voltage that starts input compensation:
VIN(AC)C = 120 VAC,
Primary side winding number of turns: NP = 40 T,
Auxiliary winding number of turns: ND = 5 T
Forward voltage of auxiliary winding: VFW1 = 20 V
VFW1 is calculated by using Equation (5) as follows:
VFW1 
ND
 VIN( AC ) C  2
NP

5
120 2  21.2V
40
R BD1 
Typ.
0.4
Min.
0.2
00
−1
-1
−2
-2
−3
-3
(8)
Thus, zener voltage of DZBD is chosen to be 22 V of
the E series.
When VFW2 = −3.0 V at maximum input voltage,
265VAC, RBD1 is calculated by using Equation (6) as
follows:
1
0
R BD 2
 VREV1  VF  ≥ 0.34 V
R BD1  R BD 2
6) The BD pin voltage, which includes surge voltage,
must be observed within the absolute maximum
rating of the BD pin voltage (–6.0 to 6.0 V) in the
actual operation at the maximum input voltage.
4) VOCP(H)' is the overcurrent threshold voltage after
input compensation. Figure 9-28 shows a
relationship of VOCP(H)' and BD pin voltage,VFW2.
VFW2 at maximum AC input voltage is calculated by
using Equation (7). VOCP(H)' and this variation are
gotten by using the result from Figure 9-28.
When VOCP(H)' including variation becomes the
Bottom-Skip Operation Threshold Voltage 1,
VOCP(BS1) = 0.572 V, or less, the operation of IC is
one bottom-skip only and the output current may be
less than target output current, IOUT.
VFW 2 
5) VREV2 is calculated by using Equation (8) and is
checked to be the Quasi-Resonant Operation
Threshold Voltage 1, VBD(TH1) = 0.34 V (max.), or
more (refer to Figure 9-11).
−4
-4
−5
-5
−6
-6

R BD2  N D

 VIN( AC ) MAX  2－VZ  VFW 2
VFW 2  N P



1k  5

   265 2  22   3   7.28kΩ
 3  40

Thus, RBD1 is chosen to be 7.5 kΩ of the E series.
BD pin voltage VFW2 (V)
Figure 9-28 Overcurrent threshold voltage after input
compensation, VOCP(H)'
(reference for design target values)
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STR-Y6700 Series
When RBD2 = 1.0 kΩ, |VFW2| value at 265 VAC is
calculated by using Equation (7) as follows:
VFW 2 
R BD 2
  VFW1  VZ 
R BD1  R BD 2

1k
 5

   265 2  22   2.92V
7.5k  1k  40

Referring to Figure 9-28, when VFW2 is compensated
to –2.92 V, the overcurrent threshold voltage after input
compensation, VOCP(H)', is set to about 0.66 V (typ).
When setting RBD2 = 1.0 kΩ, RBD1 = 7.5 kΩ,
VF = 0.7 V, and VREV1 = 20 V, VREV2 is calculated by
using Equation (8) as follows:
VREV2 
R BD 2
 VREV1  VF 
R BD1  R BD 2

When the peak drain current of ID is limited by
Overcurrent Protection 1 operation, the output voltage,
VOUT, decreases and the feedback current from the
secondary photo-coupler becomes zero. Thus, the
feedback current, IFB, charges C4 connected to the
FB/OLP pin and the FB/OLP pin voltage, VFB/OLP,
increases.
When VFB/OLP increases to the FB Pin Maximum
Voltage in Feedback Operation, VFB(MAX) = 4.05 V, or
more, C4 is charged by IFB(OLP) = − 10 µA. When VFB/OLP
increases to the OLP Threshold Voltage, VFB(OLP) = 5.96
V, the OLP function is activated, the IC stops switching
operation in the latched state. In order to keep the
latched state, when VCC pin voltage decreases to
VCC(BIAS), the bias assist function is activated and VCC
pin voltage is kept to over the VCC(OFF).
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below VCC(OFF).
GND
1k
 20  0.7   2.27V
1k  7.5k
4
R3
C4
9.11.4 When Overcurrent Input
Compensation is Not Required
When the input voltage is narrow range, or provided
from PFC circuit, the variation of the input voltage is
small. Thus, the variation of OCP point may become
less than that of the universal input voltage specification.
When overcurrent input compensation is not required,
the input compensation function can be disabled by
substituting a high-speed diode for the zener diode,
DZBD, and by keeping BD pin voltage from being minus
voltage. In addition, Equation (9) shows the reverse
voltage of a high-speed diode. The peak reverse voltage
of high-speed diode selection should take account of its
derating.
ND
 VIN( AC ) MAX  2
NP
(9)
where,
VFW1: Forward voltage of auxiliary wining
NP: Primary side number of turns
ND: Secondary side number of turns
VIN(AC)MAX: Maximum AC input voltage
9.12 Overload Protection (OLP)
Figure 9-29 shows the FB/OLP pin peripheral circuit,
Figure 9-29 shows each waveform for Overload
Protection (OLP) operation.
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IFB
VREV2 is VBD(TH1) = 0.34 V (max.) or more.
VFW1 
FB/OLP
C5
PC1
Figure 9-29 FB/OLP pin peripheral circuit
VCC pin voltage
VCC(BIAS)
VCC(OFF)
FB/OLP pin
voltage, VFB/OLP
VFB(OLP)
VFB(MAX)
Drain current, ID
AC input voltage off
Latch release
Charged by IFB(OLP)
tDLY
Figure 9-30 OLP operation waveforms
The time of the FB/OLP pin voltage from VFB(MAX) to
VFB(OLP) is defined as the OLP delay time, tDLY. Because
the capacitor C5 for phase compensation is small
compared to C4, the approximate value of tDLY is
calculated by Equation (10). When C4 = 4.7 μF, the
value of tDLY would be approximately 0.9 s. The
recommended value of R3 is 47 kΩ.
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STR-Y6700 Series
t DLY
V
≒
FB ( OLP )
9.13 Overvoltage Protection (OVP)

 VFB ( MAX )  C4
I FB ( OLP)
t DLY ≒
5.96V  4.05V  C4
(10)
 10
To enable the overload protection function to initiate
an automatic restart, 220 kΩ is connected between the
FB/OLP pin and ground, as a bypass path for I FB(OLP), as
shown in Figure 9-31. Thus, the FB/OLP pin is kept
under VFB(OLP) in OLP state.
In OLP state as an output shorted, the output voltage
and VCC pin voltage decrease. During the operation,
Bias Assist Function is disabled. Thus, VCC pin voltage
decreases to VCC(OFF), the control circuit stops operation.
After that, the IC reverts to the initial state by UVLO
circuit, and the IC starts operation when VCC pin
voltage increases to VCC(ON) by startup current. Thus the
intermittent operation by UVLO is repeated in OLP state
without latched operation as shown in Figure 9-32.
The intermittent oscillation is determined by the cycle
of the charge and discharge of the capacitor C3
connected to the VCC pin. In this case, the charge time
is determined by the startup current from the startup
circuit, while the discharge time is determined by the
current supply to the internal circuits of the IC.
When a voltage between VCC pin and GND pin
increases to VCC(OVP) = 31.5 V or more, Overvoltage
Protection (OVP) is activated, the IC stops switching
operation at the latched state. In order to keep the
latched state, when VCC pin voltage decreases to
VCC(BIAS), the bias assist function is activated and VCC
pin voltage is kept to over the VCC(OFF).
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below VCC(OFF).
When the VCC pin voltage is provided by using
auxiliary winding of transformer, the overvoltage
conditions such as output voltage detection circuit open
can be detected because the VCC pin voltage is
proportional to output voltage. The approximate value of
output voltage VOUT(OVP) in OVP condition is calculated
by using Equation (11).
VOUT(OVP) 
VOUT ( NORMAL )
VCC( NORMAL )
 31.5 (V)
(11)
where,
VOUT(NORMAL): Output voltage in normal operation
VCC(NORMAL): VCC pin voltage in normal operation
9.14 Thermal Shutdown (TSD)
GND
FB/OLP
4
5
IFB
PC1
C5
220kΩ
When the temperature of control circuit increases to
Tj(TSD) = 135 °C (min.) or more, Thermal Shutdown
(TSD) is activated, the IC stops switching operation at
the latched state. In order to keep the latched state, when
VCC pin voltage decreases to VCC(BIAS), the bias assist
function is activated and VCC pin voltage is kept to over
the VCC(OFF).
Figure 9-31 FB/OLP pin peripheral circuit
(without latched operation)
VCC pin
voltage
VCC(ON)
VCC(OFF)
FB/OLP pin
voltage
VFB(OLP)
Drain current,
ID
Figure 9-32 OLP operation waveform at output shorted
(without latched operation)
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STR-Y6700 Series
transformer matching what will be used in the actual
application, because the variation of the auxiliary
winding voltage is affected by the transformer
structural design.
10. Design Notes
10.1 External Components
Take care to use properly rated, including derating as
necessary and proper type of components.
CRD clamp snubber
BR1
VCC pin voltage
Without R2
T1
VAC
R1 P
C2
C1
With R2
D1
U1
D2
R2
Output current, IOUT
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
C3
D
DZBD
Figure 10-2 Variation of VCC pin voltage and power
2 3 4 5 6 7
1
CV
RBD1
C(RC) damper
snubber
R3
CBD
ROCP
C4
C5
RBD2
PC1
Figure 10-1 The IC peripheral circuit
 FB/OLP Pin Peripheral Circuit
C5 is for high frequency noise reduction and phase
compensation, and should be connected close to these
pins. The value of C5 is recommended to be about
470 pF to 0.01µF, and should be selected based on
actual operation in the application.
C4 is for the OLP delay time, tDLY, setting (refer to
Section 9.12).
The recommended value of R3 is 47 kΩ.
 Input and Output Electrolytic Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
 S/OCP Pin Peripheral Circuit
In Figure 10-1, ROCP is the resistor for the current
detection. A high frequency switching current flows
to ROCP, and may cause poor operation if a high
inductance resistor is used. Choose a low inductance
and high surge-tolerant type.
 VCC Pin Peripheral Circuit
The value of C3 in Figure 10-1 is generally
recommended to be 10µ to 47μF (refer to Section 9.1
Startup Operation”, because the startup time is
determined by the value of C3).
In actual power supply circuits, there are cases in
which the VCC pin voltage fluctuates in proportion to
the output current, IOUT (see Figure 10-2), and the
Overvoltage Protection function (OVP) on the VCC
pin may be activated. This happens because C3 is
charged to a peak voltage on the auxiliary winding D,
which is caused by the transient surge voltage coupled
from the primary winding when the power MOSFET
turns off.
For alleviating C3 peak charging, it is effective to add
some value R2, of several tenths of ohms to several
ohms, in series with D2 (see Figure 10-1). The
optimal value of R2 should be determined using a
STR-Y6700 - DS Rev.4.0
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 BD Pin Peripheral Circuit
Since BD pin detects the signal of bottom-on
timing and input compensation of OCP1, the values
of BD pin peripheral components (DZBD, RBD1, RBD2
and CBD) are considered about both functions and
should be adjusted.
Refer to Section 9.7.2 and Section 9.11.3.
 NF Pin
For stable operation, NF pin should be connected to
GND pin, using the shortest possible path.
 Snubber Circuit
When the surge voltage of VDS is large, the circuit
should be added as follows (see Figure 10-1);
・ A clamp snubber circuit of a capacitor-resistordiode (CRD) combination should be added on the
primary winding P.
・ A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be
added between the D/ST pin and the S/OCP pin.
When the damper snubber circuit is added, this
components should be connected near D/ST pin
and S/OCP pin.
 Peripheral circuit of secondary side shunt regulator
Figure 10-3 shows the secondary side detection circuit
with the standard shunt regulator IC (U51).
C52 and R53 are for phase compensation. The value
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STR-Y6700 Series
VOUT
(+)
D51
PC1
R55
C51
S
R54
R51
R52
C53
C52 R53
U51
R56
(-)
Figure 10-3 Peripheral circuit of secondary side shunt
regulator (U51)
 Transformer
Apply proper design margin to core temperature rise
by core loss and copper loss.
Because the switching currents contain high
frequency currents, the skin effect may become a
consideration.
Choose a suitable wire gauge in consideration of the
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
necessary, the following should be considered to
increase the total surface area of the wiring:
▫ Increase the number of wires in parallel.
▫ Use litz wires.
▫ Thicken the wire gauge.
In the following cases, the surge of VCC pin
voltage becomes high.
▫ The surge voltage of primary main winding, P, is
high (low output voltage and high output current
power supply designs)
▫ The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.
In the case of multi-output power supply, the
coupling of the secondary-side stabilized output
winding, S1, and the others (S2, S3…) should be
maximized to improve the line-regulation of those
outputs.
Figure 10-4 shows the winding structural examples
of two outputs.
Winding structural example (a):
S1 is sandwiched between P1 and P2 to
maximize the coupling of them for surge
reduction of P1 and P2.
D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of
D.
Winding structural example (b)
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2.
This structure reduces the surge of D, and
improves the line-regulation of outputs.
Margin tape
Bobbin
L51
T1
▫ The coupling of the winding D and the winding P
should be minimized.
P1 S1 P2 S2 D
Margin tape
Winding structural example (a)
Margin tape
Bobbin
of C52 and R53 are recommended to be around 0.047
μF to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively.
They should be selected based on actual operation in
the application.
P1 S1 D S2 S1 P2
Margin tape
Winding structural example (b)
Figure 10-4 Winding structural examples
When the surge voltage of winding D is high, the
VCC pin voltage increases and the Overvoltage
Protection function (OVP) may be activated. In
transformer design, the following should be
considered;
▫ The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
▫ The coupling of the winding D and the winding S
should be maximized.
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STR-Y6700 Series
10.2 Transformer Design
The design of the transformer is fundamentally the
same as the power transformer of a Ringing Choke
Converter (RCC) system: a self-excitation type flyback
converter. However, because the duty cycle will change
due to the quasi-resonant operations delaying the turn-on,
the duty cycle needs to be compensated.
Figure 10-5 shows the quasi-resonant circuit.
Each parameter, such as the peak drain current, I DP, is
calculated by the following formulas:
VF
T1
VFLY
C1 ID
where,
VIN(MIN) : C1 voltage at the minimum AC input voltage
DON: On-duty at the minimum input voltage
PO: maximum output power
fMIN: minimum operation frequency
η1: transformer efficiency
CV: the voltage resonance capacitor connected
between the drain and source of the power MOSFET
D51
LP
P
IOFF
S
VO
VIN
NP
NS
CV
U1
t ONDLY  π L P 'C V
(15)
DON '  DON 1  f MIN  t ONDLY 
(16)
C51
I IN 
PO
1

η2 VIN(MIN)
I DP 
Figure 10-5 Quasi-resonant circuit
The flyback voltage, VFLY is calculated as follows:
VFLY
NP 
N
 P  VO  VF 
NS
NS 
The on duty, DON, at the minimum AC input voltage
is calculated as follows:
VFLY
VIN( MIN )  VFLY
(13)
where,
VIN(MIN): C1 voltage at the minimum AC input voltage
VFLY: Flyback voltage.
The inductance, LP' on the primary side, taking into
consideration the delay time, is calculated using
Equation (14).
LP ' 
V
IN ( MIN )
 D ON

2
 2PO  f MIN


 VIN( MIN )  D ON  f MIN  π C V 


η1


STR-Y6700 - DS Rev.4.0
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2  I IN
D ON '
(18)
LP '
Al‐value
(19)
(12)
where,
NP: Primary side number of turns
NS: Secondary side number of turns
VO: Output voltage
VF: Forward voltage drop of D51
D ON 
(17)
2
(14)
N P  VO  VF 
VFLY
(20)
where,
tONDLY: Delay time of quasi-resonant operation
IIN: Average input current
η2: conversion efficiency of the power supply
IDP: peak drain current
DON’: On-duty after compensation
VO: Secondary side output voltage
The minimum operation frequency, fMIN, can be
calculated by the Equation (22):

f MIN

2PO
2PO 4π VIN ( MIN )  D ON

 η  η 
LP'
1
1


2π C V  VIN ( MIN )  D ON




2
C V 






2
(21)
Figure 10-6 shows the Example of NI-Limit versus
AL-Value characteristics.
Choose the ferrite core that does not saturate and
provides a design margin in consideration of
temperature effects and other variations to NI-Limit
versus AL-Value characteristics.
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STR-Y6700 Series
Al-value is calculated by using LP’ and NP. NI is
calculated by using Equation (22).
It is recommended that Al-value and NI provide the
design margin of 30 % or more for saturation curve of
core.
NI  N P  I DP (AT)
(22)
where,
NP: Primary side number of turns
IDP: Peak switching current
Saturation curve
NI-limit (AT)
Margin : about 30%
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point grounding of point A in Figure 10-7 as close
to the ROCP pin as possible.
(3) VCC Trace Layout
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C3 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
1.0 μF) close to the VCC pin and the GND pin is
recommended.
(4) ROCP Trace Layout
ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure 10-7)
which is close to the base of ROCP.
NI
LP’/NP2
Al-value (nH/T2)
Figure 10-6 Example of NI-Limit versus AL-Value
characteristics
10.3 PCB Trace Layout and Component
Placement
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide trace.
In addition, the ground traces affect radiated EMI noise,
and wide, short traces should be taken into account.
Figure 10-7 shows the circuit design example.
(1) Main Circuit Trace Layout
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible.
If C1 and the IC are distant from each other, placing
a capacitor such as film capacitor (about 0.1 μF and
with proper voltage rating) close to the transformer
or the IC is recommended to reduce impedance of
the high frequency current loop.
STR-Y6700 - DS Rev.4.0
Oct. 07, 2014
(5) Peripheral components of the IC
The components for control connected to the IC
should be placed as close as possible to the IC, and
should be connected as short as possible to the each
pin.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout:
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the D/ST pin
trace act as a heatsink, its traces should be as wide as
possible.
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STR-Y6700 Series
(1) Main trace should be wide
trace and small loop
(6) Main trace of secondary side should
be wide trace and small loop
T1
C2
D51
R1
P
C1
D1
C51
D2
U1
R2
(3) Loop of the power
supply should be small
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
C3
2 3 4 5 6 7
1
S
D
DZBD
CV
ROCP
RBD1
R3
C5
PC1
CBD
RBD2
C4
A
(7)Trace of D/ST pin
should be wide for
heat release
(4)ROCP should be as
close to S/OCP
pin as possible.
(2) Control GND trace should be
connected at a single point as
close to the ROCP as possible
CY
(5)The components connected to the IC should
be as close to the IC as possible, and should
be connected as short as possible
Figure 10-7 Peripheral circuit example around the IC
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STR-Y6700 Series
11. Pattern Layout Example
The following show the four outputs PCB pattern layout example and the schematic of circuit using STR-Y6700
series. The PCB pattern layout example is made usable to other ICs in common. The parts in Figure 11-2 are only used.
Figure 11-1 PCB circuit trace layout example
CN1
CN52
1 OUT1(+)
D50
T1
S1
C53
C50
C58
TH2
2
RC1
J2
C4
OUT1(-)
OUT2(+)
D6
TK1
P1
8
OUT2(-)
J54
C51
C12 R7 R8
C6
C2
TH1
F1
L51
J53
C1
1
2
3
D51
C3
L1
R57
R50
S2
R52
C54
R51
R9
PC1
R53
R58
R55
J56
F2
C59
R56
R54 C62
J55
R59
D55
4 OUT3(+)
D2
D52
D3
S3
IC1
D5
Q1
R5
C8
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
D10
L50
S4 C52
2
PC1
C9
C10
OUT4(-)
9 OUT5(+)
D53
S5
C7
C63
D7
R11
R2
7 OUT4(+)
C57 C65
R3
OUT3(-)
J50 J51 J52
R6 C11
C5
R1
C60
D54
D
D4
2 3 4 5 6 7
1
C64
5
D1 R4
STR-Y6700
C55
R10
C56
C61
J57
R12
6
C13
OUT5(-)
TK50
Figure 11-2 Circuit schematic for PCB circuit trace layout
STR-Y6700 - DS Rev.4.0
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STR-Y6700 Series
12. Reference Design of Power Supply
 Power supply specification
IC
Input voltage
Maximum output power
Output 1
Output 2
STR-Y6754
85 VAC to 265 VAC
40.4 W
14 V / 2.6A
8 V / 0.5 A
 Circuit schematic
D1
D2
D4
D3
T1
S2 S4
L1
C1
C3
C2
R1
D51
OUT1(+)
14V/2.6A
C53
C51
P1
F1
D52
OUT2(+)
D5
R51
C52
P2
PC1
U1
D6
R3
R55
R53 C55
U51
D/ST
2
S/OCP
VCC
GND
FB/OLP
BD
NF
C5
R56
OUT(-)
S1
2 3 4 5 6 7
1
R52
8V/0.5A
C54
D
STR-Y6700
R54
S3
DZ1
R5
C4
PC1
R4
R2
C6
R6
C8
C7
C9
 Bill of materials
Recommended
Sanken Parts
Part type
Ratings(1)
Film, X2
Electrolytic
Ceramic
Ceramic
Electrolytic
Ceramic
Ceramic
Ceramic
Ceramic, Y1
Ceramic
Ceramic
Electrolytic
Electrolytic
Ceramic
General
General
General
0.1 μF, 275 V
220 μF, 400 V
2200 pF, 630 V
100 pF, 2 kV
22 μF, 50V
4.7 μF, 16 V
4700 pF, 50V
470 pF, 50V
2200 pF, 250 V
2200 pF, 1 kV
Open
1000 μF, 50 V
470 µF, 16 V
0.1 µF
600V, 1A
600V, 1A
600V, 1A
EM01A
EM01A
EM01A
D4
General
600V, 1A
EM01A
T1
Transformer
D5
Fast recovery
1000 V, 0.5 A
EG01C
U1
IC
D6
Fast recovery
200 V, 1 A
AL01Z
U51
Shunt regulator
Symbol
C1
C2
C3
C4
C5
C6
C7
C8
C9
C51
C52
C53
C54
C55
D1
D2
D3
(2)
(2)
(2)
Symbol
D52
DZ1
F1
L1
PC1
R1
R2
R3
R4
R5
R6
R51
R52
R53
R54
R55
R56
(2)
(3)
(2)
(2)
(2)
(2)
(2)
Part type
Schottky
Zener
Fuse
CM inductor
Photo-coupler
Metal oxide
General
General
General
General
General
General
General
General
General
General, 1%
General, 1%
Ratings(1)
90 V, 1.5 A
22V
250 VAC, 3 A
3.3 mH
PC123or equiv
150 kΩ, 1 W
0.56 Ω, 1 W
15 Ω
47 kΩ
6.8 kΩ
1 kΩ
820 Ω
1.5 kΩ
22 kΩ
6.8 kΩ
39 kΩ
10 kΩ
See
the specification
－
VREF = 2.5 V
TL431or equiv
Recommended
Sanken Parts
EK 19
STR-Y6754
D51
Schottky
150 V, 10 A
FMEN-210B
Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2)
It is necessary to be adjusted based on actual operation in the application.
(3)
Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use
combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.
(1)
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STR-Y6700 Series
 Transformer specification
▫ Primary inductance, LP: 0.95 mH
▫ Core size: EER28L
▫ AL-value: 183 nH/N2 (Center gap of about 0.8 mm)
▫ Winding specification
Number of
Winding
Symbol
turns (T)
Wire diameter
Primary winding 1
P1
43
1EUW – φ 0.30
Primary winding 2
P2
29
1EUW – φ 0.30
Auxiliary winding
D
12
TEX – φ 0.23 × 2
Output winding 1
S1
5
φ 0.32 × 2
Output winding 2
S2
3
φ 0.32 × 2
Output winding 3
S3
5
φ 0.32 × 2
Output winding 4
S4
3
φ 0.32 × 2
VDC
P1
P2
P1
S4
S3
D
S2
D/ST
VCC
S1
P2
D
Construction
(mm)
S4
Two-layer,
solenoid winding
Single-layer,
solenoid winding
Single-layer,
Space winding
Single-layer,
solenoid winding
Single-layer,
solenoid winding
Single-layer,
solenoid winding
Single-layer,
solenoid winding
OUT1(+)
14V
S2
S3
OUT2(+)
8V
GND
Bobbin
S1
Cross-section view
OUT(-)
: Start at this pin
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STR-Y6700 Series
OPERATING PRECAUTIONS
In the case that you use Sanken products or design your products by using Sanken products, the reliability largely
depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation
range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to
assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric
current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused
due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum
values must be taken into consideration. In addition, it should be noted that since power devices or IC’s including power
devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly.
Because reliability can be affected adversely by improper storage environments and handling methods, please
observe the following cautions.
Cautions for Storage
 Ensure that storage conditions comply with the standard temperature (5 to 35°C) and the standard relative humidity
(around 40 to 75%); avoid storage locations that experience extreme changes in temperature or humidity.
 Avoid locations where dust or harmful gases are present and avoid direct sunlight.
 Reinspect for rust on leads and solderability of the products that have been stored for a long time.
Cautions for Testing and Handling
When tests are carried out during inspection testing and other standard test periods, protect the products from power
surges from the testing device, shorts between the product pins, and wrong connections. Ensure all test parameters are
within the ratings specified by Sanken for the products.
Remarks About Using Thermal Silicone Grease
 When thermal silicone grease is used, it shall be applied evenly and thinly. If more silicone grease than required is
applied, it may produce excess stress.
 The thermal silicone grease that has been stored for a long period of time may cause cracks of the greases, and it
cause low radiation performance. In addition, the old grease may cause cracks in the resin mold when screwing the
products to a heatsink.
 Fully consider preventing foreign materials from entering into the thermal silicone grease. When foreign material
is immixed, radiation performance may be degraded or an insulation failure may occur due to a damaged insulating
plate.
 The thermal silicone greases that are recommended for the resin molded semiconductor should be used.
Our recommended thermal silicone grease is the following, and equivalent of these.
Type
Suppliers
G746
Shin-Etsu Chemical Co., Ltd.
YG6260 Momentive Performance Materials Japan LLC
SC102
Dow Corning Toray Co., Ltd.
Cautions for Mounting to a Heatsink
 When the flatness around the screw hole is insufficient, such as when mounting the products to a heatsink that has
an extruded (burred) screw hole, the products can be damaged, even with a lower than recommended screw torque.
For mounting the products, the mounting surface flatness should be 0.05mm or less.
 Please select suitable screws for the product shape. Do not use a flat-head machine screw because of the stress to
the products. Self-tapping screws are not recommended. When using self-tapping screws, the screw may enter the
hole diagonally, not vertically, depending on the conditions of hole before threading or the work situation. That
may stress the products and may cause failures.
 Recommended screw torque: 0.588 to 0.785 N･m (6 to 8 kgf･cm).
 For tightening screws, if a tightening tool (such as a driver) hits the products, the package may crack, and internal
stress fractures may occur, which shorten the lifetime of the electrical elements and can cause catastrophic failure.
Tightening with an air driver makes a substantial impact. In addition, a screw torque higher than the set torque can
be applied and the package may be damaged. Therefore, an electric driver is recommended.
When the package is tightened at two or more places, first pre-tighten with a lower torque at all places, then tighten
with the specified torque. When using a power driver, torque control is mandatory.
STR-Y6700 - DS Rev.4.0
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STR-Y6700 Series
Soldering
 When soldering the products, please be sure to minimize the working time, within the following limits:
• 260 ± 5 °C
10 ± 1 s (Flow, 2 times)
• 380 ± 10 °C 3.5 ± 0.5 s (Soldering iron, 1 time)
 Soldering should be at a distance of at least 2.0 mm from the body of the products.
Electrostatic Discharge
 When handling the products, the operator must be grounded. Grounded wrist straps worn should have at least 1MΩ
of resistance from the operator to ground to prevent shock hazard, and it should be placed near the operator.
 Workbenches where the products are handled should be grounded and be provided with conductive table and floor
mats.
 When using measuring equipment such as a curve tracer, the equipment should be grounded.
 When soldering the products, the head of soldering irons or the solder bath must be grounded in order to prevent
leak voltages generated by them from being applied to the products.
 The products should always be stored and transported in Sanken shipping containers or conductive containers, or
be wrapped in aluminum foil.
IMPORTANT NOTES
 The contents in this document are subject to changes, for improvement and other purposes, without notice. Make
sure that this is the latest revision of the document before use.
 Application examples, operation examples and recommended examples described in this document are quoted for
the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any
infringement of industrial property rights, intellectual property rights, life, body, property or any other rights of
Sanken or any third party which may result from its use.
 Unless otherwise agreed in writing by Sanken, Sanken makes no warranties of any kind, whether express or
implied, as to the products, including product merchantability, and fitness for a particular purpose and special
environment, and the information, including its accuracy, usefulness, and reliability, included in this document.
 Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and
defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at
their own risk, preventative measures including safety design of the equipment or systems against any possible
injury, death, fires or damages to the society due to device failure or malfunction.
 Sanken products listed in this document are designed and intended for the use as components in general purpose
electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring
equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation
equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various
safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment
or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products
herein.
The use of Sanken products without the written consent of Sanken in the applications where extremely high
reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly
prohibited.
 When using the products specified herein by either (i) combining other products or materials therewith or (ii)
physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that
may result from all such uses in advance and proceed therewith at your own responsibility.
 Anti radioactive ray design is not considered for the products listed herein.
 Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of
Sanken’s distribution network.
 The contents in this document must not be transcribed or copied without Sanken’s written consent.
STR-Y6700 - DS Rev.4.0
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