H CAT25C01/02/04/08/16 EE GEN FR ALO 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM LE FEATURES A D F R E ETM ■ 1,000,000 program/erase cycles ■ 10 MHz SPI compatible ■ 100 year data retention ■ 1.8 to 6.0 volt operation ■ Self-timed write cycle ■ Hardware and software protection ■ 8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP ■ Zero standby current ■ 16/32-byte page write buffer ■ Low power CMOS technology ■ Block write protection ■ SPI modes (0,0 & 1,1)* – Protect 1/4, 1/2 or all of EEPROM array ■ Commercial, industrial, automotive and extended temperature ranges DESCRIPTION input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C01/02/04/08/16 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/14-pin TSSOP packages. The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C01/02/04 features a 16-byte page write buffer. The 25C08/16 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock PIN CONFIGURATION TSSOP Package (U14, Y) CS SO NC NC 1 14 2 3 13 12 4 11 NC 5 10 WP VSS 6 9 7 8 VCC HOLD NC NC NC SCK SI SOIC Package (S, V) SO 1 2 8 7 WP VSS 3 4 6 5 CS VCC HOLD SCK SI DIP Package (P, L) CS SO WP VSS 1 2 3 4 8 7 6 5 8 7 6 5 CS SO WP VSS SCK SI 1 2 3 8 7 6 4 5 VCC HOLD SCK SI SENSE AMPS SHIFT REGISTERS VCC HOLD SCK SI WORD ADDRESS BUFFERS *CAT25C01/02 only PIN FUNCTIONS Function SO Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +6.0V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input NC No Connect SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC CONTROL LOGIC Pin Name XDEC COLUMN DECODERS E2PROM ARRAY DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATUS REGISTER *Other SPI modes available on request. © 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice VCC HOLD TSSOP Package (U, Y) BLOCK DIAGRAM MSOP Package (R, Z)* CS SO WP VSS 1 2 3 4 1 25C128 F02 Doc. No. 1016, Rev. I CAT25C01/02/04/08/16 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS(1) .................. –2.0V to +VCC +2.0V VCC with Respect to VSS ................................ –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Endurance Min. Max. Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current (Operating Write) 5 mA VCC = 5V @ 5MHz SO=open; CS=Vss ICC2 Power Supply Current (Operating Read) 3 mA VCC = 5.5V FCLK = 5MHz ISB Power Supply Current (Standby) 0 µA CS = VCC VIN = VSS or VCC ILI Input Leakage Current 2 µA ILO Output Leakage Current 3 µA VIL(5) Input Low Voltage -1 VCC x 0.3 V VIH(5) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage VCC - 0.8 V 0.2 VCC-0.2 VOUT = 0V to VCC, CS = 0V 2.7V≤VCC<5.5V IOL = 3.0mA IOH = -1.6mA V 1.8V≤VCC<2.7V V IOL = 150µA IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) VILMIN and VIHMAX are reference values only and are not tested. Doc. No. 1016, Rev. I 2 CAT25C01/02/04/08/16 PIN CAPACITANCE (1) Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted). Symbol Test Conditions Max. Units Conditions COUT Output Capacitance (SO) 8 pF VOUT=0V CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN=0V A.C. CHARACTERISTICS Limits 1.8V-6.0V SYMBOL PARAMETER Min. 2.5V-6.0V Max. Min. Max. 4.5V-5.5V Min. Max. Test UNITS Conditions tSU Data Setup Time 50 20 20 ns VIH = 2.4V tH Data Hold Time 50 20 20 ns CL = 100pF tWH SCK High Time 250 75 40 ns VOL = 0.8V tWL SCK Low Time 250 75 40 ns VOH = 2.0v fSCK Clock Frequency DC tLZ HOLD to Output Low Z 50 Input Rise Time tFI(1) Input Fall Time tHD HOLD Setup Time 100 40 40 ns tCD HOLD Hold Time 100 40 40 ns CL = 100pF CL = 50pF tWC(3) Write Cycle Time 10 5 5 ms (2) tV Output Valid from Clock Low 250 75 40 ns tHO Output Hold Time tDIS Output Disable Time 250 75 75 ns tHZ HOLD to Output High Z 150 50 50 ns tCS CS High Time 500 100 100 ns tCSS CS Setup Time 500 100 100 ns tCSH CS Hold Time 500 100 100 ns tWPS WP Setup Time 150 50 50 ns tWPH WP Hold Time 150 50 50 ns tRI (1) 1 DC 10 MHz 50 50 ns 2 2 2 µs 2 2 2 µs 0 5 0 DC 0 ns NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL = 50pF (3) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. 3 Doc. No. 1016, Rev. I CAT25C01/02/04/08/16 FUNCTIONAL DESCRIPTION PIN DESCRIPTION The CAT25C01/02/04/08/16 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C01/02/04/08/16 to interface directly with many of today’s popular microcontrollers. The CAT25C01/02/04/08/16 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C01/02/04/08/16. Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C01/02/04/08/16. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1). After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller Figure 1. Sychronous Data Timing tCS VIH CS VIL tCSH tCSS VIH tWH SCK VIL tWL tH tSU VIH VALID IN SI VIL tRI tFI tV VOH SO tHO tDIS HI-Z HI-Z VOL Note: Dashed Line= mode (1, 1) – – – – – INSTRUCTION SET Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 X011(1) Read Data from Memory WRITE 0000 X010(1) Write Data to Memory Power-Up Timing(2)(3) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Note: (1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Doc. No. 1016, Rev. I 4 CAT25C01/02/04/08/16 04/08/16. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C01/02/04/08/16 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. and the 25C01/02/04/08/16. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1) . CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C01/ 02/04/08/16 and CS high disables the CAT25C01/02/ BYTE ADDRESS Device Address Significant Bits Address Don't Care Bits # Address Clock Pulse CAT25C01 A6 - A0 A7 8 CAT25C02 A7 - A0 — 8 CAT25C04 A7 - A0 (A8 = X bit from Opcode) — 8 CAT25C08 A9 - A0 A15 - A10 16 CAT25C16 A10 - A0 A15 - A11 16 STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN 0 1 X BP1 BP0 WEL RDY BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 25C01: 60-7F 25C02: C0-FF 25C04: 180-1FF 25C08: 0300-03FF 25C16: 0600-07FF Quarter Array Protection 1 0 25C01: 40-7F 25C02: 80-FF 25C04: 100-1FF 25C08: 0200-03FF 25C16: 0400-07FF Half Array Protection 1 1 25C01: 00-7F 25C02: 00-FF 25C04: 000-1FF 25C08: 0000-03FF 25C16: 0000-07FF Full Array Protection WRITE PROTECT ENABLE OPERATION WPEN 0 WP X WEL 0 Protected Blocks Protected Unprotected Blocks Protected Status Register Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable 5 Doc. No. 1016, Rev. I CAT25C01/02/04/08/16 WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C01/ 02/04/08/16 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch. When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. HOLD HOLD: Hold The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. HOLD is the HOLD pin. The HOLD pin is used to pause transmission to the CAT25C01/02/04/08/16 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. HOLD should be held high any time this function is not being used. HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register, (including the block protect Figure 2. WREN Instruction Timing CS SK 0 SI 0 0 0 1 0 1 0 HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) – – – – – Figure 3. WRDI Instruction Timing CS SK SI SO 0 0 0 0 0 0 HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) – – – – – Doc. No. 1016, Rev. I 1 6 0 CAT25C01/02/04/08/16 bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. ing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. DEVICE OPERATION Write Enable and Disable The CAT25C01/02/04/08/16 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when Vcc is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes(reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. WRITE Sequence The CAT25C01/02/04/08/16 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C01/02/04/08/16. The device goes into Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C01/02/04/08/16. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C01/02/04/08/16, followed by the 16-bit address for 25C08/16. (only 10-bit addresses are used for 25C08, 11-bit addresses are used for 25C16. The rest of the bits are don't care bits) and 8-bit address for 25C01/02/04 (for the 25C04, bit 3 of the read data instruction contains address A8). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continu- Figure 4. Read Instruction Timing CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 * 23 24 25 26 27 28 29 * 30 2 1 SK OPCODE SI 0 0 0 0 X* BYTE ADDRESS* 0 1 1 AN A0 DATA OUT SO HIGH IMPEDANCE 7 6 5 4 3 0 MSB *Please check the Byte Address Table. *X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04 Note: Dashed Line= mode (1, 1) – – – – 7 Doc. No. 1016, Rev. I CAT25C01/02/04/08/16 Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address for 25C08/16. (only 10-bit addresses are used for 25C08, 11-bit addresses are used for 25C16. The rest of the bits are don't care bits) and 8-bit address for 25C01/02/04 (for the 25C04, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. bility. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C01/02/04 and 32 bytes of data for 25C08/16. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant.The only restriction is that the X (X=16 for 25C01/02/04 and X=32 for 25C08/16) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C01/02/04/08/16 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. Page Write The CAT25C01/02/04/08/16 features page write capaFigure 5. RDSR Instruction Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK OPCODE 0 SI 0 0 0 0 DATA OUT HIGH IMPEDANCE SO 3 MSB Note: Dashed Line= mode (1, 1) – – – – – Figure 6. Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 * 23 24 25 26 27 28 29 30 * 31 SK BYTE ADDRESS* OPCODE SI 0 0 0 0 X* 0 1 0 AN A0 D7 HIGH IMPEDANCE SO *Please check the Byte Address Table X = 0 for CAT25C01, CAT25C02 and CAT25C08, CAT25C16; X = A8 for CAT25C04. Note: Dashed Line= mode (1, 1) – – – – – Doc. No. 1016, Rev. I 8 DATA IN D6 D5 D4 D3 D2 D1 D0 0 CAT25C01/02/04/08/16 DESIGN CONSIDERATIONS after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C01/02/04/08/16, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. The CAT25C01/02/04/08/16 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT25C01/02/04/08/ 16 goes into a write disable mode. CS must be set high Figure 7. WRSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 1 7 6 5 4 12 13 14 15 2 1 0 SCK OPCODE SI 0 0 0 0 DATA IN 0 0 0 3 MSB HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) – – – – – Figure 8. Page Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 SK SI 0 0 0 0 X* DATA IN BYTE ADDRESS* OPCODE 0 1 AN 0 A0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte N 0 7..1 HIGH IMPEDANCE SO *Please check the Byte Address Table. *X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04. Note: Dashed Line= mode (1, 1) – – – – – Figure 9. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ Note: Dashed Line= mode (1, 1) – – – – – 9 Doc. No. 1016, Rev. I CAT25C01/02/04/08/16 Figure 10. WP Timing tWPS tWPH CS tCSH SCK WP WP Note: Dashed Line= mode (1, 1) – – – – – ORDERING INFORMATION Prefix CAT Optional Company ID Device # 25C16 Product Number 25C16: 16K 25C08: 8K 25C04: 4K 25C02: 2K 25C01: 1K Suffix -1.8 I S Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) A = Automotive (-40°C to +105°C) E = Extended (-40°C to +125°C) Package P = 8-pin PDIP R = 8-pin MSOP2 S = 8-pin SOIC U = 8-pin TSSOP U14 = 14-pin TSSOP L = PDIP (Lead free, Halogen free) V = SOIC, JEDEC (Lead free, Halogen free) X = SOIC, EIAJ (Lead free, Halogen free) Y = TSSOP (Lead free, Halogen free) Z = MSOP2 (Lead free, Halogen free) TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V) Notes: (1) The device used in the above example is a 25C16SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) CAT25C01, CAT25C02 only Doc. No. 1016, Rev. I 10 CAT25C01/02/04/08/16 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ DPPs ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 11 1016 I 10/17/02 Final Doc. No. 1016, Rev. I