RENESAS HAF1008

HAF1008(L), HAF1008(S)
Silicon P Channel MOS FET Series Power Switching
REJ03G0027-0100Z
Rev.1.00
May.13.2003
Description
This FET has the over temperature shut–down capability sensing to the junction temperature. This FET has
the built–in over temperature shut–down circuit in the gate area. And this circuit operation to shut–down
the gate voltage in case of high junction temperature like applying over power consumption, over current
etc.
Features
•
•
•
•
Logic level operation (-4 to -6 V Gate drive)
High endurance capability against to the short circuit
Built–in the over temperature shut–down circuit
Latch type shut–down operation (Need 0 voltage recovery)
Outline
LDPAK
D
1
Gate resistor
G
Temperature
Sencing
Circuit
Latch
Circuit
1
Gate
Shutdown
Circuit
S
Rev.1.00, May.13.2003, page 1 of 11
2
3
2
3
1. Gate
2. Drain
(Flange)
3. Source
HAF1008(L), HAF1008(S)
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDSS
–60
V
Gate to source voltage
VGSS
–16
V
Gate to source voltage
VGSS
2.5
V
Drain current
ID
–20
A
–40
A
–20
A
Drain peak current
ID (pulse)
Note1
Body-drain diode reverse drain IDR
current
Channel dissipation
PchNote2
50
W
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
Typical Operation Characteristics
(Ta = 25°C)
Item
Symbol
Min
Typ
Max
Unit
Input voltage
VIH
–3.5
—
—
V
VIL
—
—
–1.2
V
IIH1
—
—
–100
µA
Vi = –8 V, VDS = 0
IIH2
—
—
–50
µA
Vi = –3.5 V, VDS = 0
IIL
—
—
–1
µA
Vi = –1.2 V, VDS = 0
Input current
(Gate shut down)
IIH(sd)1
—
–0.8
—
mA
Vi = –8 V, VDS = 0
IIH(sd)2
—
–0.35
—
mA
Vi = –3.5 V, VDS = 0
Shut down temperature
Tsd
—
175
—
°C
Channel temperature
Gate operation voltage
Vop
–3.5
—
–12
V
Input current
(Gate non shut down)
Rev.1.00, May.13.2003, page 2 of 11
Test Conditions
HAF1008(L), HAF1008(S)
Electrical Characteristics
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain current
ID1
–7
—
—
A
VGS = –3.5 V, VDS = –2 V
Drain current
ID2
—
—
–10
mA
VGS = –1.2 V, VDS = –2 V
Drain to source breakdown
voltage
V(BR)DSS –60
—
—
V
ID = –10 mA, VGS = 0
Gate to source breakdown
voltage
V(BR)GSS –16
—
—
V
IG = –800 µA, VDS = 0
Gate to source breakdown
voltage
V(BR)GSS 2.5
—
—
V
IG = 100 µA, VDS = 0
Gate to source leak current
IGSS1
—
—
–100
µA
VGS = –8 V, VDS = 0
IGSS2
—
—
–50
µA
VGS = –3.5 V, VDS = 0
IGSS3
—
—
–1
µA
VGS = –1.2 V, VDS = 0
IGSS4
—
—
100
µA
VGS = 2.4 V, VDS = 0
IGS(OP)1
—
–0.8
—
mA
VGS = –8 V, VDS = 0
IGS(OP)2
—
–0.35
—
mA
VGS = –3.5 V, VDS = 0
IDSS
—
—
–10
µA
VDS = –60 V, VGS = 0
Gate to source cutoff voltage VGS(off)
–1.1
—
–2.15
V
VDS = –10 V, ID = –1 mA
Forward transfer admittance
10
18.5
—
S
ID = –10 A, VDS = –10 V Note3
Static drain to source on state RDS(on)
resistance
RDS(on)
—
60
80
mΩ
ID = –10 A, VGS = –4 V Note3
—
42
54
mΩ
ID = –10 A, VGS = –10 V Note3
Output capacitance
Coss
—
865
―
pF
VDS = –10 V, VGS = 0, f = 1 MHz
Turn-on delay time
td(on)
—
5.7
―
µs
VGS = -10 V, ID= –10 A, RL = 3 Ω
Rise time
tr
—
26
—
µs
Turn-off delay time
td(off)
—
6.5
―
µs
Fall time
tf
—
9
—
µs
Body–drain diode forward
voltage
VDF
—
-0.9
—
V
IF = –20 A, VGS = 0
Body–drain diode reverse
recovery time
trr
—
100
—
ns
IF = –20 A, VGS = 0
diF/dt = 50A/µs
Over load shut down
Note4
operation time
tos1
—
1.84
—
ms
VGS = –5 V, VDD = –16 V
tos2
—
1
—
ms
VGS = –5 V, VDD = –24 V
Input current (shut down)
Zero gate voltage drain
current
|yfs|
Notes: 3. Pulse test
4. Include the time shift based on increasing of channel temperature when operate under over load
condition.
Rev.1.00, May.13.2003, page 3 of 11
HAF1008(L), HAF1008(S)
Main Characteristics
Power vs. Temperature Derating
-500
(A)
-200
Drain Current ID
60
40
20
50
100
Case Temperature
(A)
Drain Current ID
Op
er
-5
-2
PW
Operation
in this area
is limited by RDS(on)
at
ion
1
=
µs
m
s
10
m
s
c=
25
(T
°C
)
Ta = 25°C
-0.5
-1
-2
-5
-10 -20
-50 -100
Drain to Source Voltage VDS (V)
-20
Typical Transfer Characteristics
-8 V
-40
-6 V
-5 V
-30
-4 V
-20
VGS = -3.5 V
-10
-16
-12
-8
Tc = -25°C
-4
-2
-4
-6
-8
-10
Drain to Source Voltage VDS (V)
Rev.1.00, May.13.2003, page 4 of 11
25°C
75°C
V DS = -10 V
Pulse Test
Pulse Test
0
0
DC
-10
Tc (°C)
Typical Output Characteristics
-10 V
10
-20
-0.3
200
(A)
-50
150
Thermal shut down
operation area
-50
-0.5
0
Maximum Safe Operation Area
-100
-1
Drain Current ID
Channel Dissipation
Pch (W)
80
0
-1
-2
-3
-4
-5
Gate to Source Voltage VGS (V)
HAF1008(L), HAF1008(S)
Pulse Test
-0.8
-0.6
I D = -10 A
-0.4
-5 A
-0.2
0
-2
-4
-6
-8
Drain to Source On State Resistance
RDS(on) (mΩ)
Gate to Source Voltage
-10
Static Drain to Source on State Resistance
vs. Temperature
100
Pulse Test
I D = -10 A
-5 A
80
-10 A
V GS = -4 V
-5 A
60
40
-10 V
20
0
-25
0
25
50
75
100 125 150
Case Temperature
Rev.1.00, May.13.2003, page 5 of 11
200
Pulse Test
100
V GS = -4 V
50
-10 V
20
10
-0.1 -0.2
Tc (°C)
-0.5 -1
-2
-5
-10 -20
-50
Drain Current ID (A)
VGS (V)
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
-1
Static Drain to Source Sate Resistance
vs. Drain Current
Drain to Source On State Resistance
VDS(on) (mΩ)
Drain to Source Saturation Voltage
VDS(on) (V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
50
20
V DS = -10 V
Pulse Test
Tc = -25°C
10
25°C
5
75°C
2
1
0.5
-0.1 -0.2
-0.5 -1
-2
-5
-10 -20
Drain Current ID (A)
-50
HAF1008(L), HAF1008(S)
200
100
50
di / dt = 50 A / µs
V GS = 0, Ta = 25°C
20
Switching Characteristics
100
Switching Time t (µs)
Reverse Recovery Time trr (ns)
500
Body to Drain Diode Reverse
recovery Time
50
tr
20
tf
10
t d(off)
5
t d(on)
2
1
10
VGS = -10 V, VDD = -30 V
PW = 300 µs, duty < 1 %
0.5
-0.1 -0.2
-0.5 -1
-2
-5
Reverse Drain Current
-10 -20
-50
-0.1 -0.2
-2
Drain Current
Reverse Drain Current vs.
Source to Drain Voltage
-5
ID
-10 -20
-50
(A)
Typical capacitance vs.
Drain to Source Voltage
10000
-20
Pulse Test
-16
Capacitance C (pF)
Reverse Drain Current IDR (A)
-0.5 -1
IDR (A)
VGS = -5 V
-12
0V
-8
1000
-4
0
VGS = 0
f = 1 MHz
100
-0.4
-0.8
-1.2
Source to Drain Voltage
Rev.1.00, May.13.2003, page 6 of 11
-1.6
-2.0
VSD (V)
0
-10
-20
-30
-40
-50
Drain to Source Voltage VDS (V)
-60
HAF1008(L), HAF1008(S)
Gate to Source Voltage vs.
Shutdown Time of Load-Short Test
Shutdown Case Temperature vs.
Gate to Source Voltage
200
-15
-10
-16 V
V DD= -24 V
-5
0
100 µ
1m
10 m
Shutdown Case Temperature Tc (°C)
Gate to Source Voltage
VGS (V)
-20
180
160
140
120
I D = -5 A
100
0
-2
Shutdown Time of Load-Short Test
Pw (S)
-4
-6
Gate to Source Voltage
-8
-10
VGS (V)
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermal Impedance
γs (t)
3
0.5
0.3
0.2
0.1
2
0.0
.01
0
PDM
e
uls
p
ot
D=
PW
T
PW
h
1s
0.01
10 µ
θch - c(t) = γs (t) • θch - c
θch - c = 2.50°C/W, Tc = 25°C
0.05
0.1
0.03
Tc = 25°C
D=1
1
T
100 µ
1m
10 m
Pulse Width PW (S)
Rev.1.00, May.13.2003, page 7 of 11
100 m
1
10
HAF1008(L), HAF1008(S)
Switching Time Test Circuit
Switching Time Waveform
Vout
Monitor
Vin Monitor
Vin
10%
D.U.T.
RL
90%
Vin
-10 V
50Ω
V DD
= -30 V
Vout
td(on)
Rev.1.00, May.13.2003, page 8 of 11
90%
90%
10%
10%
tr
td(off)
tf
HAF1008(L), HAF1008(S)
Package Dimensions
As of January, 2003
4.44 ± 0.2
10.2 ± 0.3
1.3 ± 0.15
1.3 ± 0.2
1.37 ± 0.2
0.2
0.86 +– 0.1
0.76 ± 0.1
2.54 ± 0.5
2.54 ± 0.5
11.0 ± 0.5
8.6 ± 0.3
11.3 ± 0.5
0.3
10.0 +– 0.5
(1.4)
Unit: mm
2.49 ± 0.2
0.4 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.1.00, May.13.2003, page 9 of 11
LDPAK (L)
—
—
1.40 g
HAF1008(L), HAF1008(S)
As of January, 2003
Unit: mm
(1.5)
10.0
7.8
7.0
2.49 ± 0.2
0.2
0.1 +– 0.1
1.7
7.8
6.6
1.3 ± 0.15
+ 0.3
– 0.5
8.6 ± 0.3
(1.5)
(1.4)
4.44 ± 0.2
10.2 ± 0.3
2.2
1.37 ± 0.2
2.54 ± 0.5
0.2
0.86 +– 0.1
2.54 ± 0.5
0.4 ± 0.1
0.3
3.0 +– 0.5
1.3 ± 0.2
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.1.00, May.13.2003, page 10 of 11
LDPAK (S)-(1)
—
—
1.30 g
HAF1008(L), HAF1008(S)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.1.00, May.13.2003, page 11 of 11