February 2003
PNI-11096
3 – Axis Magneto-Inductive Sensor Driver and Controller with SPI Serial
Interface
Features
General Description
The PNI-11096 is a low cost magnetic measurement
Application Specific Integrated Circuit (ASIC)
designed for use with PNI Corp’s magneto-inductive
sensors. The PNI-11096 can control and measure
three independent magneto-inductive sensors.
Each sensor is individually selectable for
measurement, and can also be individually
configured for measurement resolution. The PNI11096 communicates through an SPI port,
effectively creating a 3 - axis magnetometer that can
be easily connected to most all microprocessors. In
addition, the PNI-11096 has diagnostic modes and
outputs to test the oscillator and counter circuits.
o
measurement system on a single chip
The PNI-11096 contains the entire measurement
circuit—both analog and digital sections.
The
sensors change inductance with an applied change
in magnetic field parallel to the sensor. In order to
make a measurement, the sensor is switched into an
LR oscillator circuit.
The bipolar differential
measurement scheme used by the PNI-11096
makes the magnetic measurement inherently
temperature independent. It also has the benefit of
transforming the measurement range into a zero
centered, positive/negative value.
VSTBY
SCLK
MISO
MOSI
SSNOT
N/C
AVDD
AVSS
+ZDRV
+ZIN
-ZIN
-ZDRV
+YDRV
+YIN
PNI 11096
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REXT
DHST
DRDY
RESET
COMP
N/C
DVSS
-XDRV
-XIN
+XIN
+XDRV
-YDRV
-YIN
DVDD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28 PIN SOIC
Complete 3-axis magnetic sensor
o
DIE form has ultra low magnetic signature
o
Low voltage Supply
o
Low supply current
1.5mA - conversion rate
<1uA - idle mode
o
Acquisition speeds up to 200samples/sec
o
96dB dynamic range
o
SPI port select for port multiplexing
Applications
•
Compassing
•
Magnetometer instruments
•
Magnetic object sensing
•
Magnetic ink sensing
28
1
26
26 PAD DIE
1
XXXXYZZ
11182
11096A
AAAA
28 PIN MLF
Pin Configuration
2001 PNI Corporation www.pnicorp.com
1
DOC 1000005 R07
Absolute Maximum Rating
Symbol
VDD
VIN
IIN
Tstrg
Parameter
DC Suppy Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
MIN
-0.3
-0.3
-10.0
-40
MAX
5.25
VDD+0.3
10.0
125
Units
V
V
MA
C
Notes
25C
Supply Operating Conditions
Symbol
VDD
IDD
IDD
IDD
ILkStby
VSS
Ta
Parameter
Digital DC Supply
On, RCOSC and LROSC Off
On, RCOSC On, LROSC Off
On, RCOSC and LROSC On
IDD @ VSTBY pin
Digital Ground
Ambient Temperature
MIN
2.2
0.0
-20
MAX
5.0
0.1
.5
1.5
100
0.0
70
Units
V
mA
mA
mA
nA
V
C
Notes
Nominal
Nominal
Nominal
(1)
(1) VSTBY = 5.5V, AVDD=DVDD=AVSS=DVSS=0Volts, Temp=27C
Electrical Specifications
Parametric Voltage and Current Levels: Testing for the below currents assumes a static test setup with
measurements performed while static data is applied to the device
Inputs
Test Type
Vil
(18)
Vih
(18)
V
AIB
IBA
IBT
Vol
V
2.0
0.8
0.8
Notes
(10)
Iih
(9)
Min Max
uA
uA
0.0 1.0
0.0 1.0
0.0 1.0
Analog Input
CMOS
CMOS, SC
Hsy = 1.0
(9) Iil and Iih are tested at VDD = 3.6 V. Not test at less than room temperature
(10) SC = Schmitt
(18) CMOS value are ‘Vin * VDD’
Outputs
Test Type
0.2
0.25
0.2
Iil
(9)
Min Max
uA
uA
0.0 -1.0
0.0 -1.0
0.0 -1.0
Voh
V
Iol
Ioh
Notes
(14) (14)
mA
mA
Min
Min
OB1
<0.4
>2.4
1.0
-1.0 VDD = 4.5-5.0 Volts
OB2
<.4V
>2.4
1.0
-1.0 VDD = 4.5-5.0 Volts
OB3
0.267 1.936 10.0 -10.0
VDD = 2.2 Volts
(14) Polarity on currents indicated direction of current (+) for sinking (-) for sourcing
I/O Pins
Test Type
Vil
(18)
V
Vih
(18)
V
Vol
(16)
V
Voh
(16)
V
Iol
(16)
mA
Ioh
(16)
uA
Ioz**
(17)
uA
Min
39
Ioz**
(17)
uA
Max
217
Notes
IO1A
.030 .070 0.40 4.1 -.640 .150
CMOS
(16) Vol, Voh, Iol Ioh are tested at Vdd = 4.8 Volts.
(17) Ioz is tested with VDD = 5.2 Volts.
(18) CMOS values are ‘Vin * VDD”
** Leakage on IO pins is typically checked for +/- 10uA with the output device turned off and no PU or PD
2001 PNI Corporation www.pnicorp.com
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DOC 1000005 R07
Pin Definition
Pin Number
28
26
28
SOIC
DIE
MLF
Pin
Name
Test
Type
Parameters
1
1
26
VSTBY
I/O
Type
(1)
DP
2
2
27
SCLK
DI
IBT
3
3
28
MISO
DO
OB2
4
4
1
MOSI
DI
IBA
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
5
IBA
AP
AP
DO
AI
AI
DO
DO
AI
DP
AI
DO
DO
AI
AI
DO
DP
VDD
VSS
OB3
AIB
AIB
OB3
OB3
AIB
VDD
AIB
OB3
OB3
AIB
AIB
OB3
VSS
22
SSNOT
N/C
AVDD
AVSS
+ZDRV
+ZIN
-ZIN
-ZDRV
+YDRV
+YIN
DVDD
-YIN
-YDRV
+XDRV
+XIN
-XIN
-XDRV
DVSS
N/C
COMP
DI
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
3
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DO
OB1
25
26
27
23
24
25
22
23
24
RESET
DRDY
DHST
DI
DO
DIO
IBA
OB1
IO1A
28
26
25
REXT
AI
AIB
Description
VDD
Input protection clamp diode
common
Serial Clock input for SPI port
Serial data output (Master In Slave
Out)
Serial data input (Master Out Slave
In)
Active low Chip select for SPI port
NOT CONNECTED
Supply Voltage for analog section
Ground pin for Analog section
Z sensor drive output
Z sensor sense input
Z sensor sense input
Z sensor drive output
Y sensor drive output
Y sensor sense input
Supply Voltage for digital section
Y sensor sense input
Y sensor drive output
X sensor drive output
X sensor sense input
X sensor sense input
X sensor drive output
Ground pin for digital section
NOT CONNECTED
Comparator output
Reset Input
Data Ready
High speed oscillator output
(Output is ½ clock speed)
External timing resistor for high
speed clock
Notes
Connect to
VDD
1Mhz Max
(Rext=100K)
Used for
diagnostics
Used for
diagnostics
100K Ohm
Typical
(1) I/O types: D = Digital, A = Analog, I = Input, O = Output, IO = Bidirectional, P = Power pad
2001 PNI Corporation www.pnicorp.com
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DOC 1000005 R07
Operation
Figure 1 illustrates the change between these two
measurements. The actual magnetic measurement
is the difference between these two measurements.
This measurement scheme is used to make the
magnetic measurement temperature independent. It
also has the benefit of transforming the
measurement range into a zero centered,
positive/negative value.
The PNI-11096 returns the data to the host
microprocessor over the SPI interface.
The
microprocessor simply asks the PNI-11096 for data
from a specific axis, and the PNI-11096 does the
rest.
The PNI-11096 contains the entire measurement
circuitry necessary to use PNI Corp’s magnetoinductive sensors. The sensors change inductance
with a change in magnetic field parallel to the
sensor. To make a measurement, the sensor is
switched into an LR oscillator circuit. One side of
the sensor is grounded; the other side is alternately
charged and discharged through the oscillator circuit
("forward bias"). The PNI-11096 will measure the
amount of time it takes to make a certain number of
oscillations.
The PNI-11096 will then switch the
bias connections to the sensor, and make another
measurement.
The side that was previously
grounded is now charged and discharged; the other
side is now ground ("reverse bias").
Osc.
Osc.
"Forward Bias"
"Reverse Bias"
Figure 1. Forward Bias vs. Reverse Bias.
1. Connections
A typical connection configuration is
shown in Figure 2. The PNI-11096 can
control up to 3 sensors; if less are
needed, the unneeded pins should be
left to float.
Vstby pin must always be equal to or
higher than any voltage present on any
other pin on the PNI-11096. Vstby is
connected to the cathode end of a
diode array. The anode end of each
diode in the array is connected to each
of the digital interface signal pins.
Leaving Vstby floating or connected to
ground when other pins are potentially
active, as in a multiplexed SPI network,
will cause excessive current drain.
* Rb value sufficient for evaluation:
Vcc
Vcc
AVDD
DVDD
Vcc
From µP
Slave Clock
SCLK
VSTBY
Data to µP
MISO
APZDRV
Data from µP
MOSI
Slave Select
SSNOT
*Rb
APZIN
ANZDRV
Sensor
RESET
PNI
11096
RevA
RESET
*Rb
*Rb
APYDRV
APYIN
Y
ANYIN
ANYDRV
End of
Conversion
Z
ANZIN
DRDY
*Rb
*Rb
DHST
APXDRV
REXT
ANXIN
APXIN
X
ANXDRV
100K
COMP
*Rb
AVSS
DVSS
5VDC – 150 Ohm for SEN-L
56 Ohm for SEN-S
3VDC – 150 Ohm for SEN-L
33 Ohm for SEN-S
Figure 2 Typical Connection
2001 PNI Corporation www.pnicorp.com
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2.1.4 PS0, PS1, PS2 Period Select
These bits select the division ratio applied to the L/R
oscillator output to set the period being measured.
2. Magnetic Measurements
The magnetic sensor operates in an oscillator circuit
composed of the external sensors and external bias
resistors along with digital gates and a comparator
internal to the PNI-11096. Only one sensor can be
measured at a time. The user sends a command
byte to the PNI-11096 through the SPI port
specifying the sensor axis to be measured. The
PNI-11096 will return the result of a complete
forward - reverse measurement of the sensor in a16bit 2’s Complement format.
(Range: -32768 to 32767)
PS2
0
0
0
0
1
1
1
1
BIT
RESET
7
6
5
4
3
2
1
0
DHST
PS2
PS1
PS0
ODIR
MOT
AS1
AS0
0
0
0
0
0
0
0
0
AS1
0
AS0
0
0
1
1
1
0
1
2.2.1 SCLK Serial Clock
The serial clock (SCLK) is used to synchronize both
the data in and out through the MISO and MOSI
lines. SCLK is generated by a master device.
SCLK should be 1 MHz or less. The PNI-11096 is
configured to run as a slave device, so this is an
input. One byte of data is exchanged over eight
clock cycles. Data is captured by the master device
on the rising edge of SCLK. Data is shifted out and
presented to the PNI-11096 on the MOSI pin on the
falling edge of SCLK.
Note:
When 2 MHz Scaling is selected, the
magnetic sensor oscillator does not run. Instead,
the internal 2 MHz oscillator is turned on. The 2
MHz clock cycles are counted until a command byte
is sent disabling the scaling function. A reset stops
the 2 MHz oscillator and clears all bits
2.2.2 SSNOT Slave Select
The slave select line (SSNOT) selects the PNI11096 as the operating slave device. The SSNOT
line must be low prior to data transfer and must stay
low during the entire transfer. Once the command
byte is received by the PNI-11096, and the PNI11096 begins to execute the command, the SSNOT
line can be deselected until the next SPI transfer.
2.1.2 MOT Magnetic Oscillator Test
When set, this bit causes the magnetic oscillator
selected by AS0 and AS1 in the directions selected
by ODIR to run continuously until PNI-11096 is
reset, or a command byte is received to disable the
test function. The MOT bit when set also enables
the mag oscillator frequency to the Comp test pad.
2.2.3 MOSI Master Out, Slave In
The master out, slave in (MOSI) line is the data sent
to the PNI-11096. Data is transferred most
significant bit first. The MOSI line will accept data
once the SPI is enabled by taking SSNOT low.
Valid data must be presented at least 100 ns before
the rising edge of the clock, and remain valid for 100
ns after the edge. New data may be presented to
the MOSI pin on the falling edge of SCLK.
2.1.3 ODIR Oscillator Direction
This bit determines the magnetic oscillator direction
if MOT is set to 1. It has no effect on direction when
the MOT bit is set to zero. This is used for debug
purposes only, and will not be set in normal
operation.
2001 PNI Corporation www.pnicorp.com
Ratio
/32
/64
/128
/256
/512
/1024
/2048
/4096
2.2 SPI Port
All accesses to and from the PNI-11096 are
through a synchronous serial port that adheres to
the Motorola SPI protocol. The port consists of
four signals; SCLK, MOSI, MISO and SSNOT.
2.1.1 AS0, AS1 Axis Select
The Axis select bits determine which axis is being
measured.
Function
2 MHz
Scaling
X axis
Y axis
Z axis
PS0
0
1
0
1
0
1
0
1
2.1.5 DHST High Speed Oscillator Test
When this bit is set, the internal high speed clock is
set to drive the DHST pad at ½ the clock speed.
When this bit is 0, the DHST pad is set to DVDD.
2.1 Command Byte
The operation of the PNI-11096 is controlled by the
data received into the SPI port. The command byte
syntax is as follows:
Position
PS1
0
0
1
1
0
0
1
1
2.2.4 MISO Master In, Slave Out
The master in, slave out (MISO) line is the data sent
from the PNI-11096 to the master.
Data is
transferred most significant bit first. The MISO line
is placed in a high impedance state if the salve is not
selected (SSNOT=1).
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DOC 1000005 R07
2.4 Pin Descriptions
SCLK -- serial clock for SPI port
MISO -- master in, slave out for SPI port
MOSI -- master out, slave in for SPI port
SSNOT -- slave select for SPI port. SSNOT must be
low to select PNI-11096 for operation.
RESET -- PNI-11096 reset.
You must toggle
RESET low after every PNI-11096 command has
been executed to enable next command.
DRDY -- Data ready. This pin is asserted after a
measurement to signal that data is ready to clock
out.
2.3 Operation
Basic operation will follow these steps.
(Reference Figures 3 and 4)
1. SSNOT is brought low.
2. Pulse RESET high (return to low state). You
must RESET the PNI-11096 before every
measurement.
3. Data is clocked in on the MOSI line. Once eight
bits are read in, the PNI-11096 will execute the
command.
4. The PNI-11096 will make the measurement. A
measurement consists of forward biasing the
sensor and making a period count; then reverse
biasing the sensor and counting again; and
finally, taking the difference between the two
bias directions.
5. At the end of the measurement, the DRDY line
is asserted to alert you that the data is ready. In
response to the next 16 SCLK pulses, data is
shift out on the MISO line.
3. Application notes
3.1 Idle mode
The PNI-11096 does not initialize in the idle mode at
power-up. The PNI-11096 must be in a data-ready
state for the idle mode to occur. After power-up the
PNI-11096 can be brought to the data-ready state
simply by sending a read command to the PNI11096. First bring SSNOT low, pulse the reset line
and then send a command to the PNI-11096 to
measure one of the sensors. The DRDY pin will
eventually go high signifying that the PNI-11096 is in
the data-ready state. The resultant data does not
have to be read from the PNI-11096. Once the
SSNOT pin is brought high again the PNI-11096 will
go into the low power idle mode.
If you need to make another measurement, go to
step 2. You can send another command after the
reset. In this case, keep SSNOT low. If you will not
be using the PNI-11096, bring SSNOT high to
disable the SPI port.
SSNOT
RESET
1
2
3
4
5
6
7
8
1
2
3
4
14
15
16
SCLK
COMMAND BYTE
MOSI
MSB
LSB
DATA WORD
MISO
MSB
LSB
DRDY
Figure 3
SPI Port Full Timing Sequence (cpol = 0)
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3.2 SPI port usage tips
A SPI port can be implemented using
different clock polarity options. The clock
can be normally low (cpol = 0) or normally
high (cpol = 1). Figure 4 graphically shows
the timing sequence of the two clock polarity
options when used to communicate with the
PNI-11096. Regardless of the polarity
chosen, data is always read in (into the PNI11096) on the rising edge of the clock and
sent out on the falling edge of the clock.
When implementing an SPI port, whether it
be a dedicated hardware peripheral port, or
a software implemented port using general
purpose I/O (also known as Bit-Banging) the
timing parameters given in Figure 4 must be
met to ensure reliable communications. The
clock set-up and hold times as depicted as
tDBSH and tDASH (Time, Data Before SCLK
High and Time, Data After SCLK High) must
be greater than 100nS.
3.3 Sample Rates
Approximate sample rate limits for sampling
2 sensors based on Period Select settings
are as follows:
Period Select Max Samples
per second
64
200
128
140
256
72
512
36
2001 PNI Corporation www.pnicorp.com
SS*
SCLK
tDBSH
tDASH
MOSI
MSB
6
5
4
3
2
1
LSB
MISO
MSB
6
5
4
3
2
1
LSB
tDBSH > 100ns tDASH > 100ns
CPOL = 0
SS*
SCLK
tDBSH
tDASH
MOSI
MSB
6
5
4
3
2
1
LSB
MISO
MSB
6
5
4
3
2
1
LSB
tDBSH > 100ns tDASH > 100ns
NOTE: DBSH = Data Before SCLK High
CPOL = 1
DASH = Data After SCLK High
Figure 4
SPI Port timing parameters (cpol = 1 & cpol = 0)
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DOC 1000005 R07
Package Information
28 Pin SOIC Outline Dim ens ions
(Unit : mm)
A M I
E
XXX XY ZZ
0 6 - 2 31 1 - 1 0 0 0
H
Pin 1
Topview
D
A
α
Seating
Plane
A
1
B
e
L
Sideview
SY MBOL
MIN
NOM
C
End view
MAX
A
2.35
-
2.65
A1
B
C
0.10
-
0.30
0.33
-
0.51
0.23
-
0.32
D
E
e
17.70
-
18.10
7.40
-
7.60
H
L
α
10.00
-
10.65
0.40
-
1.27
1.27BSC
0
8
M arkings
XXXX : Data Code
Y : Assem bly Plant identifier
ZZ : T raceability Code
06-2311-1000 : PNI Part No. (can be use with PNI’s alternate P/N:10175)
2001 PNI Corporation www.pnicorp.com
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DOC 1000005 R07
Package Information (continued)
28 Le ad M LF(5x5m m ) Outline dim e ns ions
(U n it : mm)
0.625 +/0.125
0.24 +/0.06
5.0 +/0.15
XXXXYZZ
11182
11096A
AAAA
Pin 1
5.0 +/0.15
0.5 +/0.06
4.0 +/0.12
Bottom
view
Top view
0.28 m ax
0.94
ref
4.5 +/0.1
5.36 3.48 3.28 3.18
max min max TH
0.2 +/0.02
0.9 +/0.05
Side view
PCB Land pattern
M ar k ings
XXXX : Data Code
Y : Assem bly Pl ant identifi er
ZZ : T raceabi li ty Code
11182 : PNI Part No.
11096A : Revi sion No.
AAAA : Country of Assem bl y
Pack age m ate r ials
Lead Fram e : C194H
M ol d com pound : 7351UL
Sol der pl ati ng : 85/15 Sn/Pb
M arking : Laser
2001 PNI Corporation www.pnicorp.com
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DOC 1000005 R07
Package Information (continued)
Die Package Mechanical Specifications:
PNI part number index
PNI part number
Description
10174
26 pad Die
10175
28 pin SOIC
11182
28 pin MLF
PNI Sales information
PNI Corporation
Santa Rosa, California USA
tel 888.422.6672
fax 707.566.2261
[email protected]
PNI Corporation does not assume any responsibility for use of any circuitry described. Some circuit usability are subject to patent licensing.
PNI Corporation reserves the right at any time without notice to change said circuitry and specifications
2001 PNI Corporation www.pnicorp.com
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DOC 1000005 R07