M62303FP High Precision Double Integration Type A/D Converter REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Description M62303FP is a double integration type A/D converter support system, and is a semiconductor integrated circuit which can work as A/D converter of 14 bits or more by being used with MCU and by inputting SI, SCK1, CS, and CONTIN. High precision A/D translation system can be realized without using high precision external parts by proofreading A/D acquired values with two or more known conversion values such as reference voltage, grounding (zero) voltage and so forth. Features • • • • • High precision (14 bits or more) double integration type A/D converter Positive/negative constant voltage source built-in (+6.3 V, –6.0 V Typ) Positive/negative constant current source built-in (Isource = 2 mA, Isink = 0.2 mA Max) Independent 2ch operational amplifier built-in System reset built-in (4.5 V Typ) Application High precision control systems, such as temperature control and speed control Block Diagram 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 + − + − 55 SOURCE + − 56 Pulse generator Decoder Decoder Decoder Level shift Level shift Level shift 28 27 26 Level shift Decoder Level shift 60 Decoder 59 Level shift 58 15-bit latch Shift register 57 29 Current generator + − 54 SINK 53 + − Sequence control 52 + − + − 51 25 Constant voltage 24 23 61 22 62 21 63 20 64 19 1 2 3 4 5 6 REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 1 of 10 7 8 9 10 11 12 13 14 15 16 17 18 M62303FP Pin Arrangement GD CONT IN PULSE OUT CS SCK1 SI VDD VC− VC+ MUX CH1 MUX CH2 MUX CH3 MUX CH4 MUX CH5 M62303FP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MUX CH6 1 50 RESET OUT MUX CH7 2 49 DELAY MUX CH8 3 48 VADR MUX COM 4 47 COMP IN AS1-1 5 46 INT OUT AS1-2 6 45 GA AS1-3 7 44 INT IN AS1-4 8 43 GA AS1-5 9 42 BUFFER AS1-COM 10 41 AD IN AS2-1 11 40 VREF AS2-2 12 39 OP2+ AS2-3 13 38 OP2− AS2-4 14 37 OUT2 AS2-5 15 36 OUT1 AS2-COM 16 35 OP1− AS3-1 17 34 OP1+ AS3-2 18 33 VA− R4 (Top view) Outline: PRQP0064JA-A (64P6S-A) REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 2 of 10 VA+ R1 R2H R3 R2L R5 GA VC− VC+ AS5 COM AS5 AS4-2 AS4-1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M62303FP Pin Description 56 55 Pin No. Pin Name SI SCK1 Function Serial data input terminal. Serial data of 15 bits data length is input. Shift clock input terminal. Signal from SI terminal is input into 15-bit shift register at the rise of a clock. "L" level of this terminal enables shift clock, and "H" level makes shift register contents stored into multiplexer control register (analog switches) and unenables clock input. 54 CS 52 CONT IN 57 51 VDD GD 50 49 60, 61, 62, 63, 64, 1, 2, 3 4 5, 6, 7, 8, 9 10 11, 12, 13, 14, 15 16 17, 18 19, 20 21 22 23, 59 24, 58 25 26, 27, 28, 29 30 31 32 33 34 35 36 37 38 39 40 RESET OUT DERAY MUX1 to 8 A pulse is input. Double integration type A/D converter is started synchronizing with this pulse. Moreover, the optimal full scale can be set up by setting up with C and R so that it may be set to TCONT ≤ 2.14 CR. Digital part power supply terminal Digital part GND terminal. This terminal is externally connected to analog ground terminal when IC is operative. Output terminal of reset circuit supervising the fall of a digital part power supply. Reset output rise is delayed by adding capacitor. Input side terminal of multiplexer (analog switch group) MUX. MUXCOM AS1-1 to 5 AS1COM AS2-1 to 5 Output side COMMON terminal of multiplexer MUX. Input side terminal of multiplexer (analog switch group) AS1. Output side COMMON terminal of multiplexer AS1. Input side terminal of multiplexer (analog switch group) AS2 AS2COM AS3-1 to 2 AS4-1 to 2 AS5 AS5COM VC+ VC– GA R5, R3, R2L, R2H R1 R4 VA+ VA– OP1+ OP1– OUT1 OUT2 OP2– OP2+ VREF Output side COMMON terminal of multiplexer AS2 Source type constant current source output terminal Sink type constant current source output terminal Analog switch AS5 input side terminal Analog switch AS5 output side terminal Positive power supply output terminal for analog switch drive Negative power supply output terminal for analog switch drive Analog part GND terminal Reference current setting terminal for constant current source 41 ADIN 42 BUFFER 43, 45 44 46 47 48 53 GA INTIN INTOUT COMPIN VADR PULSEOUT TCONT Source type output current setting terminal for constant current source Sink type output current setting terminal for constant current source Analog part positive power supply terminal Analog part negative power supply terminal Operational amplifier 1 non-inverting input terminal Operational amplifier 1 inverting input terminal Operational amplifier 1 output terminal Operational amplifier 2 output terminal Operational amplifier 2 inverting input terminal Operational amplifier 2 non-inverting input terminal Standard voltage input for standard integration, and constant standard voltage input terminal for source current source setup A/D conversion input terminal. Analog signal into ADIN terminal is converted into pulse width proportional to the input voltage. Output terminal of buffer amplifier which receives VREF, ADIN, and GA input. Internal analog switch for A/D conversion is switched by the CONTIN signal, and the voltage of three types of VREF, ADIN, and GA is output to BUFFER terminal through buffer amplifier. Analog part GND terminal Input terminal of integration amplifier Output terminal of integration amplifier Input terminal of the comparator part of a double integration type A/D converter Power supply output terminal used for reference terminal of comparator A/D translation output terminal. Input analog signal is changed into pulse to be output. REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 3 of 10 M62303FP Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Analog power supply voltage Switch part power supply voltage Digital section supply voltage A/D converter analog input voltage PULSE OUT output current Reset output current Switch input voltage Symbol VA+ VA– Vc+ Vc– VDD VAIN Isink (PO) Isink (RE) VSWIN Switch input current ISWIN Digital input voltage Power dissipation Operating temperature Storage temperature VDIN Pd Topr Tstg Note: Ratings 22 13.2 –0.3 to +7 –4 to +4 10 10 Vc– to Vc+ VA– to VA+ *1 ±20*1 ±100*1 –0.3 to VDD + 0.3 740 –20 to +75 –40 to +125 Unit V V V V mA mA V Conditions At the line of fault voltage impression (Per one pin) (All the switch sum totals) mA V mW °C °C 1. Represents the protection level at the time of abnormalities. Operating Conditions (Ta = 25°C) External parts Digital Analog Block Item Symbol Min Typ Max Unit Power supply voltage (positive side) VA+ +8.1 +12 +13 V Power supply voltage (negative side) VA– –9 –8 –7.2 V Power supply current (positive side) IA+ — 13 17 mA Power supply current (negative side) IA– — 12 17 mA A/D converter analog standard voltage VREF 1.0 2.5 3.0 V A/D converter analog input voltage Switch input voltage Input integration time Power supply voltage Power supply current High-level input voltage VAIN –VREF — VREF V VSWIN TCONT VDD IDD VIN –6 2 4.80*2 — 2.4 — — 5.0 1.8 — +6 20 5.5 3 — V ms V mA V Low-level input voltage Serial clock waiting time Serial input setup time Serial input hold time Serial clock low level time Serial clock high level time Chip selection hold time Integration capacitance VIL tSCSK tSIK tHKI tWLK tWHK tHKCS CINT*3 — 250 100 50 200 200 50 — — — — — — — — 0.015 0.8 — — — — — — — V ns ns ns ns ns ns µF Voltage current conversion resistor RINT 56 230 500 kΩ Notes: 2. Represents the reset release voltage. 3. Set up as in 2.14 RINT – CINT TCONT. REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 4 of 10 Test Conditions CS↓→SCKI↓ SI→SCKI↑ SCKI↑→SI SCKI↑→CS↑ M62303FP Electrical Characteristics (Ta = 25°C, unless otherwise noted) VA+ = 12 V, VA– = –SV, VREF = 2.5 V, VDD = 5.0 V, TCONT = 7.3 ms Power Supply A/D Conversion Machine Block Item Analog input current Resolution Linearity error*1 Conversion range of *2 fluctuation Conversion time Symbol Min — 14 — Typ 20 — 0.012 Max 80 — — Unit nA Bit %FS — — 0.006 — %FS Tc 8.28 15.58 22.88 — –6.0 — — — 0.4 –5.7 ms Il ER N, L Saturation voltage Vpo (sat) Conversion standard voltage VADR — — — — –6.3 Output voltage for switch part power supplies Vc+ +6.0 +6.3 +6.6 V Output voltage for switch part power supplies Vc– –6.6 –6.3 –6.6 V Input voltage fluctuation ON resistance ∆Vc — — 100 mV 200 200 300 30 — ±100 ±100 ±100 ±100 ±100 ±100 ±100 ±100 ±100 — — Ω — 100 — — — — RON match — 10 RON drift ∆RON/∆T — 0.5 — ±0.1 ISoff Input off-leak current — — — — — ±0.1 IDoff Output off-leak current — — — — — ±0.1 IDon On-channel leak current — — — — Off isolation OIRR 70 80 Cross talk CCRR 70 90 Notes: 1. –VREF to 0 and 0 to VREF is made into full scale. 2. Tolerance width at the time of repeated conversion. Switch Part RON REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 5 of 10 Test Conditions CINT = 0.015 µF VAIN = 2.5 V RINT = 230 kΩ VAIN = 0 V VAIN = –2.5 V V V Isink (PO) = 6 mA VA+: 8.1 to 13 V, VA–: –9 to –7.2 V –6 V Vds 6 V Ta = 25°C Id = 1 mA Ta = –40°C Ta = 85°C % %/°C nA nA nA dB dB Vd = –6 V, Vs = 6 V Ta = 25°C and Vs = –6 V, Vd = 6 V Ta = 0°C Ta = 50°C Vd = –6 V, Vs = 6 V Ta = 25°C and Vs = –6 V, Vd = 6 V Ta = 0°C Ta = 50°C Vs = Vd = 6 V Ta = 25°C and Vs = Vd = –6 V Ta = 50°C Ta = 0°C Vs = 2 Vp-p, f = 1 kHz, RL = 100 Ω Vs = 2 Vp-p, f = 1 kHz, RL = 100 Ω M62303FP Electrical Characteristics (cont.) The Source of Current Block Item Symbol Output source current ICS1 Output source current accuracy ∆ICS1 Output source current drift Reset Typ — Max 2 Unit mA RL1 = 0 to 3000 Ω — — ±0.2 % RL1 = 0 to 3000 Ω — ±10 — ppM/°C Permissible load resistance Output sink current RL1 — — 3000 Ω ICS2 Output sink current accuracy ∆ICS2 — — — — –0.2 ±0.2 mA % — ±10 — ppM/°C Output sink current drift Operational Amplifier Min 0.1 Test Conditions With the sauce current maximum RL2 = 0 to 1000 Ω RL2 = 0 to 1000 Ω Permissible load resistance RL2 — — 1000 Ω Reset detection voltage Vs 4.3 4.5 4.7 V Hysteresis (upper side) Delay time Saturation voltage Input offset voltage Vhys 40 70 100 mV tD VR (sat) VIO 0.6 — — 1 — 1.0 1.5 0.4 6.0 ms V mV Input offset voltage drift Input offset current ∆Vm/∆T — 3 — µV/°C IlO — 20 200 nA Input offset current drift Input bias current ∆Im/∆T — 1 — nA/°C IB Input bias current drift Open loop gain ∆lB/∆T — — 80 2 500 — nA nA/°C 20000 100000 — Ω RL = 2 kΩ, VO = +8 V, –4 V Open loop gain rejection ratio CMR 70 90 — dB Rs = 10 kΩ Power supply change rejection ratio SVR — 30 150 µV/V Rs = 10 kΩ Maximum output voltage Slew rate Vom +9, –5 +11, –7 — V RL = 10 kΩ S. R. 0.4 0.8 — V/µs Maximum output current Iop 5 10 — mA AV REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 6 of 10 With the sink current maximum CDELAY = 0.01 µF Isink = 6 mA Rs = 10 kΩ Rs = 10 kΩ AV = 1 M62303FP Digital Format First 2 Last 3 4 5 6 MUX 0 1 0 1 0 1 3. Analog switch 2 (AS2) 11th ALL OFF AS2-1ON 2-2ON 2-3ON 2-4ON 2-5ON ALL OFF ALL OFF 0 1 0 1 0 1 0 1 5. Analog switch 4 (AS4) 15th ALL OFF AS4-1ON 4-2ON ALL OFF 8 9 10 AS1 1. Multiplexer (MUX) 5th ALL OFF 0 CH1 ON 1 CH2 ON 0 CH3 ON 1 CH4 ON 0 CH5 ON 1 CH6 ON 0 CH7 ON 1 CH8 ON 0 ALL OFF 1 ALL OFF ALL OFF ALL OFF ALL OFF ALL OFF ALL OFF 7 0 1 0 1 AS2 4th 0 0 1 1 0 0 1 1 0 0 3rd 0 0 0 0 1 1 1 1 0 0 2nd 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 10th 9th 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 14th 0 0 1 1 REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 7 of 10 11 12 13 AS3 14 15 LSB AS4 AS5 2. Analog switch 1 (AS1) 8th ALL OFF 0 AS1-1ON 1 1-2ON 0 1-3ON 1 1-4ON 0 1-5ON 1 ALL OFF 0 ALL OFF 1 7th 0 0 1 1 0 0 1 1 4. Analog switch 3 (AS3) 13th 12th ALL OFF AS3-1ON 3-2ON ALL OFF 0 1 0 1 6. Analog switch 5 (AS5) LSB OFF AS5ON 0 1 0 0 1 1 6th 0 0 0 0 1 1 1 1 M62303FP Sequence Timing Chart (1) A/D conversion Tcont CONT IN Tc PULSEOUT Conversion start Conversion end (2) DATA Input CS tSWEX tHKCS tWHK SCKI tWLK SI REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 8 of 10 tSIK tHKI M62303FP About the Input Voltage VX External capacitor External resistance + − 40 42 − + 44 43 46 47 48 − + Pulse generator 41 − + 45 Given the applied voltage into 41 pin is VX in the diagram above, VX = TGND − TX TGND − TR • VR T = Pulse width TGND, TR, and TX can be respectively expressed with nGND/f, nR/f, and nX/f, (f is clock frequency; nGND, nR, nX is count values for clock frequency f.) If these are substituted for an upper formula, VX = nGND − nX nGND − nR • VR VX can be expressed in this way for the number of counters. REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 9 of 10 M62303FP Package Dimensions JEITA Package Code P-QFP64-10x14-0.65 RENESAS Code PRQP0064JA-A Previous Code 64P6S-A MASS[Typ.] 0.8g HD *2 D 50 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. ZE *1 E 32 HE 51 64 19 1 ZD Reference Symbol c 18 Index mark D E A2 HD HE A A1 bp c A2 A F y *3 bp x A1 e L Detail F REJ03D0862-0201 Rev.2.01 Dec 27, 2007 Page 10 of 10 e x y ZD ZE L Dimension in Millimeters Min Nom Max 13.8 14.0 14.2 9.8 10.0 10.2 2.8 16.5 16.8 17.1 12.5 12.8 13.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0° 10° 0.65 0.13 0.10 1.475 0.775 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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