FX-702 Low Jitter VCSO Frequency Translator Previous Part Numbers FX-703, FX-730 FX-702 Description The FX-702 is a low jitter precision frequency translator used to translate input frequencies such as 19.44, 38.88, 77.76 MHz, etc. to a binary multiple frequency as high as 1 GHz. The FX-702’s superior jitter performance is achieved through the PLL’s integrated VCSO. The FX-702 is housed in a hermetically sealed leadless surface mount package offered on tape and reel. Features Applications • 5 x 7.5 x 2.5 mm Package • Frequency Translation up to 1 GHz • VCSO based PLL for Ultra-Low Jitter • Low Power Consumption • Differential LVPECL or LVDS Output • Clock Bypass Mode • CMOS Lock Detect • -40°C/+85°C Temperature Range • Complete Easy to Implement Solution • Fully Compatible for Lead Free Assembly • SONET/SDH • 10GbE./10.3GbE • Frequency Translation • Clock Smoothing, Clock Switching • FEC Scaling • Medical Instrumentation • Test and Measurement • Military Block Diagram VCC (10) FIN (12) CFIN (11) MODE (4) ÷1, ÷4 LD (2) LFN (6) Phase Detector & LD Charge Pump Switch External Divider ÷1, ÷4, ÷8, ÷16, ÷32 CFLN (7) VCSO FOUT (8) ÷1, ÷2, ÷4, ÷8 CFOUT (9) BRCLK CBRCLK (1) (4) GND (3, 5, 13) Figure 1. Functional block diagram 1 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 1 Rev: 03Sep2015 Performance Specifications Table 1. Electrical Performance Parameter Symbol Min Frequency Input Frequency Output Frequency FIN FOUT 1 62.5 Capture Range (ordering option)1, 2, 3 APR Typical Maximum Units 1000 1000 MHz MHz 1, 2, 3 Supply Voltage 2, 3 Current (No Load) 3,9 Standard Mode LVDS Enhanced Mode LVDS Standard Mode LVPECL Enhanced Mode LVPECL VCC ±20, ±32, ±50, or ±100 2.97 3.3 3.63 V 115 140 140 162 mA mA mA mA 2.0 0 VCC 0.8 V V 0.20 3.00 V 0.1*VCC V V V mV-pp mV-pp V mV-pp mA ps ps % fs-rms fs-rms ICC ICC ICC ICC LVCMOS Input 2, 3 Input High Voltage Input Low Voltage VIH VIL LVPECL Input Peal-Peak Amplitude Swing 6, 7 Lock Detect Output Output High Voltage Logic Low Voltage VOH VOL Outputs Mid Level - LVPECL 2, 3 Single Ended Swing - LVPECL 2, 3 Differential Swing - LVPECL 2,3 Mid Level - LVDS 2, 3 Single Ended Swing - LVDS 2, 3 Current 5 Rise Time 4, 5 Fall Time 4, 5 Symmetry 2, 3 Jitter Generation - 622.08MHz output (12kHz-20MHz BW) 5 (50kHz - 80MHz BW) 5 0.9*VCC VCC-1.5 450 900 VCC-2.0 300 VCC-1.3 750 1500 VCC-1.8 450 160 160 45 50 VCC-1.1 1050 2100 VCC-1.6 600 20 400 400 55 ΦJ ΦJ 210 120 500 400 TOP 0/70, -40/85 IOUT tR tF SYM Operating Temp (ordering option) 1, 3 ppm °C 1. See Standard Frequencies and Ordering Information. 2. Parameters are tested with production test circuit below (Fig 2). 3. Parameters are tested at ambient temperature with test limits guard banded for specified operating temperature. 4. Measured from 20% to 80% of a full output swing (Fig 3). 5. Not tested in production, guaranteed by design, verified at qualification. 6. Minimum Input Low Voltage not to exceed 2.125 V. Minimum Input High Voltage not to go below 1.49 V. 7. AC coupling is recommended. There is an internal pull-up and pull-down resistor on all clock inputs (Fin, BRCLK). 8. Measured using a Wavecrest SIA3300. Best results are realized with a differential input. 9. Enhanced mode activates both 5-bit and 7-bit counters thereby drawing more current. Figure 2. LVPECL Test Circuit 2 of 10 Figure 3. 10K LVPECL Waveform Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 2 Rev: 03Sep2015 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Table 2. Absolute Maximum Ratings Symbol Ratings Unit Power Supply Parameter VCC 0 to 6 V Input Current IIN 100 mA Output Current IOUT 25 mA Storage Temperature TSTR -55 to 125 °C TPEAK/tP 260 / 40 °C/s Soldering Temperature/Duration Reliability The FX-702 is capable of meeting the following qualification tests: Table 3. Environmental Compliance Parameter Conditions Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solvents MIL-STD-883, Method 2016 Moisture Sensitivity Level Rating MSL 1 Handling Precautions Although ESD protection circuitry has been designed into the FX-702, proper precautions should be taken when handling and mounting. VI employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Table 4. Predicted ESD R$atings Model Class Minimum Conditions Human Body Model 2 2000 V MIL-STD 883, Method 3015 Charged Device Model C5 1000 V JEDEC, JESD22-C101 Machine Model M3 200 V ESD STM5.2-1999 3 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 3 Rev: 03Sep2015 Table 5. Reflow Profile (IPC/JEDEC J-STD-020C) Parameter Symbol Value tS 60 s Min, 180 s Max PreHeat Time RUP 3 °C/s Max tL 60 s Min, 150 s Max tAMB-P 480 s Max tP 20 s Min, 40 s Max RDN 6 °C/s Max Ramp Up Time Above 217 °C Time To Peak Temperature Time At 260 °C Ramp Down The device has been qualified to meet the JEDEC standard for Pb-Free assembly. The temperatures and time intervals listed are based on the PbFree small body requirements. The temperatures refer to the topside of the package, measured on the package body surface. The FX-702 device is hermetically sealed so an aqueous wash is not an issue. Figure 4. Suggested IR Profile Table 6. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 16 7.5 1.5 4 8 178 1.5 13 20.2 50 16.4 22.4 200 Figure 5. Tape and Reel 4 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 4 Rev: 03Sep2015 FX702 YWW CCC-CCCC XX-XX Y = YEAR WW = WEEK C = OPTION CODES XX = FREQUENCY CODES (SEE ORDERING INFO) Figure 6. Outline Diagram & Suggested Pad Layout Table 7. Pin Functions Pad # Symbol I/O Level 1 BRCLK I NC or LVPECL, LVDS 2 LD1 O CMOS Lock Detect Logic 0 = FX Locked Logic 1 = No Input Output transitioning = Out of Lock 3 GND GND Supply Case and electrical ground 4 MODE I CMOS FX Operating Mode Logic 0 = Standard PLL (Normal Setting) Logic 1 = FIN coupled to FOUT 5 GND GND Supply Case and electrical ground 6 LFN Analog Loop Filter Node 7 CLFN Analog Complementary Loop Filter Node 8 FOUT O LVPECL or LVDS Frequency Output 9 CFOUT O LVPECL or LVDS Complementary Frequency Output 10 VCC I Supply Power Supply Voltage (+3.3V ±5%) 11 CFIN I LVPECL Complemetary Input Frequency For CMOS inouts, AC-couple unused input to ground or negative supply 12 FIN4,5 I CMOS or LVPECL 13 GND GND Supply 14 CBRCLK I NC or LVPECL, LVDS 1. 2. 3. 4. 5. 5 of 10 2 4,5 3,4 Function NC or For External divider application = PD Feedback Frequency Input Frequency Case and electrical ground NC or For External divider applications = Comp. PD Feedback Frequency It is recommended that the Lock Detect circuit shown in Figure 7 be used for smoothing the FX-702 lock detect signal. The circuit takes the lock detect output and performs a peak follower. When out of lock, the output is VCC - 1V. Under locked conditions, it is ground. Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation. BRCLK and CBRCLK should be left floating if not used. FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs. Best jitter is realized with a differential input. Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 5 Rev: 03Sep2015 Figure 7. Typical FX-702 Application Diagram Consult with Vectron Application Engineering for recommended Loop Filter design. The lock detect has a low current output drive with narrow pulses occuring at the phase detector edge rate even under locked conditions. Figure 7 shows one method to buffer and filter the LD output. Figure 8. LVDS Input, LVDS Output The inputs, Fin and CFin, are biased with 13 kΩ pull up and pull down resistors which sets the mid supply bias on the input differential amplifier. In most applications, the input should be ACcoupled. For best signal integrity, the shown terminatiosn should be used. 6 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 6 Rev: 03Sep2015 Figure 9. 50 Ohm Impedance Matching. LVPECL Input, LVPECL Output Figure 10. Alternate LVPECL Termination Scheme, Short PC Trace 7 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 7 Rev: 03Sep2015 Table 8. Standard Frequencies (MHz) 8 of 10 18.7500000 EE 39.0625000 HH 73.7280000 K8 172.500000 NU 600.000000 PR 779.568600 T8 19.2000000 DD 39.3216000 HD 74.1250000 K1 173.370748 ND 614.400000 RG 780.881000 TD 19.3926580 DX 39.8437500 HJ 74.1758000 KA 173.437500 NP 622.080000 P2 781.250000 T9 19.4400000 D6 40.0000000 JF 74.2500000 K7 176.838175 NA 624.693800 PD 796.875000 TB 19.5312500 DZ 40.2830630 KK 75.0000000 KH 182.016000 N8 624.704800 P6 800.000000 TK 19.6608000 DB 40.9600000 J1 76.8000000 K4 182.857142 NM 625.000000 P3 805.664100 TA 19.6989680 DK 41.0888870 KM 77.7600000 K2 184.000000 NG 627.329600 P7 809.063500 TE 19.7190000 DH 41.6571440 KP 78.0000000 LH 184.320000 NH 629.987800 PA 819.200000 TH 19.9218750 ED 41.6600000 LM 78.1250000 K3 187.500000 N5 637.500000 PG 821.777300 TF 20.0000000 E2 41.8329130 KT 78.6432000 K5 195.000000 N7 640.000000 PN 850.000000 TJ 20.1416000 E3 42.0000000 JB 79.6875000 KG 200.000000 NE 644.531250 P4 983.400000 TU 20.4800000 E4 42.0101690 KV 80.0000000 K9 200.192000 N6 645.120000 RJ 1,000.0000 TM 20.5444340 EF 42.5000000 JC 80.5664130 KJ 201.416020 N1 647.239400 PE 20.7135000 E1 42.6600000 JZ 82.1777380 KL 212.500000 NF 647.250800 PK 20.8285720 EG 44.2095440 KX 82.9440000 K6 219.429571 NL 649.970300 PF 20.8286000 EB 44.4343000 LF 83.3142880 KN 240.000000 NR 657.421875 PB 20.9165460 EH 44.6218000 JW 83.6658250 KR 243.000000 NC 665.625600 PC 21.0050840 EJ 44.7360000 J3 84.0203380 KU 245.760000 N9 666.514286 P5 22.0000000 E9 44.9280000 JE 86.6853740 LJ 250.000000 NT 669.128100 R2 22.1047720 EK 45.1584000 JG 88.4190880 KW 252.571428 NJ 669.326582 R3 22.2171000 E5 45.8240000 JM 95.7000000 LK 256.000000 NK 669.642900 R1 22.5792000 E8 46.0379460 LG 97.5000000 KE 262.144000 NB 670.838600 R7 24.0000000 EC 46.7200000 JK 100.000000 L8 292.571429 NN 672.000000 RT 24.5760000 E6 46.8750000 JY 105.000000 L6 300.000000 PT 672.156250 TX 24.7040000 E7 48.0000000 JV 106.250000 L9 307.200000 RX 672.162712 R5 25.0000000 F7 49.1520000 J7 108.000000 LA 311.040000 P1 673.456600 RA 25.1658000 F8 49.4080000 J2 110.000000 L1 312.500000 PU 684.255400 R9 25.6000000 F6 50.0000000 JD 112.000000 L2 318.750000 PV 687.700000 TV 25.9200000 F2 50.0480000 KD 114.000000 L3 320.000000 PP 690.569196 R4 26.0000000 F3 51.2000000 LL 120.000000 LC 322.265650 PW 693.468750 RV 27.0000000 F4 51.8400000 J4 122.880000 LB 328.710950 PX 693.482991 R6 27.6480000 FB 52.0000000 JP 124.416000 L7 333.257150 PY 693.750000 R8 28.7040000 F1 53.3300000 JU 125.000000 L4 333.625806 VX 696.390625 RW 29.4912000 F5 54.7460000 JL 130.000000 LD 334.663300 RB 696.421478 V1 29.5000000 F9 55.0000000 JX 131.072000 LN 336.081350 RC 696.421875 TY 30.0000000 HE 60.0000000 JR 139.264000 L5 353.676350 RD 704.380600 TG 30.7200000 H1 61.3800000 KY 150.000000 M8 368.640000 RY 707.352700 TC 30.8800000 HF 61.4400000 J5 150.144000 M6 375.000000 RF 707.500000 V2 31.2500000 H8 62.2080000 J8 153.600000 MA 382.800000 RU 710.948600 T2 32.0000000 H2 62.5000000 J9 155.520000 M2 400.000000 RR 712.520000 TW 32.7680000 H3 62.9145000 LE 156.250000 M3 409.600000 RE 716.573200 T1 33.0000000 H7 63.3600000 JJ 159.375000 M7 491.520000 PM 718.750000 T5 33.3330000 HC 63.8976000 JN 160.000000 M1 500.000000 RK 719.734400 T3 34.3680000 H6 64.0000000 JT 161.132813 M4 505.000000 V3 737.280000 TL 34.5600000 HB 64.1520000 JH 164.355475 M9 531.000000 PH 739.200000 TT 36.8640000 HG 65.5360000 J6 166.628572 M5 531.250000 P8 742.500000 V4 37.0560000 H4 66.0000000 JA 166.812903 NY 568.928600 PJ 748.070900 T6 37.1250000 H9 70.0000000 KB 167.331646 N2 569.196400 P9 750.000000 T7 37.5000000 HK 70.6560000 KC 168.040678 N3 588.000000 RH 768.000000 TN 38.8800000 H5 71.6100000 KF 170.000000 N4 595.056000 PL 777.600000 T4 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 8 Rev: 03Sep2015 Ordering Information FX- 702 - E C E - H M M M - XX - XX Product Family FX: Frequency Translator Output Frequency (See Above) Input Frequency (See Above) Package 702: 5.0 x 7.5 x 2.0 mm3 Factory Use Input E: 3.3 Vdc ±10% Output C: LVPECL D: LVDS Mode3 M: Standard X: Enhanced Operating Temperature E: -40 to 85 °C T: 0 to 70 °C Feedback Divider L: Disabled (external required) M: Factory Set Absolute Pull Range E: ± 20 ppm H: ± 32 ppm K: ± 50 ppm S: ± 100 ppm 1. Not all combinations are possible. Please consult with your Vectron representative for application assistance. Other frequencies available upon request. 2. When ordering the FX-702 with the external divider option, the prescaler is set to 1. The Feedback Divider = FOUT/FIN. 3. Vectron will determine and recommend a specific part number based upon the application. The Enhanced Mode version of the FX-702 activates additional internal dividers. Example: FX-702-ECE-KMMM-M3-M3 (156.25 MHz Jitter Attenuator) Example: FX-702-EDT-SLMM-F7-L4 (25 MHz to 125 MHz Frequency Translator with external divide-by-5) Example: FX-702-ECE-SMXM-C4-L4 (10 MHz to 125 MHz Frequency Translator; Enhanced Mode) 9 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 9 Rev: 03Sep2015 Revision History Date Approved Description 03Sep2015 MK, TM 02Mar2014 MK Update of Lasermarking image Vectron Logo changed, Vectron Address Shanghai changed 07May2013 BW Updated current specification, mid levels, added application diagrams, and revised ordering information to include Enhanced Mode. 15Feb2013 BW Updated the outline diagram shown in Figure 5. 06Oct2010 BW Updated frequency code table. 01Jun2010 BW Added ±20ppm APR ordering option. 12Mar2010 BW Added the “LN”frequency code to Table 8. For Additional Information, Please Contact USA: Vectron International 267 Lowell Road, Suite 102 Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328 Europe: Vectron International Potsdamer Strasse, D-14513 Teltow, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30 Asia: Vectron International 68 Yin Cheng Road (C), 22nd Floor One LuJiaZui Pudong, Shanghai, 200120 China Tel: +86.21.6194.6886 Fax: +86.21.6194..6699 Disclaimer Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. 10 of 10 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com 10 Rev: 03Sep2015