SPECIFICATIONS FOR
LCD MODULE
CUSTOMER
CUSTOMER PART NO.
AMPIRE PART NO.
APPROVED
AM-320240NSTNQW-W1H
BY
DATE
Approved For Specifications
Approved For Specifications & Sample
AMPIRE CO., LTD.
Building D., 2F., No.88, Sec. 1, Sintai 5th Rd., Sijhih City,
Taipei County 221, Taiwan (R.O.C.)
台北縣汐止市新台五路一段 88 號 2 樓(東方科學園區 D 棟)
TEL:886-2-26967269 , FAX:886-2-86967196 or 26967270
APPROVED BY
Date : 2008/2/5
CHECKED BY
AMPIRE CO., LTD.
ORGANIZED BY
1
RECORD
Revision
Date
2008/2/5
OF
REVISION
Page
Contents
Editor
-
New Release
Edward
Date : 2008/2/5
AMPIRE CO., LTD.
2
1 Features
5.7 inch Amorphous-TFT-LCD (Thin Film Transistor Liquid Crystal Display)
module. This module is composed of a 5.7” TFT-LCD panel, LCD controller,
power driver circuit and backlight unit.
1.1 TFT Panel Feature :
(1) Construction: 5.7” a-Si color TFT-LCD, White LED Backlight and PCB.
(2) Resolution (pixel): 320(R.G.B) X240
(3) Number of the Colors : 262K colors ( R , G , B 6 bit digital each)
(4) LCD type : Transmissive Color TFT LCD ( normally White)
(5) Interface: 33 pin pitch 0.5 FFC
(6) Power Supply Voltage: 3.3V single power input. Built-in power supply
circuit.
(7) Viewing Direction:12 O’clock (The direction it’s hard to be discolored ):
1.2 LCD Controller Feature:
(1) MCU interface 8/9/16/18 bit 80&68 series MCU interface.
(2) Display RAM size : 640x240x3x6 bits. Ex:320x240 two frame buffer
with 262K colors.
(3) Arbitrary display memory start position selection.
(4) MCU interface : 16 bit 80 MPU interface.
(5) 8 bit / 16 bit interface support 65K ( R5G6B5) /262K(R6G6B6) colors
data format.
(6) 9 bit / 18 bit interface support 262K(R6G6B6) colors data format only.
2 Physical specifications
Item
Display resolution(dot)
Active area
Screen size
Pixel size
Color configuration
Overall dimension
Weight
Backlight unit
Date : 2008/2/5
Specifications
960 (W) x 240(H)
115.2 (W) x 86.4 (H)
5.7(Diagonal)
120 (W) x 360 (H)
R.G.B stripe
144.0(W)x104.6(H)x13.0(D)
T.B.D
LED
AMPIRE CO., LTD.
Unit
Mm
Mm
Mm
Um
Mm
Mg
3
3 Default Setting & Option
z Interface :
The user can select the MCU interface by change the Jumper & Resister Array.
Setting
JP1
RA1
RA2
RA3
RA4
Remark
Interface Type
80-18Bit interface
80-16Bit interface
80-9Bit interface
80-8Bit interface
68-18Bit interface
68-16Bit interface
68-9Bit interface
68-8Bit interface
z Connector
33Pin Pin Header
( Pitch 0.5 x 33 pin)
Date : 2008/2/5
1,2 short
2,3 open
1,2 short
2,3 open
1,2 short
2,3 open
1,2 short
2,3 open
1,2 open
2,3 short
1,2 open
2,3 short
1,2 open
2,3 short
1,2 open
2,3 short
2K
OPEN OPEN OPEN
ohm
OPEN
2K
OPEN OPEN
ohm
OPEN OPEN
2K
OPEN
ohm
OPEN OPEN OPEN
2K
ohm
2K
OPEN OPEN OPEN
ohm
OPEN
2K
OPEN OPEN
ohm
OPEN OPEN
2K
OPEN
ohm
OPEN OPEN OPEN
2K
ohm
80/68 8/9/16/18 bit interface
AMPIRE CO., LTD.
Default
Defaul
4
4 Electrical specification
4.1 Absolute max. ratings
4.1.1 Electrical Absolute max. ratings
Item
Symbol Condition
Power voltage
VDD
Input voltege
V in
B
VSS=0
B
Min.
Max.
Unit
-0.3
5.5
V
-0.3
VDD+0.3
V
Remark
Note 1
Note1: /CS,/WR,/RD,RS,DB0~DB7
4.1.2 Environmental Absolute max. ratings
OPERATING
STORAGE
Item
MIN
MAX
MIN
MAX
Temperature
-20
70
-30
80
Humidity
Note1
Note1
Corrosive Gas
Not Acceptable
Not Acceptable
Remark
Note2,3,4,5,6,7
Note1 : Ta <= 40℃ : 85% RH max
Ta > 40℃ : Absolute humidity must be lower than the humidity of
85%RH at 40℃
Note2 : For storage condition Ta at -30℃ < 48h , at 80℃ < 100h
For operating condition Ta at -20℃ < 100h
Note3 : Background color changes slightly depending on ambient
temperature. This phenomenon is reversible.
Note4 : The response time will be slower at low temperature.
Note5 : Only operation is guarantied at operating temperature. Contrast ,
response time, another display quality are evaluated at +25℃
Note6 :
z LED BL : When LCM is operated over 40℃ ambient temperature, the
I LED of the LED back-light should be follow :
B
B
Note7 : This is panel surface temperature, not ambient temperature.
Note8 :
z LED BL:When LCM be operated over than 40℃ , the life time of the
LED back-light will be reduced.
Date : 2008/2/5
AMPIRE CO., LTD.
5
4.1.3 LED back-light Unit Absolute max. ratings
Item
Symbol
Ratings
Unit
Peak forward Current
IF
500
mA
Reverse Voltage
VR
12
V
Power Dissipation
Po
6.0
W
Remark
4.2 Electrical characteristics
4.2.1 DC Electrical characteristic of the LCD
Typical operating conditions (VSS=0V)
Symbol Min.
Typ. Max.
Item
Power supply
Input Voltage
for logic
Output Voltage for
Logic
H Level
Unit
VDD
3.1
5.0
5.2
V
V IH
2.0
-
5.5
V
B
B
Remark
Note 1
L Level
V IL
H Level
V OH
B
B
B
B
VSS
-
0.8
V
2.4
-
VDD
V
Note 2
L Level
Power Supply current
V OL
VSS
IDD
-
B
B
150
0.4
V
-
mA
Note 3
Note1: With 5V Tolerance Input , /CS, /WR,/RD,RS,DB0~DB17
Note2: DB0~DB17
Note3: fV =60Hz , Ta=25℃ , VDD=3.3V , DCLK=10MHz, PLL frequency=40MHz,
Display pattern : All Black
Date : 2008/2/5
AMPIRE CO., LTD.
6
4.2.2 Electrical characteristic of LED Back-light
Paramenter
Symbol
Min.
Typ.
Max.
Unit
LED voltage
V AK
--
9.9
--
V
LED forward
current
I LED
--
480
500
mA
I LED
--
305
330
mA
10,000
-
-
Hr
B
B
B
Lamp life time
B
B
B
Condiction
I LED
=480mA,Ta=25℃
Ta=25℃
B
B
Ta=60℃
I LED
=480mA,Ta=25℃
B
B
The constant current source is needed for white LED back-light driving.
When LCM is operated over 60℃ ambient temperature, the I LED of the LED
back-light should be adjusted to 360mA max
B
Date : 2008/2/5
AMPIRE CO., LTD.
B
7
3.3
AC Timing characteristic of the Graphic TFT LCD controller
4.3 80 series Timing
Symbol
tcycle
PWHW
PWLW
tAS
tAH
tDSW
tHWR
tcsb-s
tcsb-h
Parameter
Enable cycle time
Enable high-level pulse width
Enable low-level pulse width
RS setup time
RS hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
Date : 2008/2/5
Min
100
66
33
16
16
50
50
16
16
Typ
200
70
130
25
45
50
40
20
30
AMPIRE CO., LTD.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remark
8
4.4 68eries Timing
Symbol
tcycle
PWEH
PWEL
tASE
tAHE
tDSWE
tHE
tcsb-s
tcsbh
Parameter
Enable cycle time
Enable high-level pulse width
Enable low level pulse width
RS setup time
RS hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
Date : 2008/2/5
Min
100
66
33
16
16
50
50
16
16
Typ
200
70
130
25
45
50
40
20
30
AMPIRE CO., LTD.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remark
9
5 Optical specification
5.1 Optical characteristic :
Item
Response
Time
Symbol
Conditon
Min.
Typ.
Max.
Unit
Remark
Tr
Tf
Θ=0°
-
15
35
30
50
ms
ms
Note 1,2,3,5
At optimized
viewing angle
200
350
-
CR≧10
55
45
55
55
60
50
60
60
-
deg.
Note1,2, 5,6
I LED =480mA,
25℃
--
800
-
cd/m 2
Note 7
Rise
Fall
Contrast ratio
Top
Botto
Viewing
m
Angle
Left
Right
Brightness
LED BL
B
B
B
B
CR
B
B
Note 1,2,4,5
P
P
XR
0.610
0.640 0.670
Note 7
YR
0.314
0.344 0.374
For reference
XG
0.268
0.298 0.328
Green chromaticity
only. These
YG
0.553
0.583 0.613
Θ=0°
data should
Θ=0°
XB
0.102
0.132 0.162
be update
Blue chromaticity
YB
0.107
0.137 0.167
according the
XW
0.282
0.312 0.342
prototype.
White chromaticity
YW
0.299
0.329 0.359
( )For reference only. These data should be update according the prototype.
Red chromaticity
Note 1: LED BL :Ambient temperature=25℃,and lamp current I LED =480mA.To be
measured in the dark room.
Note 2:To be measured on the center area of panel with a viewing cone of 1°by
Topcon luminance meter BM-7,after 10 minutes operation.
B
B
Note 3.Definition of response time:
The output signals of photo detector are measured when the input signals
are changed from “black“ to “white”(falling time) and from”white” to “black”
(rising time),respectively.The response time is defined as the time interval
between the 10% and 90% of amplitudes. Refer to figure as below.
Date : 2008/2/5
AMPIRE CO., LTD.
10
Note 4.Definition of contrast ratio:
Contrast ratio is calculated with the following formula.
Contrast ratio(CR)=
Photo detector output when LCD is at ”White” state
Photo detector Output when LCD is at “Black” state
Note 5:White V i =V i50 +1.5V
B
B
B
B
Black V i =V i50 +2.0V
“±”means that the analog input signal swings in phase with V COM signal.
“ “ means that the analog input signal swings out of phase with V COM
signal.
B
B
B
B
B
B
B
B
V i50 : The analog input voltage when transmission is 50%.The 100%
Transmission is defined as the transmission of LCD panel when all the
Input terminals of module are electrically opened.
B
B
Note 6.Definition of viewing angle,Refer to figure as below.
Date : 2008/2/5
AMPIRE CO., LTD.
11
Note 7.Measured at the center area of the panel when all the input terminals of
LCD panel are electrically opened.
Ring light
Brightness gauge
BM-7 (Topcon)
LCD module
Metal halide lamp
Glass fiber
LIGHT:OFF, LIGHT:ON
LCD
Optical Detector
Brightness gauge
BM-7 (Topcon)
LED / CCFL
Date : 2008/2/5
LIGHT:ON, LIGHT:OFF
AMPIRE CO., LTD.
12
5.2 Optical characteristic of the LED Back-light
ITEM
MIN
TYP
MAX
UNIT
Condition
Bare Brightness
-11000
-Cd/m2
I LED =480mA,Ta=25℃
AVG. X of 1931 C.I.E.
0.28
0.31
0.34
-I LED =480mA,Ta=25℃
AVG. X of 1931 C.I.E.
0.28
0.31
0.34
-I LED =480mA,Ta=25℃
Brightness Uniformity
75
--%
I LED =480mA,Ta=25℃
( )For reference only. These data should be update according the prototype.
B
B
B
B
B
B
B
B
Note1 : Measurement after 10 minutes from LED BL operating.
Note2 : Measurement of the following 9 places on the display.
Note3: The Uniformity definition
(Min Brightness / Max Brightness) x 100%
Date : 2008/2/5
AMPIRE CO., LTD.
13
6 Interface specifications
6.1 Driving signals for the TFT panel
Pin no Symbol I/O
Description
Remark
1
/RESET I Reset Signal
2
80 Series: Write Signal
/WR
I
68 Series: R/W Signal
3
/CS
I Chip Select Signal
4
RS
I Data type selection
5
80 Series: Read signal
RD
II
68 Series: Enable signal(E)
6
D0
I/O
7
D1
I/O
8
D2
I/O
9
D3
I/O
Data input/output
10
D4
I/O
11
D5
I/O
12
D6
I/O
13
D7
I/O
14
DGND
I Ground
15
D8
I/O
16
D9
I/O
17
D10
I/O
18
D11
I/O
19
D12
I/O
20
D13
I/O Data input/output
21
D14
I/O
22
D15
I/O
23
D16
I/O
24
D17
I/O
25
VDD
P Power Supply for Logic
26
VDD
P
27
DGND
P Ground
28
DGND
P
29
When use 8 or 16 bit MPU interface. The 65k/262k
data format can be select. Lo:65K Hi:262K colors
65K/262K I
When use 9 or 18bit MPU interface. The 262K data
can be used only. The 65K/262K pin must set to Hi
30
DGND
P Ground
31
NC
Not use
32
NC
Not use
33
NC
Not use
Date : 2008/2/5
AMPIRE CO., LTD.
14
7 BLOCK DIAGRAM
Date : 2008/2/5
AMPIRE CO., LTD.
15
8 Interface Protocol
8.1 16Bit-80/68- Write to Command Register
8.2 16Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[15:0]
Note1
Note2
Note3
Note4
Note5
Display
RAM
Write Enable
0x000C1
Send
Data1
Send
Data2
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[15:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[15:0] represent the writing Data1 to Display RAM
Note3: DB[15:0] represent the writing Data2 to Display RAM
Note4: DB[15:0] represent the writing DataN to Display RAM
Note5: DB[15:0] send 0x00080 to Disable the Display RAM write.
Date : 2008/2/5
AMPIRE CO., LTD.
16
8.3 Data transfer order Setting
8.3.1 16 bit interface 65K color (JP2 1,2 short 65K/262K =Low)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
8.3.2 16 bit interface 262K color (JP2 2,3 short 65K/262K =High)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1 st data
X X X X X X X X X X X X X X
P
P
2 nd data
P
P
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
1
0
B1
B0
1
0
R5
B1
R4
B0
9 Register Depiction
Register
Address
(Hex)
00
Description
Register
Address
(Hex)
01
Description
Register
Address
(Hex)
02
Description
Register
Address
(Hex)
03
Description
Register
Address
(Hex)
04
Description
Register
Address
(Hex)
05
Description
Register
Address
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis end position
01
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis end position
3F
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis start position
00
set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LSB of Y-axis start position
00
Set the vertical start position of display active region
Default
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
Date : 2008/2/5
AMPIRE CO., LTD.
Remark
Remark
17
(Hex)
MSB of Y-axis end position
06
00
Description set the vertical end position of display active region
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
LSB of Y-axis end position
07
EF
Description Set the vertical end position of display active region
Remark
To simplify the address control of display RAM access, the window area address
function
allows for writing data only within a window area of display RAM specified by
registers REG[00]~REG[07] .
After writing data to the display RAM, the Address counter will be increased within
setting window address-range which is specified by
MIN X address (REG[0] & REG[1])
MAX X address (REG[2] & REG[3])
MIN Y address (REG[4] & REG[5])
MAX Y address (REG[6] & REG[7])
Therefore, data can be written consecutively without thinking the data address.
Date : 2008/2/5
AMPIRE CO., LTD.
18
Register
Address
(Hex)
08
Default
DB7 DB6 DB5 DB4
(Hex)
01
X
X
X
X
DB3
DB2
X
X
DB1
DB0
Remark
_PanelXSize
H_Byte[1:0]
Description Set the panel X size
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1
(Hex)
(Hex)
09
40
_PanelXSize L_Byte[7:0]
Description Set the panel X size
DB0
Remark
The register REG[08] and REG[09] is use to calculate the RAM address. If you
want to use the TFT as Landscape mode (320x240), the REG[08] & RGE[09 must
set to 320. If you want to use the TFT as Portrait mode (240x320), the REG[08] &
RGE[09] must set to 240.
Register
Address
(Hex)
Default
(Hex)
0A
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
[17:16] bits of
memory write start
address
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
0B
00
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[7:0] bits of memory write start address
0C
00
Description Memory write start address
Register
Address
(Hex)
0x10
Default
(Hex)
DB7
DB6
DB5 DB4
Remark
DB3
DB2
Remark
Remark
DB1 DB0 Remark
BUS_SEL
Blanking P/S_SEL
CLK_SEL
0x0D Bit_SWAP OUT_TEST
"0x10_Clk_sel[1:0]" : The TFT controller built-in 40Mhz PLL clock. These bits
Description are for select the TFT panel dot clock frequency.
00 : 20Mhz 01: 10Mhz 02: 5 Mhz
"0x10_ps_sel[2]" : The TFT controller support parallel and serial RGB
interface. These bits are for select the output timing.
Date : 2008/2/5
AMPIRE CO., LTD.
19
0 : serial Panel 1: Parallel panel
"0x10_blanking_tmp[3]"
0 : OFF (blanking) 1: ON ( normal operation)
"0x10_bus_sel[5:4]" : It only for serial Panel
00=R , 01=G , 10=B
"0x10_out_test[6]" : Self test
0 : normal operation 1: for test (don’t use for normal operation)
When set the bit to “1” , the Rout=(Reg 2a[6:0]) Gout=(Reg 2b[6:0])
Bout=(Reg 2c[6:0])
"0x10_bit_swap[7]" : 0-normal
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
0x11
Description
Register
Address
(Hex)
0x12
Default
(Hex)
DB7
DB6
DB5 DB4
DB3
DB2
DB1 DB0 Remark
X
X
EVEN
_ODD
00
" Even line of serial panel data out sequence or data bus order of parallel
panel
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Odd line of serial panel data out sequence
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Must Set to 0x05 for AM320240N1
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_stH_Byte[3:0]
For TFT output timing adjust:
Description Hsync start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x13
00
Hsync_stL_Byte[7:0]
For TFT output timing adjust:
Description Hsync start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Date : 2008/2/5
AMPIRE CO., LTD.
20
Register
Address
(Hex)
0x14
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description Hsync pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x15
10
Hsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description Hsync pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x16
00
Hact_stH_Byte[3:0]
For TFT output timing adjust:
Description DE pulse start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x17
38
Hact_stL_Byte[7:0]
For TFT output timing adjust:
Description DE pulse start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x18
01
Hact_pwH_Byte[3:0]
For TFT output timing adjust:
Description DE pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x19
40
Hact_pwL_Byte[7:0]
For TFT output timing adjust:
Description DE pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1A
01
HtotalH_Byte[3:0]
For TFT output timing adjust:
Description Hsync total clocks H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Date : 2008/2/5
AMPIRE CO., LTD.
21
Register
Address
(Hex)
0x1B
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
B8
HtotalL_Byte[7:0]
For TFT output timing adjust:
Description Hsync total clocks H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1C
00
Vsync_stH_Byte[3:0]
For TFT output timing adjust:
Description Vsync start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1D
00
Vsync_stL_Byte[7:0]
For TFT output timing adjust:
Description Vsync start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1E
00
Vsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description Vsync pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1F
08
Vsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description Vsync pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x20
00
Vact_stH_Byte[3:0]
For TFT output timing adjust:
Description Vertical DE pulse start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x21
12
Vact_stL_Byte[7:0]
For TFT output timing adjust:
Description Vertical DE pulse start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Date : 2008/2/5
AMPIRE CO., LTD.
22
Register
Address
(Hex)
0x22
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vact_pwH_Byte[3:0]
For TFT output timing adjust:
Description Vertical Active width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x23
F0
Vact_pwL_Byte[7:0]
For TFT output timing adjust:
Description Vertical Active width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x24
01
VtotalH_Byte[3:0]
For TFT output timing adjust:
Description Vertical total width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x25
09
VtotalL_Byte[7:0]
For TFT output timing adjust:
Description Vertical total width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
Default
(Hex)
26
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
[17:16] bits of
memory read start
address
Description Memory read start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
27
00
Description Memory read start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[7:0] bits of memory write start address
28
00
Description Memory read start address
Date : 2008/2/5
AMPIRE CO., LTD.
Remark
Remark
Remark
23
Register
Address
(Hex)
29
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
DB0
Remark
[7:1] Reversed
00
[0] Load output timing related setting (H sync., V sync. and DE) to take
Description
effect
Register
Address
(Hex)
0x2A
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00
X
TestPatternRout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Rout data equal to TestPatternRout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x2B
00
X
TestPatternGout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Gout data equal to TestPatternGout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x2C
00
X
TestPatternBout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Bout data equal to TestPatternBout[6:0]
Remark
Remark
Remark
If you set the " REG[0x10]_out_test[6]" : Self test =1 , the TFT controller will skip
the connect of the display RAM. The Output port will send the
REG[2A] ,REG[2B],REG[2C] data.
Register
Address
(Hex)
Default
DB7 DB6 DB5 DB4 DB3
(Hex)
DB2
DB1 DB0 Remark
Rising/falling
_rotate
edge[2]
[1:0]
[3] Output pin X_DCON level control ; TFT Power ON/OFF control
Description 0: TFT POWER circuit OFF
1: TFT POWER circuit ON
Rising/falling edge[2] :
0: The RGB out put data are on the Rising edge of the DCLK.
1: The RGB out put data are on the Falling edge of the DCLK.
0x2D
00
Date : 2008/2/5
X
X
X
X
[3]
AMPIRE CO., LTD.
24
_rotate [1:0]:
00 : rotate 0 degree
01 : rotate90 degree
10 : rotate 270 degree
11 : rotate 180 degree
Register
Address
(Hex)
Default
(Hex)
30
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
DB2 DB1 DB0
X
_H byte
H-Offset[3:0]
Description Set the Horizontal offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
31
00
_L byte H-Offset[7:0]
Description Set the Horizontal offset
Register
Address
(Hex)
Default
(Hex)
32
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
DB2 DB1 DB0
X
_H byte
V-Offset[3:0]
Description Set the Vertical offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
33
00
_L byte V-Offset[7:0]
Description Set the Vertical offset
Register
Address
(Hex)
34
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
Remark
Remark
Remark
Remark
Remark
_H byte
H-def[3:0]
[3:0] MSB of image horizontal physical resolution in memory
00
[7:4] Reserved
Description
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
35
40
_L byte H-def[7:0]
Description [7:0] LSB of image horizontal physical resolution in memory
Date : 2008/2/5
AMPIRE CO., LTD.
Remark
25
Register
Address
(Hex)
36
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
Remark
_H byte
V-def[3:0]
[3:0] MSB of image vertical physical resolution in memory
01
[7:4] Reserved
Description
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
37
E0
_L byte V-def[7:0]
Description [7:0] LSB of image vertical physical resolution in memory
Remark
The total RAM size is 640x240x18bit. The user can arrange the Horizontal ram
size by REG[34],REG[35] and the Vertical ram size by REG[36],REG[37].
EX: 320x480x18bit REG[34]=0x01 , REG[35]=0x40 , REG[36]=0x01 ,
REG[37]=0xE0
EX: 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
10 Application Note:
void main(void)
{
Initial_AMP506 ( );
Full_386SCR(0xf800);
Full_386SCR(0x07e0);
Full_386SCR(0x001f);
}
void AMP506_80Mode_Command_SendAddress(BYTE Addr)
{
SET_nRD;
// /RD=1
CLR_RS;
// RS=0
CLR_CS1;
// /CS=0
CLR_nWRL;
// /WR=0
DB16OUT(Addr);
// Data Bus OUT
SET_nWRL;
///WR=1
SET_RS;
// RS=1
SET_CS1;
/
// CS=1
}
Date : 2008/2/5
AMPIRE CO., LTD.
26
void AMP506_80Mode_Command_SendData(BYTE Data)
{
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB16OUT(Data);
SET_nWRL;
SET_RS;
SET_CS1;
}
void AMP506_Command_Write(uint8 CMD_Address,uint8 CMD_Value)
{
AMP506_80Mode_Command_SendAddress(CMD_Address);
AMP506_80Mode_Command_SendData(CMD_Value);
}
void AMP506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit)
{
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB16OUT(Dat16bit>>8);
SET_nWRL;
// Low to High Latch Data to AMP506 Buffer
SET_CS1;
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB16OUT(Dat16bit);
SET_nWRL;
// Low to High Latch Data to AMP506 Buffer
SET_CS1;
Date : 2008/2/5
AMPIRE CO., LTD.
27
}
void Initial_AMP506(void)
{
AMP506_Command_Write(0x40,0x12); /*[7:6] Reserved
[5] PLL control pins to select out frequency range
0: 20MHz ~ 100MHz 1: 100MHz ~ 300MHz
[4] Reserved [3] Reserved
[2:1] Output Driving Capability
00: 4mA 01: 8mA 10: 12mA 11: 16mA
[0] Output slew rate
0: Fast 1: Slow
*/
AMP506_Command_Write(0x41,0x01);
AMP506_Command_Write(0x42,0x01);
//Set PLL=40Mhz * (0x42) / (0x41)
//0x41 [7:6] Reserved [5:0] PLL Programmable
pre-divider, 6bit(1~63)
//0x42 [7:6] Reserved [5:0] PLL Programmable loop
divider, 6bit(1~63)
AMP506_Command_Write(0x00,0x00);
AMP506_Command_Write(0x01,0x00);
// MSB of horizontal start coordinate value
// LSB of horizontal start coordinate value
AMP506_Command_Write(0x02,0x01);
// MSB of horizontal end coordinate value
AMP506_Command_Write(0x03,0x3F);
// LSB of horizontal end coordinate value
AMP506_Command_Write(0x04,0x00);
AMP506_Command_Write(0x05,0x00);
AMP506_Command_Write(0x06,0x01);
AMP506_Command_Write(0x07,0x3F);
// MSB of vertical start coordinate value
// LSB of vertical start coordinate value
// MSB of vertical end coordinate value
// LSB of vertical end coordinate value
AMP506_Command_Write(0x08,0x01);
// MSB of input image horizontal resolution
AMP506_Command_Write(0x09,0x40);
// LSB of input image horizontal resolution
AMP506_Command_Write(0x0a,0x00);
//[17:16] bits of memory write start address
AMP506_Command_Write(0x0b,0x00);
//[15:8] bits of memory write start address
AMP506_Command_Write(0x0c,0x00);
//[7:0] bits of memory write start address
AMP506_Command_Write(0x10,0x0D);
/*[7] Output data bits swap
0: Normal 1:Swap
[6] Output test mode enable 0: disable 1: enable
[5:4] Serial mode data out bus selection
00: X_ODATA17 ~ X_ODATA12 active , others are set to
zero
01: X_ODATA11 ~ X_ODATA06 active , others are set to
Date : 2008/2/5
AMPIRE CO., LTD.
28
zero
10: X_ODATA05 ~ X_ODATA00 active , others are set to
zero
11: reserved
[3] Output data blanking
0: set output data to 0
1: Normal display
[2] Parallel or serial mode selection
0: serial data out
1: parallel data output
[1:0] Output clock selection
00: system clock divided by 2
01: system clock divided by 4
10: system clock divided by 8
11: reserved */
AMP506_Command_Write(0x11,0x05);
/*[7] Reserved
[6:4] Even line of serial panel data out sequence or data bus order of parallel panel
000: RGB
001: RBG
010: GRB
011: GBR 100: BRG 101: BGR
Others:
reserved
[3] Reversed
[2:0] Odd line of serial panel data out sequence
000: RGB
reserved
001: RBG
010: GRB
011: GBR 100: BRG
101: BGR Others:
*/
AMP506_Command_Write(0x12,0x00);
// [3:0] MSB of output H sync. pulse start
AMP506_Command_Write(0x13,0x00);
//[7:0] LSB of output H sync. pulse start position
AMP506_Command_Write(0x14,0x00);
// [3:0] MSB of output H sync. pulse width
position
AMP506_Command_Write(0x15,0x10);
//[7:0] LSB of output H sync. pulse width
AMP506_Command_Write(0x16,0x00);
//[3:0] MSB of output DE horizontal start
AMP506_Command_Write(0x17,0x38);
//[7:0] LSB of output DE horizontal start
position
position
AMP506_Command_Write(0x18,0x01); //[3:0] MSB of output DE horizontal active region in
pixel
AMP506_Command_Write(0x19,0x40);
//[7:0] LSB of output DE horizontal active region
in pixel
AMP506_Command_Write(0x1a,0x01);
//[7:4] Reserved [3:0] MSB of output H total in
pixel
Date : 2008/2/5
AMPIRE CO., LTD.
29
AMP506_Command_Write(0x1b,0xb8);
//[7:0] LSB of output H total in pixel
AMP506_Command_Write(0x1c,0x00);
//[3:0] MSB of output V sync. pulse start
position
AMP506_Command_Write(0x1d,0x00);
//[7:0] of output V sync. pulse start position
AMP506_Command_Write(0x1e,0x00);
//[7:4] Reserved [3:0] MSB of output V sync.
pulse width
AMP506_Command_Write(0x1f,0x08);
//[7:0] LSB of output V sync. pulse width
AMP506_Command_Write(0x20,0x00);
// [3:0] MSB of output DE vertical start position
AMP506_Command_Write(0x21,0x12);
//[7:0] LSB of output DE vertical start position
AMP506_Command_Write(0x22,0x00);
// [3:0] MSB of output DE vertical active region
in line
AMP506_Command_Write(0x23,0xf0);
//[7:0] LSB of output DE vertical active region
in line
AMP506_Command_Write(0x24,0x01);
//[7:4] Reversed [3:0] MSB of output V total in
AMP506_Command_Write(0x25,0x09);
//[7:0] LSB of output V total in line
AMP506_Command_Write(0x26,0x00);
// [17:16] bits of memory read start address
AMP506_Command_Write(0x27,0x00);
//[7:0] [15:8] bits of memory read start address
AMP506_Command_Write(0x28,0x00);
//[7:0] [7:0] bits of memory read start address
line
AMP506_Command_Write(0x29,0x01);
//[7:1] Reversed [0] Load output timing related setting (H sync., V sync. and DE) to take effect
AMP506_Command_Write(0x2d,0x08); /* [7:4] Reserved
[3] Output pin X_DCON level control
[2] Output clock inversion
0: Normal 1: Inverse
[1:0] Image rotate
00: 0° 01: 90° 10: 270° 11: 180°
*/
AMP506_Command_Write(0x30,0x00); //[7:4] Reserved [3:0] MSB of image horizontal shift
value
AMP506_Command_Write(0x31,0x00); //[7:0] LSB of image horizontal shift value
AMP506_Command_Write(0x32,0x00); //[7:4] Reserved [3:0] MSB of image vertical shift
value
AMP506_Command_Write(0x33,0x00); //[7:0] LSB of image vertical shift value
AMP506_Command_Write(0x34,0x01);
// [3:0] MSB of image horizontal physical Resolution in memory
AMP506_Command_Write(0x35,0x40);
//[7:0] LSB of image horizontal physical resolution in memory
AMP506_Command_Write(0x36,0x01);
Date : 2008/2/5
AMPIRE CO., LTD.
30
//[7:4] Reserved [3:0] MSB of image vertical physical resolution in memory
AMP506_Command_Write(0x37,0xe0);
//[7:0] LSB of image vertical physical resolution in memory
}
void AMP506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y)
{
AMP506_80Mode_Command_SendAddress(0x00);
AMP506_80Mode_Command_SendData((S_X)>>8);
AMP506_80Mode_Command_SendData(S_X);
AMP506_80Mode_Command_SendData((E_X-1)>>8);
AMP506_80Mode_Command_SendData(E_X-1);
AMP506_80Mode_Command_SendData(S_Y>>8);
AMP506_80Mode_Command_SendData(S_Y);
AMP506_80Mode_Command_SendData((E_Y-1)>>8);
AMP506_80Mode_Command_SendData(E_Y-1);
}
void Full_386SCR(uint16 Dat16bit)
{
int32 k,l;
AMP506_WindowSet(0,0,Resolution_X,Resolution_Y);
AMP506_80Mode_Command_SendAddress(0xc1); //_DisplayRAM_WriteEnable_
for(k=0;k<240*2;k++)
{
for(l=0;l<320;l++)
{
AMP506_80Mode_16Bit_Memory_SendData(Dat16bit);
}
}
AMP506_80Mode_Command_SendAddress(0x80); // DisplayRAM_WriteDisable _
}
Date : 2008/2/5
AMPIRE CO., LTD.
31
The TFT LCD controller default value is for AM320240NS already. So we can start
to write our data in a few steps:
Target: To write a 640x240 data to Display RAM and scroll the display data by
change the Horizontal offset register.
10.1 Step 1: Make sure the interface Protocol.
10.2 Step 2: Define the Horizontal ram seize = 640 and Vertical ram size =240
640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
10.3 Step 3: Define the Panel X Size = 320
REG[8]=0x01 , REG[9]=0x40
10.4 Step4: Define the Write window. Start=(0,0) End=(619,239)
REG[0]=0x00 , REG[1]=0x00 , REG[2]=0x02 , REG[3]=0x6B , // Start X , End
X
REG[4]=0x00 , REG[5]=0x00 , REG[6]=0x00 , REG[7]=0xEF , // Star Y ,End Y
Date : 2008/2/5
AMPIRE CO., LTD.
32
10.5 Step5: Write the 640x240x18 bit data consecutively
10.6 Step6: The display will show the following image.
10.7 Step7: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 160 , REG[30]=00 REG[31]=A0 . You will see
Date : 2008/2/5
AMPIRE CO., LTD.
33
10.8 Step8: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 320 , REG[30]=01 REG[31]=40 . You will see
Date : 2008/2/5
AMPIRE CO., LTD.
34
DISPLAYED COLOR AND INPUT DATA
Color &
Gray
Scale
Basic
Color
Red
Green
Blue
Black
Red(0)
Green(0)
Blue(0)
Cyan
Magenta
Yellow
White
Black
Red(62)
Red(61)
:
Red(31)
:
Red(1)
Red(0)
Black
Green(62)
Green(61)
:
Green(31)
:
Green(1)
Green(0)
Black
Blue(62)
Blue(61)
:
Blue(31)
:
Blue(1)
Blue(0)
DATA SIGNAL
R5
0
1
0
0
0
1
1
1
0
0
0
:
0
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R4
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
Date : 2008/2/5
R3
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R2
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R1
0
1
0
0
0
1
1
1
0
0
1
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R0
0
1
0
0
0
1
1
1
0
1
0
:
1
:
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
G5
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
1
1
0
0
0
:
0
:
0
0
G4
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
G3
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
G2
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
AMPIRE CO., LTD.
G1
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
1
:
1
:
1
1
0
0
0
:
0
:
0
0
G0
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
1
0
:
0
:
0
1
0
0
0
:
0
:
0
0
B5
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
0
:
1
1
B4
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B3
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B2
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B1
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
1
:
1
:
1
1
35
B0
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
1
0
:
1
:
0
1
11 QUALITY AND RELIABILITY
11.1 TEST CONDITIONS
Tests should be conducted under the following conditions :
Ambient temperature : 25 ± 5°C
Humidity
: 60 ± 25% RH.
11.2 SAMPLING PLAN
Sampling method shall be in accordance with MIL-STD-105E , level II,
normal single sampling plan .
11.3 ACCEPTABLE QUALITY LEVEL
A major defect is defined as one that could cause failure to or materially
reduce the usability of the unit for its intended purpose. A minor defect is one that
does not materially reduce the usability of the unit for its intended purpose or is an
infringement from established standards and has no significant bearing on its
effective use or operation.
11.4 APPEARANCE
An appearance test should be conducted by human sight at
approximately 30 cm distance from the LCD module under flourescent light. The
inspection area of LCD panel shall be within the range of following limits.
Date : 2008/2/5
AMPIRE CO., LTD.
36
11.5 INSPECTION QUALITY CRITERIA
No.
Item
1
Non display
2
Irregular
operation
Criterion for defects
Defect type
No non display is allowed
Major
No irregular operation is allowed
Major
3
Short
No short are allowed
Major
4
Open
Any segments or common patterns that don’t activate
are rejectable.
Major
5
6
7
8
Black/White
spot (I)
Black/White
line (I)
Black/White
sport (II)
Black/White
line (II)
9
Back Light
10
Display pattern
Size D (mm)
D < 0.15
0.15 < D < 0.20
0.20 < D < 0.30
0.30 < D
U
U
U
U
U
Length(mm)
10 < L
5.0 < L < 10
1.0 < L < 5.0
L < 1.0
U
U
U
U
U
U
Acceptable number
Ignore
3
2
0
U
0.03 < W
0.04 < W
0.06 < W
0.07 < W
<
<
<
<
U
U
U
U
U
U
U
U
0.04
0.06
0.07
0.09
Size D (mm)
D < 0.30
0.30 < D < 0.50
0.50 < D < 1.20
1.20 < D
U
U
U
U
Length (mm)
20 < L
10 < L < 20
5.0 < L < 10
L < 5.0
U
U
U
U
U
U
Acceptable number
Ignore
5
3
0
U
U
Acceptable number
5
3
2
1
Width (mm)
0.05 < W < 0.07
0.07 < W < 0.09
0.09 < W < 0.10
0.10 < W < 0.15
U
U
U
U
U
U
U
U
Acceptable number
5
3
2
1
1. No Lighting is rejectable
2. Flickering and abnormal lighting are rejectable
Unit:mm
A+B
≤ 0.30 0 < C
2
Minor
Minor
Minor
Minor
Major
Minor
D+E
F+G
≤ 0.25
≤ 0.25
2
2
Note: 1. Acceptable up to 3 damages
2. NG if there’re to two or more pinholes per dot
Date : 2008/2/5
AMPIRE CO., LTD.
37
Blemish &
Foreign matters
11
Size D (mm)
D < 0.15
0.15 < D < 0.20
0.20 < D < 0.30
0.30 < D
U
Size:
A+ B
D=
2
Scratch on
Polarizer
12
U
U
U
U
Width (mm)
W < 0.0
U
U
3
0.03<W < 0.05
U
U
0.05<W < 0.08
U
Acceptable number
Ignore
3
2
0
U
U
Length (mm)
Ignore
L < 2.0
L > 2.0
L > 1.0
L < 1.0
Note (1)
U
U
U
U
Acceptable number
Ignore
Ignore
1
1
Ignore
Note(1)
Minor
Minor
0.08<W
Note(1) Regard as a blemish
Bubble in
13 polarizer
Size D (mm)
D < 0.20
0.20 < D < 0.50
0.50 < D < 0.80
0.80 < D
U
U
U
U
U
U
Acceptable number
Ignore
3
2
0
Minor
Stains on
14 LCD panel
surface
Stains that cannot be removed even when wiped lightly
with a soft cloth or similar cleaning too are rejectable.
Minor
15
Rust which is visible in the bezel is rejectable.
Minor
Defect of
land surface
16 contact (poor
soldering)
Evident crevices which is visible are rejectable.
Minor
Parts
17 mounting
1. Failure to mount parts
2. Parts not in the specifications are mounted
3. Polarity, for example, is reversed
Parts
18 alignment
1. LSI, IC lead width is more than 50% beyond pad
outline.
2. Chip component is off center and more than 50% of
the leads is off the pad outline.
Major
Major
Major
Minor
Rust in Bezel
Conductive
foreign matter
19 (Solder ball,
Solder chips)
Faulty PCB
20 correction
1. 0.45<φ
,N≧1
2. 0.30<φ < 0.45 ,N≧1
φ:Average diameter of solder ball (unit: mm)
3. 0.50<L
,N≧1
L: Average length of solder chip (unit: mm)
1. Due to PCB copper foil pattern burnout, the pattern is
connected, using a jumper wire for repair; 2 or more
places are corrected per PCB.
2. Short circuited part is cut, and no resist coating has
been performed.
Date : 2008/2/5
U
U
AMPIRE CO., LTD.
Minor
Major
Minor
Minor
Minor
Minor
38
The TFT panel may have bright dot or Dark dot.
The acceptable number defection:
21
Defect Dot
Bright
dot
2
Dark dot Total dot
3
4
Distance
between
Dark-- dark
L≧5 mm
Minor
12 Reliability test items (Note2):
No.
1
2
3
4
5
6
7
8
9
Test items
Conditions
Ta=80℃
240Hrs
High temperature storage
Ta=-30℃
240Hrs
Low temperature storage
240Hrs
High temperature operation Ta=70℃
Ta=-20℃
240Hrs
Low temperature operation
High temperature and high Ta=40℃,85% RH
240Hrs
humidity
-30℃~80℃/200 cycles 1Hrs/cycle
Heat shock
±200V,200Pf(0Ω),once for each
Electrostatic discharge
terminal
Frequency range
:8~33.3Hz
Stoke
:1.3mm
Sweep
:2.9G,33.3~400Hz
Vibration
Cycle
:15 minutes
2 hours for each direction of X,Z
4 hours for Y direction
Mechanical shock
10
Vibration (With carton)
11
Drop (with carton)
Date : 2008/2/5
100G, 6ms,±X, ±Y,±Z
3 times for each direction
Random vibration:
0.015G 2 /Hz from 5~200Hz
-6dB/octave from 200~500Hz
Height:60cm
1 corner,3 edges,6 surfaces
P
P
AMPIRE CO., LTD.
Remark
Operation
Non-operation
Non-operation
JIS C7021,
A-10
Condition A
JIS C7021,
A-7
Condition C
IEC 68~34
JIS Z0202
39
13 USE PRECAUTIONS
13.1 Handling precautions
1) The polarizing plate may break easily so be careful when handling it. Do not
touch, press or rub it with a hard-material tool like tweezers.
2) Do not touch the polarizing plate surface with bare hands so as not to make it
dirty. If the surface or other related part of the polarizing plate is dirty, soak a
soft cotton cloth or chamois leather in benzine and wipe off with it. Do not use
chemical liquids such as acetone, toluene and isopropyl alcohol. Failure to do
so may bring chemical reaction phenomena and deteriorations.
3) Remove any spit or water immediately. If it is left for hours, the suffered part
may deform or decolorize.
4) If the LCD element breaks and any LC stuff leaks, do not suck or lick it. Also if
LC stuff is stuck on your skin or clothing, wash thoroughly with soap and water
immediately.
13.2 Installing precautions
1) The PCB has many ICs that may be damaged easily by static electricity. To
prevent breaking by static electricity from the human body and clothing, earth
the human body properly using the high resistance and discharge static
electricity during the operation. In this case, however, the resistance value
should be approx. 1MΩ and the resistance should be placed near the human
body rather than the ground surface. When the indoor space is dry, static
electricity may occur easily so be careful. We recommend the indoor space
should be kept with humidity of 60% or more. When a soldering iron or other
similar tool is used for assembly, be sure to earth it.
2) When installing the module and ICs, do not bend or twist them. Failure to do
so may crack LC element and cause circuit failure.
3) To protect LC element, especially polarizing plate, use a transparent protective
plate (e.g., acrylic plate, glass etc) for the product case.
4) Do not use an adhesive like a both-side adhesive tape to make LCD surface
(polarizing plate) and product case stick together. Failure to do so may cause
the polarizing plate to peel off.
13.3 Storage precautions
1) Avoid a high temperature and humidity area. Keep the temperature between
0°C and 35°C and also the humidity under 60%.
2) Choose the dark spaces where the product is not exposed to direct sunlight or
fluorescent light.
Date : 2008/2/5
AMPIRE CO., LTD.
40
3) Store the products as they are put in the boxes provided from us or in the
same conditions as we recommend.
13.4 Operating precautions
1) Do not boost the applied drive voltage abnormally. Failure to do so may break
ICs. When applying power voltage, check the electrical features beforehand
and be careful. Always turn off the power to the LC module controller before
removing or inserting the LC module input connector. If the input connector is
removed or inserted while the power is turned on, the LC module internal
circuit may break.
2) The display response may be late if the operating temperature is under the
normal standard, and the display may be out of order if it is above the normal
standard. But this is not a failure; this will be restored if it is within the normal
standard.
3) The LCD contrast varies depending on the visual angle, ambient temperature,
power voltage etc. Obtain the optimum contrast by adjusting the LC dive
voltage.
4) When carrying out the test, do not take the module out of the low-temperature
space suddenly. Failure to do so will cause the module condensing, leading to
malfunctions.
5) Make certain that each signal noise level is within the standard (L level:
0.2Vdd or less and H level: 0.8Vdd or more) even if the module has functioned
properly. If it is beyond the standard, the module may often malfunction. In
addition, always connect the module when making noise level measurements.
6) The CMOS ICs are incorporated in the module and the pull-up and pull-down
function is not adopted for the input so avoid putting the input signal open
while the power is ON.
7) The characteristic of the semiconductor element changes when it is exposed
to light emissions, therefore ICs on the LCD may malfunction if they receive
light emissions. To prevent these malfunctions, design and assemble ICs so
that they are shielded from light emissions.
8) Crosstalk occurs because of characteristics of the LCD. In general, crosstalk
occurs when the regularized display is maintained. Also, crosstalk is affected
by the LC drive voltage. Design the contents of the display, considering
crosstalk.
Date : 2008/2/5
AMPIRE CO., LTD.
41
13.5 Other
1) Do not disassemble or take the LC module into pieces. The LC modules once
disassembled or taken into pieces are not the guarantee articles.
2) The residual image may exist if the same display pattern is shown for hours.
This residual image, however, disappears when another display pattern is
shown or the drive is interrupted and left for a while. But this is not a problem
on reliability.
3) AMIPRE will provide one year warranty for all products and three months
warrantee for all repairing products.
Date : 2008/2/5
AMPIRE CO., LTD.
42
晶采 光 電 科技
14 OUTLINE DIMENSION
14.1 OUTLINE DIMENSION
AMPIRE
Date : 2008/2/5
AMPIRE CO., LTD.
43
晶采 光 電 科技
Date : 2008/2/5
AMPIRE CO., LTD.
44