Preliminary Data Sheet R2A25107KFP Intelligent Power Device for MOSFET Pre-drive R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Description The R2A25107KFP device is an intelligent power device to pre-drive the FET inverter of a 3-phase blushless motor. This device contains three sets of pre-driver that are applicable to both 12-V and 24-V battery systems. This IC also contains a step down converter, charge pump circuit for the power supply of high-side MOSFET gate driver, 5 V series regulator, watchdog timer and protection circuits for thermal shutdown (TSD) and over-current detection. Features Wide operating voltage range: 7 V to 36 V (VBAT, VBAT2) On-chip 3-phase pre-driver circuit PWM control: up to 20 kHz Totem pole type MOSFET gate drive circuit On-chip power supplies Step down converter: 6.2 V typ. Charge pump circuit for power supply of high-side FET drive: >5 V 5-V series regulator for MCU: <70 mA On-chip protection circuits Thermal shutdown (TSD) Over-current detection in the step down converter Over-current detection of motor current On-chip watchdog timer circuit (WDT) Band gap reference circuit Internal oscillator: 265 kHz typ. 48-pin LFQFP package Application Pre-driver for middle class 3-phase blushless motors (up to 50 A) Best suited for automotive Ordering Information Part No. R2A25107KFP#U5 Lead Plating Sn-Cu Packing Tray Package PLQP0048KB-A Note: The information contained in this document is the one that was obtained when the document was issued, and may be subject to change. R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 1 of 22 R2A25107KFP Preliminary Block Diagram VBAT2 VBAT 7~36 V CP2C PGND VGT 7~36 V STEP DOWN CONVERTER SDC Band-gap VBAT2+VGB VGT CHARGE PUMP Over current protection TSD VGB P1 *T HIGH SIDE PRE DRIVER Dead short Prevention PGND Dead short Prevention 6.2 V typ. * 6.2 V typ. 5V REGULATOR PRE INPUT MATRIX REGC 5 V ± 3% LOW SIDE PRE DRIVER *B Dead short Prevention Dead short Prevention OSC VCC *G Current Reference IREF POR MOTOR CURRENT LIMIT WDT + Over-current Detection MCS – SGND DGND DGND GND CLK RST I*T I*B MUTE MCD MCR 36 35 34 33 32 31 30 29 28 27 26 25 VGB N.C. SDC N.C. VBAT VBAT2 N.C. CP1 N.C. CP2 N.C. VGT Pin Arrangement 37 38 39 40 41 42 43 44 45 46 47 48 R2A25107KFP 24 23 22 21 20 19 18 17 16 15 14 13 N.C. PGND UG UB U UT N.C. VT V VB VG N.C. IWB IWT IVB IVT IUB IUT SGND MCS WG WB W WT 1 2 3 4 5 6 7 8 9 10 11 12 N.C. REGC VCC MUTE MCD MCR RST CLK GND DGND N.C. IREF (Top view) 48-pin LFQFP: PLQP0048KB-A (48P6Q-A) R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 2 of 22 R2A25107KFP Preliminary Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 IWB IWT IVB IVT IUB IUT SGND MCS WG WB W WT N.C. VG VB V VT N.C. UT U UB UG PGND N.C. VGT N.C. CP2 N.C. CP1 N.C. VBAT2 VBAT N.C. SDC N.C. VGB N.C. REGC VCC MUTE MCD Pin Name Function Input pin for low side of W phase Input pin for high side of W phase Input pin for low side of V phase Input pin for high side of V phase Input pin for low side of U phase Input pin for high side of U phase GND pin for Motor current Input pin for Motor current detection GND pin of W phase Output pin for low side gate drive of W phase Output pin of W phase Output pin for high side gate drive of W phase No connection GND pin of V phase Output pin for low side gate drive of V phase Output pin of V phase Output pin for high side gate drive of V phase No connection Output pin for high side gate drive of U phase Output pin of U phase Output pin for low side gate drive of U phase GND pin of U phase Power GND pin No connection Power supply pin of high side gate drive No connection Pin to connect external capacitor for charge pump 2 No connection Pin to connect external capacitor for charge pump 1 No connection Power supply pin of charge pump Power supply pin to connect battery No connection Output pin for step down converter drive No connection Power supply pin of low side gate drive No connection Output pin of 5-V series regulator 5 V power supply pin Input pin of mute Output pin of motor over-current detection 42 43 44 45 46 47 48 MCR RST CLK GND DGND N.C. IREF Input pin to reset motor over-current detection Output pin of reset Input pin of watchdog timer clock GND pin GND pin of digital circuit No connection Pin for reference current R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 3 of 22 R2A25107KFP Preliminary Absolute Maximum Ratings (Ta = –40 to 125°C, All of the voltages are with respect to GND, unless otherwise specified) Symbol Min. Ratings Typ. Max. Unit Battery power supply voltage Vbat –0.3 — 40 V Step down converter power supply voltage Vgb –0.3 — 40 V VBAT, VBAT2 pin, DC and short pulse (<500 ms) condition VGB pin Step down converter output voltage Vsdc –0.3 — 40 V SDC pin High side gate driver supply voltage CP1 pin voltage Vgt — 60 V VGT pin Vcp1 VBAT2 –0.6 –0.3 — Vgb +0.3 V CP1 pin CP2 pin voltage Vcp2 VBAT2 –0.3 — Vgt +0.3 V CP2 pin High side gate driver output voltage Motor output voltage Vto — Vgt +0.3 V UT, VT, WT pin Vo Vo –0.3 –1.0 — Vgt +0.6 V U, V, W pin Low side gate driver output voltage Motor GND voltage Vbo –0.3 — Vgb +0.3 V UB, VB, WB pin Vbg –1.0 — Vgb +0.6 V UG, VG, WG pin MCS voltage Vmcs –1.0 — V MCS pin 5 V power supply voltage 5 V Input/output voltage VREGC Vin –0.3 –0.3 — — Vcc +0.3 6.0 V REGC, VCC pin Vcc +0.3 V at IUT, IUB, IVT, IVB, IWT, IWB, MUTE, CLK, RST, MCR, MCD, IREF GND voltage Vgnd –0.3 — +0.3 V SGND~GND, DGND~GND, PGND~GND Pt — 2.55 — W Kt Tj Topr Tstg — — –40 –55 20.4 — — — — 150 125 150 mW/°C °C °C °C Simulation result, Ta = 25°C, See page 5 Simulation result, See page 5 Item Power dissipation Power dissipation derating rate Junction temperature Operating temperature Storage temperature Test Conditions Recommended Operating Conditions (Ta = –40 to 125°C, VBAT = VBAT2 = 7.0 to 36 V, VGB = 5.9 to 6.5 V, REGC = VCC = 4.85 to 5.15 V, unless otherwise specified) Item Battery power supply voltage Logic input voltage PWM input frequency Symbol Min. Typ. Max. Unit Vb VIN 7.0 0 — — 36 VCC V V Test Conditions Fpwm — 20 40 kHz IUT, IUB, IVT, IVB, IWT, IWB, MUTE, CLK, MCR pin IUT, IUB, IVT, IVB, IWT, IWB pin Hz CLK pin VBAT, VBAT2 pin *Note 1 WDT clock input frequency Note: Fwdt 200 — 5k *1 This value guarantees circuit operation only; the junction temperature is not considered. R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 4 of 22 R2A25107KFP Preliminary Power Dissipation Derating Curve 2.5 Power Dissipation Pdp (W) 2.55 W 2.0 1.5 1.0 0.51 W 0.5 0 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Simulated values Mounted on a Renesas standard circuit board (4 layers) Notes: *1 This data is obtained under recommended conditions and is not intended to guarantee the absolute maximum rating. *2 Actual power dissipation derating rate should be evaluated with this device mounted on the circuit board of the actual application. R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 5 of 22 R2A25107KFP Preliminary Electrical Characteristics (Ta = –40 to 125°C, VBAT = VBAT2 = 7.0 to 36 V, VGB = 5.9 to 6.5 V, REGC = VCC = 4.85 to 5.15 V, unless otherwise specified) Power Supply (VBAT, VBAT2, VGB, SDC, REGC, VCC, VGT, CP1, CP2, IREF) DC characteristics Item Battery power supply current Symbol IVBAT Min. — Typ. — Max. 3 Unit mA Step down converter power supply current IVGB — — 3 mA VGB pin, IUT, IUB, IVT, IVB, IWT, IWB: High, MUTE: Low VCC power supply current IVCC — — 5 mA VCC pin, IUT, IUB, IVT, IVB, IWT, IWB: High, MUTE: Low, IREF: High DGND current IDGND –10 — — A DGND pin, IUT, IUB, IVT, IVB, IWT, IWB: High, MUTE: Low, IREF: High Step down converter threshold voltage VthVGB 5.9 6.2 6.5 V VGB pin, VBAT = 12 V Step down converter output On resistance RVGB 0.92 2.3 6.0 SDC pin, VGB < 5.9 V, VBAT = 12 V, IL = –0.1 A Step down converter output leakage current ILVGB –10 — 0 A SDC pin, VGB > 6.5 V, VBAT = 12 V, SDC = 0 V Step down converter overcurrent detection current IlimVGB –1.4 –1.0 –0.6 A SDC pin, See figure 3 High side gate driver output voltage VGT VBAT2 +5.0 VBAT2 +5.5 VBAT2 +6.2 V VGT pin, VGB = 6.2 V, fCP1 = 135 kHz, Cp = 0.1 F, Cgb = 1.0 F, Io = 3 mA 5 V regulator output voltage Vo(REGC) 4.85 5.0 5.15 V VGB = 6.2 V, Io(external load) = 0 mA, CL = 33 F 5 V regulator output current Io(REG) REGIN –70 — — 5.0 — 30 mA mV VGB = 6.2 V REGOUT — 5.0 30 mV Io(external load) = 0~70 mA, VGB = 6.2 V Vo(IREF) TSDon TSDhys 1.16 170 30 1.25 200 40 1.34 230 50 V °C °C Item Symbol Step down converter OFF time at over-current detection TSDC Min. 10 Typ. 25 Max. 50 Unit s Test Conditions SDC pin, See figure 3 Step down converter driving frequency fSDC 205 265 325 kHz SDC pin, Rref = 47 k Charge pump driving frequency fCP1 105 135 165 kHz CP1 pin, Rref = 47 k High side gate drive precharge time TGT — 5.0 30 ms VGT pin, fCP1 = 135 kHz, Cp = 0.1 F, Cgt = 1.0 F, See figure 5 5 V regulator input voltage stability 5 V regulator load current stability IREF output voltage TSD temperature TSD hysteresis temperature Test Conditions VBAT, VBAT2 pin, IUT, IUB, IVT, IVB, IWT, IWB: High, MUTE: Low VGB = 5.9~6.5 V, Io(external load) = 0 mA Not subjected to production test, but guaranteed through designing. AC characteristics Note: Current flowing directions are: Plus (+) or none: from outside to IC, Minus (–): from IC to outside R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 6 of 22 R2A25107KFP Preliminary Electrical Characteristics (cont.) (Ta = –40 to 125°C, VBAT = VBAT2 = 7.0 to 36 V, VGB = 5.9 to 6.5 V, REGC = VCC = 4.85 to 5.15 V, unless otherwise specified) Watchdog Timer (CLK, RST, REGC) DC characteristics Item WDT start voltage Symbol Von Min. Typ. Max. Unit Test Conditions — 0.7 REGC 0.74 REGC V REGC low voltage detection reset voltage Vprl Vprh 0.90 REGC 100 0.93 REGC 140 V REGC low voltage detection hysteresis voltage CLK high level input voltage 0.87 REGC 60 WDT start operation when REGC Von REGC pin: HighLow mV VIH(CLK) — VCC V CLK pin CLK low level input voltage VIL(CLK) 0.7 VCC 0 — V CLK pin CLK high level input current CLK low level input current RST high level output voltage IIH(CLK) IIL(CLK) VOH(RST) A A V CLK = 5 V, Pull-Down = 100 k CLK = 0 V RST pin, Io = –2 mA RST low level output voltage VOL(RST) 0.8 VCC 0 0.3 VCC 250 0 VCC RST pin, Io = +2 mA 20 –10 50 — — REGC pin: LowHigh — 0.2 VCC V Max. 16 Unit cycle Test Conditions RST pin *Note 2 AC characteristics Symbol Min. Typ. REGC minimum low voltage detection time Power on reset time Item Tprw 8 — Tpr — 1.25 4 10 — cycle RST pin *Note 2 WDT reset time Twd — — cycle RST pin *Note 2 WDT reset pulse width Twr — 2.5 3 10 16 — cycle RST pin *Note 2 Note: Current flowing directions are: Plus (+) or none: from outside to IC, Minus (–): from IC to outside Notes: *1 See figure 7 for the electrical characteristics in this page. *2 Is defined by the number of cycles of WDT driving frequency (265 kHz typ.: = fSDC). R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 7 of 22 R2A25107KFP Preliminary Electrical Characteristics (cont.) (Ta = –40 to 125°C, VBAT = VBAT2 = 7.0 to 36 V, VGB = 5.9 to 6.5 V, REGC = VCC = 4.85 to 5.15 V, unless otherwise specified) Over-Current Detection of Motor (MCS, SGND, MCD, MCR) DC characteristics Item Over-current detection threshold voltage Over-current detection threshold hysteresis voltage Symbol VthMCS Min. 1.0 Typ. 1.1 Max. 1.2 Unit V VhysMCS — 40 — mV — A V MCS pin, Not subjected to production test, but guaranteed through designing. MCS pin, VMCS = 0 V MCS pin V MCR pin V MCR pin A A V MCR = 5 V, Pull-Down = 100 k MCR = 0 V MCD pin, Io = –2 mA MCD pin, Io = +2 mA MCS common mode input voltage range MCR high level input voltage IinMCS V(MCS) –1.0 0 — — VIH(MCR) — MCR low level input voltage VIL(MCR) 0.8 VCC 0 MCR high level input current MCR low level input current MCD high level output voltage IIH(MCR) IIL(MCR) VOH(MCD) 20 –10 50 MCD low level output voltage VOL(MCD) MCS input bias current 0.8 VCC 0 — — — VCC –2.0 VCC 0.4 VCC 250 0 VCC — 0.2 VCC V Typ. — Max. 3.0 Unit s Test Conditions MCS pin AC characteristics Item Symbol Over-current detection filtering time tFLT Min. 0 Over-current detection latch clear pulse width tMCR 1 — — s MCR, MCD pin, I*T, I*B: Low, MUTE: High, MCS < (VthMCS – VhysMCS), See figure 9 Over-current detection latch clear delay time tDLY — — 1 s MCR, MCD pin, I*T, I*B: Low, MUTE: High, MCS < (VthMCS – VhysMCS), See figure 9 Note: Test Conditions MCS, MCD pin, I*T, I*B: Low, MUTE: High, MCR: Low, See figure 9 Current flowing directions are: Plus (+) or none: from outside to IC, Minus (–): from IC to outside R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 8 of 22 R2A25107KFP Preliminary Electrical Characteristics (cont.) (Ta = –40 to 125°C, VBAT = VBAT2 = 7.0 to 36 V, VGB = 5.9 to 6.5 V, REGC = VCC = 4.85 to 5.15 V, unless otherwise specified) Gate Drive (I*T, I*B, MUTE, *T, *, *B, *G) DC characteristics Symbol Min. Typ. Gate drive input pin high level input voltage Item VIH — Gate drive input pin low level input voltage VIL 0.6 VCC 0 Max. VCC Unit V IUT, IUB, IVT, IVB, IWT, IWB pin V IUT, IUB, IVT, IVB, IWT, IWB pin — 0.2 VCC 10 Gate drive input pin high level input current IIH 0 A IUT, IUB, IVT, IVB, IWT, IWB = 5 V Gate drive input pin low level input current MUTE high level input voltage IIL –250 –50 –20 A IUT, IUB, IVT, IVB, IWT, IWB = 0 V, Pull-Up = 100 k VIH(MUTE) — VCC V MUTE pin VIL(MUTE) 0.8 VCC 0 MUTE low level input voltage — V MUTE pin IIH(MUTE) IIL(MUTE) Io(MTR) 20 –10 –180 50 0.4 VCC 250 0 –40 MUTE high level input current MUTE low level input current Output pin output current — — –90 A A A Test Conditions MUTE = 5 V, Pull-Down = 100 k MUTE = 0 V U, V, W pin, I*T = I*B = VCC (*T = *B = “L” output), U, V, W = 0, VGT = VBAT2 + 5.5 V High side gate drive high level output voltage Vtoh 0.4 1.0 2.5 V Vtoh = VGT-UT, VGT-VT, VGT-WT VBAT2 = 12 V, VGB = 6.2 V, VGTVBAT2 = 5.5 V, IUT = IVT = IWT = 0 V, Iload = –20 mA High side gate drive low level output voltage Vtol 0.4 1.0 2.5 V Vtol = UT-U, VT-V, WT-W, VBAT2 = 12 V, VGB = 6.2 V, VGTVBAT2 = 5.5 V, IUT = IVT = IWT = 5V, Iload = 40 mA Low side gate drive high level output voltage Vboh 0.56 1.4 3.5 V Vboh = VGB-UB, VGB-VB, VGB-WB VBAT2 = 12 V, VGB = 6.2 V, VGTVBAT2 = 5.5 V, IUB = IVB = IWB = 0 V, Iload = –20 mA Low side gate drive low level output voltage Vbol 0.4 1.0 2.5 V Vbol = UB-UG, VB-VG, WB-WG VBAT2 = 12 V, VGB = 6.2 V, VGTVBAT2 = 5.5 V, IUB = IVB = IWB = 5 V, Iload = 40 mA AC characteristics Item Turn-on delay time Symbol Ton Min. 100 Typ. 200 Max. 400 Unit ns Turn-off delay time Toff 100 200 400 ns IUT, IUB, IVT, IVB, IWT, IWB, MUTE pin, See figure 10 High side gate drive rise time High side gate drive fall time Ttr Ttf 500 450 1000 900 2000 1800 ns ns IUT, IVT, IWT, MUTE pin, Low side gate drive rise time Low side gate drive fall time Tbr Tbf 500 450 1000 900 2000 1800 ns ns IUB, IVB, IWB, MUTE pin, Note: Test Conditions IUT, IUB, IVT, IVB, IWT, IWB, MUTE pin, See figure 10 CL = 3000 pF, RL = 100 , See figure 10 CL = 3000 pF, RL = 100 , See figure 10 Current flowing directions are: Plus (+) or none: from outside to IC, Minus (–): from IC to outside R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 9 of 22 R2A25107KFP Preliminary Equivalent Circuits of Input/Output Circuits <IUT, IUB, IVT, IVB, IWT, IWB> <MUTE, CLK, MCR> VCC <RST, MCD> VCC VCC 100 k 3k ggNMOS 3k 100 k ggNMOS GND GND <Power supply, GND> 45 V 45 V 45 V 80 V Clamp Clamp Clamp Clamp VGT VBAT VGB VCC ggNMOS GND GND GND <VGB> VBAT VBAT2 Internal 5 V Power supply ggNMOS 39 k VGB GND 10 k ggNMOS DGND SGND PGND GND <IREF> Internal 5 V Power supply <MCS, SGND> VBAT2 GND GND VCC 10 k MCS 2k 108 k 110 k 45 V Clamp ggNMOS SGND ggNMOS GND GND <UT, U, VT, V, WT, W> <UB, UG, VB, VG, WB, WG> VGT UB, VB, WB U, V, W UG, VG, WG R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 GND <REGC> VGB Output Dr ggNMOS ggNMOS GND GND GND VGB UT, VT, WT ggNMOS GND GND GND Page 10 of 22 R2A25107KFP Preliminary Equivalent Circuits of Input/Output Circuits (cont.) <SDC> <VGB, CP1, PGND> <VBAT2, CP2, VGT> VGB VBAT VGT Output Dr CP1 CP2 PGND VBAT2 GND <DGND> VCC WDT Logic Circuit DGND R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 11 of 22 R2A25107KFP Preliminary Function Description Step Down Converter +B VBAT SDC VGB <R2A25107KFP> C IVGB Drive circuit Thermal Protection M1 M2 A – + – + Reference voltage Charge pump for high side gate drive 5V regulator Low side Gate Pre-driver B Reference voltage OSC Over-current detection circuit + – PWM comparator Error Amplifier <Step down converter> Figure 1 Block Diagram of Step Down Converter Circuit This IC contains a step down converter circuit to generate a typical 6.2-V voltage from VBAT voltage for efficiently powering the charge pump circuit for high-side gate drive and the 5 V series regulator. The resulting 6.2-V output of the step down converter is also used for powering the low-side gate drive. The block diagram of the step down converter circuit is shown in figure 1. This circuit contains an error amplifier, PWM comparator, drive circuit, over-current detection circuit and thermal shutdown (TSD) circuit. As shown in figure 2, this circuit controls the VGB voltage based on VthVGB of 6.2 V typical through the PWM operation. The over-current detection circuit monitors the current flowing the drive transistor M1 (IVGB). If over load is generated at power up or in the load circuits (gate drive circuit and 5 V regulator) and then IVGB exceeds the over -current detection current, IlimVGB (–1.0 A), the drive transistor M1 is placed to off for typical 25 s of TSDC (Step down converter off time at over-current detection). In addition, if the chip junction temperature is increased to the TSD temperature (TSDon: 200°C typ.) through intermittent operation of the over-current detection circuit, drive transistor M1 is placed to off until the TSD circuit starts to be operated and the chip temperature is decreased by TSD hysteresis temperature (TSDhys: 40°C typ.). These operations prevent the IC from being thermally destructed. Table 1 and figure 3 show the operation of over-current detection circuit and thermal shutdown circuit. 265 kHz B A High Low C Figure 2 Step Down Converter PWM Timing Chart R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 12 of 22 R2A25107KFP Table 1 Preliminary Operations under Protection Over-Current Protection OFF Thermal Shutdown OFF Step Down Converter Output: M1 ON (detected) OFF OFF OFF (Stopped by PWM) ON (detected) OFF (Stopped by PWM) ON (detected) OFF (Stopped by PWM) ON (detected) Normal Operation Over-Current Protection ON (Driven by PWM) Thermal shutdown VBAT SDC PWM PWM PWM PWM 0V 6.2 V VGB VthVGB 0V 1.0 A IlimVGB IVGB 0A TSDC 200°C Tj 160°C TSDC TSDC TSDon TSDhys 0°C Figure 3 Step Down Converter Operation under Protection R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 13 of 22 R2A25107KFP Preliminary Charge Pump This IC contains a charge pump circuit (upper side gate drive voltage: VGT = VBAT2 + 5.5 V typ.) to drive the gate of the high-side external power MOSFET. This circuit is also configured to add the low-side gate drive voltage (step down converter output: VGB) to the VBAT2 power supply voltage. Figure 4 shows the charge pump circuit configuration. Figure 5 shows timing chart for pre-charge. +B Cp VGB VBAT2 CP2 Cgt CP1 VGT <R2A25107KFP> M3 265 kHz M4 135 kHz M1 OSC Vcp ON → OFF OFF → ON ON → OFF 1/2 divider M2 OFF → ON Figure 4 Charge Pump Circuit (1) When M1 and M4 = OFF and M2 and M3 = ON External capacitor, Cp is charged. Vcp = VBAT2 – Vds3 (Vds3; Drain to Source voltage of M3) (2) When M1 and M4 = ON and M2 and M3= OFF The electric charge on external capacitance, Cp is moved to external capacitance, Cgt and the resulting VGT voltage is: Vcp = (VBAT2 – Vds3) + VGB = VBAT2 + VGB – Vds3 Thus VGT = Vcp – Vds4 = (VBAT2 + VGB – Vds3) – Vds4 (Vds4; Drain to Source voltage of M4) = VBAT2 + VGB – 2 Vds (Vds = Vds3 Vds4) Vo(REGC) REGC/VCC Von 0V VGT VGT × 90% 0V TGT Figure 5 Pre-charge Operation Timing of Charge Pump R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 14 of 22 R2A25107KFP Preliminary 5 V Regulator This IC contains the 5 V series regulator with internal Nch MOS driver for MCU power supply circuit. Figure 6 shows the 5 V regulator circuit. The over-current detection circuit of the step down converter is activated if an over-current is caused due to the short circuit of REGC output. If the over-current condition is continued, this regulator circuit is protected by the thermal shutdown circuit in the same way as the step down converter. If the junction temperature of the chip exceeds the TSD temperature (TSDon) of 200°C typical, the TSD circuit starts to be operated to place the drive transistor M1 to off until the chip temperature is decreased by the TSD hysteresis temperature (TSDhys) of 40°C typical. This operation protects the chip from thermal destruction. Table 2 shows the operation of over-current detection circuit and thermal shutdown circuit. This IC also contains watchdog timer (WDT), and returns the reset signal (RST) to the MCU when the low voltage of REGC is detected. Figure 7 shows the timing chart of the watchdog timer. <R2A25107KFP> VGB 6.2 V M1 Thermal shutdown circuit REGC 5V VCC CLK VGB – + + Analog Digital (WDT) MCU RST Amp. GND DGND Figure 6 5 V Regulator Circuit Table 2 Operations under Protection Over-Current Protection OFF Thermal Shutdown OFF 5 V Regulator Output ON Step Down Converter Output ON (detected) OFF OFF ON OFF (Stopped by PWM) ON (detected) OFF OFF (Stopped by PWM) ON (detected) OFF OFF (Stopped by PWM) ON (detected) R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 ON (Driven by PWM) Page 15 of 22 R2A25107KFP Preliminary Vo(REGC) Vprh REGC Vprl Von 0V VCC CLK 0V Twr Tprw Twr Twr Twr Twr Twr Twr VCC RST 0V Tpr Twd Tpr Twd Twd Twd Twd Twd Twd CLK count start Figure 7 Timing Chart of Watchdog Timer R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 16 of 22 R2A25107KFP Preliminary Motor Over-Current Detection Circuit This IC contains a motor over-current detection circuit. Figure 8 shows the block diagram of this circuit and figure 9 shows the timing chart when over-current is detected. This circuit monitors the MCS pin voltage. If the MCS voltage exceeds the over-current detection threshold voltage (VthMCS) of 1.1 V typical, motor over-current detection signal (ILIM) is output to the MCU by the time the motor overcurrent detection filtering time (tFLT) of 3 s max. has elapsed. When motor over-current is detected, the over-current detection output remains low until a high level signal pulse (with a pulse width longer than the over-current detection latch clear pulse width, tMCR of 1 s min.) is applied to the MCR pin. +B <R2A25107KFP> *T I*T HIGH SIDE PREDRIVER * I*B PRE INPUT MATRIX MUTE *B LOW SIDE PREDRIVER MCU MCD + – OVER-CURRENT DETECTION *G MCS SGND MCR Figure 8 Block Diagram of Motor Over-Current Detection Circuit VMCS VhysMCS VthMCS 0V TFLT VCC 90% 90% VMCD 10% 0V TDLY TDLY VCC VMCR 50% 0V 50% TMCR Figure 9 Timing Chart of Motor Over-Current Detection Circuit R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 17 of 22 R2A25107KFP Preliminary Gate Pre-driver This IC contains three sets of totem pole type output FET gate drive circuits. Figure 10 shows the timing chart and table 3 shows the truth table of the gate pre-driver functions. VCC VCC × 60% I*T (IUT, IUB, IVT, IVB, IWT, IWB) VCC × 20% 0V VA (*Note2) VA × 90% Vout (*Note1) VA × 10% 0V Ton Ttr, Tbr Toff Ttf, Tbf VCC VCC × 80% MUTE VCC × 40% 0V VA (*Note2) VA × 90% Vout (*Note1) VA × 10% 0V Ton Ttr, Tbr Notes: Toff Ttf, Tbf *1 Vout is the gate to source voltage for external power MOSFET (UT-U, VT-V, WT-W: U = V = W = VBAT2 = 12 V, capacitive load: CL = 3000 pF, gate resistance RL = 100 ) (UB-UG, VB-VG, WB-WG: capacitive load CL = 3000 pF, gate resistance RL = 100 ) *2 VA is the power supply voltage of gate drive output (UT-U, VT-V, WT-W: 5.5 V (= VGT – VBAT2)) (UB-UG, VB-VG, WB-WG: 6.2 V (= VGB)) Figure 10 Timing Chart of Input/Output Signals of Gate Drive Pins Table 3 Truth Table of Gate Pre-driver I*T H H L L H/L Note: Input I*B H L H L H/L Output MUTE H H H H L *T L L H L L *B L H L L L (I*T, I*B, *T, *B) = (IUT, IUB, UT, UB), (IVT, IVB, VT, VB), (IWT, IWB, WT, WB) R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 18 of 22 R2A25107KFP Preliminary Thermal Protection Circuit This IC contains a thermal shutdown protection circuit to prevent the IC from thermal destruction. Table 4 shows the operating temperatures of this circuit. When this circuit detects an over temperature, the step down converter and 5 V regulator are stopped. When the over temperature is reduced to a TSD hysteresis temperature, operation is resumed. (See figure 3 on page 13.) The TSD temperatures are not intended to guarantee device operation at the TSD temperatures. The guaranteed operating temperature of this IC is Tjmax defined in the absolute maximum rating, not the TSD temperatures. The TSD temperatures should be only for protection if the chip temperature rises above the TJmax. Accordingly, this IC should be operated under Tj 150°C condition. Table 4 Operating Temperatures of TSD Symbol TSDon TSDhys Item TSD temperature TSD hysteresis temperature R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Min. Value Typ. Max. Unit 170 30 200 40 230 50 °C °C Page 19 of 22 R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Cvcc + Csd + Lsd Cref Rref Dsd Cvbat + VGB SDC VBAT IREF VCC REGC +B DGND 5 V ± 3% TSD 7~36 V DGND WDT Current Reference OSC 5V REGULATOR GND CLK POR 6.2 V typ. Over current protection STEP DOWN CONVERTER RST I*T Band-gap 7~36 V + MCU I*B MUTE VBAT2 +B P1 MCD VBAT2+VGB PGND +B MCR Over-current Detection – + Dead short Prevention LOW SIDE PRE DRIVER 6.2 V typ. Dead short Prevention HIGH SIDE PRE DRIVER VGT Cgt MOTOR CURRENT LIMIT Dead short Prevention PRE INPUT MATRIX Dead short Prevention PGND VGT CHARGE PUMP CP2C Cp Rgt SGND Rgb Rdb MCS *G *B * *T Rdt Rgsb Db Rgst Dt Rsen ZDb FET ZDt FET +B R2A25107KFP Preliminary Application Example Page 20 of 22 R2A25107KFP Preliminary Recommended Values for External Components Component Name Remarks *Note 1 Value Typ. 10 10 100 47 0.6 33 47 100 100 1.0 3000 Max. — — — — — 47 — — 220 — 5000 Unit Cvbat Cvbat2 Lsd Csd VFsd Cvcc Rref Cref Cp Cgt Ciss Min. — — — — — — — — 68 — — Symbol F F H F V F k pF nF F pF Cvbat Cvbat2 Lsd Csd Dsd Cvcc Rref Cref Cp Cgt FET Rgt, Rgb Bypass Capacitor for VBAT Bypass Capacitor for VBAT2 *Note 1 Step Down Converter Coil *Note 2 Bypass Capacitor for Step Down Converter *Note 1, 2 Diode for Step Down Converter Bypass Capacitor for REGC, VCC *Note 1 External Resistance for Current Reference *Note 2 Filter Capacitor for Current Reference *Note 2, 3 Charge-pump Capacitor *Note 2 Bypass Capacitor for Charge-pump Voltage *Note 1, 2 Nch Power MOSFET Gate Resistances of FETs 2 Rise time adjustment *Note Rg 100 — — Rdt, Rdb Reverse Gate Resistances of FETs 2 Fall time adjustment *Note Gate-Source Resistances of FETs Diode Rd 51 — — Rgs VFd 100 — — 0.7 — — k V Vak — 16 — V Rsen — *Note 4 — m Rgst, Rgsb Dt, Db ZDt, ZDb Rsen Zener Diode FET gate protection Resister for Motor Current sensing Notes: *1 Capacitors connected to the power supply pins (Cvbat, Cvbat2, Csd, Cvcc, Cgt) should be mounted as closely as to this IC. *2 Since these values determine the electrical characteristics of this IC, they should be set with the consideration of the actual application. *3 Since this value determines the operation at power up, it should be set with the consideration of the actual application. If the value is changed, contact us separately. *4 Since this value determines the constant for motor over-current detection, it should be set with the consideration of the limited current of the motor. *5 For the components with the Min. and Max. values defined in the table above, the values of the components should be determined in the range of the Min. to Max. For the components with the Min. and Max. values not defined, those values should be determined based on the Typ. value, with the consideration of the actual application. R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 Page 21 of 22 R2A25107KFP Preliminary Package Dimensions JEITA Package Code P-LFQFP48-7x7-0.50 RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 37 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 24 bp c c1 *2 E HE b1 Reference Dimension in Millimeters Symbol 48 13 1 ZE Terminal cross section 12 c A F A2 Index mark ZD S A1 L D E A2 HD HE A A1 bp b1 c c1 e R07DS0689EJ0100 Rev.1.00 Mar 22, 2012 *3 bp Detail F x 8.8 8.8 0 0.17 0.09 0° L1 y S Min 6.9 6.9 e x y ZD ZE L L1 0.35 Nom Max 7.0 7.1 7.0 7.1 1.4 9.0 9.2 9.0 9.2 1.7 0.1 0.2 0.22 0.27 0.20 0.145 0.20 0.125 8° 0.5 0.08 0.10 0.75 0.75 0.5 0.65 1.0 Page 22 of 22 Revision History Rev. 1.00 Date Mar 22, 2012 R2A25107KFP Data Sheet Description Summary Page — First Edition Issued All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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