CY7C1061DV33 PRELIMINARY 16-Mbit (1M x 16) Static RAM Features Functional Description • High speed The CY7C1061DV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • Low active power — ICC = 125 mA @ 10 ns • Low CMOS standby power — ISB2 = 25 mA • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free 54-pin TSOP II package and 48-ball VFBGA packages Reading from the device is accomplished by enabling the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1061DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball Very fine-pitch ball grid array (VFBGA) package Logic Block Diagram Pin Configuration 54-pin TSOP II (Top View) 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE CE2 CE1 OE BLE Cypress Semiconductor Corporation Document #: 38-05476 Rev. *C • 198 Champion Court • I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2006 [+] Feedback CY7C1061DV33 PRELIMINARY Selection Guide –10 Unit Maximum Access Time 10 ns Maximum Operating Current 125 mA Maximum CMOS Standby Current 25 mA Pin Configuration[1] 48-ball VFBGA (Top View) 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 CE2 A A3 A4 CE1 I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O 3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F A12 A13 WE I/O7 G A9 A10 A11 A19 H I/O15 NC A18 A8 Note: 1. NC pins are not connected on the die Document #: 38-05476 Rev. *C Page 2 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V Range Industrial DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Ambient Temperature VCC –40°C to +85°C 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range –10 Parameter Description Test Conditions[7] VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Min. Max. Unit 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V 2.4 Voltage[2] V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC 125 mA ISB1 VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Automatic CE Power-down CE2 <= VIL, Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current —TTL Inputs 30 mA ISB2 Automatic CE Power-down Current —CMOS Inputs 25 mA CE2 <= 0.3V, Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TSOP II VFBGA Unit 6 8 pF 8 10 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Thermal Resistance[3] Parameter ΘJA ΘJC Description Test Conditions All-Packages Unit TBD °C/W TBD °C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Thermal Resistance (Junction to Case) AC Test Loads and Waveforms[4] High-Z characteristics: 3.3V 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω R1 317Ω OUTPUT 30 pF* 5 pF* (a) ALL INPUT PULSES * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 3.0V 90% GND Rise time > 1 V/ns 90% R2 351Ω INCLUDING JIG AND SCOPE (d) 10% 10% (c) Fall time: > 1 V/ns Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05476 Rev. *C Page 3 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY AC Switching Characteristics Over the Operating Range [5] –10 Parameter Description Min. Max. Unit Read Cycle tpower VCC(typical) to the first access[6] 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW/CE2 HIGH to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low-Z 10 tHZOE OE HIGH to High-Z CE1 LOW/CE2 HIGH to Low-Z[7] tHZCE CE1 HIGH/CE2 LOW to High-Z[7] CE1 LOW/CE2 HIGH to Power-Up[8] Power-Down[8] tPU ns 5 tPD CE1 HIGH/CE2 LOW to tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z 3 ns ns 5 0 ns ns 10 ns 5 ns 1 Byte Disable to High-Z tHZBE ns 1 [7] tLZCE Write Cycle 3 ns ns 5 ns [9, 10] tWC Write Cycle Time 10 ns tSCE CE1 LOW/CE2 HIGH to Write End 7 ns tAW Address Set-up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5.5 ns tHD Data Hold from Write End 0 ns tLZWE WE HIGH to Low-Z[7] 3 ns tHZWE WE LOW to High-Z [7] tBW Byte Enable to End of Write 5 7 ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05476 Rev. *C Page 4 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time Min. Typ. Max. 2 Unit V 25 VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE ] Switching Waveforms Read Cycle No. 1[12,13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH. 13. WE is HIGH for Read cycle. Document #: 38-05476 Rev. *C Page 5 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2(OE Controlled)[13,14] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IICC CC 50% 50% ISB Write Cycle No. 1(CE Controlled)[15,16,17] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW. Document #: 38-05476 Rev. *C Page 6 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2(BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Write Cycle No. 3(WE Controlled, OE LOW)[15,16,17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Document #: 38-05476 Rev. *C Page 7 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Truth Table CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X X High-Z High-Z Power-down Standby (ISB) X L X X X X High-Z High-Z Power-down Standby (ISB) L H L H L L Data Out Data Out Read All Bits Active (ICC) L H L H L H Data Out High-Z Read Lower Bits Only Active (ICC) L H L H H L High-Z Data Out Read Upper Bits Only Active (ICC) L H X L L L Data In Data In Write All Bits Active (ICC) L H X L L H Data In High-Z Write Lower Bits Only Active (ICC) L H X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1061DV33-10ZXI Package Diagram Package Type 51-85160 54-pin TSOP II (Pb-Free) Operating Range Industrial CY7C1061DV33-10BVXI 51-85178 48-ball Very Fine Pitch Ball Grid Array (8 × 9.5 × 1 mm) (Pb-Free) Package Diagrams 54-pin TSOP Type II (51-85160) 51-85160-** Document #: 38-05476 Rev. *C Page 8 of 10 [+] Feedback CY7C1061DV33 PRELIMINARY Package Diagrams (continued) 48-ball FBGA (8 x 9.5 x 1 mm) (51-85178) BOTTOM VIEW TOP VIEW A1 CORNER C Ø0.05 M Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 3 4 5 6 6 5 4 3 2 1 A B C B F G D E 2.625 E C 0.75 D 5.25 A 9.50±0.10 9.50±0.10 1 2 F G H H A 1.875 A B 8.00±0.10 0.75 B 0.10 C 0.21±0.05 0.25 C 0.55 MAX. 3.75 51-85178. ** SEATING PLANE C 1.00 MAX 0.26 MAX. 8.00±0.10 0.15(4X) All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05476 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1061DV33 PRELIMINARY Document History Page Document Title: CY7C1061DV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05476 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Data sheet for C9 IPP *A 233748 See ECN RKF 1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free offering in the ‘ordering information’ *B 469420 See ECN NXR Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed –8 and –12 speed bins from product offering Removed Commercial Operating Range Changed 2G ball of FBGA and pin #40 of TSOPII from DNU to NC Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 125 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1. Updated the Ordering Information Table *C 499604 See ECN NXR Added note# 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Updated the 48-ball FBGA Package Document #: 38-05476 Rev. *C Description of Change Page 10 of 10 [+] Feedback