Formosa MS

Formosa MS
SMD MOSFET
2N7002W
List
List................................................................................................. 1
Package outline............................................................................... 2
Features.......................................................................................... 2
Mechanical data............................................................................... 2
Maximum ratings ............................................................................. 2,3
Rating and characteristic curves........................................................ 4,5
Pinning information........................................................................... 6
Marking........................................................................................... 6
Suggested solder pad layout............................................................. 6
Packing information.......................................................................... 7
Reel packing.................................................................................... 8
Suggested thermal profiles for soldering processes............................. 8
High reliability test capabilities........................................................... 9
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TEL:886-2-22696661
FAX:886-2-22696141
Page 1
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
60V N-Channel Enhancement
Mode MOSFET
Package outline
solid-state relays drivers, relays, displays, lamps,
solenoids, memories, etc.
In compliance with EU RoHS 2002/95/EC directives.
Suffix "-H" indicates Halogen-free part, ex. 2N7002W-H.
0.016 (0.40)
.056(1.40)
.048(1.20)
(B)
(C)
(A)
0.054 (1.35)
0.021 (0.53)
0.017 (0.42)
0.046 (1.15)
0.096 (2.40)
Mechanical data
0.040 (1.00)
0.004 (0.10)
0.080 (2.00)
0.010 (0.25)
•
•
0.088 (2.20)
• R DS(ON), V GS@10V, I DS@500mA=5 Ω
• R DS(ON), V [email protected], I DS@75mA=7.5 Ω
• Advanced trench process technology.
• High density cell design for ultra low on-resistance.
• Specially designed for battery operated system,
0.072 (1.80)
0.026 (0.65)Max
Features
0.012 (0.30)
SOT-323
0.032 (0.80)
• Epoxy:UL94-V0 rated flame retardant
• Case : Molded plastic, SOT-323
• Terminals : Solder plated, solderable per
Dimensions in inches and (millimeters)
MIL-STD-750, Method 2026
• Mounting Position : Any
• Weight : Approximated 0.006 gram
M aximum ratings (AT T
A
=25 oC unless otherwise noted)
PARAMETER
MAX.
UNIT
Drain-source voltage
CONDITIONS
V DSS
60
V
Drain-gate voltage(G RS = 1.0MΩ)
V DGR
60
V
ID
±115
I DM
±800
V GS
±20
V GSM
±40
Drain to current-continue
Symbol
MIN.
TYP.
mA
-pulsed
Gate to source voltage-continue
V
-non-repetitive
Total power dissipation
200
mW
1.6
mW/ OC
PD
Derate above 25 OC
Operation junction and storage temperature range
T J , T STG
Junction to ambient thermal resistance
-55
o
+150
o
625
R θJA
C
C/W
Single pulse drain-to-source avalanche energy - T J = 25 OC
(V DD = 50V, V GS = 10V, I AS = 0.8A, L = 30mH,
R G = 25Ω)
E AS
9.6
mJ
Maximum lead temperature for soldering purposes
1/8" from case for 10 seconds
TL
300
o
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Page 2
C
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
Electrical characteristics (AT T =25 C unless otherwise noted)
o
A
PARAMETER
Drain-source breakdown voltage
Drain-source leakage current
CONDITIONS
Symbol
MIN.
V GS = 0V, I D = 10uA
V (BR)DSS
60
V DS = 60V, V GS = 0V
V DS = 60V, V GS = 0V, T J = 125 OC
I DSS
Gate-source leakage current-forward
V GSF = 20V
I GSS
Gate-source leakage current-reverse
V GSF = -20V
I GSS
V DS = V GS, I D = 250uA
Gate threshold voltage*
V DS > 20V DS(on), V GS = 10V
On-state drain current
Static drain-source on-resistance*
V GS = 10V, I D = 0.5A
V GS = 10V, I D = 0.5A, T C = 125 OC
V GS = 5.0V, I D = 50mA
V GS = 5.0V, I D = 50mA, T C = 125 OC
Drain-source on-voltage*
V GS = 10V, I D = 0.5A
V GS = 5.0V, I D = 50mA
Forward transconductance
V DS > 2.0V DS(on), I D = 200mA*
Input capacitance
V DS = 25V, V GS = 0V, f = 1.0MHz
Output capacitance
Reverse transfer capacitance
Turn-On Delay Time
V DD = 25V, I D = 500mA,
V gen = 10V, R G = 25Ω, R L = 50Ω*
Turn-Off Delay Time
V GS(th)
1.0
I D(on)
500
TYP.
MAX.
V
1.0
uA
0.5
mA
100
nA
-100
nA
V
2.5
mA
7.5
13.5
7.5
13.5
Ω
3.75
0.375
V
R DS(on)
V DS(on)
g FS
UNIT
200
ms
C iss
50
C oss
25
C rss
5.0
t d(on)
9
15
t d(off)
21
26
pF
ns
Diode forward on-voltage
I S = 115mA, V GS = 0V
V SD
-1.2
V
Source current continuous
Body diode
IS
-250
mA
I SM
-800
mA
Source current pulsed
-0.93
*Pules test : Pules width < 300uS, duty cycle < 2%
Gate Charge
Test Circuit
Switching
Test Circuit
V DD
V DD
RL
V IN
RL
V GS
D
D
V OUT
V GS
1mA
RG
DUT
G
G
RG
S
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Page 3
S
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Rating and characteristic curves (2N7002W)
FIG.2 TRANSFER CHARACTERISTIC
FIG.1 TYPICAL FORWARD CHARACTERISTIC
1.2
V GS = 6V~10V
DRAIN TO SOURCE CURRENT,(A)
DRAIN TO SOURCE CURRENT,(A)
1.2
5.0V
1.0
0.8
4.0V
0.6
0.4
3.0V
0.2
V DS = 10V
1.0
0.8
0.6
0.4
o
25 C
0.2
0
0
0
1
2
3
4
5
0
1
DRAIN TO SOURCE VOLTAGE, (V)
2
3
4
5
6
GATE TO SOURCE VOLTAGE, (V)
FIG.4 ON RESISTANCE VS GATE TO SOURCE VOLTAGE
FIG.3 ON RESISTANCE VS DRAIN CURRENT
5
10
4
8
3
ON-RESISTANCE, (ohm)
ON-RESISTANCE, (ohm)
I D = 500mA
V GS = 4.5V
2
V GS = 10V
1
6
o
125 C
4
2
o
25 C
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
2
3
4
5
6
7
8
9
10
GATE TO SOURCE VOLTAGE, (V)
DRAIN current, (A)
FIG.5 ON RESISTANCE VS JUNCTION TEMPERATURE
ON-RESISTANCE, (ohm) NORMALIZED
2.0
V GS = 10V
1.8
I D = 500mA
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-50
-25
0
25
50
75
100
125
150
o
JUNCTION TEMPERATURE, ( C)
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Page 4
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Rating and characteristic curves (2N7002W)
FIG.7 GATE CHARGE
FIG.6 GATE CHARGE WAVEFORM
10
Vgs
Qsw
Vgs(th)
V DS = 15V
GATE TO SOURCE VOLTAGE,(V)
Qg
8
I D = 500mA
6
4
2
0
0
Qg(th)
Qgs
0.2
0.6
0.8
1.0
GATE CHARGE, (nC)
Qg
Qgd
0.4
GATE CHARGE WAVEFORM
FIG.9 BREAKDOWN VOLTAGE VS JUNCTION TEMPERATURE
73
1.2
I D = 250uA
1.0
0.9
0.8
0.7
I D = 250uA
72
1.1
BREAKDOWN VOLTAGE, (V)
THRESHOLD VOLTAGE, (V) NORMALIZED
FIG.8 THRESHOLD VOLTAGE VS TEMPERATURE
71
70
69
68
67
66
65
64
0.6
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
o
125
150
o
JUNCTION TEMPERATURE, ( C)
JUNCTION TEMPERATURE, ( C)
FIG.10 SOURCE-DRAIN DIODE FORWARD VOLTAGE
10
SOURCE CURRENT,(A)
V GS = 0V
1
o
25 C
o
125 C
0.1
o
-55 C
0.01
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
SOURCE TO DRAIN VOLTAGE, (V)
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Page 5
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
Pinning information
Pin
Simplified outline
Symbol
D
PinD
PinG
PinS
Drain
Drain
Gate
Source
Gate
G
Source
S
Marking
Type number
2N7002W
Marking code
72
Suggested solder pad layout
SOT-323
0.025(0.65)
0.025(0.65)
0.063(1.6)
0.031(0.80)
0.023(0.60)
Dimensions in inches and (millimeters)
http://www.formosams.com/
TEL:886-2-22696661
FAX:886-2-22696141
Page 6
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
Packing information
P0
P1
d
E
F
B
A
W
P
D2
D1
T
C
W1
D
unit:mm
Item
Symbol
Tolerance
SOT-323
Carrier width
Carrier length
Carrier depth
Sprocket hole
13" Reel outside diameter
13" Reel inner diameter
7" Reel outside diameter
7" Reel inner diameter
Feed hole diameter
Sprocket hole position
Punch hole position
Punch hole pitch
Sprocket hole pitch
Embossment center
Overall tape thickness
Tape width
Reel width
A
B
C
d
D
D1
D
D1
D2
E
F
P
P0
P1
T
W
W1
0.1
0.1
0.1
0.1
2.0
min
2.0
min
0.5
0.1
0.1
0.1
0.1
0.1
0.1
0.3
1.0
1.47
2.95
1.15
1.50
178.00
62.00
13.00
1.75
3.50
4.00
4.00
2.00
0.23
8.00
11.40
Note:Devices are packed in accor dance with EIA standar RS-481-A and specifications listed above.
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TEL:886-2-22696661
FAX:886-2-22696141
Page 7
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
Reel packing
PACKAGE
SOT-323
REEL SIZE
7"
REEL
(pcs)
COMPONENT
SPACING
(m/m)
BOX
(pcs)
INNER
BOX
(m/m)
REEL
DIA,
(m/m)
3,000
4.0
30,000
183*183*123
178
CARTON
SIZE
(m/m)
382*262*387
CARTON
(pcs)
APPROX.
GROSS WEIGHT
(kg)
240,000
9.5
Suggested thermal profiles for soldering processes
1.Storage environment: Temperature=5 oC ~40 oC Humidity=55%±25%
2.Reflow soldering of surface-mount devices
Critical Zone
TL to TP
Tp
TP
Ramp-up
TL
TL
Tsmax
Temperature
Tsmin
tS
Preheat
Ramp-down
25
t25o C to Peak
Time
3.Reflow soldering
Profile Feature
Soldering Condition
Average ramp-up rate(T L to T P )
o
<3 C /sec
Preheat
-Temperature Min(Tsmin)
-Temperature Max(Tsmax)
-Time(min to max)(t s )
150 oC
200 oC
60~120sec
Tsmax to T L
-Ramp-upRate
<3 oC/sec
Time maintained above:
-Temperature(T L )
-Time(t L )
217 oC
60~260sec
255 oC-0/+5 oC
Peak Temperature(T P )
Time within 5 oC of actual Peak
Temperature(t P )
10~30sec
Ramp-down Rate
<6 oC/sec
Time 25 oC to Peak Temperature
<6minutes
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TEL:886-2-22696661
FAX:886-2-22696141
Page 8
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9
Formosa MS
SMD MOSFET
2N7002W
High reliability test capabilities
Item Test
Conditions
Reference
Ta=150℃ Vgs=0.8 x BVGSS for 1000hours
JESD22-A108-C
Ta=150℃ Vds=0.8 x BVDSS for 1000hours
JESD22-A108-C
2. High Temperature Reverse Bias
3. Solder ability Test
Temp= 245℃ for 5sec
1. High Temperature Gate Bias
JESD22-B102-D
Ta=121℃/100% RH Pressure=2Atm for 168hours
JESD22-A102-C
JESD22-A104-B
5. Temperature Cycle Test
- 65℃/ 10min~150℃/10min
Transfer<5min . total 1000 cycles.
6. Temperature Humidity Test
Ta=85℃ Humidity=85% RH for 1000hours
7. High Temperature Storage Test
Ta=150℃ for 1000hours
4. Pressure Cooker Test
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Page 9
JESD22-A101-B
JESD22-B103-B
Document ID
Issued Date
Revised Date
Revision
Page.
DS-251109
2008/02/10
2010/06/10
C
9