REJ03F0272-0100 Rev. 1.00 Apr.01.2008 R8A66170DD/SP 4-CH 16-BIT PWM GENERATOR DESCRIPTION R8A66170 is a programmable 4-channel PWM generator produced using the silicon gate CMOS process. R8A66170 can connect directly to the MPU data bus, and consists of a 16-bit prescaler and a PWM counter. The pulse output includes three kinds of modes, allowing the independent control of each channel. R8A66170 provides a software servo system in combination with the A-D function and the timer function of a one-chip microcomputer. R8A66170 is a succession product of M66240. FEATURES • • • • • • • • • • 4-channel individually controllable Built-in three kind of pulse output modes PWM repetitive frequency: 50 kHz (max.) (Mode 0, 8-bit resolution, fxin/255 at prescaler setting = 0) Output polarity selection possible External triggering possible The output after reset is in the high impedance state. Change of mode setting becomes effective after the current cycle. High output current : Io = ±24 mA (VCC = 5.0V) Wide operating power voltage range (VCC = 5.0V or 3.3V single power supply) Wide operating temperature range (Ta = -40~85 ºC) APPLICATION • Control of DC motors and stepping motors • Control of Heater phase controllers • Software servos for office automation equipment , and industrial equipment PIN CONFIGURATION (TOP VIEW) D0 1 24 Vcc D1 2 23 PWM1 PWM output 1 D2 3 22 TRG1 Trigger input 1 D3 4 21 PWM2 PWM output 2 D4 5 20 TRG2 Trigger input 2 D5 6 19 PWM3 PWM output 3 D6 7 18 TRG3 Trigger input 3 D7 8 17 PWM4 PWM output 4 Write control input WR 9 16 TRG4 Trigger input 4 Command/Data control input C/D 10 15 RESET Reset input Chip select input CS 11 14 X1 Clock input GND 12 13 X2 Clock output Data bus inputs REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 1 of 20 R8A66170DD/SP FUNCTION Four separate 16-bit prescalers and 16-bit PWM counters can be separately programmed by the control instruction from the MPU. The output is made in one of three modes (Mode 0, Mode 1, and Mode 2). In Mode0, setting only the value of H width repeatedly outputs the set pulse width. In Mode1, setting only the value of H width outputs one shot of the pulse width set by trigger input. In Mode2, setting both H width and L width repeatedly outputs the set pulse width. BLOCK DIAGRAM Vcc 24 X1 14 X2 13 Oscillator circuit TRG 16-bit prescaler Selector D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 F/F Buffer PWM Inverter circuit H register L register Data bus buffer CS 11 Write control circuit WR 9 C / D 10 Selector Register RESET 15 16-bit, 8-bit PWM counter another channel 12 GND PIN DESCRIPTIONS Pin name Description I/O Function RESET Reset input Input Clears the command register and the flip-flop at “L”. D0~D7 Data bus input Input Inputs the data from MPU over the 8-bit data bus. WR Write control input Input Writes the data on data bus to the control register or data register when its state changes from “L” to “H” of rising edge. Input The Data on data bus is regarded as a command at “H” level, and as data at “L” level. Input Communication with MPU is enabled at “L” level. Any control from MPU is ignored at “H” level. C/D CS Command/Data control input Chip select input X1 Clock input Input X2 Clock output Output TRG1~ TRG4 Trigger input Input PWM1~ PWM4 PWM output Output Input and output to the built-in clock generator circuit. By providing a crystal resonator between X1 and X2, sets the frequency. To make external clock input, connect the clock source to X1 pin and leave X2 pin open. These are used when external trigger is selected in mode setting. These should be set to “L” level when not in use. PWM output pins. Outputs become the high-impedance state after reset is inputted or after disable is specified by command 3. D0 of command 1 allows the selection of output polarity. REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 2 of 20 R8A66170DD/SP OPERATION Commands The information on data bus inputs D0 through D7 is treated as command when command / data control input C/D = 1, and is treated as data when C/D = 0. There are three kinds of commands. (See Figure 1.) • Command 1 selects the output mode and external trigger input of each channel and sets the output polarity of H width. • Command 2 specifies, on a byte basis, to which 16-bit register of the prescaler and PWM counter of each channel data is to be written. The second and subsequent bytes of command 2 write prescaler value and PWM value. Depending on the location specified by command 2, the data of the second and subsequent bytes must be written in the order shown in Figure2. • Command 3 is used to start or stop the prescalers and PWM counters operation. Data input At initialization, all 16-bit of prescaler values must be written. In mode 0 or 1, the PWM values must be written to all 16-bits of H register (*1), In mode 2, the value must be written to all 16-bits of H and L registers. (*1): In mode0, at 8-bit resolution, only the lower byte of the H register is used. In case of changing the value of prescaler and PWM during for operation, the procedure is as follows. • To change the values of all 16-bits in the prescaler or the PWM counter during operation, values should be written to the upper byte first and then to the lower byte. • To change the values of the lower byte only, the values of only the lower byte should be written. • To change the values of the upper byte only, the values of all 16-bits should be written. • To change the values of H register in Mode 2, the H register values should be written followed by the L register value. When values are written to the lower byte (lower byte of L register in Mode 2), the write cycle of data registers is completed. (Note) • If the data registers values is changed during a PWM signal is outputted (exactly, finish to write those values), the PWM output is updated at the start of next cycle. • To change the mode (i.e., to execute command 1), disable the output first (i.e., execute command 3). Figure 3 shows the flow chart of the basic operation. The order of the prescaler’s and PWM counter’s data setting is not fixed. REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 3 of 20 R8A66170DD/SP Command 1 D7 "1" Mode selection enabled D6 D5 PWM number selection 00 : PWM 1 01 : PWM 2 10 : PWM 3 11 : PWM 4 D4 D3 D2 D1 PWM resolution selection 0 : 8 bit 1 : 16 bit Effective only in Mode 0 Mode selection 00 : Mode 0 01 : Mode 1 10 : Mode 2 11 : Prohibition External trigger 0 : OFF 1 : ON D0 "H" width polarity selection 0:L 1:H Command 2 D7 "0" Enable/numerical control selection enabled D6 D5 PWM number selection 00 : PWM 1 01 : PWM 2 10 : PWM 3 11 : PWM 4 D4 "0" numeriacal control enabled D3 "0" prescaler numeric value "1" PWM numeric value D2 D1 X 0 : For L width 1 : For H width D0 0 : For lower byte 1 : For upper byte X 0 : For lower byte 1 : For upper byte X "1" is specified for Mode 0 and 1. (See Fig.2) Command 3 D7 "0" Enable/numerical control selection enabled D6 D5 X X D4 "1" Enable/ control enabled D3 PWM 4 D2 D1 PWM 3 PWM 2 "0" : Disable "1" : Enable attention ① Mode 0~2 ② Mode 1, External trigger on ③ Mode 2 M = 0 Prohibition (right after Reset or Disable) M = 0 Prohibition M = N = 0 Prohibition M: H width set value N: L width set value X : Don't care Fig.1 Commands REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 4 of 20 Prescaler value and PWM counter value are set by the unit of byte after the second byte. D0 PWM 1 R8A66170DD/SP First byte (Command 2) D3 D2 D1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 0 0 0 X 1 0 X 0 The second byte Upper byte of PWM H register Lower byte of PWM H register Upper byte of PWM H register Lower byte of PWM H register Upper byte of PWM L register Lower byte of PWM L register Upper byte of prescaler register Lower byte of prescaler register The third byte The fourth byte The fifth byte - - - - Lower byte of PWM H register In Mode 0 or 1 Lower byte of PWM H register Upper byte of PWM L register Lower byte of PWM L register Remark Upper byte of PWM L register Lower byte of PWM L register Lower byte of prescaler register - Lower byte of PWM L register In Mode 2 - - - - - - - - Fig.2 Data-setting sequence for registers Reset 1 C/D=1 Mode setting (command 1) C/D=1 Prescaler setting (upper byte) (command 2) C/D=0 Prescaler value upper byte C/D=0 Prescaler value lower byte C/D=1 PWM counter setting (upper byte) (command 2) C/D=0 PWM counter upper byte C/D=0 PWM counter lower byte D7 = 1 Change setting? D7, D4, D3 = 0 D1 = 1 Yes D7, D4 = 0 Prescaler or PWM counter D3 = 0 or 1 C/D=1 setting change D2 = 1 (command 2) D1 = 0 or 1 D7, D4 = 0 D3, D2, D1 = 1 C/D=0 Upper byte of prescaler or PWM counter C/D=0 Lower byte of prescaler or PWM counter Yes C/D=1 Setting completed? Yes Output enable (command 3) Change setting? No C/D=1 No No Yes D7 = 0 D4 = 1 Start 1 Fig.3 Flow chart in Mode 0 or 1 (for one channel) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 5 of 20 Output disable (command 3) Change mode? No End D7=0 D4=1 R8A66170DD/SP PWM WAVEFORM OUTPUT R8A66170 has a built-in 16-bit prescaler and a PWM counter. The duty cycle of output pulse can be freely specified by changing the values of the prescaler and the PWM counter. The output is made in one of three modes (Mode 0, Mode 1, and Mode 2). The description of these modes is given below. (1) Mode 0 This mode is selected by writing “0” to D4 and D3 in command 1. Figure 9 shows the block diagram in this mode (for one channel). The 16-bit PWM counter can be used as an 8-bit PWM counter only in this mode (command 1: D2 = 0). The setting with PWM resolution = 8-bits must be written to the lower 8 bytes of H register. In this mode, the H output pulse width is determined by the prescaler register value L and PWM register value M. The PWM output cycle time is determined by the prescaler register value L, irrespective of the PWM register value M. (See Fig.4) 1 f (XIN) Oscillator source Internal signal Prescaler output (PWM clock) (at L = 1) L+1 f (XIN) M=0 "L" M=1 M=2 PWM output M=3 L+1 ・M f (XIN) ・ ・ ・ M=65534 (254) M=65535 (255) "H" L+1 ・(2A-1) f (XIN) ( ): When PWM resolition is 8-bits Fig.4 (When H width polarity is “H”) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 6 of 20 :Cycle time (μs) T f(XIN) :Oscillator frequency (MHz) :Prescaler set value L :Ｈ width set value M :PWM resolution (8 or 16) A R8A66170DD/SP (2) Mode1 This mode is selected by setting D4 = 0 and D3 = 1 in command 1. Figure 10 shows the block diagram in this mode (for one channel). This mode outputs the pulse which is determined by value M of PWM register as one shot by trigger signal. The type of this output operation is determined by whether the external trigger signal or the internal trigger signal is used. Operation varies according to the choice of external and internal trigger signals. (a) External trigger selected (D1 = 1 in command 1) This mode outputs, when a trigger pulse is applied to trigger input TRG, one shot of output pulse. Therefore, cycle time T becomes cycle time fIN of the trigger pulse to be applied to trigger input TRG. The output pulse width is determined by the prescaler register value L and PWM register value M. (See Fig.5) 1 f (XIN) Oscillator source 1 f IN TRG trigger input Internal signal Prescaler output (PWM clock) (at L = 1) M=0 L+1 f (XIN) "L" M=1 PWM output M=2 M=3 ・ ・ ・ L+1 ・M f (XIN) T= 1 f IN :Cycle time (μs) T f(XIN) :Oscillator frequency (MHz) :Prescaler set value L :Ｈ width set value M fIN :Trigger input frequency (MHz) Fig.5 (When H width polarity is “H”) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 7 of 20 R8A66170DD/SP (b) Internal trigger selected (D1 = 0 in command 1) In this mode, the trigger signal is generated by the prescaler. Therefore, the cycle time T of output pulse is determined by the prescaler register value L. In this case, the oscillator source becomes the PWM counter clock and the output pulse width is determined by the PWM register value M. (See Fig.6) 1 f (XIN) Oscillator source Internal signal L+1 f (XIN) Prescaler output (Internal trigger) (at L = 11) M=0 "L" M=1 PWM output M=2 M=3 ・ ・ ・ M f (XIN) T= L+1 f (XIN) :Cycle time (μs) T f(XIN) :Oscillator frequency (MHz) L :Prescaler set value :Ｈ width set value M Fig.6 (When H width polarity is “H”) In Mode 1, the retrigger state is caused when the cycle time of trigger pulse gets smaller than the value M of PWM register. REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 8 of 20 R8A66170DD/SP (3) Mode 2 This mode is selected by writing D4 = 1 and D3 = 0 in command 1. Fig.11 shows the block diagram of this mode (for one channel). The high-level pulse value M is set to the H register of PWM in Mode 0 and 1, but in this mode, the high-level pulse value M is set to the H register of PWM and the low-level pulse value N is set to the L register of PWM. Therefore, the pulse width and cycle time T of PWM output are determined by value L of the prescaler register and values M and N of H and L registers of PWM. (See Fig.7) 1 f (XIN) Oscillator source Internal signal Prescaler output (PWM clock) (at L = 1) M=0 N=3 L+1 f (XIN) "L" M=1 N=3 M=2 N=3 M=3 N=3 ・ ・ ・ PWM output M=65535 N=3 M=3 N=0 "H" M=3 N=1 M=3 N=2 M=3 N=3 ・ ・ ・ L+1 f (XIN) ・M M=3 N=65535 L+1 f (XIN) ・N T= L+1 ・(M+N) f (XIN) Fig.7 (When H width polarity is “H”) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 9 of 20 :Cycle time (μs) T f(XIN) :Oscillator frequency (MHz) :Prescaler set value L :Ｈ width set value M N :L width set value R8A66170DD/SP Initial state In the case of command 1, if the D1 is set as “external trigger ON” it does not output a pulse to PWM output and its status is held in the high impedance even if the operation of internal circuit is started by specifying enable condition with command 3. In this case the pulse can be output to PWM output by entering H level into TRG input in Mode 0,Mode 2 or entering H pulse into TRG input in Mode1. (See Fig.8) In Mode 0 or Mode 2, putting TRG input to L level during PWM is outputting pulse makes PWM output keeps its state. When TRG input is put back to H level, the operation are resumed from that point. Command 3 D0～D7 Enable CS C/D WR Oscillator source Internal signal Prescaler output (PWM clock) External trigger off PWM output "Z" External trigger on TRG PWM output "Z" (L=1, M=3) Fig.8 (When H width polarity is “H”) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 10 of 20 R8A66170DD/SP Control circuit Oscillator circuit TRG H 8 16-bit Prescaler 16- and 8-bit PWM counter Register Inverting circuit H register 8 F/F Buffer PWM 8 Fig.9 Block diagram in Mode 0 (for one channel) Control circuit Oscillator circuit TRG 8 16-bit Prescaler 16-bit PWM counter Register H register F/F Buffer PWM 8 8 Fig.10 Block diagram in Mode 1 (for one channel) Oscillator circuit TRG 16-bit Prescaler Register H 16-bit PWM counter H register Control circuit L register 8 8 8 Fig.11 Block diagram in Mode 2 (for one channel) REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 11 of 20 F/F Buffer PWM R8A66170DD/SP ABSOLUTE MAXIMUM RATINGS ( Ta=-40~85°C, unless otherwise noted ) Symbol Parameter Conditions Ratings Unit Vcc Power voltage -0.5~+7.0 V VI Input voltage -0.5~Vcc+0.5 V VO Output voltage -0.5~Vcc+0.5 V Pd Power dissipation 500 mW Tstg Storage temperature -65~150 °C RECOMMENDED OPERATING CONDITIONS ( Ta=-40~85°C, unless otherwise noted ) Symbol Parameter 5.0V support 3.3V support Vcc Power voltage GND VI VO Topr Power voltage Input voltage Output voltage Ambient operating temperature Min. 4.5 3.0 Limits Typ. 5.0 3.3 0 0 0 -40 Max. 5.5 3.6 Vcc Vcc 85 Unit V V V V V °C ELECTRICAL CHARACTERISTICS 5.0V version support specifications ( Ta=-40~85°C, Vcc=4.5~5.5V, unless otherwise noted ) Limits Symbol Parameter Test conditions Unit Min. VT+ VT- Positive going threshold voltage Negative going threshold voltage VH Hysteresis width VIH "H" input voltage VIL "L" input voltage VIH "H" input voltage RESET, TRG1~4 D0~D7, CS,WR,C/D "L" input voltage VOH "H" output voltage VOL "L" output voltage IIH Max. 0.35×Vcc 0.8×Vcc V 0.2×Vcc 0.65×Vcc V 0.4 V 0.75×Vcc V IO=20uA 0.25×Vcc 0.8×Vcc X1 VIL IO=20uA Typ. V IO=20uA 0.2×Vcc PWM1~ PWM4 V IOH=-24mA Vcc - 0.8 V V IOL=24mA 0.55 V "H" input current VI=Vcc 1.0 uA IIL "L" input current VI=GND -1.0 uA IOZH Off-state "H" output current VO=Vcc 5.0 uA IOZL Off-state "L" output current VO=GND -5.0 uA Icc Quiescent current consumption VI=Vcc, GND, Outputs are open. 100 uA REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 12 of 20 R8A66170DD/SP ELECTRICAL CHARACTERISTICS 3.3V version support specifications ( Ta=-40~85°C, Vcc=3.0~3.6V, unless otherwise noted ) Limits Symbol Parameter Test conditions Unit Min. VT+ VT- Positive going threshold voltage Negative going threshold voltage VH Hysteresis width VIH "H" input voltage VIL "L" input voltage VIH "H" input voltage RESET, TRG1~4 D0~D7, CS,WR,C/D "L" input voltage VOH "H" output voltage VOL "L" output voltage IIH Max. 0.35×Vcc 0.8×Vcc V 0.2×Vcc 0.65×Vcc V 0.4 V 0.75×Vcc V IO=20uA 0.25×Vcc 0.8×Vcc X1 VIL IO=20uA Typ. V IO=20uA 0.2×Vcc PWM1~ PWM4 V IOH=-12mA Vcc - 0.6 V V IOL=12mA 0.4 V "H" input current VI=Vcc 1.0 uA IIL "L" input current VI=GND -1.0 uA IOZH Off-state "H" output current VO=Vcc 5.0 uA IOZL Off-state "L" output current VO=GND -5.0 uA Icc Quiescent current consumption VI=Vcc, GND, Outputs are open. 100 uA REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 13 of 20 R8A66170DD/SP SWITCHING CHARACTERISTICS ( Ta=-40~85°C, Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise noted) 5.0V specification Symbol Parameter 3.3V specification Test conditions Unit Min. Typ. Max. Min. Typ. Max. 2 f +110 2 f +130 ns tpZH(W-PWM) 2 f +110 2 f +130 ns tpZL(W-PWM) 3 f +110 3 f +130 ns tpZH(W-PWM) 3 f +110 3 f +130 ns tpZL(T-PWM) 2 f +110 2 f +130 ns tpZH(T-PWM) 2 f +110 2 f +130 ns tpZL(T-PWM) L+2 f +110 L+2 f +130 ns L+2 f +110 L+2 f +130 ns 110 130 ns 110 130 ns L+2 f +110 L+2 f +130 ns L+2 f +110 L+2 f +130 ns 150 160 ns tpHZ(R-PWM) 150 160 ns tpLZ(W-PWM) 150 160 ns 150 160 ns tpZL(W-PWM) Output enable time after write (Mode0, 2, external trigger OFF) Output enable time after write (Mode1, external trigger OFF) Output enable time after trigger (Mode0, 2, external trigger ON) Output enable time after trigger (Mode1, external trigger ON) tpZH(T-PWM) CL=50pF tpLH(X1-PWM) tpHL(X1-PWM) tpLH(T-PWM) tpHL(T-PWM) Output propagation time after clock (all modes) Output propagation time after trigger (Mode1, external trigger ON) tpLZ(R-PWM) Output disable time after reset Output disable time after write tpHZ(W-PWM) f : Clock input frequency (MHz) L: Prescaler set value REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 14 of 20 R8A66170DD/SP TIMING REQUIREMENTS ( Ta=-40~85°C, Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise noted) Symbol Parameter tc(X1) Clock cycle tWH(X1) Test conditions 5.0V specification 3.3V specification Unit Min. Typ. Max. Min. Typ. Max. 78.5 78.5 ns Clock "H" pulse width 35 35 ns tWL(X1) Clock "L" pulse width 35 35 ns tr(X1) Clock rise time 20 20 ns tf(X1) Clock fall time 20 20 ns tsu(A-W) Address setup time before write (CS, C/D) 0 0 ns th(W-A) Address hold time after write (CS, C/D) 0 0 ns tsu(D-W) Data setup time before write 100 100 ns th(W-D) Data hold time after write 0 0 ns tw(W) Write pulse width 100 100 ns trec(W) Write recovery time 100 100 ns tw(T) Trigger pulse width 100 100 ns tw(R) Reset pulse width 100 100 ns trec(R-W) Recovery time before write 100 100 ns REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 15 of 20 R8A66170DD/SP TIMING DIAGRAM (1) MCU interface Vcc X1 0V tw (CK) Vcc CS 0V th(W-A) tsu(A-W) Vcc C/D 0V tsu(A-W) th(W-A) th(W-A) tsu(A-W) Vcc WR 0V trec(W) D0～D7 tw (W) tsu(D-W) Vcc Command3 (Enable) Data 0V th(W-D) (External trigger = OFF) Internal signal (Prescaler output) tpZH(W-PWM) VOH PWM 1～4 VOL tpZL(W-PWM) VOH PWM 1～4 VOL (External trigger = ON) Vcc TRG 1～4 0V tpZH(T-PWM) VOH PWM 1～4 VOL tpZL(T-PWM) VOH PWM 1～4 VOL REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 16 of 20 R8A66170DD/SP (2) In operation Mode 0,2 (external trigger ON, OFF) Vcc X1 50% 50% 0V Internal signal (Prescaler output) tpLH(X1-PWM) tpHL(X1-PWM) VOH PWM 1～4 50% 50% VOL tpHL(X1-PWM) tpLH(X1-PWM) VOH PWM 1～4 50% 50% VOL Mode 1 (external trigger ON) Vcc 50% X1 0V Internal signal (Prescaler output) tw (T) Vcc TRG 1～4 50% 50% 0V tpHL(X1-PWM) tpLH(T-PWM) VOH PWM 1～4 50% 50% VOL tpHL(T-PWM) tpLH(X1-PWM) PWM 1～4 50% VOH 50% VOL Mode 1 (external trigger OFF) Vcc X1 50% 50% 0V Internal signal (Prescaler output) tpLH(X1-PWM) tpHL(X1-PWM) VOH PWM 1～4 50% 50% VOL tpHL(X1-PWM) tpLH(X1-PWM) VOH PWM 1～4 50% 50% VOL REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 17 of 20 R8A66170DD/SP (3) At reset Vcc RESET 50% 50% 0V tw (R) trec(R-W) Vcc WR 50% 0V tpLZ PWM 1 ～4 10% VOL tpHZ PWM 1 ～4 VOH 90% (4) At disable Vcc ＣＳ 0V Vcc 50% WR 0V Vcc C/D 0V Vcc D0～D7 Command 3 (Disable) 0V tpLZ PWM 1～4 10% VOL tpHZ PWM 1～4 REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 18 of 20 90% VOH R8A66170DD/SP TEST CIRCUIT Input Vcc Output Vcc RL=500Ω SW DUT P.G. 50Ω GND CL Parameter tTLH, tTHL tpLH, tpHL tpLZ tpHZ tpZL tpZH SW Open Close Open Close Open RL=500Ω (1) Characteristics of pulse generater(P.G.) (10%～90%) tr=3ns, tf=3ns (2) CL includes stray probe and wiring capacitance. APPLICATION EXAMPLE Run-system motor MCU Pulse cycle measuring FG pulse Analog input Eraser Voltage ROM R8A66170 Driver Lamp Light volume RAM Peripheral Fixing heater REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 19 of 20 Temperatrure R8A66170DD/SP PACKAGE OUTLINE Product Name Package RENESAS Code Previous Code R8A66170DD 24pin DIP PRDP0024AF-A 24P4X-A R8A66170SP 24pin SOP PRSP0024DF-A 24P2X-B All trademarks and registered trademarks are the property of their respective owners. REJ03F0272-0100 Rev.1.00 Apr.01.2008 Page 20 of 20