Formosa MS

Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
List
List................................................................................................. 1
Package outline............................................................................... 2
Features.......................................................................................... 2
Mechanical data............................................................................... 2
Maximum ratings ............................................................................. 2,3
Rating and characteristic curves........................................................ 4,5
Pinning information........................................................................... 6
Marking........................................................................................... 6
Suggested solder pad layout............................................................. 6
Packing information.......................................................................... 7
Reel packing.................................................................................... 8
Suggested thermal profiles for soldering processes............................. 8
High reliability test capabilities........................................................... 9
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Page 1
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
60V N-Channel Enhancement
Mode MOSFET- ESD Protection
Package outline
Features
0.012 (0.30)
0.020 (0.50)
.084(2.10)
.068(1.70)
0.110 (2.80)
0.120 (3.04)
solid-state relays drivers, relays, displays, lamps,
solenoids, memories, etc.
In compliance with EU RoHS 2002/95/EC directives.
Suffix "-H" indicates Halogen-free part, ex. 2N7002K-H.
(B)
(C)
(A)
0.063 (1.60)
0.027 (0.67)
0.013 (0.32)
0.047 (1.20)
0.108 (2.75)
R 0.05
(0.002)
Mechanical data
0.051 (1.30)
0.003 (0.09)
0.083 (2.10)
0.007 (0.18)
•
•
0.045 (1.15)
• R DS(ON), V GS@10V, I D@500mA=3.0 Ω
• R DS(ON), V [email protected], I D@200mA=4.0 Ω
• ESD protection 2KV (Human body mode)
• Advanced trench process technology.
• High density cell design for ultra low on-resistance.
• Very low leakage current in off condition
• Specially designed for battery operated system,
0.034 (0.85)
SOT-23
0.034 (0.89)
• Epoxy:UL94-V0 rated flame retardant
• Case : Molded plastic, SOT-23
• Terminals : Solder plated, solderable per
Dimensions in inches and (millimeters)
MIL-STD-750, Method 2026
• Polarity : Indicated by cathode band
• Mounting Position : Any
• Weight : Approximated 0.0084 gram
M aximum ratings (AT T
A
=25 oC unless otherwise noted)
PARAMETER
CONDITIONS
Symbol
Ratings
UNIT
Drain-Source voltage
V DS
60
V
Gate-source voltage
V GS
±20
V
Continuous drain current
ID
300
mA
I DM
2000
mA
Pulsed drain current
1)
PARAMETER
CONDITIONS
P D@T A= 25°C
Total power dissipation
Symbol
MIN.
TYP.
Thermal resistance(PCB mounted)
2)
W
0.21
T J , T STG
Junction to ambient
UNIT
0.35
PD
P D@ T A=75°C
Operation junction and storage temperature range
MAX.
o
+150
-55
o
357
R θJA
C
C/W
Note : 1. Maximum DC current limited by package
2. Surface mounted on FR4 board, t < 5 sec
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Page 2
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
Electrical characteristics (AT T =25 C unless otherwise noted)
o
A
PARAMETER
CONDITIONS
Drain-source Breakdown Voltage
Gate Threshold Voltage
Symbol
MIN.
V GS = 0V, I D = 10µA
BV DSS
60
V DS = V GS , I D = 250µA
V GS(th)
1.0
TYP.
MAX.
V
2.5
V GS = 10V, I D = 500mA
V
3.0
Drain-Source On-State Resistance
Ω
R DS(on)
V GS = 4.5V, I D = 200mA
4.0
µA
V DS = 60V, V GS = 0V
I DSS
1
Gate-Body leakage Current
V GS = +/-20V, V DS = 0V
I GSS
±10
Forward TransConductance
V DS = 15V, I D = 250mA
g fS
V DS = 15V, I D = 200mA
V GS = 4.5V
Qg
0.80
t on
20
t off
40
Zero Gate Voltage Drai n Current
UNIT
µA
mS
100
DYNAMIC
Total Gate Charge
Turn-On Delay Time
V DD = 30V, R L = 150Ω, I D = 200mA,
V gen = 10V, R G = 10Ω
Turn-Off Delay Time
ns
Input Capacitance
V DS = 25V, V GS = 0V
f = 1.0 MHz
Output Capacitance
nC
Reverse Transfer Capacitance
C iss
35
C oss
10
C rss
5
pF
Source-Drain Diode
Diode Forward Voltage
V SD
I S=200mA, V GS=0V
Switching
Test Circuit
0.82
Gate Charge
Test Circuit
V DD
V DD
RL
V IN
V GS
V
1.3
RL
V OUT
D
V GS
D
1mA
RG
V GS
DUT
DUT
G
G
RG
S
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S
Page 3
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Rating and characteristic curves (2N7002K)
FIG.2 TRANSFER CHARACTERISTIC
FIG.1 TYPICAL FORWARD CHARACTERISTIC
1.2
V GS = 6V~10V
DRAIN TO SOURCE CURRENT,(A)
DRAIN TO SOURCE CURRENT,(A)
1.2
5.0V
1.0
4.0V
0.8
0.6
0.4
3.0V
0.2
V DS = 10V
1.0
0.8
0.6
0.4
o
25 C
0.2
0
0
0
1
2
3
4
5
0
1
DRAIN TO SOURCE VOLTAGE, (V)
4
5
6
FIG.4 ON RESISTANCE VS GATE TO SOURCE VOLTAGE
5
5
4
4
ON-RESISTANCE, (ohm)
ON-RESISTANCE, (ohm)
3
GATE TO SOURCE VOLTAGE, (V)
FIG.3 ON RESISTANCE VS DRAIN CURRENT
3
V GS = 4.5V
2
2
1
3
I D = 500mA
2
I D = 200mA
1
V GS = 10V
0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
2
3
4
5
6
7
8
9
10
GATE TO SOURCE VOLTAGE, (V)
DRAIN current, (A)
STATIC DRAIN-SOURCE ON-RESISTANCE
, VDS(0N) (NORMALIZED)
FIG.5 ON RESISTANCE VS JUNCTION TEMPERATURE
7.7
7.0
V GS = 10V
6.3
I D = 500mA
5.6
4.9
4.2
3.5
2.8
2.1
1.4
0.7
-60
-20
+20
+60
+100
+140
o
JUNCTION TEMPERATURE, ( C)
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Page 4
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Rating and characteristic curves (2N7002K)
FIG.7 GATE CHARGE
FIG.6 GATE CHARGE WAVEFORM
10
Vgs
Qsw
Vgs(th)
V DS = 10V
GATE TO SOURCE VOLTAGE,(V)
Qg
8
I D = 250mA
6
4
2
0
0
Qg(th)
Qgs
0.2
0.6
0.8
1.0
GATE CHARGE, (nC)
Qg
Qgd
0.4
GATE CHARGE WAVEFORM
FIG.8 THRESHOLD VOLTAGE VS TEMPERATURE
FIG.9 BREAKDOWN VOLTAGE VS JUNCTION TEMPERATURE
90
V DS =V GS
88
1.10
I D = 10mA
86
BREAKDOWN VOLTAGE, (V)
THRESHOLD VOLTAGE, (V) NORMALIZED
1.20
1.15
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
I D = 250uA
84
82
80
78
76
74
72
-60
-20
+20
+60
+100
+140
-50
o
-25
0
25
50
75
100
125
150
o
JUNCTION TEMPERATURE, ( C)
JUNCTION TEMPERATURE, ( C)
FIG.10 SOURCE-DRAIN DIODE FORWARD VOLTAGE
10
SOURCE CURRENT,(A)
V GS = 0V
1
o
25 C
o
125 C
o
-55 C
0.1
0.01
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
SOURCE TO DRAIN VOLTAGE, (V)
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Page 5
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
Pinning information
Pin
Simplified outline
Symbol
D
PinD
PinG
PinS
Drain
Drain
Gate
Source
Gate
G
Source
S
Marking
Type number
Marking code
02KYM
(Note 1)
K72
2N7002K
7002K
Note:1.YM indicate Date ode,
Y= year code, 8=2008, 9=2009
M= week code, A~Z = 1st ~ 26th week
a ~z= 27th ~ 52nd week
. =53rd week
Suggested solder pad layout
SOT-23
0.037(0.95)
0.037(0.95)
0.079(2.0)
0.035(0.90)
0.031(0.80)
Dimensions in inches and (millimeters)
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TEL:886-2-22696661
FAX:886-2-22696141
Page 6
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
Packing information
P0
P1
d
E
F
B
A
W
P
D2
D1
T
C
W1
D
unit:mm
Item
Symbol
Tolerance
SOT-23
Carrier width
Carrier length
Carrier depth
Sprocket hole
13" Reel outside diameter
13" Reel inner diameter
7" Reel outside diameter
7" Reel inner diameter
Feed hole diameter
Sprocket hole position
Punch hole position
Punch hole pitch
Sprocket hole pitch
Embossment center
Overall tape thickness
Tape width
Reel width
A
B
C
d
D
D1
D
D1
D2
E
F
P
P0
P1
T
W
W1
0.1
0.1
0.1
0.1
2.0
min
2.0
min
0.5
0.1
0.1
0.1
0.1
0.1
0.1
0.3
1.0
3.15
2.77
1.22
1.50
178.00
55.00
13.00
1.75
3.50
4.00
4.00
2.00
0.23
8.00
12.0
Note:Devices are packed in accor dance with EIA standar RS-481-A and specifications listed above.
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TEL:886-2-22696661
FAX:886-2-22696141
Page 7
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
Reel packing
PACKAGE
REEL SIZE
SOT-23
7"
REEL
(pcs)
COMPONENT
SPACING
(m/m)
BOX
(pcs)
INNER
BOX
(m/m)
REEL
DIA,
(m/m)
3,000
4.0
15,000
183*183*123
178
CARTON
SIZE
(m/m)
382*262*387
CARTON
(pcs)
APPROX.
GROSS WEIGHT
(kg)
11.6
240,000
Suggested thermal profiles for soldering processes
1.Storage environment: Temperature=5 oC ~40 oC Humidity=55%±25%
2.Reflow soldering of surface-mount devices
Critical Zone
TL to TP
Tp
TP
Ramp-up
TL
TL
Tsmax
Temperature
Tsmin
tS
Preheat
Ramp-down
25
t25o C to Peak
Time
3.Reflow soldering
Profile Feature
Soldering Condition
Average ramp-up rate(T L to T P )
o
<3 C /sec
Preheat
-Temperature Min(Tsmin)
-Temperature Max(Tsmax)
-Time(min to max)(t s )
150 oC
200 oC
60~120sec
Tsmax to T L
-Ramp-upRate
<3 oC/sec
Time maintained above:
-Temperature(T L )
-Time(t L )
217 oC
60~260sec
255 oC-0/+5 oC
Peak Temperature(T P )
Time within 5 oC of actual Peak
Temperature(t P )
10~30sec
Ramp-down Rate
<6 oC/sec
Time 25 oC to Peak Temperature
<6minutes
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Page 8
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9
Formosa MS
ESD N-Channel SMD MOSFET
2N7002K
High reliability test capabilities
Item Test
Conditions
Reference
MIL-STD-750D
METHOD-2031
O
1. Solder Resistance
at 260 ± 5 C for 10 ± 2sec.
immerse body into solder 1/16"±1/32"
at 245±5 C for 5 sec.
MIL-STD-202F
METHOD-208
V DS =0.8 X BV DSS, V GS =0V at T J=150 OC for 168 hrs.
MIL-STD-750D
METHOD-1026
O
2. Solderability
3. High Temperature Reverse Bias
MIL-STD-750D
METHOD-1027
O
4. Operation Life Test
Continuous operation at max rated T A=25 C,
P C=P C(max) for 500hrs.
5. Pressure Cooker
15P SIG at T A=121 OC for 4 hrs.
6. Temperature Cycling
-55 C to +125 C dwelled for 30 min.
and transferred for 5min. total 10 cycles.
7. Thermal Shock
0 OC for 5 min. rise to 100 OC for 5 min. total 10 cycles.
MIL-STD-750D
METHOD-1056
8. Humidity
at T A=85 OC, RH=85% for 1000hrs.
MIL-STD-750D
METHOD-1038
9. High Temperature Storage Life
at 175 OC for 1000 hrs.
MIL-STD-750D
METHOD-1031
O
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JESD22-A102
MIL-STD-750D
METHOD-1051
O
Page 9
Document ID
Issued Date
Revised Date
DS-251105
2008/02/10
2010/05/10
Revision
E
Page.
9