Le58083

™
Le58083
Low Voltage Subscriber Line Audio-processing Circuit
VE580 Series
APPLICATIONS
RELATED LITERATURE
■ Codec function on telephone switch line cards
■ 080753 Le58QL02/021/031 QLSLAC™ Data Sheet
■ 080754 Le58QL061/063 QLSLAC™ Data Sheet
■ 080761 QSLAC™ to QLSLAC™ Design Conversion
FEATURES
■ Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
■ Pin programmable PCM/MPI or GCI interface
■ Software and coefficient compatible to the VE580
series QLSLAC™ devices
■ Standard PCM/microprocessor interface
(PCM/MPI mode)
—
—
—
—
—
Single or Dual PCM ports available
Time slot assigner (up to 128 channels per port)
Clock slot and transmit clock edge options
Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,
or 8.192 MHz master clock derived from MCLK or PCLK
— µP access to PCM data
— Real Time Data with interrupt (open drain or TTL)
— Broadcast mode
■ General Circuit Interface (GCI mode)
— Control and PCM data on a single port
— 2.048 Mbits/s data rate
— 2.048 MHz or 4.096 MHz clock option
■ Performs the functions of eight codec/filters
■ Software programmable:
— SLIC device input impedance and Transhybrid balance
— Transmit and receive gains and Equalization
— Programmable Digital I/O pins with debouncing
■ A-law, µ-law, or linear coding
■ Built-in test modes with loopback, tone generation,
and µP access to PCM data
■
■
■
■
Mixed state (analog and digital) impedance scaling
Guide
■ 080758 QSLAC™ to QLSLAC™ Guide to New Designs
DESCRIPTION
The Le58083 Octal Low Voltage Subscriber Line AudioProcessing Circuit (Octal SLAC™) devices integrate the key
functions of analog line cards into high-performance, veryprogrammable, eight-channel codec-filter devices. The
Le58083 Octal SLAC devices are based on the proven design
of Zarlink’s reliable SLAC device families. The advanced
architecture of the Le58083 Octal SLAC devices implements
eight independent channels and employs digital filters to allow
software control of transmission, thus providing a cost-effective
solution for the audio-processing function of programmable line
cards. The Le58083 Octal SLAC devices are software and
coefficient compatible to the VE580 series QLSLAC™ devices.
Advanced submicron CMOS technology makes the Le58083
Octal SLAC devices economical, with both the functionality and
the low power consumption needed in line card designs to
maximize line card density at minimum cost. When used with
multiple Zarlink SLIC devices, an Le58083 Octal SLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
GCI/PCM
Interface
ANALOG
DXA/DU
DRA/DD
VIN(1-8)
VOUT (1-8)
TSCA
Signal
Processing
Channels 1-8
PCM & GCI Interface
&
Time Slot Assigner
(TSA)
Performance guaranteed over a 12 dB gain range
DXB
DRB
TSCB
Supports multiplexed SLIC device outputs
256 kHz or 293 kHz chopper clock for Zarlink SLIC
devices with switching regulator
■ Maximum channel bandwidth for V.90 modems
ORDERING INFORMATION
Device
Le58083ABGC
Package
121-pin BGA (Green package)*
VREF_1, VREF_2
SLIC
CONTROLS
Clock
&
Reference
Circuits
CD1(1-8)
CD2(1-8)
C3(1-8)
C4(1-8)
FS/FSC
PCLK/DCL
MCLK_1, MCLK_2
SLIC
Interface
(SLI)
DCLK-S0_1, DCLK-SO_2
C5(1-8)
CS/PG_1, CS/PG_2
C6(1-8)
C7(1-8)
GCI Control Logic &
Microprocessor Interface
(MPI)
DIO-S1_1, DIO-S1_2
INT_1, INT_2
*Green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
RST
Document ID# 080921 Date:
Rev:
E
Version:
Distribution:
Public Document
Sep 18, 2007
2
Le58083
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Clock and Reference Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Microprocessor Interface (MPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Time Slot Assigner (TSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Signal Processing Channels (CHx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SLIC Device Interface (SLI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
121-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Transmission Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gain Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against 12- and 16-kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Operating the Le58083 Octal SLAC Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PCM and GCI State Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Channel Enable (EC) Register (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
SLIC Device Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Debounce Filters Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Inactive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Frequency Response Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Transhybrid Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Transmit PCM Interface (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Data Upstream Interface (GCI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Receive PCM Interface (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Data Downstream Interface (GCI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Double PCLK (DPCK) Operation (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Signaling on the PCM Highway (PCM/MPI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Robbed-Bit Signaling Compatibility (PCM/MPI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Default Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Command Description and Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Command Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Microprocessor Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Summary of MPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
MPI Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
00h Deactivate (Standby State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
02h Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
04h Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
06h No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
0Eh Activate Channel (Operational State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
40/41h Write/Read Transmit Time Slot and PCM Highway Selection . . . . . . . . . . . . . . . . . . . . . .47
42/43h Write/Read Receive Time Slot and PCM Highway Selection . . . . . . . . . . . . . . . . . . . . . .47
44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge . . . . . . .48
46/47h Write/Read Chip Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4A/4Bh Write/Read Channel Enable and Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . .49
4D/4Fh Read Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
50/51h Write/Read AISN and Analog Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
52/53h Write/Read SLIC Device Input/Output Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits . . . . . . . . . . . . . . . . . .51
60/61h Write/Read Operating Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6C/6Dh Write/Read Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
70/71h Write/Read Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
73h Read Revision Code Number (RCN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
80/81h Write/Read GX Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
82/83h Write/Read GR Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
84/85h Write/Read Z Filter Coefficients (FIR and IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
86/87h Write/Read B1 Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
88/89h Write/Read X Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8A/8Bh Write/Read R Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
96/97h Write/Read B2 Filter Coefficients (IIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
98/99h Write/Read FIR Z Filter Coefficients (FIR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
9A/9Bh Write/Read IIR Z Filter Coefficients (IIR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
C8/C9h Write/Read Debounce Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
CDh Read Transmit PCM Data (PCM/MPI Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
E8/E9h Write/Read Ground Key Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
General Circuit Interface (GCI) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
GCI General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
GCI Format and Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Signaling and Control (SC) Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Programming with the Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Channel Identification Command (CIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
General Structure of Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Summary of Monitor Channel Commands (GCI Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
TOP (Transfer Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SOP (Status Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SOP Control Byte Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
COP (Coefficient Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Details of COP, CSD Data Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
General Description of CSD Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
User Test States and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Line card parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
LFBGA (121 Balls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revision E1 to E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Transmit Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
µ-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Spurious Out-of-Band Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Analog-to-Analog Overload Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Microprocessor Interface (Output Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . .24
PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . .25
Double PCLK PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.096 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.048 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Mode Options (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation. . . . . . . . . . . .34
E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MPI Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Le58083 Octal SLAC Transmission Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Robbed-Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Time Slot Control and GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Multiplexed GCI Time Slot Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Security Procedure for C/I Downstream Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Maximum Speed Monitor Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Monitor Transmitter Mode Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Monitor Receiver State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Le57D11 SLIC/Le58083 Octal SLAC™ Application Circuit . . . . . . . . . . . . . . . . . . . . .91
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Le58083 Octal SLAC™ Device Pin Names and Numbers . . . . . . . . . . . . . . . . . . . . . . . .8
0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR . . . . . . . . . . .14
PCM/GCI Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Channel Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Channel Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Global Chip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Global Chip Status Monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
GCI Channel Assignment Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Generic Byte Transmission Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Byte Transmission Sequence for TOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
General Transmission Sequence of SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Generic Transmission Sequence for COP Command . . . . . . . . . . . . . . . . . . . . . . . . . .79
A-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
PRODUCT DESCRIPTION
The Le58083 Octal SLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber
line interface circuitry in telecommunications equipment. These functions involve converting audio signals into digital PCM
samples and converting digital PCM samples back into audio signals. During conversion, digital filters are used to band limit the
voice signals. All of the digital filtering is performed in digital signal processors operating from a master clock, which can be
derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI mode.
The Le58083 Octal SLAC device is configured as two four-channel groups that share a common reset and PCM/GCI interface.
Each four-channel group has its own chip select for individual programming. The signal names for each four-channel SLAC
device are differentiated by _1 or _2. Generic naming of each signal is C_X, where the subscript C equals the channel number
1 through 4 and the _X equals the four-channel group number 1 or 2. For example, VIN3_2 would identify channel 3 of the second
four-channel group.
Eight independent channels allow the Le58083 Octal SLAC device to function as eight SLAC devices. In PCM/MPI mode, each
channel has its own enable bit (EC1, EC2, EC3, etc.) to allow individual channel programming. If more than one Channel Enable
bit is High or if all Channel Enable bits are High, all channels enabled will receive the programming information written; therefore,
a Broadcast mode can be implemented by simply enabling all channels in the device to receive the information and enabling both
chip selects. The Channel Enable bits are contained in the Channel Enable (EC) register, which is written and read using
Commands 4A/4Bh. The Broadcast mode is useful in initializing Le58083 Octal SLAC devices in a large system.
In GCI mode, one GCI channel controls two channels of the Le58083 Octal SLAC device. The Monitor channel and SC channel
within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write data to/from
the programmable I/O ports of the two channels. Two pairs of GCI channels control the two four-channel groups in the Le58083
Octal SLAC device. The four GCI channels used, of the eight total available, are determined by S0 and S1 inputs.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment
of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All programmable digital filter
coefficients can be calculated using the WinSLAC™ software.
In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code (with an optional 8-bit
signaling byte in the transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time slot, while the 16-bit code
appears in two consecutive time slots. The compressed PCM codes can be either 8-bit companded A-law or µ-law. The PCM
data is read from and written to the PCM highway in user-programmable time slots at rates of 128 kHz to 8.192 MHz. The transmit
clock edge and clock slot can be selected for compatibility with other devices that can be connected to the PCM highway.
In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM codes can be
either 8-bit companded A-law or µ-law. There is no Signaling or Linear mode available when GCI mode is selected.
The programming software is backward compatible to the Zarlink Le58000 SLAC family of devices.
DEVICE DESCRIPTION
PCM/GCI Highway
Programmable I/O
per Channel
Dual/single
Chopper Clock
Package
Part Number
Yes
BGA
Le58083GC
Five I/O
Two Output
BLOCK DESCRIPTIONS
Clock and Reference Circuits
This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog reference voltage
for the analog circuits.
Microprocessor Interface (MPI)
This block communicates with the external control microprocessor over a serial interface. It passes user control information to
the other blocks, and it passes status information from the blocks to the user. In addition, this block contains the reset circuitry.
When GCI is selected, this block is combined with the TSA block.
Time Slot Assigner (TSA)
This block communicates with the PCM highway, where the PCM highway is a time division mutiplexed bus carrying the digitized
voice samples. The block implements programmable time slots and clocking arrangements in order to achieve a first layer of
switching. Internally, this block communicates with the Signal Processing Channels (CHx). When GCI is selected, this block is
combined with the TSA block.
6
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Signal Processing Channels (CHx)
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is interfaced to the VIN
and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot Assigner (TSA) block.
SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to
operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering.
CONNECTION DIAGRAM
121-Pin BGA
L
VIN 4 _1
VIN 4 _2
NC
C5 3 _1
C4 3 _2
DGND
C5 4 _1
C3 4 _2
C7 4 _2
DRA/DD
DXB
K
VOUT 4 _1
VOUT 4 _2
VCCA
C4 3 _1
C3 3 _2
VCCD
C4 4 _1
CD2 4 _2
C6 4 _2
DRB
DXA/DU
J
NC
NC
AGND
C3 3 _1
CD2 3 _2
C7 3 _2
C3 4 _1
CD1 4 _2
C5 4 _2
FS/FSC
TSCB
H
VREF_2
AGND
AGND
CD2 3 _1
CD1 3 _2
C6 3 _2
CD2 4 _1
NC
C4 4 _2
RST
TSCA
G
VREF_1
VCCA
VCCA
CD1 3 _1
C7 3 _1
C5 3 _2
CD1 4 _1
C7 4 _1
INT_2
NC
PCLK/
DCL
F
VIN 3 _1
VIN 2 _2
VIN 3 _2
NC
C6 3 _1
NC
CD1 1 _1
C6 4 _1
INT_1
VCCD
DIO_1/
S1_1
E
VOUT 3 _1
VOUT 2 _2
VOUT 3 _2
CD1 2 _1
NC
C3 2 _2
CD2 1 _1
C5 1 _1
C3 1 _2
DGND
DCLK_1/
S0_1
D
NC
NC
NC
CD2 2 _1
C6 2 _1
C4 2 _2
C3 1 _1
C6 1 _1
C4 1 _2
CS_1/
PG_1
DIO_2/
S1_2
C
NC
NC
NC
C3 2 _1
C7 2 _1
C5 2 _2
C4 1 _1
C7 1 _1
C5 1 _2
CS_2/
PG_2
DCLK_2/
S0_2
B
VOUT 1 _1
VOUT 2 _1
VOUT 1 _2
C4 2 _1
CD1 2 _2
C6 2 _2
VCCD
CD1 1 _2
C6 1 _2
MCLK_1/
E1_1
MCLK_2/
E1_2
A
VIN 1 _1
VIN 2 _1
VIN 1 _2
C5 2 _1
CD2 2 _2
C7 2 _2
DGND
CD2 1 _2
C7 1 _2
CHCLK_1
CHCLK_2
1
2
3
6
7
4
5
7
Zarlink Semiconductor Inc.
8
9
10
11
Le58083
Data Sheet
Table 1. Le58083 Octal SLAC™ Device Pin Names and Numbers
Pin Name
Pin #
Pin Name
Pin #
Pin Name
Pin #
VIN1_1
A1
CD14_2
J8
C51_1
E8
VIN2_1
A2
CD21_1
E7
C52_1
VIN3_1
F1
CD22_1
D4
VIN4_1
L1
CD23_1
VIN1_2
A3
VIN2_2
Pin Name
Pin #
Pin Name
Pin #
CHCLK_1
A10
VCCD
B7
A4
CHCLK_2
A11
VCCD
F10
C53_1
L4
MCLK_1/E1_1
B10
AGND
H2
H4
C54_1
L7
MCLK_2/E1_2
B11
AGND
H3
CD24_1
H7
C51_2
C9
CS_1/PG_1
D10
AGND
J3
F2
CD21_2
A8
C52_2
C6
CS_2/PG_2
C10
DGND
L6
VIN3_2
F3
CD22_2
A5
C53_2
G6
DCLK_1/S0_1
E11
DGND
A7
VIN4_2
L2
CD23_2
J5
C54_2
J9
DCLK_2/S0_2
C11
DGND
E10
VOUT1_1
B1
CD24_2
K8
C61_1
D8
DIO_1/S1_1
F11
NC
C1
VOUT2_1
B2
C31_1
D7
C62_1
D5
DIO_2/S1_2
D11
NC
C2
VOUT3_1
E1
C32_1
C4
C63_1
F5
INT_1
F9
NC
C3
VOUT4_1
K1
C33_1
J4
C64_1
F8
INT_2
G9
NC
D1
VOUT1_2
B3
C34_1
J7
C61_2
B9
PCLK/DCL
G11
NC
D2
VOUT2_2
E2
C31_2
E9
C62_2
B6
FS/FSC
J10
NC
D3
VOUT3_2
E3
C32_2
E6
C63_2
H6
DRA/DD
L10
NC
J1
VOUT4_2
K2
C33_2
K5
C64_2
K9
DRB
K10
NC
J2
VREF_1
G1
C34_2
L8
C71_1
C8
DXA/DU
K11
NC
L3
VREF_2
H1
C41_1
C7
C72_1
C5
DXB
L11
NC
F4
CD11_1
F7
C42_1
B4
C73_1
G5
TSCA
H11
NC
E5
CD12_1
E4
C43_1
K4
C74_1
G8
TSCB
J11
NC
F6
CD13_1
G4
C44_1
K7
C71_2
A9
RST
H10
NC
H8
CD14_1
G7
C41_2
D9
C72_2
A6
VCCA
G2
NC
G10
CD11_2
B8
C42_2
D6
C73_2
J6
VCCA
G3
CD12_2
B5
C43_2
L5
C74_2
L9
VCCA
K3
CD13_2
H5
C44_2
H9
VCCD
K6
8
Zarlink Semiconductor Inc.
Le58083
Data Sheet
PIN DESCRIPTIONS
Pin Names
AGND, DGND
CD1C_X,
CD2C_X
Type
Power
Inputs/Outputs
Description
Separate analog and digital grounds are provided to allow noise isolation; however, the two
grounds are connected inside the part, and the grounds must also be connected together on
the circuit board.
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O)
ports. They can be used to monitor or control the state of SLIC device or any other device
associated with the subscriber line interface. The direction, input or output, is programmed
using MPI Command 54/55h or GCI Command SOP 8. As outputs, CD1 and CD2 can be used
to control relays, illuminate LEDs, or perform any other function requiring a latched TTL
compatible signal for control. In PCM/MPI mode, the output state of CD1 and CD2 is written
using MPI Command 52h. In GCI mode, the output state of CD1 and CD2 is determined by
the C1 and C2 bits contained in the down stream C/I channel for the respective channel. As
inputs, CD1 and CD2 can be processed by the Le58083 Octal SLAC device (if programmed
to do so). CD1 can be debounced before it is made available to the system. The debounce
time is programmable from 0 to 15 ms in 1 ms increments using MPI Command C8/C9h and
GCI Command SOP 11. CD2 can be filtered using the up/down counter facility and
programming the sampling interval using MPI Command E8/E9h or GCI Command SOP 12.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing
function. The E1 demultiplexing function of the Le58083 Octal SLAC device was designed to
interface directly to Zarlink SLIC devices supporting the ground key function. With the proper
Zarlink SLIC device and the E1 function of the Le58083 Octal SLAC device enabled, the
CD1 bit can be demultiplexed into an Off-Hook/Ring Trip signal and Ground Key signal. In the
demultiplex mode, the second bit, Ground Key, takes the place of the CD2 as an input. The
demultiplexed bits can be debounced (CD1) or filtered (CD2) as explained previously. A more
complete description of CD1, CD2, debouncing, and filtering functions is contained in the
Operating the Le58083 Octal SLAC Device section on page 30.
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed) by
the Le58083 Octal SLAC device, the information can be accessed by the system in two ways
in the PCM/MPI mode: 1) on a per channel basis along with C3, C4, and C5 of the specific
channel using MPI Command 53h, or 2) by using MPI Command 4D/4Fh, which obtain the
CD1 and CD2 bits from all four channels, of a selected four-channel, simultaneously. This
feature reduces the processor overhead and the time required to retrieve time-critical signals
from the line circuits, such as off-hook and ring trip. With this feature, hookswitch status and
ring trip information, for example, can be obtained from four channels of a Le58083 Octal
SLAC device with one read command.
C3C_X,
C4C_X,
Inputs/Outputs
C5C_X
C6C_X,
C7C_X
CHCLK_X
In the GCI mode, the processed CD1 and CD2 inputs are transmitted upstream on the CD1
and CD2 bits for the respective analog channel, 1 or 2, using the C/I channel.
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of the SLIC device or any other device associated
with subscriber line interface. The direction, input or output, is programmed using MPI
Command 54/55h or GCI Command SOP 8. As outputs, C3, C4, and C5 can be used to
control relays, illuminate LEDs, or perform any other function requiring a latched TTL
compatible signal for control. In PCM/MPI mode, the output state of C3, C4, and C5 is written
using MPI Command 52h. In GCI mode, the output state of C3, C4, and C5 is determined by
the C3, C4, and C5 bits contained in the down stream C/I channel for the respective analog
channel. As inputs, C3, C4, and C5 can be accessed by the system in PCM/MPI mode by
using MPI Command 53h. In GCI mode, C3 is transmitted upstream, along with CD1 and
CD2, for the respective analog channel using C3 of the C/I channel. Also, in GCI mode, C3,
C4, and C5 can be read along with CD1 and CD2 using GCI Command SOP 10.
Outputs
Additional Control outputs.
Output
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTLcompatible clock for use by up to four SLIC devices with built-in switching regulators. The
CHCLK frequency is synchronous to the master clock, but the phase relationship to the
master clock is random.
9
Zarlink Semiconductor Inc.
Le58083
Pin Names
Type
Data Sheet
Description
Chip Select/PCM-GCI. The CS/PG input along with the DCLK/S0 input are used to determine
the operating state of the programmable PCM/GCI interface. On power up, the Le58083 Octal
SLAC device will initialize to GCI mode if CS/PG is low and there is no toggling (no high to
low or low to high transitions) of the DCLK/S0 input. The device will initialize to the PCM/MPI
mode if either CS is high or DCLK is toggling.
CS_X/PG_X
Input
Input
DCLK_X/S0_X
Input
DIO_X/S1_X
Input/Output
Input
Inputs
DRA/DD, DRB
Input
Outputs
DXA/DU, DXB
Output
Input
FS/FSC
Input
Once the device is in PCM/MPI mode, it is ready to receive commands through its serial
interface pins, DIO and DCLK. Once a valid command has been sent through the MPI serial
interface, GCI mode cannot be entered unless a hardware reset is asserted or power is
removed from the part. If a valid command has not been sent since the last hardware reset or
power up, then GCI mode can be re-entered (after a delay of one PCM frame) by holding CS/
PG low and keeping DCLK static. While the part is in GCI mode, then CS/PG going high or
DCLK toggling will immediately place the device in PCM/MPI mode.
In the PCM/MPI mode, the Chip Select input (active Low) enables the device so that control
data can be written to or read from the part. The channels selected for the write or read
operation are enabled by writing 1s to the appropriate bits in the Channel Enable Registers of
the Le58083 Octal SLAC device prior to the command. See EC1, EC2, EC3, EC4. of the
Channel Enable Register and Command 4A/4Bh for more information. If Chip Select is held
Low for 16 rising edges of DCLK, a hardware reset is executed when Chip Select returns
High.
Data Clock. In addition to providing both a data clock input and an S0 GCI address input,
DCLK/S0 acts in conjunction with CS/PG to determine the operational mode of the system
interface, PCM/MPI or GCI. See CS/PG for details.
In the PCM/MPI mode, the Data Clock input shifts data into and out of the microprocessor
interface of the Le58083 Octal SLAC device. The maximum clock rate is 8.192 MHz.
Select Bit 0. In GCI mode, S0 is one of two inputs (S0, S1) that is decoded to determine on
which GCI channel pair a four-channel group of the Le58083 Octal SLAC device transmits and
receives data.
Data Input/Output. In the PCM/MPI mode, control data is serially written into and read out of
the Le58083 Octal SLAC device via the DIO pin, most significant bit first. The Data Clock
determines the data rate. DIO is high impedance except when data is being transmitted from
the Le58083 Octal SLAC device.
Select Bit 1. In GCI mode, S1 is the second of two inputs (S0, S1) that is decoded to determine
on which GCI channel pair a four-channel group of the Le58083 Octal SLAC device transmits
and receives data.
PCM Data Receive (A/B). In the PCM/MPI mode, the PCM data is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear mode, 2 consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate.
GCI Data Downstream. In GCI mode, the B1, B2, Monitor and SC channel data is serially
received, from the individual channels, on the Data Downstream input for all four channels of
the Le58083 Octal SLAC device. The Le58083 Octal SLAC device requires four of the eight
GCI channels for operation. The four GCI Channels, out of the eight possible, are determined
by the S0 and S1 inputs. Data is always received with the most significant bit first. 4 bytes of
data for each GCI channel is received every 125 µs at the 2.048 Mbit/s data rate.
PCM Data Transmit. In the PCM/MPI mode, the transmit data, from the individual channels,
is sent serially out on either the DXA or DXB port or on both ports during user-programmed
time slots. Data is always transmitted with the most significant bit first. The output is available
every 125 µs and the data is shifted out in 8-bit (16-bit in Linear or PCM Signaling mode)
bursts at the PCLK rate. DXA and DXB are High impedance between time slots, while the
device is in the Inactive mode with no PCM signaling, or while the Cutoff Transmit Path bit
(CTP) is on.
GCI Data Upstream. In the GCI mode, the B1, B2, Monitor and SC channel data is serially
transmitted on the Data Upstream output of the Le58083 Octal SLAC device. Which GCI
channels the device uses is determined by the S0 and S1 inputs. Data is always transmitted
with the most significant bit first. 4 bytes of data for each GCI channel is transmitted every 125
µs at the DCL rate.
Frame Sync. In the PCM/MPI mode, the Frame Sync (FS) pulse is an 8 kHz signal that
identifies Time Slot 0 and Clock Slot 0 of a system’s PCM frame. The Le58083 Octal SLAC
device references individual time slots with respect to this input, which must be synchronized
to PCLK.
Frame Sync. In GCI mode, the Frame Sync (FSC) pulse is an 8 kHz signal that identifies the
beginning of GCI channel 0 of a system’s GCI frame. The Le58083 Octal SLAC device
references individual GCI channels with respect to this input, which must be synchronized to
DCL.
10
Zarlink Semiconductor Inc.
Le58083
Pin Names
INT_X
MCLK_X/E1_X
Type
Output
Input/Output
NC
—
Input
PCLK/DCL
Input
RST
Input
TSCA, TSCB
Outputs
VCCA, VCCD
Power
VINC_X
Inputs
VOUTC_X
Outputs
VREF_X
Output
Data Sheet
Description
Interrupt. INT is an active Low output signal, which is programmable as either TTL-compatible
or open drain. The INT output goes Low any time one of the input bits in the Real Time Data
register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed. INT remains Low until the appropriate register is read via
the microprocessor interface, or the Le58083 Octal SLAC device receives either a software
or hardware reset. The individual CDxC bits in the Real Time Data register can be masked
from causing an interrupt by using MPI Command 6C/6Dh or GCI Command SOP 14. The
transmit data interrupt must be armed with a bit in the Operating Conditions Register.
Master Clock/Enable CD1 Multiplex. In PCM/MPI mode only, the Master Clock can be a 1.536
MHz, 1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor.
If the internal clock is derived from the PCM Clock Input (PCLK) or if GCI mode is selected,
this pin can be used as an E1 output to control Zarlink SLIC devices having multiplexed hook
switch and ground key detector outputs.
No connect. This pin is not internally connected.
PCM Clock. In the PCM/MPI mode, the PCM clock determines the rate at which PCM data is
serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync
frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is
128 kHz for dual PCM highway versions and 256 kHz for single PCM highway versions. The
minimum clock rate must be doubled if Linear mode or PCM signaling is used. PCLK
frequencies between 1.03 MHz and 1.53 MHz are not allowed. Optionally, the digital signal
processor clock can be derived from PCLK rather than MCLK. In PCM/MPI mode, PCLK can
be operated at twice the PCM data rate in the Double PCLK mode (bit 1 of PCM/MPI
Command C8/C9h).
GCI Data Clock. In GCI mode, DCL is either 2.048 MHz or 4.096 MHz, which is an integer
multiple of the frame sync frequency. Circuitry internal to the Le58083 Octal SLAC device
monitors this input to determine which frequency is being used, 2.048 MHz or 4.096 MHz.
When 4.096 MHz clock operation is detected, internal timing is adjusted so that DU and DD
operate at the 2.048 Mbit/s rate.
Reset. A logic Low signal at this pin resets both four-channel groups of the Le58083 Octal
SLAC device to their default state.
Time Slot Control. The Time Slot Control outputs are open-drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (high impedance). In the PCM/MPI mode, TSCA
or TSCB is active (low) when PCM data is transmitted on the DXA or DXB pin, respectively.
In GCI mode, TSCA is active (low) during the two GCI time slots selected by the S1 and S0.
Analog and digital power supply inputs. VCCA and VCCD are provided to allow for noise
isolation and proper power supply decoupling techniques. For best performance, all of the
VCC power supply pins should be connected together at the connector of the printed circuit
board.
Analog Input. The analog voice band signal is applied to the VIN input of the Le58083 Octal
SLAC device. The VIN input is biased at VREF by a large internal resistor. The audio signal
is sampled, digitally processed and encoded, and then made available at the TTL-compatible
PCM output (DXA or DXB) or in the B1 and B2 of the GCI channel. If the digitizer saturates in
the positive or negative direction, VIN is pulled by a reduced resistance toward AGND or
VCCD, respectively.
Analog Output. The received digital data at DRA/DRB or DD (GCI mode) is processed and
converted to an analog signal at the VOUT pin.The VOUT voltages are referenced to VREF.
Analog Voltage Reference. The VREF output is provided in order for an external capacitor to be
connected from VREF to ground, filtering noise present on the internal voltage reference.
VREF is buffered before it is used by internal circuitry. The voltage on VREF and the output
resistance are given in Electrical Characteristics, on page 13. The leakage current in the
capacitor must be low.
11
Zarlink Semiconductor Inc.
Le58083
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Storage Temperature
–60° C < TA < +125° C
Ambient Temperature, under Bias
Ambient relative humidity (non condensing)
VCCA with respect to AGND
5 to 95%
–0.4 to + 4.0 V
VCCA with respect to VCCD
±0.4 V
VCCD with respect to DGND
–0.4 to + 4.0 V
–0.4 V to (VCCA + 0.4 V)
–40° C < TA < +85° C
VIN with respect to AGND
AGND with respect to DGND
Digital pins with respect to DGND
Total combined CD1–C7 current for each four-channel group:
Source from VCCD
Sink into DGND
Latch up immunity (any pin)
Total VCC current if rise rate of VCC > 0.4 V/µs
±50 mV
–0.4 to 5.5 V or VCCD + 2.37 V, whichever is smaller
40 mA
40 mA
± 100 mA
1.0 A
Package Assembly
The green package devices are assembled with enhanced environmental, compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Zarlink guarantees the performance of this device over commercial (0º C to 70º C) and industrial (−40º C to 85º C) temperature
ranges by conducting electrical characterization over each range and by conducting a production test with single insertion
coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE
Component Reliability Assurance Requirements for Telecommunications Equipment
Environmental Ranges
Ambient Temperature
−40° C < TA < +85° C
Ambient Relative Humidity
15 to 85%
Electrical Ranges
+3.3 V ± 5%
VCCD ± 50 mV
Analog Supply VCCA
Digital Supply VCCD
+3.3 V ± 5%
DGND
AGND
CFIL Capacitance: VREF_X to AGND
Digital Pins
0V
±10 mV
0.1 µF ± 20%
DGND to +5.25 V
12
Zarlink Semiconductor Inc.
Le58083
Data Sheet
ELECTRICAL CHARACTERISTICS
Typical values are for TA = 25º C and nominal supply voltages. Minimum and maximum values are over the temperature and
supply voltage ranges shown in Operating Ranges, except where noted.
Symbol
VIL
Digital Input Low voltage
Parameter Descriptions
VIH
Digital Input High voltage
IIL
Digital Input leakage current
Pins connected to one channel group
0 < V < VCCD
Otherwise
Pins connected to both channel groups
0 < V < VCCD
Otherwise
VOL
Digital Output Low voltage
CD1–C7 (IOL = 4 mA)
CD1–C7 (IOL = 8 mA)
TSCA/ TSCB (IOL =14 mA)
Other digital outputs (IOL = 2 mA)
VOH
Digital Output High voltage
CD1–C7 (IOH = 4 mA)
CD1–C7 (IOH = 8 mA)
Other digital outputs (IOH = 400 µA)
VIR
VIOS
Max
2.0
Digital Input hysteresis
GIN
Typ
0.8
VHYS
IOL
Min
–7
–120
+7
+180
–14
–240
+14
+360
0.16
0.25
0.34
0.4
0.8
0.4
0.4
VCCD – 0.4 V
VCCD – 0.8 V
2.4
Digital Output leakage current (Hi-Z state)
Pins connected to one channel group
0 < V < VCCD
Otherwise
Pins connected to both channel groups
0 < V < VCCD
Otherwise
Input attenuator gain
DGIN = 0
DGIN = 1
Analog input voltage range (Relative to VREF)
AX = 0 dB, attenuator on (DGIN = 0)
AX = 6.02 dB, attenuator on (DGIN = 0)
AX = 0 dB, attenuator off (DGIN = 1)
AX = 6.02 dB, attenuator off (DGIN = 1)
–7
–120
+7
+180
–14
–240
+14
+360
0.6438
1
Unit
V
µA
V
1
V
1
µA
6
V/V
±1.584
±0.792
±1.02
±0.51
Vpk
Offset voltage allowed on VIN
–50
50
mV
Analog input impedance to VREF, 300 to 3400 Hz
600
1400
kΩ
IIP
Current into analog input for an input voltage of 3.3 V
50
115
IIN
Current out of analog input for an input voltage of –0.3 V
50
130
ZOUT
VOUT output impedance
1
Allowable capacitance, VOUT to AGND
10
Ω
pF
4
mApk
IOUT
VOUT output current (F< 3400 Hz)
VREF_X output open circuit voltage (leakage < 20 nA)
ZREF
VREF_X output impedance (F <3400 Hz)
VOR
VOUT analog output voltage range (Relative to VREF)
AR = 0 dB
AR = −6.02 dB
VOOS
VOUT offset voltage (AISN off)
–40
40
VOOSA
VOUT offset voltage (AISN on)
–80
80
–0.010
–0.016
0.010
0.016
GAISN
PD
1.43
1.5
70
AISN gain - expected gain (input = 0 dBm0, 1014 Hz)
Attenuator on (DGIN = 0)
Attenuator off (DGIN = 1)
Power dissipation
All channels active
1 channel active
All channels inactive
13
Zarlink Semiconductor Inc.
1.57
V
130
kΩ
±1.02
±0.51
260
55
26
µA
500
VREF
–4
6
V
ZIN
CLOUT
Note
2
2
3
Vpk
340
100
36
mV
4
V/V
mW
5
Le58083
Symbol
CI
CO
PSRR
Data Sheet
Parameter Descriptions
Digital Input capacitance
Pins connected to one channel group
Pins connected to both channel groups
Digital Output capacitance
Pins connected to one channel group
Pins connected to both channel groups
Power supply rejection ratio (1.02 kHz, 100 mVRMS, either
path, GX = GR = 0 dB)
Min
Typ
Max
10
20
Unit
Note
6
pF
10
20
40
6
dB
Notes:
1.
The CD1, CD2, C3–C7 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
2.
When the digitizer saturates, a resistor of 50 kΩ ± 20 kΩ is connected either to AGND or to VCCA as appropriate to discharge the coupling
capacitor.
3.
When the Le58083 Octal SLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15
kΩ resistor (VMODE = 0) or a high impedance (VMODE = 1).
4.
If there is an external DC path from VOUT to VIN with a gain of GDC and the AISN has a gain of hAISN, then the output offset will be multiplied
by 1 / [1 – (hAISN • GDC)].
5.
Power dissipation in the Inactive state is measured with all digital inputs at VIH = VCCD and VIL = DGND and with no load connected to
VOUTC_X pins.
6.
The PCM/GCI pins (DRA/DD, DRB, DXA/DU, DXB, FS/FSC, PCLK/DCL, TSCA and TSCB) connect to both four-channel groups and have
double the capacitance and leakage. Also, RST is in this category.
Transmission Characteristics
Table 2. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Signal at Digital Interface
Transmit
(DGIN = 0)
Transmit
(DGIN = 1)
Receive
A-law digital mW or equivalent (0 dBm0)
0.7804
0.5024
0.5024
µ-law digital mW or equivalent (0 dBm0)
0.7746
0.4987
0.4987
±22,827 peak linear coded sine wave
0.7804
0.5024
0.5024
Unit
Vrms
When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for any setting
of the GX gain from 0 dB to 12 dB, the GR loss from 0 dB to 12 dB, and the input attenuator (GIN) on or off.
Description
Gain accuracy, D/A or A/D
Gain accuracy digital-to-digital
Gain accuracy analog-to-analog
Attenuation distortion
Single frequency distortion
Second harmonic distortion, D/A
Idle channel noise
Analog out
Digital out
Test Conditions
0 dBm0, 1014 Hz
AX = AR = 0 dB
0 to 85° C
–40° C
AX = +6.02 dB and/or
AR = –6.02 dB
0 to 85° C
–40° C
300 Hz to 3 kHz
Crosstalk between channels
TX or RX to TX
TX or RX to RX
End-to-end group delay
Typ
Digital looped backweighted
unweighted
Digital input = 0 A-law
Digital input = 0 µ-law
Analog VIN = 0 VACA-law
0 dBm0
300 to 3400 Hz
0 dBm0
300 to 3400 Hz
0 dBm0
SLIC device imped. < 5000 Ω
1014 Hz, Average
1014 Hz, Average
B = Z = 0; X = R = 1
14
Zarlink Semiconductor Inc.
Max
Unit
–0.25
–0.30
+0.25
+0.30
–0.30
–0.40
–0.25
–0.25
–0.125
+0.30
+0.40
+0.25
+0.25
+0.125
–46
–55
dB
–68
–55
–78
12
–68
16
dBm0p
dBm0
dBm0p
dBrnc0
dBm0p
dBrnc0
–75
–75
dBm0
GR = 0 dB
Analog VIN = 0 VAC µ-law
Crosstalk TX to RX
same channel RX to TX
Min
0
0
–76
–78
678
Note
1
2
3
3
3
3, 6
3
3, 6
dBm0
4
µs
5
Le58083
Data Sheet
Notes:
1.
See Figure 1 and Figure 2.
2.
0 dBm0 input signal, 300 Hz to 3400 Hz; measurement at any other frequency, 300 Hz to 3400 Hz.
3.
No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0.
4.
The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, fN
= 3300 Hz, f1 = 300 Hz, and the frequency points (fJ, j = 2..N) are closely spaced:
1
------ • C ( f j – 1 )
20
 fj 
 ----------
 f j – 1
j
-------------------------------------------------------------------------------------------------------- f N
log  -----
 f1 
10
Average = 20 • log
1
------ • C ( f j )
20
+ 10
- • log
∑ --------------------------------------------------------------2
5.
The End-to-End Group Delay is the sum of the transmit and receive group delays (both measured using the same time and clock slot).
6.
Typical values not tested in production.
Attenuation Distortion
The signal attenuation in either path is nominally independent of the frequency. The deviations from nominal attenuation will stay
within the limits shown in Figure 1 and Figure 2. The reference frequency is 1014 Hz and the signal level is –10 dBm0.
Figure 1. Transmit Path Attenuation vs. Frequency
Attenuation (dB)
1.8
0.75
0.125
0
-0.125
15
Zarlink Semiconductor Inc.
3400
Frequency (Hz)
0
3000
0
200
300
Acceptable Region
Le58083
Data Sheet
Figure 2. Receive Path Attenuation vs. Frequency
1
0.75
0.125
0
-0.125
Acceptable Region
3400
Frequency (Hz)
200
300
0
0
3000
Attenuation (dB)
2
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 3. The minimum value of the group
delay is taken as the reference. The signal level should be 0 dBm0.
Figure 3. Group Delay Distortion
420
Delay (µS)
150
Acceptable
Region
2800
Frequency (Hz)
2600
1000
600
0
500
90
Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 4 (A-law) and Figure 5 (µ-law) for either
transmission path when the input is a sine wave signal of 1014 Hz.
16
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Figure 4. A-law Gain Linearity with Tone Input (Both Paths)
1.5
0.55
0.25
Acceptable Region
Gain (dB)
0
-0.25
-55 -50
-40
-10
0
Input
Level
+3 (dBm0)
-0.55
-1.5
Figure 5. µ-law Gain Linearity with Tone Input (Both Paths)
1.4
0.45
0.25
Acceptable Region
Gain (dB)
0
-55 -50
-37
-10
-0.25
-0.45
-1.4
17
Zarlink Semiconductor Inc.
0
Input
Level
+3 (dBm0)
Le58083
Data Sheet
Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 6 for either path when the input signal is a sine wave
signal of frequency 1014 Hz.
Figure 6.
Total Distortion with Tone Input (Both Paths)
Acceptable Region
B
A
A
B
C
D
C
D
A-Law
35.5dB
35.5dB
30dB
25dB
µ-Law
35.5dB
35.5dB
31dB
27dB
Signal-to-Total
Distortion (dB)
-45
-40
-30
0
Input Level (dBm0)
Discrimination Against Out-of-Band Input Signals
When an out-of-band sine wave signal of frequency f, and level A is applied to the analog input, there may be frequency
components below 4 kHz at the digital output which are caused by the out-of-band signal. These components are at least the
specified dB level below the level of a signal at the same output originating from a 1014 Hz sine wave signal with a level of A
dBm0 also applied to the analog input. The minimum specifications are shown in the following table.
Frequency of Out-of-Band Signal
16.6 Hz < f < 45 Hz
45 Hz < f < 65 Hz
65 Hz < f < 100 Hz
3400 Hz < f < 4600 Hz
4600 Hz < f < 100 kHz
Amplitude of Out-of-Band Signal
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
18
Zarlink Semiconductor Inc.
Level below A
18 dB
25 dB
10 dB
see Figure 7
32 dB
Le58083
Data Sheet
Figure 7. Discrimination Against Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB, -25 dBm0 < input , 0 dBm0
-40
-50
3.4
4.0
4.6
Frequency (kHz)
Note:
The attenuation of the waveform below amplitude A, between 3400 Hz and 4600 Hz, is given by the formula:
π ( 4000 – f )
Attenuation (db) = 14 – 14 sin  -----------------------------


1200
Discrimination Against 12- and 16-kHz Metering Signals
If the Le58083 Octal SLAC device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the
telephone line toward the subscriber, a portion of these tones also may appear at the VIN terminal. These out-of-band signals
may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or 16 kHz tone, the frequency
components below 4 kHz are reduced from the input by at least 70 dB. The sum of the peak metering and signal voltages must
be within the analog input voltage range.
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the
digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Frequency
4.6 kHz to 40 kHz
40 kHz to 240 kHz
240 kHz to 1 MHz
Level
–32 dBm0
–46 dBm0
–36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital
input, the level of the signals at the analog output are below the limits in Figure 8. The amplitude of the spurious out-of-band
signals between 3400 Hz and 4600 Hz is given by the formula:
π ( f – 4000 )
Level = – 14 – 14 sin  ----------------------------- dBm0


1200
19
Zarlink Semiconductor Inc.
Le58083
Figure 8.
Data Sheet
Spurious Out-of-Band Signals
0
-10
-20
Level (dB)
-28 dBm
-30
-32 dB
-40
-50
3.4
4.0
4.6
Frequency (kHz)
Overload Compression
Figure 9 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The
conditions for this figure are:
1.
2.
3.
4.
1.2 dB < GX ≤ + 12 dB
–12 dB ≤ GR < –1.2 dB
Digital voice output connected to digital voice input.
Measurement analog-to-analog.
Figure 9. Analog-to-Analog Overload Compression
9
8
7
Fundamental
Output Power
(dBm0)
6
Acceptable
Region
5
4
3
2.6
2
1
1
7
2
3
4
5
6
Fundamental Input Power (dBm0)
20
Zarlink Semiconductor Inc.
8
9
Le58083
Data Sheet
SWITCHING CHARACTERISTICS
The following are the switching characteristics over operating range (unless otherwise noted). Min and max values are valid for
all digital outputs with a 115 pF load, except CD1–C7 with a 30 pF load. (See Figure 11 and Figure 12 for the microprocessor
interface timing diagrams.)
Microprocessor Interface
No.
Symbol
1
tDCY
Parameter
Min
Typ
Max
Data clock period
122
2
tDCH
Data clock HIGH pulse width
48
3
tDCL
Data clock LOW pulse width
48
4
tDCR
Rise time of clock
5
tDCF
Fall time of clock
6
tICSS
Chip select setup time, Input mode
30
t DCY –10
7
tICSH
Chip select hold time, Input mode
0
t DCH –20
8
tICSL
Chip select pulse width, Input mode
Chip select off time, Input mode
Unit
Note
25
25
8t DCY
9
tICSO
10
tIDS
Input data setup time
25
11
tIDH
Input data hold time
30
12
tOLH
SLIC device output latch valid
2500
1
ns
2500
13
tOCSS
Chip select setup time, Output mode
30
t DCY –10
14
tOCSH
Chip select hold time, Output mode
0
t DCH –20
15
tOCSL
Chip select pulse width, Output mode
8t DCY
16
tOCSO
Chip select off time, Output mode
17
tODD
Output data turn on delay
18
tODH
Output data hold time
19
tODOF
Output data turn off delay
50
20
tODC
Output data valid
50
21
tRST
Reset pulse width
2500
1
50
2
3
50
µs
PCM Interface
PCLK not to exceed 8.192 MHz.
Pull-up resistors to VCCD of 240 Ω are attached to TSCA and TSCB. (See Figure 13 through Figure 15 for the PCM interface
timing diagrams.)
No.
Symbol
22
tPCY
PCM clock period
Parameter
Min.
122
Typ
Max
23
tPCH
PCM clock HIGH pulse width
48
24
tPCL
PCM clock LOW pulse width
48
25
tPCF
Fall time of clock
26
tPCR
Rise time of clock
27
tFSS
FS setup time
25
28
tFSH
FS hold time
50
30
tTSD
Delay to TSC valid
5
80
31
tTSO
Delay to TSC off
5
80
32
tDXD
PCM data output delay
5
70
33
tDXH
PCM data output hold time
5
70
34
tDXZ
PCM data output delay to High-Z
5
70
35
tDRS
PCM data input setup time
25
36
tDRH
PCM data input hold time
5
Unit
Note
3
15
15
21
Zarlink Semiconductor Inc.
t PCY –30
ns
4
4,5
Le58083
Data Sheet
Master Clock
(See Figure 16 for the Master Clock timing diagram.)
No.
Symbol
Parameter
Min
Typ
Max
Unit
37
JMCY
Master clock jitter
50
38
tMCR
Rise time of clock
15
39
tMCF
Fall time of clock
15
ns
40
tMCH
MCLK HIGH pulse width
48
41
tMCL
MCLK LOW pulse width
48
Max
Unit
Notes
6
Auxiliary Output Clocks
No.
Symbol
Parameter
Chopper clock frequencyCHP = 0
CHP = 1
42
fCHP
42A
DCCHP
50
%
7
43
fE1
E1 output frequency (CMODE = EE1 = 1)
4.923
kHz
7
44
tE1
E1 pulse width (CMODE = EE1 = 1)
31.25
µs
7
Chopper clock duty cycle
Min
Typ
256
292.57
kHz
7
Notes:
1.
If CFAIL = 1 (Command 55h), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or
switching them to default coefficients; otherwise, a chip select off time of 25 µs is required.
2.
The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3.
The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192
MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128
kHz in Companded state and 256 kHz in Linear state, PCM Signaling state, or double PCLK state. The minimum PCM clock rates should
be doubled for parts with only one PCM highway in order to allow simultaneous access to all four channels.
4.
TSC is delayed from FS by a typical value of N • tPCY, where N is the value stored in the time/clock-slot register.
5.
tTSO is defined as the time at which the output achieves the Open Circuit state.
6.
PCLK and MCLK are required to be integer multiples of the frame sync (FS) frequency. Frame sync is expected to be an accurate 8 kHz
pulse train. If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
7.
Phase jumps of 81 ns will be present when the master clock frequency is a multiple of 1.544 MHz.
22
Zarlink Semiconductor Inc.
Le58083
Data Sheet
SWITCHING WAVEFORMS
Figure 10. Input and Output Waveforms for AC Tests
2.4 V
2.0 V
2.0 V
TEST
POINTS
0.8 V
0.8 V
0.45 V
Figure 11.
Microprocessor Interface (Input Mode)
1
2
5
V IH
DCLK
V IL
V IH
V IL
3
7
9
4
CS
6
8
10
DI/O
Data
Valid
11
Data
Valid
Data
Valid
12
Outputs
CD1 - C7
Data
Valid
Data
Valid
23
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Figure 12. Microprocessor Interface (Output Mode)
VIH
VIL
DCLK
14
13
16
15
CS
20
18
17
DI/O
Three-State VOH
Data
Valid
VOL
19
Data
Valid
Data
Valid
Three-State
Figure 13. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)
Time Slot Zero
Clock Slot Zero
22
26
VIH
PCLK
25
VIL
23
24
27
28
FS
30
31
TSCA/
TSCB
32
33
34
VOH
DXA/DXB
First Bit
VOL
35
DRA/DRB
First
Bit
VIH
Second
Bit
VIL
24
Zarlink Semiconductor Inc.
36
Le58083
Data Sheet
Figure 14. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero
Clock Slot Zero
22
26
25
VIH
PCLK
VIL
23
24
27
28
FS
30
31
TSCA/
TSCB
32
33
34
VOH
DXA/DXB
First Bit
VOL
35
DRA/DRB
First
Bit
VIH
Second
Bit
VIL
25
Zarlink Semiconductor Inc.
36
Le58083
Figure 15.
Data Sheet
Double PCLK PCM Timing
PCLK
FS
First Bit
DXA/DXB,
DRA/DRB
Second Bit
Detail Below
26
PCLK
tPCF 25
tPCR
23
22
tPCH
tPCY
tPCL
24
FS
27
tFSS
28
tFSH
DXA/DXB
tDXD
35
32
DRA/DRB
26
Zarlink Semiconductor Inc.
tDRS
tDRH
36
Le58083
Figure 16.
Data Sheet
Master Clock Timing
37
40
V
V
IH
IL
41
39
38
GCI Timing Specifications
Symbol
Signal
Parameter
Min
Typ
tR, tF
DCL
JDCL
DCL
tDCL
DCL
tWH, tWL
DCL
tR, tF
FS
Rise/fall time
tSF
FS
Setup time
70
tHF
FS
Hold time
50
tWFH
FS
High pulse width
130
tDDC
DU
Delay from DCL edge
100
tDDF
DU
Delay from FS edge
150
tSD
DD
Data setup
twH + 20
tHD
DD
Data hold
50
Rise/fall time
DCL jitter
Unit
Notes
60
FDCL = 2.048 kHz
50
50
FDCL = 4.096 kHz
Period
Max
FDCL = 2.048 kHz
488
244
FDCL = 4.096 kHz
Pulse width
1
90
2
60
tDCL – 50
Notes:
1.
If DCL has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
2.
The Data Clock (DCL) can be stopped in the high or low state without loss of information.
27
Zarlink Semiconductor Inc.
ns
Le58083
Data Sheet
GCI Waveforms
Figure 17. 4.096 MHz DCL Operation
DCL
4.096 MHz
FS
Bit 7
DD, DU
Bit 6
Detail Below
tR
tF
DCL
twH
tDCL
tWL
FS
tSF
tHF
tWFH
tDDF
DU
tDDC
tSD
DD
28
Zarlink Semiconductor Inc.
tHD
Le58083
Data Sheet
Figure 18. 2.048 MHz DCL Operation
DCL
2.048 MHz
FS
Bit 7
DD, DU
Bit 6
Bit 5
Detail Below
tR
tF
DCL
tDCL
twH
FS
tSF
tHF
tWFH
tDDF
DU
tDDC
tSD
tHD
DD
29
Zarlink Semiconductor Inc.
tWL
Le58083
Data Sheet
OPERATING THE LE58083 OCTAL SLAC DEVICE
The following sections describe the operation of the Le58083 Octal SLAC device. The description is valid for all eight channels;
consequently the subscripts have been dropped. For example, VOUT refers to either VOUT1_1, VOUT1_2, etc.
The command addresses are the same for both of the internal four-channel groups. Therefore, chip select one (CS_1) controls
the first four channel group and chip select two (CS_2) controls the second four-channel group.
Power-Up Sequence
The recommended Le58083 Octal SLAC device power-up sequence is to apply:
1.
2.
3.
Analog and digital ground
VCC, signal connections, and Low on RST (refer to the switching characteristics section for timing specifications of RST)
High on RST
The software initialization recommended for each internal four-channel group includes:
1.
2.
Wait 1 ms. after Reset.
For PCM/MPI mode, select master clock frequency and source (Command 46/47h). This should turn off the CFAIL bit
(Command 55h) within 400 µs.
In GCI mode, DCL is the clock source. The CFAIL bit (GCI Command SOP 8) is set to 1 until the device has determined and
synchronized to the DCL frequency, 4.096 MHz or 2.048 MHz. If channels are activated while CFAIL is a 1, no device
damage will occur, but high audible noise may appear on the line. Also, the CD1, CD2, and C3 - C7 bits may not be stable.
3.
4.
Program filter coefficients and other parameters as required.
Activate (MPI Command 0Eh, GCI Command SOP 4).
If the power supply (VCCD) falls below an internal threshold, the device is reset and will require complete reprogramming with
the above sequence. A reset may be initiated by connection of a logic Low to the RST pin. A reset will also be generated on a
selected internal four-channel SLAC device when chip select _1(CS/PG_1) or chip select _2 or both chip selects are held low for
16 rising edges of DCLK when chip selects returns high. The RST pin may be tied to VCCD if it is not used in the system.
PCM and GCI State Selection
The Le58083 Octal SLAC device can switch between PCM/MPI and GCI modes. Table Table 3 lists the selection requirements.
Table 3.
From State
PCM/GCI Mode Selection
To State
Requirement
Power On or
Hardware
Reset
PCM
CS_1 and CS_2 = 1 or
DCLK_1 and DCLK_2 have
ac clock present
Power On or
Hardware
Reset
GCI
CS_1 and CS_2 = 0 and
DCLK_1 and DCLK_2 do
not have ac clock present
GCI
PCM
CS_1 and CS_2 = 1 or
DCLK_1 and DCLK_2 have
ac clock present
PCM
GCI
No commands yet sent in
PCM state andCS_1 and
CS_2 = 0 (for more than 2
FS) and DCLK_1 and
DCLK_2 do not have ac
clock present
PCM
Power On or
Hardware
Reset
Commands have been sent
in PCM state and Hardware
Reset generated
GCI
Power On or
Hardware
Reset
Not allowed
30
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Channel Enable (EC) Register (PCM/MPI Mode)
In PCM/MPI mode, a channel enable (EC) register has been implemented in each four-channel group of the Le58083 Octal SLAC
device in order to reduce the effort required to address individual or multiple channels of the Le58083 Octal SLAC device. The
register is written using MPI Command 4A/4Bh. Each bit of the register is assigned to one unique channel, bit 0 for channel 1,
bit 1 for channel 2, bit 2 for channel 3, and bit 3 for channel 4. The channel or channels are enabled when their corresponding
enable bits are High. All enabled channels receive the data written to the Le58083 Octal SLAC device. Since, the Le58083 Octal
SLAC device consist of two four-channel SLAC devices both chip selects need to be enabled, along with all the channel enable
bits, to program all eight channels. This enables a Broadcast mode (all channels enabled) to be implemented simply and
efficiently, and multiple channel addressing is accomplished without increasing the number of I/O pins on the device. The
Broadcast mode can be further enhanced by providing the ability to select many chips at once; however, care must be taken not
to enable more than one chip in the Read state. This can lead to an internal bus contention, where excess power is dissipated.
(Bus contention will not damage the device.)
In GCI mode, the individual channels are controlled by their respective Monitor and SC channels embedded in the GCI channels
selected by the device (S0, S1).
SLIC Device Control and Data Lines
The Le58083 Octal SLAC device has five SLIC device programmable digital input/output pins per channel (CD1–C5). Each of
these pins can be programmed as either an input or an output using the I/O Direction register (MPI Command 54/55h, GCI
Command SOP 8). Also, there are the two additional output only pins per channel, C6-C7 (see Figure 20). The output latches
can be written with MPI Command 52h or through the CI1 to CI5 bits present in the downstream SC channel; however, only those
bits programmed as outputs will actually drive the pins. The inputs can be read with MPI Command 53h, GCI Command SOP 10
or on the Upstream CI bits, in the SC channel. If a pin is programmed as an output, the data read from it will be the contents of
the output latch. In GCI mode, this data can be read using GCI Command SOP 10, but the output bits are not sent upstream in
the SC channel. It is recommended that any of the SLIC device input/output control and data pins, which are to be programmed
as outputs, be written to their desired state before writing the data which configures them as outputs with the I/O direction register
MPI Command 54/55h, GCI Command SOP 8. This ensures that when the output is activated, it is already in the correct state,
and will prevent unwanted data from being driven from the SLIC device output pins. It is possible to make a SLIC device control
output pull up to a non-standard voltage (V < 5.25 V) by connecting a resistor from the output to the desired voltage, sending zero
to the output, and using the DIO bit to tri-state the output.
Clock Mode Operation
The Le58083 Octal SLAC device operates with multiple clock signals. The master clock is used for internal timing including
operation of the digital signal processing. In PCM/MPI mode, the master clock may be derived from either the MCLK or PCLK
source. When MCLK is used as the master clock, it should be synchronous to FS. In GCI mode, the master clock is obtained
from the DCL clock only. The allowed frequencies are listed under Command 46/47h for PCM/MPI mode. In GCI mode, DCL can
be only 2.048 MHz or 4.096 MHz.
In PCM/MPI mode, the PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync frequency. The
internal master clock can be optionally derived from the PCLK source by setting the CMODE bit (bit 4, Command 46/47h) to one.
In this mode, the MCLK/E1 pin is free to be used as an E1 signal output. In GCI mode, since the master clock is derived only
from the DCL clock, this MCLK/E1 pin is always available as an E1 output. Clock mode options and E1 output functions are
shown in Figure 19.
31
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Figure 19. Clock Mode Options (PCM/MPI Mode)
MCLK/E1
PCLK
(= 0)
Time
Slot
Assigner
(= 1)
E1
(= 1)
(= 0)
CMODE
(= 1)
(= 0)
EE1
÷N
DSP
Engine
CSEL
E1
Pulses
E1P
Notes:
1. CMODE = Command 46/47h
Bit 4
2. CSEL = Command 46/47h
Bits 0–3
3. EE1 = Command C8/C9h
Bit 7
4. E1P = Command C8/C9h
Bit 6
E1 Multiplex Operation
The Le58083 Octal SLAC device can multiplex input data from the CD1 SLIC device I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC device Input/Output register, MPI Command 52/53h, GCI Command SOP 10 and CDA
and CDB bits in the Real Time Data register, MPI Command 4D/4Fh, GCI Command SOP 13, GCI C/I Channel) using the E1
multiplex mode. This multiplex mode provides the means to accommodate dual detect states when connected to an Zarlink
SLIC device, which also supports ground-key detection in addition to loop detect. Zarlink SLIC devices that support ground-key
detect use their E1 pin as an input to switch the SLIC device’s single detector (DET) output between internal loop detect or
ground-key detect comparators. Using the E1 multiplex mode, a single Le58083 Octal SLAC device can monitor both loop detect
and ground-key detect states of all eight connected SLIC devices without additional hardware. Although normally used for ground
key detect, this multiplex function can also be used for monitoring other signal states.
The E1 multiplex mode is selected by setting the EE1 bit (bit 7, MPI Command C8/C9h, GCI Command SOP 11) and CMODE
bit (bit 4, Command 46/47h) in the Le58083 Octal SLAC device. In PCM/MPI mode, the CMODE bit must be selected (CMODE
= 1) for the master clock to be derived from PCLK so that the MCLK/E1 pin can be used as an output for the E1 signal. The
multiplex mode is then turned on by setting the EE1 bit. With the E1 multiplex mode enabled, the Le58083 Octal SLAC device
generates the E1 output signal. This signal is a 31.25 µs (1/32 kHz) duration pulse occurring at a 4.923 kHz (64 kHz/13) rate. If
EE1 is reset,
MCLK/E1 is programmed as an input and should be connected to ground if it is not connected to a clock source. The polarity of
this E1 output is selected by the E1P bit (bit 6, MPI Command C8/C9h, GCI Command SOP 11) allowing this multiplex mode to
accommodate all SLIC devices regardless of their E1 high/low logic definition.
Figure 20 shows the SLIC device Input/Output register, I/O pins, E1 multiplex hardware operation for one Le58083 Octal SLAC
device channel. It also shows the operation of the Real Time Register. Each Le58083 Octal SLAC device E1 output signal
connects directly to the E1 inputs of all four connected SLIC devices and is used by those SLIC devices to select an internal
comparator to route to the SLIC device’s DET output. This E1 signal is also used internally by the Le58083 Octal SLAC device
for controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC device Input/Output register are isolated from the CD1 pin by transparent latches. When the
E1 pulse is off, the CD1 pin data is routed directly to the CD1 bit of the SLIC device I/O register and changes to the CD1B bit of
that register are disabled by its own latch. When E1 pulses on, the CD1 latch holds the last CD1 state in its register. At the same
32
Zarlink Semiconductor Inc.
Le58083
Data Sheet
time, the CD1B latch is enabled, which allows CD1 pin data to be routed directly to the CD1B bit. Therefore, during this
multiplexing, the CD1 bit always has loop-detect status and the CD1B bit always has ground-key detect status.
This multiplexing state changes almost instantaneously within the Le58083 Octal SLAC device but the SLIC device may require
a slightly longer time period to respond to this detect state change before its DET output settles and becomes valid. To
accommodate this delay difference, the internal signals within the Le58083 Octal SLAC device are isolated by 15.625 µs before
allowing any change to the CD1 bit and CD1B bit latches. This operation is further described by the E1 multiplex timing diagram
in Figure 21. In this timing diagram, the E1 signal represents the actual signal presented to the E1 output pin. The GK Enable
pulse allows CD1 pin data to be routed through the CD1B latch. The LD Enable pulse allows CD1 pin data to be routed through
the CD1 latch. The uncertain states of the SLIC device’s DET output, and the masked times where that DET data is ignored are
shown in this timing diagram. Using this isolation of masked times, the CD1 and CD1B registers are guaranteed to contain
accurate representations of the SLIC device detector output.
33
Zarlink Semiconductor Inc.
Le58083
Figure 20.
Data Sheet
SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation
SLIC device Input Register
MPI Command 53h
or GCI Upstream
SC Channel Data
D
C7
Q
C6 CD1B C5
C4
C3 CD2 CD1
EN/HOLD
*
CD1
CD2
C3
C4
C5
C6
C7
D
I/O Direction
Register
MPI Command
54/55h or GCI
Command SOP 8
Q
EN/HOLD
*
Output Latch
SLIC Output
Register
MPI Command 52h
or GCI Downstream
SC Channel Data
EE1 Bit
E1 Source
(Internal)
Delay
1
Ground Key Filter (time set
via
MPI Command E8/E9h or
GK Enable
Debounce Time
(set via MPI Command C8/C9h or
GCI Command SOP 11)
(Channel 1
Shown)
{
Same for
Channels
2, 3, 4
Real Time Data Register
(MPI Command 4D/4Fh
or GCI UpstreamSC Channel data)
E1P
INT
MUX
LD Enable
(See Figure 21
for details)
MCLK/E1
0
CDB4 CDA4 CDB3 CDA3 CDB2 CDA2 CDB1 CDA1
ATI (MPI Command 70/71h
or GCI Command SOP 5)
Interrupt Mask Register
(MPI Command 6C/6Dh
or GCI Command SOP 14)
MCDB4 MCDA4 MCDB3 MCDA3 MCDB2 MCDA2 MCDB1 MCDA1
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last state.
34
Zarlink Semiconductor Inc.
Le58083
Data Sheet
Figure 21. E1 Multiplex Internal Timing
Pulse Period 203.125 µs
4.923 kHz (64 kHz/13) pulse rate
31.25 µs
E1
15.625 µs 15.625 µs
GK Enable
LD Enable
15.625 µs
DET Output
from SLIC
(CD1 Pin Input)
CD1 Pin
Input Data
Contains
Valid LD
Status
CD1
Register
Operation
Tracks
DET State
CD1B
Register
Operation
CD1 Pin
State
Ignored
Contains
Valid GK
Status
CD1 Pin
State
Ignored
Tracks
DET State
Hold Last State
Hold Last State
Tracks
DET State
Contains
Valid LD
Status
Hold Last State
Debounce Filters Operation
Each channel is equipped with two debounce filter circuits to buffer the logic status of the CD1 and CD2/CD1B bits of the SLIC
device Input Data Register (MPI Command 53h and GCI Command SOP 10) before providing filtered bit’s outputs to the RealTime Data Register (MPI Command 4D/4Fh or GCI Command SOP 13). One filter is used only for the CD1 bit. The other filter
either acts upon the CD1B bit if E1 multiplexing is enabled or on the CD2 bit if the multiplexing is not enabled.
The CD1 bit normally contains SLIC device loop-detect status. The CD1 debouncing time is programmable with the Debounce
Time Register (MPI Command C8/C9h or GCI Command SOP 11), and even though each channel has its own filter, the
programmed value is common to all four channels. This debounce filter is initially clocked at the frame sync rate of 125 µs, and
any occurrence of changing data at this sample rate resets a programmable counter. This programmable counter is clocked at a
1 ms rate, and the programmed count value of 0 to 15 ms, as defined by the Debounce Time Register, must be reached before
updating the CDA bit of the Real Time Data register with the CD1 state. Refer to Figure 22a for this filter’s operation.
The ground-key filter (Figure 22b) provides a buffering of the signal, normally ground-key detect, which appears in the CD1B bit
of the Real-Time Data Register and the SC upstream channel in GCI mode. Each channel has its own filter, and each filter’s time
can be individually programmed. The input to the filter comes from either the CD2 bit of the SLIC device I/O Data Register (MPI
Command 53h), when E1 multiplexing is not enabled, or from the CD1B bit of that register when E1 multiplexing is enabled. The
feature debounces ground-key signals before passing them to the Real Time Data Register, although signals other than groundkey status can be routed to the CD2 pin and then through the registers.
The ground-key debounce filter operates as a duty-cycle detector and consists of an up/down counter which can range in value
between 0 and 6. This six-state counter is clocked by the GK timer at the sampling period of 1–15 ms, as programmed by the
value of the four GK bits (GK3, GK2, GK1, GK0) of the Ground-Key Filter Data register (MPI Command E8/E9h, GCI Command
SOP 12). This sampling period clocks the counter, which buffers the CD2/CD1B bit’s status before it is valid for presenting to the
CDB bit of the Real Time Data Register. When the sampled value of the ground-key (or CD2) input is high, the counter is
incremented by each clock pulse. When the sampled value is low, the counter is decremented. Once the counter increments to
its maximum value of 6, it sets a latch whose output is routed to the corresponding CDB bit. If the counter decrements to its
minimum value of 0, this latch is cleared and the output bit is set to zero. All other times, the latch (and the CDB status) remains
in its previous state without change. It therefore takes at least six consecutive GK clocks with the debounce input remaining at
the same state to effect an output change. If the GK bit value is set to zero, the buffering is bypassed and the input status is
passed directly to CDB.
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Zarlink Semiconductor Inc.
Le58083
Figure 22.
Data Sheet
MPI Real-Time Data Register
CD1
D
Q
D
Q
D
Debounce Counter
Q
DSH0 – DSH3
Debounce Period
(0 – 15 ms)
CK
8
FS (8 kHz)
D
Q
CDA
EN/HOLD
*
Q
RST
a. Loop Detect Debounce Filter
Notes:
*Transparent latch: Output follows input when EN is high; output holds last state when EN is low.
Debounce counter: Output is high after counting to programmed (DSH) number of 1 ms clocks; counter is reset for CD1 input changes at 125 µs
sample period. DSH0 - DSH3 programmed value is common for all four channels, but debounce counter is separate per channel.
MUX
CD2 or CD1B
GK = 0
CDB
UP/DN
GK0 – GK3
Ground-Key
Sampling Interval
1 – 15 ms
Q
GK = 0
GK
1 kHz
RST
Clock Divider
(1 – 15 ms
clock output)
Six-State
Up/Down
Counter
b. Ground-Key Filter
Notes:
Programmed value of GK0 - GK3 determines clock rate (1 - 15 ms) of six-state counter.
If GK value = 0, the counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero.
Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and ring trip information from the SLIC device with a minimum of processor time
and effort, the Le58083 Octal SLAC device contains two 8-bit Real Time Data registers. These registers each contain CDA and
CDB bits from four channels. The CDA bit for each channel is a debounced version of the CD1 input. The CDA bit is normally
used for hook switch. The CDB bit for each channel normally contains the debounced value of the CD2 input bit; however, if the
E1 multiplex operation is enabled, the CDB bit will contain the debounced value of the CD1B bit. CD1 and CD2 can be assigned
to off-hook, ring trip, ground key signals, or other signals. Frame sync is needed for the debounce and the ground-key signals. If
Frame sync is not provided, the real-time register will not work. The register is read using MPI Command 4D/4Fh, GCI Command
SOP 13, and may be read at any time regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip,
or ground key information for four channels to be obtained from the Le58083 Octal SLAC device with one read operation versus
one read per channel. If these data bits are not used for supervision information, they can be accessed on an individual channel
basis in the same way as C3–C5; however, CD1 and CD1B will not be debounced. This Real-Time Data register is available in
both MPI and GCI modes. In the GCI mode, this real-time data is also available in the field of the upstream SC octet.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Interrupt
In addition to the Real Time Data registers, interrupt signals have been implemented in the Le58083 Octal SLAC device. An
interrupt signal is an Active Low output signal which pulls Low whenever the unmasked CD bits change state (Low to High or
High to Low); or whenever the transmit PCM data changes on a channel in which the Arm Transmit Interrupt (ATI) bit is on. The
interrupt control is shown in Figure 20. The interrupt remains Low until the appropriate register is read. This output can be
programmed as TTL or open drain output by the INTM bit, MPI Command 46/47h or GCI Command SOP 6. When an interrupt
is generated, all of the unmasked bits in the Real Time Data register latch and remain latched until the interrupt is cleared. The
interrupt is cleared by reading the register with MPI Command 4Fh or GCI Command SOP 13, by writing to the interrupt mask
register (MPI Command 6Ch, GCI Command SOP 14), or by a reset. If any of the inputs to the unmasked bits in the Real Time
Data register are different from the register bits when the interrupt is cleared by reading the register, a new interrupt is immediately
generated with the new data latched into the Real Time Data register. For this reason, the interrupt logic in the controller should
be level-sensitive rather than edge-sensitive.
Interrupt Mask Register
The Real Time Data register data bits can be masked from causing an interrupt to the processor using the interrupt mask register.
The contents of the mask register can be written or read via the MPI Command 6C/6Dh, GCI Command SOP 14.
Active State
Each channel of the Le58083 Octal SLAC device can operate in either the Active (Operational) or Inactive (Standby) state. In the
Active state, individual channels of the Le58083 Octal SLAC device can transmit and receive PCM or linear data and analog
information. The Active state is required when a telephone call is in progress. The activate command (MPI Command 0Eh, GCI
Command SOP 4) puts the selected channels (see channel enable register for PCM/MPI Mode) into this state (CSTAT = 1).
Bringing a channel of the Le58083 Octal SLAC device into the Active state is only possible through the MPI command or the GCI
command.
Inactive State
All channels of the Le58083 Octal SLAC device are forced into the Inactive (Standby) state by a power-up or hardware reset.
Individual channels can be programmed into this state (CSTAT = 0) by the deactivate command (MPI Command 00h, GCI
Command SOP 1) or by the software reset command (MPI Command 02h, GCI Command SOP 2). Power is disconnected from
all nonessential circuitry, while the MPI remains active to receive commands. The analog output is tied to VREF through a resistor
whose value depends on the VMODE bit. All circuits that contain programmed information retain their data in the Inactive state.
Chopper Clock
The Le58083 Octal SLAC device provides chopper clock outputs to drive the switching regulators on some Zarlink SLIC
devices. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (MPI Command 46/47h, GCI Command SOP
6). The duty cycle is given in the Switching Characteristics section. The chopper output must be turned on with the ECH bit (MPI
Command C8/C9h, GCI Command SOP 11).
Reset States
The Le58083 Octal SLAC device can be reset by application of power, by an active Low on the hardware Reset pin (RST), by a
hardware reset command, or by CS_1 or CS_2 Low for 16 or more rising edges of DCLK (resets the internal four-channel SLAC
selected only). This resets the Le58083 Octal SLAC device to the following state:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
A-law companding is selected.
Default B, X, R, and Z filter values from ROM are selected and the AISN is set to zero.
Default digital gain blocks (GX and GR) from ROM are selected. The analog gains, AX and AR, are set to 0 dB and the input
attenuator is turned on (DGIN = 0).
The previously programmed B, Z, X, R, GX, and GR filters in RAM are unchanged.
SLIC device input/outputs CD1, CD2, C3, C4, and C5 are set to the Input mode.
All of the test states in the Operating Conditions register are turned off (0s).
All four channels are placed in the Inactive (Standby) mode.
For PCM/MPI mode, transmit time slots and receive time slots are set to 0, 1, 2, and 3 for channels 1, 2, 3, and 4, respectively.
The clock slots are set to 0, with transmit on the negative edge. For GCI mode, operation is determined by S0 and S1.
DXA/DU port is selected for all channels.
DRA/DD port is selected for all channels.
The master clock frequency in PCM/MPI mode is selected to be 8.192 MHz and is programmed to come from PCLK. In GCI
mode, DCL is 2.048 or 4.096 MHz and is determined by the Le58083 Octal SLAC device.
All four channels are selected in the Channel Enable Register for PCM/MPI mode.
Any pending interrupts are cleared, all interrupts are masked, and the Interrupt Output state is set to open drain.
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Zarlink Semiconductor Inc.
Le58083
14.
15.
16.
17.
Data Sheet
The supervision debounce time is set to 8 ms.
The chopper clock frequency is set to 256 kHz, but the chopper clock is turned off.
The E1 Multiplex state is turned off (E1 is Hi-Z) and the polarity is set for high-going pulses.
No signaling on the PCM highway (PCM/MPI mode).
SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the performance
of the Le58083 Octal SLAC device for the system. Figure 23 shows the Le58083 Octal SLAC device signal processing and
indicates the programmable blocks.
The advantages of digital filters are:
■
■
■
■
■
■
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.90 modems
Figure 23. Le58083 Octal SLAC Transmission Block Diagram
Cutoff
Transmit
Path
(CTP)
Digital
TSA
TX
High Pass Filter (HPF)
V IN
*
AX
GIN
ADC
Decimator
Decimator
+
GX
X
*
*
LPF &
HPF
Compressor
TSA Loopback
(TLB)
AISN
Full
Digital
Loopback
(FDL)
*
B
*
*
Cutoff Receive
Path (CRP)
+
V OUT
Z
*
AR
DAC
Interpolator
+
Interpolator
GR
VREF
*
R
Expander
LPF
* Receive
Lower
Gain (LRG)
0
TSA
Digital
RX
1 kHz Tone
(TON)
* programmable blocks
Two-Wire Impedance Matching
Two feedback paths on the Le58083 Octal SLAC device synthesize the two-wire input impedance of the SLIC device by providing
a programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a programmable analog
gain of
−0.9375 • GIN to +0.9375 • GIN from VIN to VOUT. (See GIN in Electrical Characteristics, on page 13.) The Z filter is a
programmable digital filter providing an additional path and programming flexibility over the AISN in modifying the transfer
function from VIN to VOUT. Together, the AISN and the Z-Filter enable the user to synthesize virtually all required SLIC device
input impedances.
Frequency Response Correction and Equalization
The Le58083 Octal SLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be
programmed for line equalization and to correct any attenuation distortion caused by the Z filter.
Transhybrid Balancing
The Le58083 Octal SLAC device’s programmable B filter is used to adjust transhybrid balance (MPI Commands 86/87h and 96/
97h, GCI Commands COP 5 and COP 8). The filter has a single pole IIR section (BIIR) and an eight-tap FIR section (BFIR), both
operating at 16 kHz.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Gain Adjustment
The Le58083 Octal SLAC device’s transmit path has three programmable gain blocks. Gain block GIN is an attenuator with a
gain of GIN (see Electrical Characteristics, on page 13 for the value). Gain block AX is an analog gain of 0 dB or 6.02 dB (unity
gain or gain of 2.0), located immediately before the A/D converter. GX is a digital gain block that is programmable from 0 dB to
+12 dB, with a worst-case step size of 0.1 dB for gain settings below +10 dB, and a worst-case step size of 0.3 dB for gain settings
above +10 dB. The filters provide a net gain in the range of 0 dB to 18 dB.
The Le58083 Octal SLAC device receive path has two programmable loss blocks. GR is a digital loss block that is programmable
from 0 dB to 12 dB, with a worst-case step size of 0.1 dB. Loss block AR is an analog loss of 0 dB or 6.02 dB (unity gain or gain
of 0.5), located immediately after the D/A converter. This provides a net loss in the range of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of GR, which can be inserted by setting the LRG bit of MPI Command 70/71h,
GCI Command SOP 5. This allows writing of a single bit to introduce 6 dB of attenuation into the receive path without having to
reprogram GR. This 6 dB loss is implemented as part of GR and the total receive path attenuation must remain in the specified 0 to –
12 dB range. If the LRG bit is set, the programmed value of GR must not introduce more than an additional 6 dB attenuation.
Transmit Signal Processing
In the transmit path (A/D), the analog input signal (VIN) is A/D converted, filtered, companded (for A-law or µ-law), and made
available to the PCM highway or General Circuit Interface (GCI). Linear mode is only available in the PCM/MPI mode. If linear
form is selected, the 16-bit data will be transmitted in two consecutive time slots starting at the programmed time slot. The signal
processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The B, X, and GX blocks are userprogrammable digital filter sections with coefficients stored in the coefficient RAM, while AX is an analog amplifier that can be
programmed for 0 dB or 6.02 dB gain. The B, X, and GX filters can also be operated from an alternate set of default coefficients
stored in ROM (MPI Command 60/61h, GCI Command SOP 7).
The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a six-tap FIR
section which is part of the frequency response correction network. The B filter operates on samples from the receive signal path
in order to provide transhybrid balancing in the loop. The high-pass filter rejects low frequencies such as 50 Hz or 60 Hz, and
may be disabled.
Transmit PCM Interface (PCM/MPI Mode)
In PCM/MPI mode, the transmit PCM interface transmits a 16-bit linear code (when programmed) or an 8-bit compressed code
from the digital A-law/µ-law compressor. Transmit logic controls the transmission of data onto the PCM highway through output
port selection and time/clock slot control circuitry. The linear data requires two consecutive time slots, while a single time slot is
required for A-law/µ-law data.
In the PCM Signaling state (SMODE = 1), the transmit time slot following the A-law or µ-law data is used for signaling information.
The two time slots form a single 16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the transmit frame and all channels (time slots) are referenced to it. The logic
contains user-programmable Transmit Time Slot and Transmit Clock Slot registers.
The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature
allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system. The data is transmitted in bytes,
with the most significant bit first.
The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK periods to
eliminate any clock skew in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a nonzero
remainder, R, and when the transmit clock slot is greater than R. In that case, the R-bit fractional time slot after the last full time
slot in the frame will contain random information and will have the TSC output turned on. For example, if the PCLK frequency is
1.544 MHz (R = 1) and the transmit clock slot is greater than 1, the 1-bit fractional time slot after the last full time slot in the frame
will contain random information, and the TSC output will remain active during the fractional time slot. In such cases, problems
can be avoided by not using the last time slot.
The PCM data may be user programmed for output onto either the DXA or DXB port or both ports simultaneously.
Correspondingly, either TSCA or TSCB or both are Low during transmission.
The DXA/DXB and TSCA/TSCB outputs can be programmed to change either on the negative or positive edge of PCLK.
Transmit data can also be read through the microprocessor interface using Command CDh.
Data Upstream Interface (GCI Mode)
In the GCI mode, the Data Upstream (DU) interface transmits a total of 4 bytes per GCI channel. Two bytes are from the A-law
or µ-law compressor, one for voice channel 1, one for voice channel 2, a single Monitor channel byte, and a single SC channel
byte. Transmit logic controls the transmission of data onto the GCI bus as determined by the frame synchronization signal (FSC)
and the S0 and S1 channel select bits. No signaling or Linear mode options are available when GCI mode is selected.
The frame synchronization signal (FSC) identifies GCI channel 0 and all GCI channels are referenced to it.
Upstream Data is always transmitted at a 2.048 MHz data rate.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Receive Signal Processing
In the receive path (D/A), the digital signal is expanded (for A-law or µ-law), filtered, converted to analog, and passed to the VOUT
pin. The signal processor contains an ALU, RAM, ROM, and Control logic to implement the filter sections. The Z, R, and GR
blocks are user-programmable filter sections with their coefficients stored in the coefficient RAM, while AR is an analog amplifier
which can be programmed for a 0 dB or 6.02 dB loss. The Z, R, and GR filters can also be operated from an alternate set of
default coefficients stored in ROM (MPI Command 60/61h, GCI Command SOP 7).
The low-pass filter band limits the signal. The R filter is composed of a six-tap FIR section operating at a 16 kHz sampling rate and
a one-tap IIR section operating at 8 kHz. It is part of the frequency response correction network. The Analog Impedance Scaling
Network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different SLIC device input
impedances from a single external SLIC device impedance. The Z filter provides feedback from the transmit signal path to the
receive path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior
to
D/A conversion.
Receive PCM Interface (PCM/MPI Mode)
The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to the A-law or µlaw expansion logic for compressed signals, and then passes the data to the receive path of the signal processor. If the data
received from the PCM highway is programmed for linear code, the A-law or µ-law expansion logic is bypassed and the data is
presented to the receive path of the signal processor directly. The linear data requires two consecutive time slots, while the Alaw or µ-law data requires a single time slot.
The frame sync (FS) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to it. The logic
contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and allows
up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz
and 8.192 MHz (2 to 128 channels) in a system.
The Clock Slot register is 3 bits wide and can be programmed to offset the time slot assignment by 0 to 7 PCLK periods to
eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a
nonzero remainder (R), and when the receive clock slot is greater than R. In this case, the last full receive time slot in the frame
is not usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the receive clock slot can be only 0 or 1 if the last time
slot is to be used. The PCM data can be user-programmed for input from either the DRA or DRB port.
Data Downstream Interface (GCI Mode)
The Data Downstream (DD) interface logic controls the reception of data bytes from the GCI highway. The GCI channels received
by a four-channel group of the Le58083 Octal SLAC device is determined by the logic levels on S0 and S1, the GCI channel
select bits. The two compressed voice channel data bytes of the GCI channel are transferred to the A-law or µ-law expansion
logic. The expanded data is passed to the receive path of the signal processor. The Monitor channel and SC channel bytes are
transferred to the GCI control logic for processing.
The frame synchronization signal (FSC) identifies GCI channel 0 of the GCI frame, and all other GCI channels are referenced to it.
Downstream Data is always received at a 2.048 MHz data rate.
Analog Impedance Scaling Network (AISN)
The AISN is incorporated in the Le58083 Octal SLAC device to scale the value of the external SLIC device impedance. Scaling
this external impedance with the AISN (along with the Z filter) allows matching of many different line conditions using a single
impedance value. Line cards can meet many different specifications without any hardware changes.
The AISN is a programmable transfer function connected from VIN to VOUT of each Le58083 Octal SLAC device channel. The
AISN transfer function can be used to alter the input impedance of the SLIC device to a new value (ZIN) given by:
Z IN = Z SL • ( 1 – G 44 • h AISN ) ⁄ ( 1 – G 440 • h AISN )
where G440 is the SLIC device echo gain into an open circuit, G44 is the SLIC device echo gain into a short circuit, and ZSL is the
SLIC device input impedance without the Le58083 Octal SLAC device.
The gain can be varied from −0.9375 • GIN to +0.9375 • GIN in 31 steps of 0.0625 • GIN. The AISN gain is determined by the
following equation:
 4

i
h AISN = 0.0625 • GIN  ∑ AISNi • 2  – 16


i = 0

where AISNi = 0 or 1
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
There are two special cases to the formula for hAISN: 1) a value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value
of AISN = 10000 is a special case where the AISN circuitry is disabled and VOUT is connected internally to VIN after the input
attenuator with a gain of 0 dB. This allows a Full Digital Loopback state where an input digital PCM signal is completely processed
through the receive section, looped back, processed through the transmit section, and output as digital PCM data. During this
test, the VIN input is ignored and the VOUT output is connected to VREF.
Speech Coding
The A/D and D/A conversion follows either the A-law or the µ-law standard as defined in ITU-T Recommendation G.711. A-law
or µ-law operation is programmed using MPI Command 60/61h or GCI Command SOP 7. Alternate bit inversion is performed as
part of the A-law coding. In PCM/MPI mode, the Le58083 Octal SLAC device provides linear code as an option on both the
transmit and receive sides of the device. Linear code is selected using MPI Command 60/61h. Two successive time slots are
required for linear code operation. The linear code is a 16-bit two’s-complement number which appears sign bit first on the PCM
highway. Linear code occupies two time slots.
Double PCLK (DPCK) Operation (PCM/MPI Mode)
The Double PCLK Operation allows the PCM clock (PCLK) signal to be clocked at a rate of twice that of the PCM data. This mode
provides compatibility of the Le58083 Octal SLAC device with other existing system architectures, such as a GCI interface system
in terminal mode operating at a 768 kHz data rate with a 1.536 MHz clock rate.
The operation is enabled by setting the DPCK bit of Command C8/C9h in both four-channel groups. When set to zero, operation
is unchanged from normal PCM clocking and the PCM data and clock rates are the same. When the bit is set to 1, clocking of
PCM data is divided by two and occurs at one half of the PCLK PCM clock rate. The internal PLL used for synchronization of the
master DSP clock (MCLK) receives its input from either the MCLK or PCLK pin, depending on the clock mode (CMODE)
selection. If PCLK is used for MCLK (CMODE = 1), then the clock input is routed to both the DSP clock input and to the time slot
assigner. The timing division related to the double PCLK mode occurs only within the time slot assigner, and therefore, double
PCLK operation is available with either CMODE setting. This allows the MCLK/E1 pin to be available for E1 multiplexing operation
if both double PCLK and E1 multiplexing modes are simultaneously required.
Specifications for Double PCLK Operation are shown in the Switching Characteristics section on page 21.
Signaling on the PCM Highway (PCM/MPI Mode)
If the SMODE bit is set in the Configuration registers of both four-channel groups (MPI Command 46/47h), each data point
occupies two consecutive time slots. The first time slot contains A-law or µ-law data and the second time slot contains the
following information:
Bit 7:Debounced CD1 bit (usually hook switch)
Bit 6:CD2 bit or CD1B bit
Bits 5–3:Reserved
Bit 2:CFAIL
Bits 1–0:Reserved
Bit 7 of the signaling byte appears immediately after bit 0 of the data byte. A-law or µ-law Companded mode must be specified
in order to put signaling information on the PCM highway. The signaling time slot remains active, even when the channel is
inactive.
Robbed-Bit Signaling Compatibility (PCM/MPI Mode)
The Le58083 Octal SLAC device supports robbed bit signaling compatibility. Robbed bit signaling allows periodic use of the least
significant bit (LSB) of the receive path PCM data to be used to carry signaling information. In this scheme, separate circuitry
within the line card or system intercepts this bit out of the PCM data stream and uses this bit to control signaling functions within
the system. The Le58083 Octal SLAC device does not perform any processing of any of the robbed bits during this operation; it
simply allows for the robbed bit presence by performing the LSB substitution.
If the RBE bit is set in the Channel Enable and Operating Mode register (MPI Command 4A/4Bh), then the robbed-bit signaling
compatibility mode is enabled. Robbed-bit signaling is only available in the µ-law companding mode of the device. Also, only the
receive (digital-to-analog) path is involved. There is no change of operation to the transmit path and PCM data coming out of the
Le58083 Octal SLAC device will always contain complete PCM byte data for each time slot, regardless of robbed-bit signaling
selection.
In the absence of actual PCM data for the affected time slots, there is an uncertainty of the legitimate value of this bit to accurately
reconstruct the analog signal. This bit can always be assumed to be a 1 or 0; hence, the reconstructed signal is correct half the
time. However, the other half of the time, there is an unacceptable reconstruction error of a significance equal to the value
weighting of the LSB. To reduce this error and provide compatibility with the robbed bit signaling scheme, when in the robbed-bit
signaling mode, the Le58083 Octal SLAC device ignores the LSB of each received PCM byte and replaces its value in the
expander with a value of half the LSB’s weight. This then guarantees the reconstruction is in error by only half this LSB weight.
In the expander, the eight bits of the companded PCM byte are expanded into linear PCM data of several more bits within the
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
internal signal processing path of the device. Therefore, accuracy is not limited to the weight of the LSB, and a weight of half this
value is realizable.
When this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte requires its LSB
substituted with the half-LSB weight. This substitution only occurs for valid PCM time slots within frames for which this robbed bit
has been designated. To determine which time slots are affected, the device monitors the frame sync (FS) pulse. The current
frame is a robbed-bit frame and this half-LSB value is used only when this criteria is met:
■
■
■
■
The RBE bit is set, and
The device is in the µ-law companding mode, and
The current frame sync pulse (FS) is two PCLK cycles long, and
The previous frame sync pulse (FS) was not two PCLK cycles long.
The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 24, if the above criteria is met, and if FS is
high for two consecutive falling edges of PCLK then low for the third falling edge, it is considered a robbed-bit frame. Otherwise,
it is a normal frame.
Figure 24.
Robbed-Bit Frame
PCLK
FS
Normal Frame (Not Robbed-Bit)
PCLK
FS
Robbed-Bit Frame
Default Filter Coefficients
The Le58083 Octal SLAC device contains an internal set of default coefficients for the programmable filters. The default filter
gains are calculated based on the application circuit shown on page 91. This SLIC device has a transmit gain of 0.5 (GTX) and
a current gain of 500 (K1). The transmit relative level is set to +0.28 dBr, and the receive relative level is set to –4.39 dBr. The
equalization filters (X and R) are not optimized and the Z and B filters are set to zero. The nominal input impedance was set to
812 Ω. If the SLIC device circuit differs significantly from this design, the default gains cannot be used and must be replaced by
programmed coefficients. The balance filter (B) must always be programmed to an appropriate value.
To obtain this above-system response, the default filter coefficients are set to produce these values:
GX gain = +6 dB, GR gain = –8.984 dB
AX gain = 0 dB, AR gain = 0 dB, input attenuator on (DGIN = 0)
R filter: H(z) = 1, X filter: H(z) = 1
Z filter: H(z) = 0
B filter: H(z) = 0
AISN = cutoff
Notice that these default coefficient values are retained in read-only memory areas within the Le58083 Octal SLAC device, and
those values cannot be read back using any data commands. When the device is selected to use default coefficients, it obtains
those values directly from the read-only memory area, where the coefficient read operations access the programmable random
access data memory only. If an attempt is made to read back any filter values without those values first being written with known
programmed data, the values read back are totally random and do not represent the default or any other values.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
COMMAND DESCRIPTION AND FORMATS
Command Field Summary
A microprocessor can program and control the Le58083 Octal SLAC device using the MPI and GCI. Data programmed previously
can be read out for verification. See the tables below for the channel and global chip parameters assigned.
Commands are provided to assign values to the following channel parameters:
Table 4. Channel Parameters
Parameter
Description
MPI
GCI
TTS
Transmit time slot
40/41h
—
RTS
Receive time slot
42/43h
—
GX
Transmit gain
80/81h
COP 2
GR
Receive loss
82/83h
COP 3
B1
B1-filter coefficients
86/87h
COP 5
B2
B2-filter coefficients
96/97h
COP 8
X
X-filter coefficients
88/89h
COP 6
R
R-filter coefficients
8A/8Bh
COP 7
ZFIR
Z-FIR filter coefficients
98/99h
COP 4
ZIIR
Z-IIR filter coefficients
9A/9Bh
COP 9
Z-filter coefficients (both FIR and IIR)
84/85h
—
AISN coefficient
50/51h
COP1
Z
AISN
CD1–C7
Read SLIC device Outputs
52h
SOP 10
IOD1–5
SLIC device Input/Output Direction
54/55h
SOP 8
A/µ
Select A-law or µ-law
60/61h
SOP 7
C/L
Compressed/linear
60/61h
—
Select Transmit PCM highway A or B
40/41h
—
Transmit on A and B
44/45h
—
TPCM
TAB
RPCM
Select Receive PCM highway A or B
42/43h
—
EB
Programmed/Default B filter
60/61h
SOP 7
EZ
Programmed/Default Z filter
60/61h
SOP 7
EX
Programmed/Default X filter
60/61h
SOP 7
Programmed/Default R filter
60/61h
SOP 7
EGX
ER
Programmed/Default GX filter
60/61h
SOP 7
EGR
Programmed/Default GR filter
60/61h
SOP 7
DGIN
Disable input attenuator
50/51h
COP 1
AX
Enable/disable AX amplifier
50/51h
COP 1
AR
Enable/disable AR amplifier
50/51h
COP 1
CTP
Cutoff Transmit Path
70/71h
SOP 5
CRP
Cutoff Receive Path
70/71h
SOP 5
HPF
Disable High Pass Filter
70/71h
SOP 5
LRG
Lower Receive Gain
70/71h
SOP 5
ATI
Arm Transmit Interrupt
70/71h
SOP 5
ILB
Interface Loopback
70/71h
SOP 5
SOP 5
FDL
Full Digital Loopback
70/71h
TON
1 kHz Tone On
70/71h
SOP 5
Ground Key Filter
E8/E9h
SOP 12
55h
00h, 0Eh
SOP 8
SOP 1, SOP 4
GK
CSTAT
Select Active or Inactive (Standby) mode
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Commands are provided to read values from the following channel monitors:
Table 5. Channel Monitors
Monitor
CD1–C5
Description
MPI
GCI
Read SLIC device Inputs
53h
SOP 10
CD1B
Multiplexed SLIC device Input
53h
SOP 10
XDAT
Transmit PCM data
CDh
—
Commands are provided to assign values to the following global (four-channel group) chip parameters. Parameters marked with
an asterisk (*) must be programmed the same in both four-channel groups.
Table 6. Global Chip Parameters
Parameter
Description
MPI
GCI
*
XE
Transmit PCM Clock Edge
44/45h
—
*
RCS
Receive Clock Slot
44/45h
—
*
TCS
Transmit Clock Slot
44/45h
—
INTM
Interrupt Output Drive Mode
46/47h
SOP 6
CHP
Chopper Clock Frequency
46/47h
SOP 6
ECH
Enable Chopper Clock Output
C8/C9h
SOP 11
*
SMODE
Select Signaling on the PCM Highway
46/47h
—
*
CMODE
Select Master Clock Mode
46/47h
—
*
CSEL
Select Master Clock Frequency
46/47h
—
RBE
Robbed Bit Enable
4A/4Bh
—
VMODE
VOUT Mode
4A/4Bh
SOP 9
EC
Channel Enable Register
4A/4Bh
—
DSH
Debounce Time for CD1
C8/C9h
SOP 11
EE1
Enable E1 Output
C8/C9h
SOP 11
E1P
E1 Polarity
C8/C9h
SOP 11
DPCK
Double PCLK Operation
C8/C9h
—
MCDxC
Interrupt Mask Register
6C/6Dh
SOP 14
*
Commands are provided to read values from the following global four-channel group chip status monitors:
Table 7. Global Chip Status Monitors
Monitor
MPI
GCI
CDxC
Real Time Data Register
4D/4Fh
SOP 13, C/I
CFAIL
Clock Failure Bit
54/55h
SOP 8
73h
TOP 1
Configuration (0000)
—
CIC
Device Type (10)
—
CIC
RCN
CONF
DT
Description
Revision Code Number
Microprocessor Interface Description
When PCM/MPI mode is selected via the CS/PG and DCLK/S0 pins, a microprocessor can be used to program the Le58083
Octal SLAC device and control its operation using the Microprocessor Interface (MPI). Data programmed previously can be read
out for verification.
The following description of the MPI (Microprocessor Interface) for a four-channel group is valid for channels 1– 4. If desired,
multiple channels can be programmed simultaneously with identical information by setting multiple Channel Enable bits. Channel
enables are contained in the Channel Enable register and are written or read using Command 4A/4Bh. If multiple Channel Enable
bits are set for a read operation, only data from the first enabled channel will be read.
The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS). Individual Channel
Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable register of the Le58083 Octal SLAC device.
The serial input consists of 8-bit commands that can be followed with additional bytes of input data, or can be followed by the
Le58083 Octal SLAC device sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data
bytes are read or written one at a time, with CS going High for at least a minimum off period before the next byte is read or written.
Only a single channel should be enabled during read commands.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
All commands that require additional input data to the device must have the input data as the next N words written into the device
(for example, framed by the next N transitions of CS). All unused bits must be programmed as 0 to ensure compatibility with future
parts. All commands that are followed by output data will cause the device to output data for the next N transitions of CS going
Low. The Le58083 Octal SLAC device will not accept any commands until all the data has been shifted out. The output values
of unused bits are not specified.
An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses, the DCLK
may run continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of
Le58083 Octal SLAC devices, and the individual CS lines will select the appropriate device to access. Between command
sequences, DCLK can stay in the High state indefinitely with no loss of internal control information regardless of any transitions
on the CS lines. Between bytes of a multibyte read or write command sequence, DCLK can also stay in the High state indefinitely.
DCLK can stay in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a High
level.
If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive transitions, only
the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the part occurs. If the chip is in the
middle of a read sequence when CS goes Low, data will be present at the DIO pin even if DCLK has no activity. If CS is held low
for two or more cycles of Frame Sync (FS) and DCLK is static (no toggling), then the Le58083 Octal SLAC device switches to
the General Circuit Interface mode of operation.
SUMMARY OF MPI COMMANDS
Hex*
00h
02h
04h
06h
0Eh
40/41h
42/43h
44/45h
46/47h
4A/4Bh
4Dh
4Fh
50/51h
52/53h
54,55h
60/61h
6C/6Dh
70/71h
73h
80/81h
82/83h
84/85h
86/87h
88/89h
8A/8Bh
96/97h
98/99h
9A/9Bh
C8/C9h
CDh
E8/E9h
Description
Deactivate (Standby state)
Software Reset
Hardware Reset
No Operation
Activate (Operational state)
Write/Read Transmit Time Slot and PCM Highway Selection
Write/Read Receive Time Slot and PCM Highway Selection
Write/Read REC & TX Clock Slot and TX Edge
Write/Read Configuration Register
Write/Read Channel Enable & Operating Mode Register
Read Real Time Data Register
Read Real Time Data Register and Clear Interrupt
Write/Read AISN and Analog Gains
Write/Read SLIC device Input/Output Register
Write/Read SLIC device Input/Output Direction and Status Bits
Write/Read Operating Functions
Write/Read Interrupt Mask Register
Write/Read Operating Conditions
Read Revision Code Number (RCN)
Write/Read GX Filter Coefficients
Write/Read GR Filter Coefficients
Write/Read Z Filter Coefficients (FIR and IIR)
Write/Read B1 Filter Coefficients (FIR)
Write/Read X Filter Coefficients
Write/Read R Filter Coefficients
Write/Read B2 Filter Coefficients (IIR)
Write/Read Z Filter Coefficients (FIR only)
Write/Read Z Filter Coefficients (IIR only)
Write/Read Debounce Time Register
Read Transmit PCM Data
Write/Read Ground Key Filter Sampling Interval
Note:
*All codes not listed are reserved by Zarlink and should not be used.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
MPI COMMAND STRUCTURE
This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow.
For details of the filter coefficients of the form CXYmXY, refer to the General Description of CSD Coefficients section page 86.
Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.
*Default field values are marked by an asterisk. A hardware reset forces the default values.
Global bits and commands refer to a four-channel group of the device.
00h Deactivate (Standby State)
MPI Command
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
In the Deactivate (Standby) state:
All programmed information is retained.
The Microprocessor Interface (MPI) remains active.
The PCM inputs are disabled and the PCM outputs are high impedance unless signaling on the PCM high
way is programmed (SMODE = 1).
The analog output (VOUT) is disabled and biased at VREF.
The channel status (CSTAT) bit in the SLIC device I/O Direction and Channel Status Register is set to 0.
02h Software Reset
MPI Command
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
0
The action of this command is identical to that of the RST pin except that it only operates on the channels selected by the
Channel Enable Register and it does not change clock slots, time slots, PCM highways, ground key sampling interval
or global chip parameters. See the note under the hardware reset command that follows.
04h Hardware Reset
MPI Command
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
Hardware reset is equivalent to pulling the RST on a four-channel group of the device Low. This command does not depend on
the state of the Channel Enable Register.
Note:
The action of a hardware reset is described in Reset States on page 37 of the section Operating the Le58083 Octal SLAC Device.
06h No Operation
MPI Command
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
1
0
0Eh Activate Channel (Operational State)
MPI Command
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until after the
second FS pulse is received following the execution of the Activate command.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
40/41h Write/Read Transmit Time Slot and PCM Highway Selection
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
Transmit PCM Highway
TPCM = 0*
TPCM = 1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
R/W
TPCM
TTS6
TTS5
TTS4
TTS3
TTS2
TTS1
TTS0
Transmit on Highway A (see TAB in Commands 44/45h)
Transmit on Highway B (see TAB in Commands 44/45h)
Transmit Time Slot
TTS = 0–127
Time Slot Number (TTS0 is LSB, TTS6 is MSB)
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for channels 1, 2, 3, and 4 of a four-channel group, respectively.
42/43h Write/Read Receive Time Slot and PCM Highway Selection
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
Receive PCM Highway
RPCM = 0*
RPCM = 1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
1
R/W
RPCM
RTS6
RTS5
RTS4
RTS3
RTS2
RTS1
RTS0
Receive on Highway A
Receive on Highway B
Receive Time Slot
RTS = 0–127
Time Slot Number (RTS0 is LSB, RTS6 is MSB)
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for channels 1, 2, 3, and 4 of a four-channel group, respectively.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
R/W
TAB
XE
RCS2
RCS1
RCS0
TCS2
TCS1
TCS0
Command
I/O Data
Transmit on A and B
TAB = 0*
TAB = 1
Transmit data on highway selected by TPCM (see Commands 40/41h).
Transmit data on both highways A and B
Transmit Edge (Global parameter) - Program the same in both four channel groups
XE = 0*
Transmit changes on negative edge of PCLK
XE = 1
Transmit changes on positive edge of PCLK
Receive Clock Slot (Global parameter) - Program the same in both four channel groups
RCS = 0*–7
Receive Clock Slot number
Transmit Clock Slot (Global parameter) - Program the same in both four channel groups
TCS = 0*–7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read unless at least one channel is
selected in the Channel Enable Register; however, TAB is channel specific.
* Power Up and Hardware Reset (RST) Value = 00h.
46/47h Write/Read Chip Configuration Register
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
Interrupt Mode (Global parameter)
INTM = 0
INTM = 1*
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
R/W
INTM
CHP
SMODE
CMODE
CSEL3
CSEL2
CSEL1
CSEL0
TTL-compatible output
Open drain output
Chopper Clock Control (Global parameter)
CHP = 0*
Chopper Clock is 256 kHz (2048/8 kHz)
CHP = 1
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode (Global parameter) - Program the same in both four channel groups
SMODE = 0*
No signaling on PCM highway
SMODE = 1
Signaling on PCM highway
Clock Source Mode (Global parameter) - Program the same in both four channel groups
CMODE = 0
MCLK used as master clock; no E1 multiplexing allowed
CMODE = 1*
PCLK used as master clock; E1 multiplexing allowed if enabled in Command C8/C9h.
The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels.
Master Clock Frequency (Global parameter) - Program the same in both four channel groups
CSEL = 0000
1.536 MHz
CSEL = 0001
1.544 MHz
CSEL = 0010
2.048 MHz
CSEL = 0011
Reserved
CSEL = 01xx
Two times frequency specified above (2 x 1.536 MHz, 2 x 1.544 MHz, or 2 x 2.048 MHz)
CSEL = 10xx
Four times frequency specified above (4 x 1.536 MHz, 4 x 1.544 MHz, or 4 x 2.048 MHz)
CSEL = 11xx
Reserved
CSEL = 1010*
8.192 MHz is the default
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
These commands do not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 9Ah.
4A/4Bh Write/Read Channel Enable and Operating Mode Register
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
R/W
RSVD
RBE
LPM
EC4
EC3
EC2
EC1
VMOD
E
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read
Robbed-bit Mode (Global parameter)
RBE = 0*
Robbed-bit Signaling mode is disabled
RBE = 1
Robbed-bit Signaling mode is enabled on PCM receiver if µ-law is selected
VOUT Mode (Global parameter)
VMODE = 0*
VMODE = 1
VOUT = VREF through a resistor when channel is deactivated
VOUT high impedance when channel is deactivated
Low Power Mode (Global parameter)
LPM
LPM reduced the power in the QSLAC device, but it is not needed and not used in the
Le58083 Octal SLAC device
Channel Enable 4
EC4 = 0
Disabled, channel 4 cannot receive commands
EC4 = 1*
Enabled, channel 4 can receive commands
Channel Enable 3
EC3 = 0
EC3 = 1*
Disabled, channel 3 cannot receive commands
Enabled, channel 3 can receive commands
EC2 = 0
EC2 = 1*
Disabled, channel 2 cannot receive commands
Enabled, channel 2 can receive commands
EC1 = 0
EC1 = 1*
Disabled, channel 1 cannot receive commands
Enabled, channel 1 can receive commands
Channel Enable 2
Channel Enable 1
* Power Up and Hardware Reset (RST) Value = 0Fh.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
4D/4Fh Read Real-Time Data Register
MPI Command
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without clearing the interrupt.
Command
Output Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
C
1
CDB4
CDA4
CDB3
CDA3
CDB2
CDA2
CDB1
CDA1
Real Time Data
CDA1
CDB1
CDA2
CDB2
CDA3
CDB3
CDA4
CDB4
Debounced data bit 1 on channel 1
Data bit 2 or multiplexed data bit 1 on channel 1
Debounced data bit 1 on channel 2
Data bit 2 or multiplexed data bit 1 on channel 2
Debounced data bit 1 on channel 3
Data bit 2 or multiplexed data bit 1 on channel 3
Debounced data bit 1 on channel 4
Data bit 2 or multiplexed data bit 1 on channel 4
This command does not depend on the state of the Channel Enable Register.
50/51h Write/Read AISN and Analog Gains
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
R/W
DGIN
AX
AR
AISN4
AISN3
AISN2
AISN1
AISN0
Disable Input Attenuator (GIN)
DGIN = 0*
DGIN = 1
Input attenuator on
Input attenuator off
Transmit Analog Gain
AX = 0*
AX = 1
0 dB gain
6.02 dB gain
Receive Analog Loss
AR = 0*
AR = 1
0 dB loss
6.02 dB loss
AISN coefficient
AISN = 0* – 31
See below (Default value = 0)
The Impedance Scaling Network (AISN) gain can be varied from −0.9375 • GIN to +0.9375 • GIN in
multiples of 0.0625 • GIN.
The gain coefficient is decoded using the following equation:
h AISN = 0.0625 • GIN [ ( 16 • AISN4 + 8 • AISN3 + 4 • AISN2 + 2 • AISN1 + AISN0 ) – 16 ]
where hAISN is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode and
a value of AISN = 0000* indicates a gain of 0 (cutoff).
* Power Up and Hardware Reset (RST) Value = 00h.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
52/53h Write/Read SLIC Device Input/Output Register
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
R/W
C7
C6
CD1B
C5
C4
C3
CD2
CD1
Pins CD1, CD2, and C3 through C7 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC I/O
pins, provided they were set in the Output mode (see Command 54/55h). The data sent to any of the pins set to the
Input mode is latched, but does not appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
C7 and C6 are outputs only.
* Power Up and Hardware Reset (RST) Value = 00h
54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
1
0
R/W
Input Data
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read status only, write as 0)
CSTAT = 0
Channel is inactive (Standby state).
CSTAT = 1
Channel is active.
Clock Fail (Read status only, write as 0) (Global status bit)
CFAIL* = 0
The internal clock is synchronized to frame synch.
CFAIL = 1
The internal clock is not synchronized to frame synch.
* The CFAIL bit is independent of the Channel Enable Register.
I/O Direction (Read/Write)
IOD5 = 0*
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually.
* Power Up and Hardware Reset (RST) Value = 00h
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
60/61h Write/Read Operating Functions
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
R/W
C/L
A/µ
EGR
EGX
EX
ER
EZ
EB
Command
I/O Data
Linear Code
C/L = 0*
C/L = 1
Compressed coding
Linear coding
A/µ = 0*
A/µ = 1
A-law coding
µ-law coding
EGR = 0*
EGR = 1
Default GR filter enabled
Programmed GR filter enabled
EGX = 0*
EGX = 1
Default GX filter enabled
Programmed GX filter enabled
EX = 0*
EX = 1
Default X filter enabled
Programmed X filter enabled
ER = 0*
ER = 1
Default R filter enabled
Programmed R filter enabled
EZ = 0*
EZ = 1
Default Z filter enabled
Programmed Z filter enabled
EB = 0*
EB = 1
Default B filter enabled
Programmed B filter enabled
A-law or µ-law
GR Filter
GX Filter
X Filter
R Filter
Z Filter
B Filter
* Power Up and Hardware Reset (RST) Value = 00h.
6C/6Dh Write/Read Interrupt Mask Register
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
0
R/W
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
Mask CD Interrupt
CDxC bit is NOT MASKED
MCDxC = 0
CDxC bit is MASKED
MCDxC = 1*
x
Bit number (A or B)
C
Channel number (1 through 4)
Masked: A change does not cause the Interrupt Pin to go Low.
This command does not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = FFh.
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Le58083
Data Sheet
70/71h Write/Read Operating Conditions
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
Cutoff Transmit Path
CTP = 0*
CTP = 1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
0
R/W
CTP
CRP
HPF
LRG
ATI
ILB
FDL
TON
Transmit path connected
Transmit path cut off
Cutoff Receive Path
CRP = 0*
CRP = 1
Receive path connected
Receive path cutoff (see note)
HPF = 0*
HPF = 1
Transmit Highpass filter enabled
Transmit Highpass filter disabled
LRG = 0*
LRG = 1
6 dB loss not inserted
6 dB loss inserted
High Pass Filter
Lower Receive Gain
Arm Transmit Interrupt
ATI = 0*
ATI = 1
Transmit Interrupt not Armed
Transmit Interrupt Armed
Interface Loopback
ILB = 0*
ILB = 1
Full Digital Loopback
FDL = 0*
FDL = 1
TSA loopback disabled
TSA loopback enabled
Full digital loopback disabled
Full digital loopback enabled
1 kHz Receive Tone
TON = 0*
TON = 1
1 kHz receive tone off
1 kHz receive tone on
* Power Up and Hardware Reset (RST) Value = 00h.
The B Filter is disabled during receive cutoff.
73h Read Revision Code Number (RCN)
MPI Command
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
1
RCN7
RCN6
RCN5
RCN4
RCN3
RCN2
RCN1
RCN0
This command returns an 8-bit number (RCN) describing the revision number of the Le58083 Octal SLAC device. The revision
code of the Le58083 Octal SLAC device will be 14h or higher. This command does not depend on the state of the Channel
Enable Register.
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Le58083
Data Sheet
80/81h Write/Read GX Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GX filter is defined as:
H GX = 1 + ( C10 • 2
– m10
{ 1 + C20 • 2
– m20
[ 1 + C30 • 2
– m30
( 1 + C40 • 2
– m40
)]}
Power Up and Hardware Reset (RST) Values = A9F0 (Hex) (HGX = 1.995 (6 dB)).
Note:
The default value is contained in a ROM register separate from the programmable coefficient RAM. There is a filter enable bit in Operating Functions Register to switch between the default and programmed values.
82/83h Write/Read GR Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
Command:
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
1
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GR filter is defined as:
H GR = C10 • 2
– m10
{ 1 + C20 • 2
– m20
[ 1 + C30 • 2
– m30
( 1 + C40 • 2
Power Up and Hardware Reset (RST) Values = 23A1 (Hex) (HGR = 0.35547 (–8.984 dB)).
See note under Command 80/81h on page 54.
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– m40
)]}
Le58083
Data Sheet
84/85h Write/Read Z Filter Coefficients (FIR and IIR)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes and reads both the FIR and IIR filter sections simultaneously.
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
I/O Data Byte 3
C41
m41
C31
m31
I/O Data Byte 4
C21
m21
C11
m11
I/O Data Byte 5
C42
m42
C32
m32
I/O Data Byte 6
C22
m22
C12
m12
I/O Data Byte 7
C43
m43
C33
m33
I/O Data Byte 8
C23
m23
C13
m13
I/O Data Byte 9
C44
m44
C34
m34
I/O Data Byte 10
C24
m24
C14
m14
I/O Data Byte 11
C45
m45
C35
m35
I/O Data Byte 12
C25
m25
C15
m15
I/O Data Byte 13
C26
m26
C16
m16
I/O Data Byte 14
C47
m47
C37
m37
I/O Data Byte 15
C27
m27
C17
m17
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z5 • z6 • z7 • z
+ -----------------------------------------1 – z7 • z
–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
z 6 = C16 • 2
– m16
– m1i
{ 1 + C2i • 2
{ 1 + C26 • 2
– m26
– m2i
[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(HZ(z) = 0)
See note under Command 80/81h on page 54.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
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Data Sheet
86/87h Write/Read B1 Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
1
R/W
Command
I/O Input Data Byte 1
C32
m32
C22
m22
I/O Input Data Byte 2
C12
m12
C33
m33
I/O Input Data Byte 3
C23
m23
C13
m13
I/O Input Data Byte 4
C34
m34
C24
m24
I/O Input Data Byte 5
C14
m14
C35
m35
I/O Input Data Byte 6
C25
m25
C15
m15
I/O Input Data Byte 7
C36
m36
C26
m26
I/O Input Data Byte 8
C16
m16
C37
m37
I/O Input Data Byte 9
C27
m27
C17
m17
I/O Input Data Byte 10
C38
m38
C28
m28
I/O Input Data Byte 11
C18
m18
C39
m39
I/O Input Data Byte 12
C29
m29
C19
m19
I/O Input Data Byte 13
C310
m310
C210
m210
I/O Input Data Byte 14
C110
m110
RSVD
RSVD
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the B filter is defined as:
HB ( z ) = B2 • z
–2
+ … + B9 • z
–9
– 10
B 10 • z
+ -------------------------------1 – B 11 • z
–1
Sample rate = 16 kHz
The coefficients for the FIR B section and the gain of the IIR B section are defined as:
For i = 2 to 10,
B i = C1i • 2
– mli
[ 1 + C2i • 2
– m2i
( 1 + C3i • 2
– m3i
)]
The feedback coefficient of the IIR B section is defined as
B 11 = C111 • 2
– m111
{ 1 + C211 • 2
– m211
[ 1 + C311 • 2
– m311
( 1 + C411 • 2
Refer to Command 96/97h for programming of the B11 coefficients.
Power Up and Hardware Reset (RST) Values = 09 00 90 09 00 90 09 00 90 09 00 90 09 00 (Hex)
HB ( z ) = 0
See note under Command 80/81h on page 54.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
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– m411
)]}
Le58083
Data Sheet
88/89h Write/Read X Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
R/W
I/O Input Data Byte 1
C40
m40
C30
m30
I/O Input Data Byte 2
C20
m20
C10
m10
I/O Input Data Byte 3
C41
m41
C31
m31
I/O Input Data Byte 4
C21
m21
C11
m11
I/O Input Data Byte 5
C42
m42
C32
m32
I/O Input Data Byte 6
C22
m22
C12
m12
I/O Input Data Byte 7
C43
m43
C33
m33
I/O Input Data Byte 8
C23
m23
C13
m13
I/O Input Data Byte 9
C44
m44
C34
m34
I/O Input Data Byte 10
C24
m24
C14
m14
I/O Input Data Byte 11
C45
m45
C35
m35
I/O Input Data Byte 12
C25
m25
C15
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the X filter is defined as:
Hx ( z ) = x0 + x1 z
–1
+ x2 z
–2
+ x3 z
–3
+ x4 z
–4
+ x5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the X filter are defined as:
Xi = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190 (Hex)
(HX(z) = 1)
See note under Command 80/81h on page 54.
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[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
)]}
Le58083
Data Sheet
8A/8Bh Write/Read R Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
1
R/W
I/O Input Data Byte 1
C46
m46
C36
m36
I/O Input Data Byte 2
C26
m26
C16
m16
I/O Input Data Byte 3
C40
m40
C30
m30
I/O Input Data Byte 4
C20
m20
C10
m10
I/O Input Data Byte 5
C41
m41
C31
m31
I/O Input Data Byte 6
C21
m21
C11
m11
I/O Input Data Byte 7
C42
m42
C32
m32
I/O Input Data Byte 8
C22
m22
C12
m12
I/O Input Data Byte 9
C43
m43
C33
m33
I/O Input Data Byte 10
C23
m23
C13
m13
I/O Input Data Byte 11
C44
m44
C34
m34
I/O Input Data Byte 12
C24
m24
C14
m14
I/O Input Data Byte 13
C45
m45
C35
m35
I/O Input Data Byte 14
C25
m25
C15
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
HR = H IIR • H FIR
The Z-transform equation for the IIR filter is defined as:
–1
1–z
H IIR = -----------------------------------–1
1 –  R 6 • z 
Sample rate = 8 kHz
The coefficient for the IIR filter is defined as:
R 6 = C16 • 2
– ml6
{ 1 + C26 • 2
– m26
[ 1 + C36 • 2
– m36
( 1 + C46 • 2
– m46
)]}
The Z-transform equation for the FIR filter is defined as:
H FIR ( z ) = R 0 + R 1 z
–1
+ R2 z
–2
+ R3 z
–3
+ R4 z
–4
+ R5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the R2 filter are defined as:
R i = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
)]}
Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex)
(HFIR (z) = 1, R6 = 0.9902)
See note under Command 80/81h on page 54.
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Le58083
Data Sheet
96/97h Write/Read B2 Filter Coefficients (IIR)
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
1
1
R/W
I/O Data Byte 1
C411
m411
C311
m311
I/O Data Byte 2
C211
m211
C111
m111
This function is described in Write/Read B1 Filter Coefficients (FIR) on page 56.
Power Up and Hardware Reset (RST) Values = 0190 (Hex) (B11 = 0)
See note under Command 80/81h on page 54.
98/99h Write/Read FIR Z Filter Coefficients (FIR only)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes and reads only the FIR filter section without affecting the IIR.
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
I/O Data Byte 3
C41
m41
C31
m31
I/O Data Byte 4
C21
m21
C11
m11
I/O Data Byte 5
C42
m42
C32
m32
I/O Data Byte 6
C22
m22
C12
m12
I/O Data Byte 7
C43
m43
C33
m33
I/O Data Byte 8
C23
m23
C13
m13
I/O Data Byte 9
C44
m44
C34
m34
I/O Data Byte 10
C24
m24
C14
m14
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z5 • z6 • z7 • z
+ -----------------------------------------1 – z7 • z
–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
z 6 = C16 • 2
– m1i
– m16
– m2i
[ 1 + C3i • 2
– m26
}
{ 1 + C2i • 2
{ 1 + C26 • 2
– m3i
( 1 + C4i • 2
– m4i
) ]}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(HZ(z) = 0)
See note under Command 80/81h on page 54.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
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Le58083
Data Sheet
9A/9Bh Write/Read IIR Z Filter Coefficients (IIR only)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes/reads the IIR filter section only, without affecting the FIR.
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
1
R/W
I/O Data Byte 1
C45
m45
C35
m35
I/O Data Byte 2
C25
m25
C15
m15
I/O Data Byte 3
C26
m26
C16
m16
I/O Data Byte 4
C47
m47
C37
m37
I/O Data Byte 5
C27
m27
C17
m17
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z5 • z6 • z7 • z
+ -----------------------------------------1 – z7 • z
–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
z 6 = C16 • 2
– m1i
{ 1 + C2i • 2
– m16
– m2i
{ 1 + C26 • 2
[ 1 + C3i • 2
– m26
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(HZ(z) = 0)
See note under Command 80/81h on page 54.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter
section is first increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within
this filter. The IIR filter output is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by
the programmed coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and
normalization, is actually Z5/Z6.
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Le58083
Data Sheet
C8/C9h Write/Read Debounce Time Register
This command applies to all channels and does not depend on the state of the Channel Enable Register.
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
0
0
R/W
EE1
E1P
DSH3
DSH2
DSH1
DSH0
DPCK
ECH
Enable E1 (Global parameter)
EE1 = 0*
EE1 = 1
E1 multiplexing turned off
E1 multiplexing turned on
E1 Polarity (Global parameter)
E1P = 0*
E1P = 1
E1 is a high-going pulse
E1 is a low-going pulse
There is no E1 output unless CMODE = 1.
Debounce for hook switch (Global parameter)
DSH = 0–15
Debounce period in ms
DSH contains the debouncing time (in ms) of the CD1 data (usually hook switch) entering the Real Time
Data register described earlier. The input data must remain stable for the debouncing time in order to
change the appropriate real time bit.
Default = 8 ms
Double PCLK Operation (Global parameter) - Program the same in both four channel groups
DPCK = 0*
Double PCLK operation is off. PCLK and PCM data at same rate.
DPCK = 1
Double PCLK enabled. PCLK operates at twice the PCM data rate.
Enable Chopper (Global parameter)
ECH = 0*
ECH = 1
Chopper output (CHCLK) turned off
Chopper output (CHCLK) turned on
* Power Up and Hardware Reset (RST) Value = 20h.
CDh Read Transmit PCM Data (PCM/MPI Mode Only)
MPI Command
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
1
0
1
Output Data Byte 1
XDAT7
XDAT6
XDAT5
XDAT4
XDAT3
XDAT2
XDAT1
XDAT0
Output Data Byte 2
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Command
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Upper Transmit Data
XDAT contains A-law or µ-law transmit data in Companded mode.
XDAT contains upper data byte in Linear mode with sign in XDAT7.
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Le58083
Data Sheet
E8/E9h Write/Read Ground Key Filter
MPI Command
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
0
0
R/W
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
GK0
Filter Ground Key
GK = 0–15
Filter sampling period in 1 ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the Real Time Data register
described earlier. A value of 0 disables the Ground Key filter for that particular channel.
Power Up and Hardware Reset (RST) Value = x0h.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
GENERAL CIRCUIT INTERFACE (GCI) SPECIFICATIONS
GCI General Description
When the CS/PG_1 and CS/PG_2 device pins are connected to DGND and DCLK/S0_1and DCLK/S0_2 are static (not toggling),
GCI operation is selected. The Le58083 Octal SLAC device conforms to the GCI standard where data for eight GCI channels are
combined into one serial bit stream. A GCI channel contains the control and voice data for two analog channels of the Octal SLAC
device. Four GCI channels are required to access all eight channels of the Le58083 Octal SLAC device. The Le58083 Octal
SLAC device sends Data Upstream out of the DU pin and receives Downstream Data on the DD pin. Data clock rate and frame
synchronization information goes to the Le58083 Octal SLAC device on the DCL (Data Clock) and FSC input pins, respectively.
Two of eight GCI channels are selected by connecting the S0 and S1 channel selection pins on the Le58083 Octal SLAC device
to DGND or VCCD as shown in Table Table 8. As an example, doing GCI operation selection if DCLK/S0_1, DIO/S1_1, and DIO/
S1_2 were tied to DGND and DCLK/S0_2 was tied to VCCD, then the internal four-channel SLAC 1 device would communicate
on GCI channels 0 & 1 and internal SLAC 2 would communicate on GCI channels 2 and 3.
Table 8. GCI Channel Assignment Codes
S1
S0
GCI Channels #
DGND
DGND
0&1
DGND
VCCD
2&3
VCCD
DGND
4&5
VCCD
VCCD
6&7
In the time slot control block (shown in Figure 25), the Frame Sync (FSC) pulse identifies the beginning of the Transmit and
Receive frames and all GCI channels are referenced to it. Voice (B1 and B2), C/I, and monitor data are sent to the Upstream
Multiplexer where they are combined and serially shifted out of the DU pin during the selected GCI Channels. The Downstream
Demultiplexer uses the same channel control block information to demultiplex the incoming GCI channels into separate voice
(B1 and B2), C/I, and monitor data bytes.
The Le58083 Octal SLAC device supports an eight GCI channel bus (16 analog channels). The external clock applied to the DCL
pin is either 2.048 MHz or 4.096 MHz. The Le58083 Octal SLAC device determines the incoming clock frequency and adjusts
internal timing automatically to accommodate single or double clock rates.
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Le58083
Figure 25.
Data Sheet
Time Slot Control and GCI Interface
Voice data for B1 byte
Voice data for B2 byte
Upstream
Multiplexer
C/I Data
DU
Monitor Data
FS
S0
Time Slot
Control
DCL
S1
Voice data for B1 byte
Voice data for B2 byte
Downstream
Demultiplexer
C/I Data
Monitor Data
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Zarlink Semiconductor Inc.
DD
Le58083
Data Sheet
GCI Format and Command Structure
The GCI interface provides communication of both control and voice data between the GCI highway and subscriber line circuits
over a single pair of pins on the Le58083 Octal SLAC device. A complete GCI frame is sent upstream on the DU pin and received
downstream on the DD pin every 125 µs. Each frame consists of eight 4 byte GCI channels (CHN0 to 7) that contain voice and
control information for eight pairs of channels. A particular channel pair is identified by its position within the frame (see Figure
26). Therefore, a total of 16 voice channels can be uniquely addressed each frame. The overall structure of the GCI frame is
shown in Figure 26.
The 4 byte GCI channel contains the following:
■ 2 bytes; B1 and B2 for voice channels 1 and 2.
■ One Monitor (M) byte for reading/writing control data/coefficients to the Le58083 Octal SLAC device for both
channels.
■ One Signaling and Control (SC) byte containing a 6-bit Command/Indicate (C/I) channel for control information and
a 2-bit field with Monitor Receive and Monitor Transmit (MR, MX) bits for handshaking functions for both channels.
All principal signaling (real-time critical) information is carried on the C/I channel. The Le58083 Octal SLAC device
utilizes the full C/I channel capacity of the GCI channel.
Figure 26.
Multiplexed GCI Time Slot Structure
FS
DU, DD
0−3
4−7
8−11
12−15
16−19
CHN0
CHN1
CHN2
CHN3
CHN4
20−23
CHN5
8
8
8
8
B1
B2
M
SC
0
1
2
3
24−27
28−31
CHN6
CHN7
6
1
1
C/I
MR
MX
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Signaling and Control (SC) Channel
The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the Le58083
Octal SLAC device in the C/I field. This allows the upstream processor to have immediate access to the output (downstream) and
input (upstream) data present on the Le58083 Octal SLAC device’s programmable I/O port.
The MR and MX bits are used for handshaking during data exchanges on the monitor channel.
Downstream C/I Channel
The Le58083 Octal SLAC device receives the MSBs first.
<---------------- Downstream SC Octet ------------------>
MSB
LSB
7
6
5
4
3
2
1
0
A
C7C
C6C
C5C
C4C
C3C
MR
MX
|<------------------- C/I Field ------------------->|
A: Channel Address Bit
0: Selects CH 1 or 3 as the downstream data destination
1: Selects CH 2 or 4 as the downstream data destination
C7C–C3C: SLIC device output latch bits 7–3 of the channel selected by A.
C = 1 or 2, the channel selected by A
If the Le58083 Octal SLAC device’s programmable I/O ports, CD1, CD2, and C3 are programmed for Input mode, then data is
obtained through the Upstream C/I channel.
Figure 27 shows the transmission protocol for the downstream C/I. Whenever the received pattern of C/I bits 6–1 is different from
the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/I register and a latch is set. When the
next pattern is received (in the following frame) while the latch is set, the following rules apply:
1.
2.
3.
If the received pattern corresponds to the pattern in the secondary register, the new pattern is loaded into the C/I register for
the addressed channel and the latch is reset. The updated C/I register data appears at the programmable I/O pins of the
device one frame (125 µs) later if they are programmed as outputs.
If the received pattern is different from the pattern in the secondary register and different from the pattern currently in the C/
I register, the newly received pattern is loaded into the secondary C/I register and the latch remains set. The data at the PI/
O port remains unchanged.
If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and the latch is
reset.
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Zarlink Semiconductor Inc.
Le58083
Figure 27.
Data Sheet
Security Procedure for C/I Downstream Bytes
Receive New C/I Code
=I?
Yes
No
I: C/I Register Contents
Store in S
S: C/I Secondary Register Contents
Receive New C/I Code
Yes
Load C/I Register
with New Code
=S?
No
=I?
Yes
No
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Upstream C/I Channel
The SC channel, which includes the six C/I channel bits, is transmitted upstream every frame. The bit definitions for the upstream
C/I channel are shown below. These bits are transmitted by the Le58083 Octal SLAC device (Most significant bit first).
GCI Format
<------------------------ Upstream SC Octet ------------------>
MSB
LSB
7
6
5
4
3
2
1
0
C31
CDB1
CDA1
C32
CDB2
CDA2
MR
MX
|<----------------------- C/I FIELD ------------->|
Upstream Bit Definitions of the C/I field require the programmable I/O ports to be programmed as inputs. Otherwise, these bits
follow the downstream C/I bits for CD1C, CD2C, and C3C.
CDAC: Debounced CD1C bit of channel X.
CDBC: The filtered CD2C bit of channel x in non-E1 demultiplexed mode or the filtered CD1BC bit in the E1 demultiplexed mode.
C3C–C3C of channel C.
In GCI mode, C4 and C5 are not available as upstream C/I data but can be obtained by reading the SLIC device I/O register.
Monitor Channel
The Monitor Channel (see Figure 28) is used to read and write the Le58083 Octal SLAC device’s coefficient registers, to read
the status of the device and the contents of the internal registers, and to provide supplementary signaling. Information is
transferred on the Monitor Channel using the MR and MX bits of the SC channel, providing a secure method of data exchange
between the upstream and downstream devices.
The Monitor byte is the third byte in the 4 byte GCI channel and is received every 125 µs over the DU or DD pins. A Monitor
command consists of one address byte, one or more command bytes, and is followed by additional bytes of input data as
required. The command may be followed by the Le58083 Octal SLAC device sending data bytes upstream via the DU pin.
Monitor Channel Protocol
Figure 28. Maximum Speed Monitor Handshake Timing
1st Byte
2nd Byte
3rd Byte
MX
Transmitter
EOM
MX
MR
Receiver
MR
ACK
1st Byte
ACK
2nd Byte
ACK
3rd Byte
125 µs
■ An inactive (high) MX and MR pair bit for two or more consecutive frames shows an idle state on the monitor channel
and the end of message (EOM).
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Le58083
Data Sheet
■ Figure 28 shows that transmission is initiated by the transition of the transmitter MX bit from the inactive to the
active state. The transition coincides with the beginning of the first byte sent on the monitor channel. The receiver
acknowledges the first byte by setting MR bit to active and keeping it active for at least one more frame.
■ The same data must be received in two consecutive frames in order to be accepted by the receiver.
■ The same byte is sent continuously in each of the succeeding frames until either a new byte is transmitted, the end
of message, or an abort.
■ Any false MX or MR bit received by the receiver or transmitter leads to a request for abort or an abort, respectively.
■ For maximum data transfer speed, the transmitter anticipates the falling edge of the receiver's acknowledgment, as
shown in Figure 28.
Figure 29 and Figure 30 are state diagrams that define the operation of the monitor transmitter and receiver sections in the
Le58083 Octal SLAC device.
Figure 29.
Monitor Transmitter Mode Diagram
Idle
MX=1
Initial
state
MR ⋅ RQT
1st byte
MX=0
MR ⋅ RQT
MR ⋅ RQT
MR
nth byte
ACK, MX=1
MR
MR ⋅ RQT
MR ⋅ RQT
wait for
ACK, MX=0
MR ... MR - bit received
MX ... MX - bit calculated and expected on the DU line
RQT ... Request for transmission from internal source
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
Figure 30. Monitor Receiver State Diagram
Idle
MR = 1
MX • LL
1st Byte
Received
MR = 0
MX
MX
Abort
MR = 1
ABT
MX
MX • LL
Byte
Valid
MR = 0
MX
Initial
State
Any
State
MX
MX
MX • LL
Wait for
LL MR = 0
MX • LL
MX
MX
MX • LL
MX • LL
nth Byte
Received
MR = 1
New Byte
MR = 1
MX
Wait for
LL MR = 0
21108A-033
MR: MR bit transmitted on DU line
MX: MX bit received on DD line
LL: Last look at monitor byte received
ABT: Abort indication from internal source
Programming with the Monitor Channel
The Le58083 Octal SLAC device uses the monitor channel for the transfer of status or mode information to and from higher level
processors.
The messages transmitted in the monitor channel have different data structures. The first byte of monitor channel data indicates
the address of the device either sending or receiving the data.
All Monitor channel messages to and from the Le58083 Octal SLAC device begin with the following address byte::
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
A
B
0
0
C
Address
A = 0; Channel 1 is the source (upstream) or destination (downstream)
A = 1; Channel 2 is the source (upstream) or destination (downstream)
B = 0; Data destination determined by A
B = 1; Both channels, 1 and 2, receive the data
C = 0; Address for channel identification command
C = 1; Address for all other commands
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Le58083
Data Sheet
The monitor channel address byte is followed by a command byte. If the command byte specifies a write, then from 1 to 14
additional data bytes may follow (see Table Table 9). If the control byte specifies a read, additional data bytes may follow. The
Le58083 Octal SLAC device responds to the read command by sending up to 14 data bytes upstream containing the information
requested by the upstream controller. Shown next is the generic byte transmission sequence over the GCI monitor channel.
Table 9.
Generic Byte Transmission Sequence
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, write
Data byte 1*
•
Data byte m*
ADDRESS
Control byte, read
Data byte 1
•
Data Byte n
n ≤ 14
m ≤ 14
Note:
* May or may not be present
Channel Identification Command (CIC)
When the monitor channel address byte is 80H or 90H, a command of 00H is interpreted by the Le58083 Octal SLAC device as
a two byte Channel Identification Command (CIC).
The format for this command is shown next.:
D7
D6
D5
D4
D3
D2
D1
D0
Address Byte
1
0
0
A
0
0
0
0
Command Byte
0
0
0
0
0
0
0
0
A=0
A=1
Channel 1 is the destination
Channel 2 is the destination
Immediately after the last bit of the CIC command is received, the Le58083 Octal SLAC device responds with the 2 byte
channel ID code:
D7
D6
D5
D4
D3
D2
D1
D0
Byte 1
1
0
0
A
CONF
CONF
CONF
CONF
Byte 2
DT
DT
0
0
0
1
1
0
A=0
A=1
CONF
DT
Channel 1 is the source
Channel 2 is the source
Configuration value is always 0000 for the Le58083 Octal SLAC device
Device Type value is always 1,0: Analog Transceiver. Other types are defined as:
D7
D6
0
0
U Transceiver
0
1
S Transceiver
1
0
Analog Transceiver
1
1
Future
Description
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
General Structure of Other Commands
When the Le58083 Octal SLAC device has completed transmission of the channel ID information, it sends an EOM (MX = 1 for
two successive frames) on the upstream C/I channel. The Le58083 Octal SLAC device also expects an EOM to be received on
the downstream C/I channel before any further message sequences are received.
When the monitor channel address byte is 81h, 89h, 91h, or 99h, the command byte is interpreted by the Le58083 Octal SLAC
device as either a Transfer Operation (TOP), Status Operation (SOP), or a Coefficient Operation (COP).
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
A
B
0
0
1
Address Byte
A = 0; Channel 1 is the destination
A = 1; Channel 2 is the destination
B = 0; Data destination determined by A
B = 1; Both channels 1 and 2 receive the data
Commands are sent to the Le58083 Octal SLAC device to:
■ Read the status of the system without changing its operation (Transfer Operation (TOP) command)
■ Write/read the Le58083 Octal SLAC device operating state (Status Operation (SOP) command)
■ Write/read filter coefficients (Coefficient Operation (COP) command).
SUMMARY OF MONITOR CHANNEL COMMANDS (GCI COMMANDS)
Commands
C#
Hex
Channel Information
Command
CIC
00h
Channel Identification Command (CIC); Requires unique address byte (80h, 90h)
Transfer Operation
Commands
TOP 1
73h
Read revision code number
SOP 1
00h
Deactivate channel
SOP 2
02h
Software Reset
SOP 3
04h
Hardware Reset
Status Operation
Commands
Coefficient Operation
Commands
Description
SOP 4
0Eh
SOP 5
70/71h
Write/Read Operating Conditions (Configuration Register 1, CR1)
Activate channel
SOP 6
46/47h
Write/Read Chip Configuration (Configuration Register 2, CR2)
SOP 7
60/61h
Write/Read Operating Functions (Configuration Register 3, CR3)
SOP 8
54/55h
Write/Read SLIC device I/O direction and Status Bits (Configuration Register 4, CR4)
SOP 9
4A/4Bh
Write/Read Operating Mode (Configuration Register 5, CR5)
SOP 10
53h
SOP 11
C8/C9h
Write/Read Debounce Time Register
SOP 12
E8/E9h
Write/Read Ground Key Filter Sampling Interval
SOP 13
4D/4Fh
Read Real-Time Data Register
SOP 14
6C/6Dh
Write/Read Interrupt Mask Register
COP 1
50/51h
Write/Read AISN & Analog gains
COP 2
80/81h
Write/Read GX Filter Coefficients
COP 3
82/83h
Write/Read GR Filter Coefficients
COP 4
98/99h
Write/Read Z Filter Coefficients (FIR)
COP 5
86/87h
Write/Read B1 Filter Coefficients (FIR)
Read SLIC device I/O Register
COP 6
88/89h
Write/Read X Filter Coefficients
COP 7
8A/8Bh
Write/Read R Filter Coefficients
COP 8
96/97h
Write/Read B2 Filter Coefficients (IIR)
COP 9
9A/9Bh
Write/Read Z Filter (IIR)
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
TOP (Transfer Operation) Command
The TOP (transfer operation) command, a GCI command, is used when no status modification of the Le58083 Octal SLAC device
is required. The byte transmission sequence for a TOP command is shown in Table Table 10.
Table 10.
Byte Transmission Sequence for TOP Command
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, TOP read
TOP Byte 1
•
•
TOP Byte n
n ≤ 14
TOP 1. Read Revision Code Number (RCN)
GCI Command
(73h)
Command
Output Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
1
RCN7
RCN6
RCN5
RCN4
RCN3
RCN2
RCN1
RCN0
The revision code of the Le58083 Octal SLAC device will be 14h or higher.
SOP (Status Operation) Command
To modify or evaluate the Le58083 Octal SLAC device status, the contents of configuration registers CR1–CR5 and the SLIC
device I/O register can be transferred to and from the Le58083 Octal SLAC device. This is done by a SOP (Status Operation)
command, which is a GCI command. The general transmission sequence of the SOP command is shown in Table Table 11.
Table 11.
General Transmission Sequence of SOP Command
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, SOP write
CR1
•
•
CRm
SOP Read
CR1
•
•
CRn
n≤8
m≤7
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Le58083
Data Sheet
SOP Control Byte Command Format
SOP 1. Deactivate Channel (Standby Mode)
GCI Command
(00h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
In the Deactivated (Standby) mode:
All of the programmed information is retained.
The upstream and downstream Monitor and SC channels remain active.
The B channel for an inactive channel is idle, no data is received or transmitted.
The analog output (VOUT) is disabled and biased at VREF.
The Channel Status (CSTAT bit in the SLIC device I/O and Status Bits register is set to 0.
SOP 2. Software Reset
GCI Command
(02h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
0
The action of this command is identical to that of the RST pin except it only operates on the addressed channel and does not
reset the ground key filtering interval.
SOP 3. Hardware Reset
GCI Command
(04h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
The Hardware reset command is equivalent to pulling the RST pin on a four-channel group of the device low. This command
resets all four channels of the device. The action of the Hardware reset function is described in Reset States on page 37.
SOP 4. Activate Channel (Operational Mode)
GCI Command
(0Eh)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
This command places the addressed channel of the device in the Active mode. No valid B-Channel data is transmitted until after
the second FSC pulse is received following the execution of the Activate command. The Channel Status (CSTAT) bit in the SLIC
device I/O and Status Bits register is set to 1.
SOP 5. Write/Read Configuration Register 1 (CR1), Operating Conditions
GCI Command
(70/71h)
Operating Conditions (Configuration Register 1, CR1)
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
0
R/W
CTP
CRP
HPF
LRG
ATI
ILB
FDL
TON
Configuration register CR1 enables or disables test features and controls feeding states. The reset value of CR1 = 04H
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Le58083
Cutoff Transmit Path
CTP = 0*
CTP = 1
Transmit path connected
Transmit path disconnected
Cutoff Receive Path**
CRP = 0*
CRP = 1
Receive path connected
Receive path cutoff
Data Sheet
High Pass Filter
HPF = 0*
HPF = 1
Transmit Highpass filter enabled
Transmit Highpass filter disabled
LRG = 0*
LRG = 1
6 dB loss not inserted
6 dB loss inserted
Lower Receive Gain
Arm Transmit Interrupt
ATI = 0*
ATI = 1
Transmit interrupt not armed
Transmit interrupt armed
Interface Loop Back
ILB = 0*
ILB = 1
Full Digital Loopback
FDL = 0*
FDL = 1
Interface (GCI) loopback disabled
Interface (GCI) loopback enabled
Full Digital Loopback disabled
Full Digital Loopback enabled
1 kHz Receive Tone
TON = 0*
TON = 1
1 kHz receive tone off
1 kHz receive tone on
Power Up and Hardware Reset (RST) Value = 00h
**B Filter is disabled during receive cutoff.
SOP 6. Write/Read Configuration Register 2 (CR2), Chip Configuration
GCI Command
(46/47h)
Chip Configuration (Configuration Register 2, CR2)
Command
I/O Data
Interrupt Mode (Global parameter)
INTM = 0
INTM = 1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
R/W
INTM
CHP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TTL-compatible output
Open drain output
Chopper Clock Control (Global parameter)
CHP = 0*
Chopper Clock is 256 kHz (2048/8 kHz)
CHP = 1
Chopper Clock is 292.57 kHz (2048/7 kHz)
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
* Power Up and Hardware Reset (RST) Value = 9Ah
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
SOP 7. Write/Read Configuration Register 3 (CR3), Operating Functions
GCI Command
(60/61h)
Operating Functions (Configuration Register 3, CR3)
Command
I/O Data
RSVD:
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
R/W
RSVD
A/µ
EGR
EGX
EX
ER
EZ
EB
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
A-law/µ-law
A/µ = 0*
A/µ = 1
A-law coding
µ-law coding
EGR = 0*
EGR = 1
GR filter default coefficients used:
GR filter programmed coefficients used
EGX = 0*
EGX = 1
GX filter default coefficients used
GX filter programmed coefficients used
EX = 0*
EX = 1
X filter default coefficients used
X filter programmed coefficients used
ER = 0*
ER = 1
R filter default coefficients used
R filter programmed coefficients used
EZ = 0*
EZ = 1
Z filter default coefficients used
Z filter programmed coefficients used
EB = 0*
EB = 1
B filter default coefficients used
B filter programmed coefficients used
GR filter
GX filter
X filter
R filter
Z filter
B filter
*Power Up and Hardware Reset (RST) Value = 00h
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Le58083
Data Sheet
SOP 8. Write/Read Configuration Register 4 (CR4), SLIC Device I/O Direction and Status Bits
GCI Command
(54/55h)
SLIC Device I/O Direction and Status Bits (Configuration Register 4, CR4)
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
R/W
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually.
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read only, write as 0)
CSTAT = 0
Channel is inactive (Standby mode)
CSTAT = 1
Channel is active
Clock Fail (Read only, write as 0; Global status bit)
CFAIL = 0
The internal clock is synchronized to frame sync
CFAIL = 1
The internal clock is not synchronized to frame sync
The CFAIL bit is universal for the Le58083 Octal SLAC device and is independent of the channel addressed.
IOD1–IOD5
Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins)
*0 = Pin is set as an input port
1 = Pin is set as an output port
*Power Up and Hardware Reset (RST) Value = 00h
SOP 9. Write/Read Configuration Register 5 (CR5), Operating Mode
GCI Command
(4A/4Bh)
Operating Mode (Configuration Register 5, CR5)
Command
I/O Data
RSVD:
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
R/W
VMODE
LPM
RSVD
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
VOUT Mode (Global parameter)
VMODE = 0*
VMODE = 1
VOUT = VREF through a resistor when channel is inactive
VOUT high impedance when channel is inactive.
Low Power Mode (Global parameter)
LPM
LPM reduced the power in the QSLAC device, but it is not needed and not used in the
Le58083 Octal SLAC device
Power Up and Hardware Reset (RST) Value = 0Fh
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Data Sheet
SOP 10. Read SLIC Device Input/Output Register
GCI Command
(53h)
Command
Output Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
1
C7
C6
CD1B
C5
C4
C3
CD2
CD1
The logic states present on the CD1, CD2, C3, C4, and C5 pins of the Le58083 Octal SLAC device for the addressed channel
are read using this command, independent of their programmed direction (see SLIC device I/O Direction Register). CD1B is the
multiplexed CD1 bit and is valid only if the E1 multiplexing mode is enabled (EE = 1). If CD1, CD2, C3, C4, and C5 are
programmed as inputs, then the logic states reported are determined by the external driving signal. In addition, CDA (the
debounced state of CD1) and CDB (the debounced state of CD2, non-E1 multiplexed mode) or CD1B (E1 multiplexed mode),
and the logic state present on the C3 pin of the device are sent directly upstream on the C/I bits of the upstream SC channel. If
the CD1, CD2, C3, C4, and C5 pins are programmed as outputs then the logic states of these pins are controlled directly by the
bits present in the C/I portion of the downstream SC channel and are not sent directly upstream in the SC channel. This command
is normally used only to read the bit status via Command 53h. It is also possible although not recommended, if the CD1, CD2,
and C3–C7 pins are programmed as outputs, to write the output state as Command 52h. The register is programmed upon
execution of Command 52h but the status is overwritten when the next C/I portion of the downstream SC channel is received.
SOP 11. Write/Read Debounce Time Register*
GCI Command
(C8/C9h)
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
0
0
R/W
EE1
E1P
DSH3
DSH2
DSH1
DSH0
RSVD
ECH
Enable E1 (Global parameter)
EE1 = 0*
EE1 = 1
E1 Multiplexing is turned off
E1 Multiplexing is turned on
E1 Polarity (Global parameter)
E1P = 0*
E1P = 1
E1 is a high-going pulse
E1 is a low-going pulse
Debounce for hook switch (Global parameter)
DSH = 0–15
Debounce period in ms
DSH contains the debouncing time in ms of the CD1 data (usually hook switch) entering the CD1B bit of the
read SLIC device Input/Output register and the CD1B transmitted on the C/I bit of the upstream SC channel. The input data on CD1 must remain stable for the debounce time in order for the state of CD1B to
change.
Default = 8 ms
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Enable Chopper (Global parameter)
ECH = 0*
ECH = 1
Chopper clock output is turned off.
Chopper clock output is turned on.
Power Up and Hardware Reset (RST) Value = 20h
Note:
* This command applies to all channels of the device.
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Data Sheet
SOP 12. Write/Read Ground Key Filter Sampling Interval
GCI Command
(E8/E9h)
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
0
0
R/W
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
GK0
Command
I/O Data
Filter Ground Key
GK = 0–15
Filter sampling period in ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the
upstream C/I channel described earlier.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Power Up and Hardware Reset (RST) Value = x0h.
SOP 13. Read Real-Time Data Register
GCI Command
(4D/4Fh)
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without closing the interrupt.
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
C
1
CDB4
CDA4
CDB3
CDA3
CDB2
CDA2
CDB1
CDA1
Real Time Data
CDA1
CDB1
CDA2
CDB2
CDB3
CDA3
CDB4
CDA4
Debounced data bit 1 on Channel 1
Data bit 2 or multiplexed data bit 1 on Channel 1
Debounced data bit 1 on Channel 2
Data bit 2 or multiplexed data bit 1 on Channel 2
Debounced data bit 1 on Channel 3
Data bit 1 on Channel 3
Debounced data bit 1 on Channel 4
Data bit 2 or multiplexed data bit 1 on Channel 4
This data is also available in the C/I field of the upstream SC channel.
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Data Sheet
SOP 14. Write/Read Interrupt Mask Register
GCI Command
(6C/6Dh)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
0
R/W
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
Mask CD Interrupt
MCDxC = 0
MCDxC = 1*
x
C
Masked
CDxC bit is NOT MASKED
CDxC bit is MASKED
Bit number (A or B)
Channel number (1 through 4)
A change does not cause the Interrupt Pin to go Low.
*Power Up and Hardware Reset (RST) Value = FFh
COP (Coefficient Operation) Command
The COP command, which is a GCI command, writes or reads data related to filter coefficients. Filter coefficient data is used by
the voice processors within the Le58083 Octal SLAC device to configure the various filters in the voice channel. In this case, 1
to 14 coefficient bytes follow the command byte. The Le58083 Octal SLAC device interprets the bytes as canonic signed digital
(CSD) data and sets the coefficients accordingly.
The Le58083 Octal SLAC device responds to the read coefficient command by sending up to 14 CSD bytes upstream. These
bytes contain the coefficients requested by the upstream controller. For diagnostic purposes, various RAM locations containing
data to which the Le58083 Octal SLAC device has access can also be read back by this command.
The generic transmission sequence for the COP command is shown in Table Table 12.
Table 12. Generic Transmission Sequence for COP Command
Downstream
Upstream
ADDRESS
Command byte, COP write
Data1
•
•
DataM
Control byte, COP read
Data1
•
•
DataN
n ≤ 14
m ≤ 14
The following tables show the format of the COP bytes that follow a downstream address byte.
D7
D6
D5
D4
D3
D2
D1
D0
Command
CMD
CMD
CMD
CMD
CMD
CMD
CMD
CMD
Data
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Data
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
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Data Sheet
The format in the upstream direction is the same except that the command byte is omitted.
Details of COP, CSD Data Commands
This section describes in detail each of the monitor channel COP commands. Each of the commands is shown along with the
format of any additional data bytes that follow. For details of the filter coefficients of the form CXYmXY, please refer to the
Description of Coefficients section on page 86.
COP 1. Write/Read AISN Coefficients and Analog Gains
GCI Command
(50/51h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
W/R
DGIN
AX
AR
AISN4
ASIN3
AISN2
AISN1
AISN0
Disable Input Attenuator (GIN)
DGIN = 0*
DGIN = 1
Input attenuator on
Input attenuator off
Transmit analog gain
AX = 0*:
AX = 1:
0 dB gain
6.02 dB gain
Receive Analog Loss
AR = 0*:
AR = 1:
0 dB loss
6.02 dB loss
AISN coefficient
AISN = 0*–31 See below (Default value = 0)
The Analog Impedance Scaling Network (AISN) gain can be varied from −0.9375 • GIN to +0.9375 • GIN in
multiples of 0.0625 • GIN. The gain coefficient is decoded using the following equation:
h AISN = 0.0625 • GIN [ ( 16 • AISN4 + 8 • AISN3 + 4 • AISN2 + 2 • AISN1 + AISN0 ) – 16 ]
where hAISN is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode.
* Power Up and Hardware Reset (RST) Value = 00h
COP 2. Write/Read GX Filter Coefficients
GCI Command
(80/81h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
W/R
Coefficient Byte 1
C40
m40
C30
m30
Coefficient Byte 2
C20
m20
C10
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
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Data Sheet
The coefficient for the GX filter is defined as:
H GX = ( 1 + ( C10 • 2
– m10
( 1 + C20 • 2
– m20
( 1 + C30 • 2
– m30
( 1 + C40 • 2
– m40
)))))
Power Up and Hardware Reset (RST) Value = A9F0h, (HGX = 1.995, or +6 dB)
Note:
The default value is contained in a ROM register separate from the programmable coefficient RAM. There is a filter enable bit in Operating Functions Register to switch between the default and programmed values.
COP 3. Write/Read GR Filter Coefficients
GCI Command
(82/83h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
1
W/R
Coefficient Byte 1
C40
m40
C30
m30
Coefficient Byte 2
C20
m20
C10
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GR filter is defined as:
H GR = ( C10 • 2
– m10
( 1 + C20 • 2
– m20
( 1 + C30 • 2
– m30
( 1 + C40 • 2
– m40
))))
Power Up and Hardware Reset (RST) Value = 23A1h, (HGR = 0.35547, or –8.984 dB)
See note under COP Command 2.
COP 4. Write/Read Z Filter FIR Coefficients
GCI Command
(98/99h)
R/W = 1: Read
R/W = 0: Write
This command writes and reads only the FIR portion of the Z filter without affecting the IIR.
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
I/O Data Byte 3
C41
m41
C31
m31
I/O Data Byte 4
C21
m21
C11
m11
I/O Data Byte 5
C42
m42
C32
m32
I/O Data Byte 6
C22
m22
C12
m12
I/O Data Byte 7
C43
m43
C33
m33
I/O Data Byte 8
C23
m23
C13
m13
I/O Data Byte 9
C44
m44
C34
m34
I/O Data Byte 10
C24
m24
C14
m14
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
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Data Sheet
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z5 • z6 • z7 • z
+ -----------------------------------------1 – z7 • z
–1
Sample rate = 32 kHz
For i = 0–5 and 7
z i = C1i • 2
z 6 = C16 • 2
– m1i
{ 1 + C2i • 2
– m16
– m2i
{ 1 + C26 • 2
[ 1 + C3i • 2
– m26
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(HZ(z) = 0)
See note under COP Command 2 on page 80.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also
includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
COP 5. Write/Read B1 Filter Coefficients (B-FIR)
GCI Command
(86/87h)
R/W = 1: Read
R/W = 0: Write
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
1
R/W
I/O Data Byte 1
C32
m32
C22
m22
I/O Data Byte 2
C12
m12
C33
m33
I/O Data Byte 3
C23
m23
C13
m13
I/O Data Byte 4
C34
m34
C24
m24
I/O Data Byte 5
C14
m14
C35
m35
I/O Data Byte 6
C25
m25
C15
m15
I/O Data Byte 7
C36
m36
C26
m26
I/O Data Byte 8
C16
m16
C37
m37
I/O Data Byte 9
C27
m27
C17
m17
I/O Data Byte 10
C38
m38
C28
m28
I/O Data Byte 11
C18
m18
C39
m39
I/O Data Byte 12
C29
m29
C19
m19
I/O Data Byte 13
C310
m310
C210
m210
I/O Data Byte 14
C110
m110
RSVD
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the B filter is defined as:
HB ( z ) = B2 • z
–2
+ … + B9 • z
–9
– 10
B 10 • z
+ -----------------------------1 – B 11 • z
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Le58083
Data Sheet
Sample rate = 16 kHz
The coefficients for the FIR B section and the gain of the IIR B section are defined as:
B i = C1i • 2
For i = 2 to 10,
– m1i
[ 1 + C2i • 2
– m2i
( 1 + C3i • 2
– m3i
)]
The feedback coefficient of the IIR B section is defined as:
B 11 = C111 • 2
– m111
{ 1 + C211 • 2
– m211
[ 1 + C311 • 2
– m311
( 1 + C411 • 2
– m411
)]}
Refer to Command COP8 for programming the B11 coefficients.
Power Up and Hardware Reset (RST) Values = 09 00 90 09 00 90 09 00 90 09 00 90 09 00 (Hex)
HB ( z ) = 0
RSVD:
Reserved for future use. Reset to 0. Always write as 0, but 0 is not guaranteed when read.
See note under COP Command 2 on page 80.
COP 6. Write/Read X Filter Coefficients
GCI Command
(88/89h)
R/W = 1: Read
R/W = 0: Write
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
W/R
Coefficient Byte 1
C40
m40
C30
m30
Coefficient Byte 2
C20
m20
C10
m10
Coefficient Byte 3
C41
m41
C31
m31
Coefficient Byte 4
C21
m21
C11
m11
Coefficient Byte 5
C42
m42
C32
m32
Coefficient Byte 6
C22
m22
C12
m12
Coefficient Byte 7
C43
m43
C33
m33
Coefficient Byte 8
C23
m23
C13
m13
Coefficient Byte 9
C44
m44
C34
m34
Coefficient Byte 10
C24
m24
C14
m14
Coefficient Byte 11
C45
m45
C35
m35
Coefficient Byte 12
C25
m25
C15
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the X filter is defined as:
Hx ( z ) = X0 + X1 z
–1
+ X2 z
–2
+ X3 z
–3
+ X4 z
–4
+ X5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the X filter are defined as:
Xi = C1i • 2
– m1i
( 1 + C2i • 2
– m2i
( 1 + C3i • 2
– m3i
( 1 + C4i • 2
Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190h
HX(z) = 1
See note under COP Command 2 on page 80.
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– m4i
)))
Le58083
Data Sheet
COP 7. Write/Read R Filter Coefficients
GCI Command
(8A/8Bh)
R/W = 1: Read
R/W = 0: Write
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
1
W/R
Coefficient Byte 1
C46
m46
C36
m36
Coefficient Byte 2
C26
m26
C16
m16
Coefficient Byte 3
C40
m40
C30
m30
Coefficient Byte 4
C20
m20
C10
m10
Coefficient Byte 5
C41
m41
C31
m31
Coefficient Byte 6
C21
m21
C11
m11
Coefficient Byte 7
C42
m42
C32
m32
Coefficient Byte 8
C22
m22
C12
m12
Coefficient Byte 9
C43
m43
C33
m33
Coefficient Byte 10
C23
C23
C13
m13
Coefficient Byte 11
C44
m44
C34
m34
Coefficient Byte 12
C24
m24
C14
m14
Coefficient Byte 13
C45
m45
C35
m35
Coefficient Byte 14
C25
m25
C15
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
HR = H IIR • H FIR
The Z-transform equation for the IIR filter is defined as:
–1
1–z
H IIR = ---------------------------------– 1

1 – R6 • z


Sample rate = 8 kHz
The coefficient for the IIR filter is defined as:
R 6 = C16 • 2
– ml6
{ 1 + C26 • 2
– m26
[ 1 + C36 • 2
– m36
( 1 + C46 • 2
– m46
)]}
The Z-transform equation for the FIR filter is defined as:
H FIR ( z ) = R 0 + R 1 z
–1
+ R2 z
–2
+ R3 z
–3
+ R4 z
–4
+ R5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the R2 filter are defined as:
R i = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex)
(HFIR (z) = 1, R6 = 0.9902)
See note under COP Command 2 on page 80.
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Le58083
Data Sheet
COP 8. Write/Read B2 Filter Coefficients (B-IIR)
GCI Command
(96/97h)
R/W = 1: Read
R/W = 0: Write
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
1
1
W/R
Coefficient Byte 1
C411
m411
C311
m311
Coefficient Byte 2
C211
m211
C111
m111
This function is described in Write/Read B1 Filter Coefficients on page 82.
Power Up and Hardware Reset (RST) Value = 0190h
(B11 = 0)
COP 9. Write/Read IIR Z Filter Coefficients
GCI Command
(9A/9B)
R/W = 0: Write
R/W = 1: Read
This command writes and reads only the IIR portion of the Z filter without affecting the FIR.
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
1
R/W
I/O Data Byte 1
C45
m45
C35
m35
I/O Data Byte 2
C25
m25
C15
m15
I/O Data Byte 3
C26
m26
C16
m16
I/O Data Byte 4
C47
m47
C37
m37
I/O Data Byte 5
C27
m27
C17
m17
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z5 • z6 • z7 • z
+ -----------------------------------------1 – z7 • z
–1
Sample rate = 32 kHz
For i = 0–5 and 7
z i = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
z 6 = C16 • 2
[ 1 + C3i • 2
– m16
– m3i
{ 1 + C26 • 2
( 1 + C4i • 2
– m26
– m4i
)] }
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(HZ(z) = 0)
See note under COP Command 2 on page 80.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also
includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
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Data Sheet
PROGRAMMABLE FILTERS
General Description of CSD Coefficients
The filter functions are performed by a series of multiplications and accumulations. A multiplication occurs by repeatedly shifting
the multiplicand and summing the result with the previous value at that summation node. The method used in the Le58083 Octal
SLAC device is known as Canonic Signed Digit (CSD) multiplication and splits each coefficient into a series of CSD coefficients.
Each programmable FIR filter section has the following general transfer function:
HF ( z ) = h 0 + h 1 z
–1
+ h2 z
–2
+ … + hn z
–n
Equation 1
where the number of taps in the filter = n + 1.
The transfer function for the IIR part of Z and B filters:
1
HI ( z ) = ---------------------------------1 – h( n + 1 ) z
Equation 2
–1
The transfer function of the IIR part of the R filter is:
–1
1–z
HI ( z ) = ---------------------------------1 – h( n + 1 ) z
Equation 3
–1
The values of the user-defined coefficients (hi) are assigned via the MPI. Each of the coefficients (hi) is defined in the following
general equation:
hi = B1 2
– M1
+ B2 2
– M2
+ … + BN 2
– MN
Equation 4
where:
Mi = the number of shifts = Mi ≤ Mi + 1
Bi = sign = ±1
N = number of CSD coefficients.
The value of hi in Equation 4 represents a decimal number, broken down into a sum of successive values of:
1)±1.0 multiplied by 2–0, or 2–1, or 2–2 … 2–7 …
2)±1.0 multiplied by 1, or 1/2, or 1/4 … 1/128 …
The limit on the negative powers of 2 is determined by the length of the registers in the ALU.
The coefficient hi in Equation 4 is a value made up of N binary 1s in a binary register where the left part represents whole numbers,
the right part decimal fractions, and a decimal point separates them. The first binary 1 is shifted M1 bits to the right of the decimal
point; the second binary 1 is shifted M2 bits to the right of the decimal point; the third binary 1 is shifted M3 bits to the right of the
decimal point, and so on.
When M1 is 0, the value is a binary 1 in front of the decimal point, that is, no shift. If M2 is also 0, the result is another binary 1 in
front of the decimal point, giving a total value of binary 10 in front of the decimal point (i.e., a decimal value of 2.0). The value of
N, therefore, determines the range of values the coefficient hi can take (e.g., if N = 3 the maximum and minimum values are ±3,
and if N = 4 the values are between ±4).
Detailed Description of Le58083 Octal SLAC Device Coefficients
The CSD coding scheme in the Le58083 Octal SLAC device uses a value called mi, where m1 represents the distance shifted
right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary 1, and m3
represents the number of shifts to the right of the second binary 1. Note that the range of values determined by N is unchanged.
Equation 4 is now modified (in the case of N = 4) to:
hi = B1 2
– m1
h i = C1 • 2
+ B2 2
– m2
+ B3 2
– m3
– m1
+ C1 • C 2 • 2
– m1
{ 1 + C2 • 2
+ B4 2
– ( m1 + m2 )
– m4
Equation 5
+ C1 • C 2 • C 3 • 2
– ( m1 + m2 + m3 )
+ C1 • C2 • C3 • C4 • 2
Equation 6
h i = C1 • 2
– m2
[ 1 + C3 • 2
– m3
( 1 + C4 • 2
– m4
) ] } Equation 7
where:
M1 = m1B1 = C1
M2 = m1 + m2B2 = C1 • C2
M3 = m1 + m2 + m3B3 = C1 • C2 • C3
M4 = m1 + m2 + m3 + m4B4 = C1 • C2 • C3 • C4
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Zarlink Semiconductor Inc.
– ( m1 + m2 + m3 + m4 )
Le58083
Data Sheet
In the Le58083 Octal SLAC device, a coefficient, hi, consists of N CSD coefficients, each being made up of 4 bits and formatted
as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows:
Cxyis the sign bit (0 = positive, 1 = negative).
mxyis the 3-bit shift code. It is encoded as a binary
number as follows:
000:0 shifts
001:1 shifts
010:2 shifts
011:3 shifts
100:4 shifts
101:5 shifts
110:6 shifts
111:7 shifts
yis the coefficient number (the i in hi).
x is the position of this CSD coefficient within the hi coefficient. The most significant binary 1 is represented by x = 1. The
next most significant binary 1 is represented by x = 2, and so on.
Thus, C13 m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h3) coefficient.
The number of CSD coefficients, N, is limited to 4 in the GR, GX, R, X, and Z filters; 4 in the IIR part of the B filter; 3 in the FIR
part of the B filter; and 2 in the post-gain factor of the Z-IIR filter. The GX filter coefficient equation is slightly different from the
other filters.
h iGX = 1 + h i Equation 8
Please refer to Summary of MPI Commands on page 45 for complete details on programming the coefficients.
User Test States and Operating Conditions
The Le58083 Octal SLAC device supports testing by providing test states and special operating conditions as shown in Figure
23 (see Operating Conditions register).
Cutoff Transmit Path (CTP): When CTP = 1, DX and TSC are High impedance and the transmit time slot does not exist. This
state takes precedence over the TSA Loopback (TLB) and Full Digital Loopback (FDL) states.
Cutoff Receive Path (CRP): When CRP = 1, the receive signal is forced to 0 just ahead of the low pass filter (LPF) block. This
state also blocks Full Digital Loopback (FDL), the 1 kHz receive tone, and the B-filter path.
High Pass Filter Disable (HPF): When HPF = 1, all of the High pass and notch filters in the transmit path are disabled.
Lower Receive Gain (LRG): When LRG = 1, an extra 6.02 dB of loss is inserted into the receive path.
Arm Transmit Interrupt (ATI) and Read Transmit PCM Data (PCM/MPI mode only): The read transmit PCM data command,
Command CDh, can be used to read transmit PCM data through the microprocessor interface. If the ATI bit is set, an interrupt
will be generated whenever new transmit data appears in the channel and will be cleared when the data is read. When combined
with Tone Generation and Loopback states, this allows the microprocessor to test channel integrity.
Interface Loopback (ILB): When ILB = 1, data from the receive/downstream path is looped back to the transmit/Upstream path.
Any other data in the transmit path is overwritten.
Full Digital Loopback (FDL): When FDL = 1, the VOUT output is turned off and the analog output voltage is routed to the input
of the transmit path, replacing the voltage from VIN. The AISN path is temporarily turned off. This test mode can also be entered
by writing the code 10000 into the AISN register.
1 kHz Receive Tone (TON): When TON = 1, a 1 kHz digital mW is injected into the receive path, replacing any receive or
downstream signal.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
A-Law and µ-Law Companding
Table Table 13 and Table Table 14 show the companding definitions used for A-law and µ-law PCM encoding.
Table 13.
A-Law: Positive Input Values
1
Segment
Number
2
3
4
# Intervals Value at
x Interval
Segment
Size
End Points
Decision
Value
Number n
5
6
7
Character
Signal pre
Quantized
Decision Inversion of
Value (at
Even
Bits
Value xN
Decoder
(See Note 1)
Output) yN
Bit No.
8
Decoder
Output
Value No.
12345678
4096
7
(128)
(4096)
127
3968
113
2176
112
2048
11111111
16 x 128
4032
128
2112
113
1056
97
528
81
264
65
132
49
66
33
1
1
See Note 2
2048
11110000
See Note 2
6
16 x 64
1024
97
1088
96
1024
11100000
See Note 2
5
16 x 32
512
81
544
80
512
11010000
See Note 2
4
16 x 16
256
65
272
64
256
11000000
See Note 2
3
16 x 8
128
49
136
48
128
10110000
See Note 2
2
16 x 4
64
33
68
32
64
10100000
See Note 2
1
32 x 2
1
2
0
0
10000000
Notes:
1.
4096 normalized value units correspond to TMAX = 3.14 dBm0.
2.
The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character signal
corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4) is 128+n, expressed
as a binary number.
3.
n–1
n
- , for n = 1,...127, 128.
The value at the decoder output is y n = ------------------------
4.
x128 is a virtual decision value.
5.
Bit 1 is a 0 for negative input values.
x
+x
2
88
Zarlink Semiconductor Inc.
Le58083
Table 14.
1
Segment
Number
Data Sheet
µ-Law: Positive Input Values
2
3
# Intervals Value at
x Interval
Segment
Size
End Points
4
5
Decision
Value
Number n
6
7
Character
Signal pre
Quantized
Decision Inversion of
Value (at
Even
Bits
Value xN
Decoder
(See Note 1)
Output) yN
Bit No.
8
Decoder
Output
Value No.
12345678
8159
8
(128)
(8159)
127
7903
113
4319
112
4063
10000000
8031
127
4191
112
2079
96
1023
80
495
64
231
48
99
32
33
16
11111110
2
1
11111111
0
0
16 x 256
See Note 2
4063
10001111
See Note 2
7
16 x 128
2015
97
2143
96
2015
10011111
See Note 2
6
16 x 64
991
81
1055
80
991
10101111
See Note 2
5
16 x 32
479
65
511
64
479
10111111
See Note 2
4
16 x 16
223
49
239
48
223
11001111
See Note 2
3
16 x 8
95
33
103
32
95
11011111
See Note 2
2
16 x 4
31
17
35
16
31
11101111
See Note 2
1
15 x 2
1x1
2
3
1
1
0
0
Notes:
1.
8159 normalized value units correspond to TMAX = 3.17 dBm0.
2.
The character signal corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4)
is 255-n, expressed as a binary number.
3.
The value at the decoder is y0 = x0 = 0 for n = 0, and y n = ------------------------- , for n = 1, 2,...127.
2
4.
5.
xn + 1 + xn
x128 is a virtual decision value.
Bit 1 is a 0 for negative input values.
89
Zarlink Semiconductor Inc.
Le58083
Data Sheet
APPLICATIONS
The Le58083 Octal SLAC device performs a programmable codec/filter function for eight telephone lines. It interfaces to the
telephone lines through a Zarlink SLIC device or a transformer with external buffering. The Le58083 Octal SLAC device provides
latched digital
I/O to control and monitor eight SLIC devices and provides access to time-critical information, such as off/on-hook and ring trip,
for four channels via a single read operation or via the upstream C/I bits in the GCI SC channel. When various country or
transmission requirements must be met, the Le58083 Octal SLAC device enables a single SLIC device design for multiple
applications. The line characteristics (such as apparent impedance, attenuation, and hybrid balance) can be modified by
programming each Le58083 Octal SLAC device channel’s coefficients to meet desired performance. The Le58083 Octal SLAC
device may require an external buffer to drive transformer SLIC devices.
In PCM/MPI mode, connection to a PCM back plane is implemented by means of a simple buffer chip. Several Le58083 Octal
SLAC devices can be tied together in one bus interfacing the back plane through a single buffer. An intelligent bus interface chip
is not required because each Le58083 Octal SLAC device provides its own buffer control (TSCA/TSCB). The Le58083 Octal SLAC
device is controlled through the microprocessor interface, either by a microprocessor on the line card or by a central processor.
In GCI mode, the Le58083 Octal SLAC device decodes the S0 and S1 inputs and determines the DCL frequency, 2.048 MHz or
4.096 MHz automatically. The Le58083 Octal SLAC device transmits and receives the GCI channel information in accordance
with S0, S1 and DCL, synchronized by Frame Sync. (FSC). Up to two Le58083 Octal SLAC devices can be bussed together
forming one bidirectional 16 channel GCI bus. A simple inexpensive buffer should be used between the GCI bus and the
backplane of the system.
Controlling the SLIC Device
The Le58083 Octal SLAC device has five TTL-compatible I/O pins (CD1, CD2, C3, C4 and C5) and two output only pins (C6 and
C7) for each channel. The outputs are programmed using MPI Command 52h or the downstream C/I bits in the GCI SC channel.
The logic states are read back using MPI Command 53h or GCI Command SOP 10. In GCI mode CD1 (debounced), CD2, and
C3 are also present on the upstream C/I bits in the GCI SC channel. In PCM/MPI mode, CD1 and CD2 for all channels can be
read back using MPI Command 4D/4Fh. The direction of the I/O pins (input or output) is specified by programming the SLIC
device I/O direction register (MPI Command 54/55h, GCI Command SOP 8).
Calculating Coefficients with WinSLAC Software
The WinSLAC software is a program that models the Le58083 Octal SLAC device, the line conditions, the SLIC device, and the
line card components to obtain the coefficients of the programmable filters of the Le58083 Octal SLAC device and some of the
transmission performance plots.
The following parameters relating to the desired line conditions and the components/circuits used in the line card are to be
provided as input to the program:
1.
2.
3.
4.
5.
6.
7.
Line impedance or the balance impedance of the line is specified by the local telephone system.
Desired two-wire impedance that is to appear at the line card terminals of the exchange.
Tabular data for templates describing the frequency response and attenuation distortion of the design.
Relative analog signal levels for both the transmit and receive two-wire signals.
Component values and SLIC device selection for the analog portion of the line circuits.
Two-wire return loss template is usually specified by the local telephone system.
Four-wire return loss template is usually specified by the local telephone system.
The output from the WinSLAC program includes the coefficients of the GR, GX, Z, R, X, and B filters as well as transmission
performance plots of two-wire return loss, receive and transmit path frequency responses, and four-wire return loss.
The software supports the use of the Zarlink SLIC devices or allows entry of a SPICE netlist describing the behavior of any type
of SLIC device circuit.
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Zarlink Semiconductor Inc.
R50
R50
U3
RF2B R50
U4
RF2A R50
BAT
RF1B
RF1A
D1
2.2nF
2.2nF
C20
C19
DAC
B2
Note 2
100nF
C17
HP2
A2
TMG2
VBAT
TMG1
B1
DB2
2.2nF
2.2nF
1.6K
100nF
C16
HP1
A1
DB1
Note 2
R11
R10 1.6K
C18
C10
Note 2
Notes:
1. Two of eight channels shown.
2. Ring-trip circuitry not shown.
RING2
TIP2
RING1
TIP1
U2
5V
VCC
R5
15K
Dual SLIC
Le57D11
C9 .1uF
CD22_1
CD12_1
VOUT2_1
100nF
1.5uF
91
C15
C14
Zarlink Semiconductor Inc.
C11
330nF
CDC2
.1uF
C3
.1uF
C4
MCLK/E1_1
MCLK/E1_2
PCLK/DCL
FS/FSC
DXA/DU
DRA/DD
DIO/S1_1
DIO/S1_2
DCLK/S0_1
DCLK/S0_2
RST
CS/PG_1
CS/PG_2
Octal SLAC
VIN2_1
C52_1
C7 .1uF
C8 .1uF
C1
.1uF
VCCD
MCLK/E1_1
MCLK/E1_2
PCLK/DCL
FS/FSC
DXA/DU
VOUT1_1
DRA/DD
TSCA
DIO/S1_1
CD11_1
DIO/S1_2
CD21_1
DCLK/S0_1
DCLK/S0_2
C41_1
CS/PG_1
CS/PG_2
RST
C51_1
Le58083 INT_1
INT_2
VIN1_1
C2
C22
124K
124K
C6 .1uF
C5 .1uF
U1
C42_1
R2
R4
82.5K
R1
R3
82.5K
100nF
1.5uF
C12
CFLT2
DET2
RSN2
VTX2
CDC1
C21
C11
CFLT1
DET1
RSN1
VTX1
C13
C12
.1uF
Le57D11 SLIC/Le58083 Octal SLAC™ Application Circuit
AGND
Figure 31.
AGND
APPLICATION CIRCUIT
IREF
VCCA
VREF_1
BGND
Le58083
CAS
DGND
VREF_2
AGND
E1_1
E1_2
DCL
FSC
DU
DD
S1_1
S1_2
S0_1
S0_2
RST
DGND
GCI Mode
MCLK_1
MCLK_2
PCLK
FS
DXA
DRA
TSCA
DIO_1
DIO_2
DCLK_1
DCLK_2
CS_1
CS_2
RST
INT_1
INT_2
PCM/MPI
Mode
3.3V
Data Sheet
Le58083
Data Sheet
LINE CARD PARTS LIST
The following list defines the parts and part values, between the Le58083 Octal SLAC and Le57D11 Dual SLIC devices, required
to meet target specification limits for two channels.
Item
Quantity
Value
Tol.
Rating
C2
3
Capacitor
Type
0.1 µF
20%
10 V
Bypass capacitor
Comments
C1
3
Capacitor
0.1 µF
20%
10 V
Bypass capacitor
C3, C4
2
Capacitor
0.1 µF
20%
10 V
Bypass capacitor
C5, C8
2
Capacitor
0.1 µF
20%
10 V
Coupling capacitor
R1, R2
2
Resistor
124 kΩ
1%
0.01 W
C6, C7
2
Capacitor
0.1 µF
20%
10 V
R3, R4
2
Resistor
82.5K kΩ
1%
0.01 W
RFA
1
Fuse resistor
50 Ω
RFB
1
Fuse resistor
50 Ω
See Note
Note:
For all other components, please refer to the Le57D11 Data Sheet, document ID#080676.
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Zarlink Semiconductor Inc.
Coupling capacitor
Le58083
Data Sheet
PHYSICAL DIMENSIONS
LFBGA (121 Balls)
Symbol
A
A1
A2
A3
b
D
E
e
D1
E1
Min
0.30
121 BGA
Max
1.40
0.40
0.26 REF
0.70 REF
0.35
0.45
10 BSC
10 BSC
0.8 BSC
8 BSC
8 BSC
NOTES:
1
Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z.
2
Datum Z is defined by the spherical crowns of the solder balls.
3
Parallelism measurement shall exclude any effect of mark on top surface of package.
UNIT
DIMENSION AND
TOLERANCES
MM
ASME_Y14.5M
REFERENCE DOCUMENT
M0-219-B
121-Lead LFBGA
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Zarlink Semiconductor Inc.
Le58083
Data Sheet
REVISION HISTORY
Revision A to B
•
In Transmission Characteristics, Second Harmonic Distortion, changed GX=0 to GR=0; added D-A in Description field
Revision B to C
•
•
•
•
•
•
•
•
•
•
•
•
•
Clarified device description on page 6
Modified 121-pin BGA connection diagram and Pin Names table
Modified Pin Descriptions table
Added a maximum VCC current limit of 1.0 A to the Absolute Maximum Ratings if the rise rate of VCC is greater than
0.4 V/µs
Changed VREF to VREF_X throughout document
The following changes were made to the Electrical Characteristics table:
– Reduced the leakage spec to ±7 µA
– Added note 6 to IL, IOL, CI, and CO and doubled the values for pins connected to both channel groups
– Power Dissipation, one channel active: changed the Typ and Max values to 55 and 100, respectively
– Power Dissipation, all channels inactive: changed the Typ and Max values to 26 and 36, respectively
– Added note 6, and doubled the leakage and capacitance spec for pins connected to both channel groups
Modified power-up sequence
In E1 Multiplex Operation, added text noting that if EE1 is reset, E1 is an input and should be grounded if not used as a
clock
In Reset States, #16, added "E1 is Hi-Z"
In Command Field Summary, modified text before tables 6 and 7; modified table 6
Modified parameter descriptions in the following commands: 44/45h, 46/47h, C8/C9h
Required the XE, RCS, TCS, SMODE, CMODE, CSEL, and DPCK fields be the same in both four channel groups.
Made the application circuit fit the page.
Revision C1 to D1
•
•
•
Changed standard package OPN from Le58083GC to Le58083AGC
Added green package OPN
Added Package Assembly, on page 12
Revision D1 to E1
•
Removed standard (non-green) OPN from Ordering Information, on page 1
Revision E1 to E2
•
•
Enhanced format of package drawing in Physical Dimensions, on page 93
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
94
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE