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ZL50020
Enhanced 2 K Digital Switch
Data Sheet
Features
•
November 2006
2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048, 4.096,
8.192 and 16.384 Mbps
O rdering Information
ZL50020GAC
ZL50020QCC
ZL50020QCG1
256 Ball PBGA
256 Lead LQFP
256 Lead LQFP*
ZL50020GAG2
256 Ball PBGA**
Trays
Trays
Trays, Bake &
Drypack
Trays, Bake &
Drypack
•
32 serial TDM input, 32 serial TDM output
streams
•
Output streams can be configured as bidirectional for connection to backplanes
•
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
•
Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
•
Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
•
Four frame pulse and four reference clock outputs
•
Three programmable delayed frame pulse outputs
•
Per-stream high impedance control outputs
(STOHZ) for 16 output streams
•
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
•
Per-stream input bit delay with flexible sampling
point selection
•
Input frame pulses:61 ns, 122 ns, 244 ns
•
•
Per-stream output bit and fractional bit
advancement
Per-channel constant or variable throughput delay
for frame integrity and low latency applications
•
Per Stream (32) Bit Error Rate Test circuits
complying to ITU-O.151
VDD_CORE
VDD_COREA
VDD_IOA
S/P Converter
VSS
RESET
ODE
P/S Converter
Data Memory
STio[31:0]
Output HiZ
Control
Input Timing
STOHZ[15:0]
Connection Memory
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Output Timing
Internal Registers &
Microprocessor Interface
TRST
TCK
TDo
TDi
TMS
D[15:0]
A[13:0]
R/W_WR
DTA_RDY
DS_RD
Test Port
CS
FPi
CKi
MODE_4M0
MODE_4M1
-40°C to +85°C
MOT_INTEL
STi[31:0]
VDD_IO
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
Figure 1 - ZL50020 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50020
•
Per-channel high impedance output control
•
Per-channel message mode
•
Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
•
Connection memory block programming
•
Supports ST-BUS and GCI-Bus standards for input and output timing
•
IEEE-1149.1 (JTAG) test port
•
3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Data Sheet
Applications
•
PBX and IP-PBX
•
Small and medium digital switching platforms
•
Remote access servers and concentrators
•
Wireless base stations and controllers
•
Multi service access platforms
•
Digital Loop Carriers
•
Computer Telephony Integration
Description
The ZL50020 is a maximum 2048 x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has
thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be
independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or
16.384 Mbps. The ZL50020 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the
use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be
configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored.
The device contains two types of internal memory - data memory and connection memory. There are four modes of
operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the
contents of the connection memory define, for each output stream and channel, the source stream and channel
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with
a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the
input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.
The configurable non-multiplexed microprocessor port allows users to program various device operating modes
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection
memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or
Intel-type microprocessors.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.0 Device Operation in Divided Clock and Multiplied Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1 Divided Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.2 Multiplied Clock Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.3 Output Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14.0 Pseudo Random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.0 PCM A-law/m-law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16.0 Quadrant Frame Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
19.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
21.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Table of Contents
22.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
List of Figures
Figure 1 - ZL50020 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 8
Figure 3 - ZL50020 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 33 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 34 - Output Drive Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 37 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 38 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39 - FPo3 and CKo3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
List of Tables
Table 1 - CKi and FPi Configurations for Divided Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2 - CKi and FPi Configurations for Multiplied Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - ZL50020 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11 - Quadrant Frame Bit Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 18 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 19 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 22 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 23 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 25 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Changes Summary
The following table captures the changes from January 2006 to November 2006.
Page
Item
Change
1
Updated Ordering Information.
The following table captures the changes from the October 2004 issue.
Page
Item
Change
13
Pin Description “CKi” on page 13
•
Clarified pin description for CKi.
32
11.3, “Output Clock Frequencies“
•
Added new section to describe output clock
frequencies.
7
Zarlink Semiconductor Inc.
ZL50020
1.0
Pinout Diagrams
1.1
BGA Pinout
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
STi29
STi28
STi27
STi25
STi26
STi24
NC
NC
STio22
STio23
STio21
STio20
NC
NC
VSS
A
B
STi31
STi10
STi5
STi4
CKo2
STi0
CKo0
NC
VDD_
COREA
FPi
CKi
ODE
STio19
B
C STi30
STi9
VSS
STi7
STi6
STi1
CKo1
NC
VSS
IC_Open
VSS
STio15
STio18
C
D STi17
STi11
VDD_IO
STi3
STi2
NC
NC
NC
NC
VSS
FPo_
OFF1
IC_GND
STio13
VDD_IO
STio14
STio16
D
E
STi16
STi14
STi8
VDD_IO
VSS
VDD_
CORE
NC
NC
NC
NC
VDD_
CORE
VSS
VDD_IO
STio12
FPo2
STio17
E
F
STi19
STi15
STi12
STi13
VDD_IO
VDD_
CORE
VDD_
CORE
VSS
VSS
VDD_
CORE
VDD_
CORE
VDD_IO
IC
FPo3
FPo_
OFF2
STOHZ15 F
TDo
VDD_IO
VSS
VSS
VSS
VSS
VDD_IO
A12
A13
FPo1
FPo0
STOHZ14 G
IC_Open
IC_Open IC_Open IC_GND
IC_Open IC_GND
G STi18
RESET
H STi21
VSS
VSS
VDD_
COREA
NC
VSS
VSS
VSS
VSS
VSS
A7
A9
A10
FPo_
OFF0
A11
STOHZ12 H
IC_GND IC_Open
J
STi20
VDD_IOA
VDD_IOA
VSS
VSS
CKo3
VSS
VSS
VSS
VSS
A3
A4
A5
A8
A6
STOHZ13 J
K
STi22
VSS
TMS
VSS
VDD_
COREA
VDD_IO
VSS
VSS
VSS
VSS
VDD_IO
IC_Open
A0
A2
A1
STOHZ11 K
L
STi23
VDD_
COREA
TRST
TCK
VDD_IO
VDD_
CORE
VDD_
CORE
VSS
VSS
VDD_
CORE
VDD_
CORE
VDD_IO
STio10
STio11
STio9
STOHZ10 L
M STio25
NC
TDi
D0
VSS
VDD_
CORE
VDD_
CORE
D6
D10
VDD_
CORE
VDD_
CORE
VSS
MOT
_INTEL
MODE_
4M0
STio8
STOHZ9 M
N STio24
NC
VDD_IO
STio0
STOHZ3
D1
D5
D7
D11
D13
R/W
_WR
DTA_
RDY
STio4
VDD_IO
STOHZ5
STOHZ8
N
P STio26
NC
VSS
STio1
STio3
STOHZ1
D3
D8
D14
NC
STio5
VSS
STOHZ7
NC
P
R STio27
NC
STOHZ0
STio2
STOHZ2
D2
D4
D9
D12
D15
CS
DS_RD
MODE_
4M1
STio6
STio7
NC
R
VSS
STio28
STio29
STio31
STio30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
T
STOHZ4 STOHZ6
Note: A1 corner identified by metallized marking.
Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
8
Zarlink Semiconductor Inc.
ZL50020
STi27
STi26
STi25
STi24
VSS
STi_7
VDD_IO
STi_6
STi_5
STi_4
STi_3
STi_2
STi_1
STi_0
VSS
VDD_IO
NC
VSS
CKo2
VDD_CORE
CKo1
VSS
CKo0
VDD_IO
NC
NC
NC
NC
NC
NC
VSS
NC
VDD_IO
NC
VSS
VDD_COREA
VSS
FPi
CKi
IC_Open
IC_Open
IC_Open
IC_Open
IC_Open
IC_GND
VSS
VDD_CORE
VSS
IC_GND
VDD_IO
VSS
ODE
NC
NC
NC
NC
NC
NC
NC
VDD_IO
STio_23
STio_22
STio_21
STio_20
QFP Pinout
126
196
124
198
122
200
120
202
118
204
116
206
114
208
112
210
110
212
108
214
106
216
104
218
102
220
100
222
98
224
96
226
94
228
92
230
90
232
88
234
86
236
84
238
82
240
80
242
78
244
76
246
74
248
72
250
70
252
68
254
66
6
8
10
12
14
16
18
20
22
24
26
28
30 32
34
36
38
40
42
44
46
48
VSS
50
52
54
56
58 60
62
64
VSS
NC
NC
NC
NC
4
STOHZ_7
2
VSS
STio_4
STio_5
STio_6
STio_7
STOHZ_4
STOHZ_5
VDD_IO
STOHZ_6
256
VDD_IO
STio_27
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130
128
194
MODE_4M1
STi28
STi29
VDD_IO
STi30
STi31
STi_8
VSS
STi_9
STi_10
STi_11
STi_12
STi_13
STi_14
STi_15
VDD_IO
IC_GND
VSS
IC_Open
RESET
TDo
VDD_CORE
VSS
NC
VSS
VDD_COREA
VSS
NC
VDD_IOA
NC
VSS
VSS
VDD_COREA
NC
VDD_IOA
CKo3
VSS
NC
VSS
VDD_COREA
VSS
VDD_CORE
TMS
VSS
NC
NC
TCK
TRST
TDi
VDD_IO
VSS
STi_16
STi_17
STi_18
STi_19
STi_20
STi_21
VDD_IO
STi_22
VSS
STi_23
STio_24
STio_25
STio_26
STio_28
STio_29
STio_30
STio_31
VDD_IO
STio_0
STio_1
VSS
STio_2
STio_3
STOHZ_0
STOHZ_1
STOHZ_2
STOHZ_3
VDD_IO
D0
VSS
D1
VDD_CORE
D2
VSS
D3
D4
D5
D6
D7
D8
D9
VDD_IO
D10
VSS
D11
VDD_CORE
D12
VSS
D13
D14
D15
R/W_WR
CS
MOT_INTEL
DS_RD
NC
DTA_RDY
VDD_CORE
MODE_4M0
1.2
Data Sheet
Figure 3 - ZL50020 256-Lead 28 mm x 28 mm LQFP (top view)
9
Zarlink Semiconductor Inc.
STio_19
STio_18
STio_17
STio_16
STOHZ_15
VSS
STOHZ_14
VDD_IO
STOHZ_13
STOHZ_12
STio_15
STio_14
STio_13
STio_12
VSS
VDD_IO
FPo3
VSS
FPo2
VDD_CORE
FPo_OFF2
IC_GND
FPo1
IC_Open
FPo_OFF1
VSS
FPo0
VDD_IO
FPo_OFF0
A13
A12
VSS
A11
VDD_CORE
A10
A9
A8
A7
A6
A5
A4
A3
A2
VSS
A1
VDD_CORE
A0
VSS
IC_Open
VDD_IO
STOHZ_11
STOHZ_10
STOHZ_9
STOHZ_8
STio_11
STio_10
STio_9
VSS
STio_8
VDD_IO
NC
NC
NC
NC
ZL50020
2.0
Data Sheet
Pin Description
PBGA Pin
Number
LQFP Pin
Number
E6, E11, F6,
F7, F10,
F11, L6, L7,
L10, L11,
M6, M7,
M10, M11
19, 33,
45, 83,
95, 109,
146, 173,
213, 233
VDD_CORE
Power Supply for the core logic: +1.8 V
H4, K5, B9,
L2
217, 231,
157, 224
VDD_COREA
Power Supply for analog circuitry: +1.8 V
D3, D14, E4,
E13, F5,
F12, G6,
G11, K6,
K11, L5,
L12, N3,
N14
5, 15, 29,
49, 57,
69, 79,
101, 113,
121, 133,
143, 160,
169, 177,
186, 195,
207, 241,
249
VDD_IO
Power Supply for I/O: +3.3 V
J2, J3
220, 226
VDD_IOA
Power Supply for the CKo5 and CKo3 outputs: +3.3 V
A1, A16, C3,
C9, C14,
D10, E5,
E12, F8, F9,
G7, G8, G9,
G10, H2,
H3, H6, H7,
H8, H9,
H10, J4, J5,
J7, J8, J9,
J10, K2, K4,
K7, K8, K9,
K10, L8, L9,
M5, M12,
P3, P14, T1,
T16
8, 17, 21,
31, 35,
47, 50,
60, 71,
81, 85,
97, 103,
111, 114,
123, 142,
145, 147,
156, 158,
162, 171,
175, 178,
188, 199,
209, 214,
216, 218,
222, 223,
228, 230,
232, 235,
242, 251
VSS
Pin Name
Description
Ground
10
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
K3
234
TMS
Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
L4
238
TCK
Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic.
L3
239
TRST
Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
M3
240
TDi
Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
G5
212
TDo
Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.
B12, B13,
C10, C11,
F13, G4,
K12, C12,
80, 105,
150, 151,
152, 153,
210, 149
IC_Open
Internal Test Mode (5 V-Tolerant Input with Internal Pull-down)
These pins may be left unconnected.
G3, D12,
B14, C13
144, 107,
148, 208
IC_GND
Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.
11
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
PBGA Pin
Number
LQFP Pin
Number
A8, A9, A14,
A15, E10,
M2, N2, P2,
P16, R2,
R16, T6, T7,
T8, T9, T10,
T11, T12,
T13, T14,
T15, D9, E8,
C8, E7, D6,
H5, P10, E9,
D8, B8, D7
61, 62,
63, 64,
65, 66,
67, 68,
134, 135,
136, 137,
138, 139,
140, 152,
215, 219,
225, 229,
236,
237159,
163, 165,
167, 176,
221, 43,
161, 164,
166, 168
NC
M14, R13
46, 48
MODE_4M0,
MODE_4M1
4M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal
pull-down) These two pins should be tied together and are
typically used to select CKi = 4.096 MHz operation. See Table 7,
“ZL50020 Operating Modes” on page 32 for a detailed explanation.
See Table 13, “Control Register (CR) Bits” on page 39 for CKi and
FPi selection using the CKIN1 - 0 bits.
G15, G14,
E15, F14
102, 106,
110, 112
FPo0 - 3
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
H14, D11,
F15
100, 104,
108
FPo_OFF0 - 2
B7, C7, B5,
J6
170, 172,
174, 227
CKo0 - 3
Pin Name
Description
No Connect
These pins MUST be left unconnected.
Generated Offset Frame Pulse Outputs 0 to 2 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
ST-BUS/GCI-Bus Clock Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz or 16.384 MHz programmable
output clock. 32.768 MHz if in multiplied clock mode.
12
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
B10
155
FPi
ST-BUS/GCI-Bus
Frame
Pulse
Input
(5 V-Tolerant
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the CKi must
be applied to this pin. If the data rate is 16.384 Mbps, a 61 ns wide
frame pulse must be used. By default, the device accepts a
negative frame pulse in ST-BUS format, but it can accept a
positive frame pulse instead if the FPINP bit is set high in the
Control Register (CR). It can accept a GCI-formatted frame pulse
by programming the FPINPOS bit in the Control Register (CR) to
high.
B11
154
CKi
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
In divided clock mode the clock frequency applied to this pin must
be twice the highest input or output data rate. In multiplied clock
mode the clock frequency applied to this pin must be twice the
highest input data rate.
The exception is, when data is running at 16.384 Mbps, a
16.384 MHz clock must be used. By default, the clock falling edge
defines the input frame boundary, but the device allows the clock
rising edge to define the frame boundary by programming the
CKINP bit in the Control Register (CR).
B6, C6, D5,
D4, B4, B3,
C5, C4, E3,
C2, B2, D2,
F3, F4, E2,
F2, E1, D1,
G1, F1, J1,
H1, K1, L1,
A7, A5, A6,
A4, A3, A2,
C1, B1
179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
205, 206,
243, 244,
245, 246,
247, 248,
250, 252,
189, 190,
191, 192,
193, 194,
196, 197
STi0 - 31
Serial Input Streams 0 to 31 (5 V-Tolerant Inputs with Internal
Pull-downs)
The data rate of each input stream can be selected independently
using the Stream Input Control Registers (SICR[n]). In the
2.048 Mbps mode, these pins accept serial TDM data streams at
2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode,
these pins accept serial TDM data streams at 4.096 Mbps with 64
channels per frame. In the 8.192 Mbps mode, these pins accept
serial TDM data streams at 8.192 Mbps with 128 channels per
frame. In the 16.384 Mbps mode, these pins accept TDM data
streams at 16.384 Mbps with 256 channels per frame.
13
Zarlink Semiconductor Inc.
ZL50020
PBGA Pin
Number
LQFP Pin
Number
N4, P4, R4,
P5, N13,
P11, R14,
R15, M15,
L15, L13,
L14, E14,
D13, D15,
C15, D16,
E16, C16,
B16, A13,
A12, A10,
A11, N1,
M1, P1, R1,
T2, T3, T5,
T4
Data Sheet
Pin Name
Description
6, 7, 9,
10, 51,
52, 53,
54, 70,
72, 73,
74, 115,
116, 117,
118, 125,
126, 127,
128, 129,
130, 131,
132, 253,
254, 255,
256, 1, 2,
3, 4
STio0 - 31
Serial Output Streams 0 to 31 (5 V-Tolerant Slew-Rate-Limited
Three-state I/Os with Enabled Internal Pull-downs)
The data rate of each output stream can be selected
independently using the Stream Output Control Registers
(SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM
data streams at 2.048 Mbps with 32 channels per frame. In the
4.096 Mbps mode, these pins output serial TDM data streams at
4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode,
these pins output serial TDM data streams at 8.192 Mbps with 128
channels per frame. In the 16.384 Mbps mode, these pins output
serial TDM data streams at 16.384 Mbps with 256 channels per
frame.These output streams can be used as bi-directionals by
programming BDH (bit 7) and BDL (bit 6) of Internal Mode
Selection (IMS) register.
R3, P6, R5,
N5, P12,
N15, P13,
P15, N16,
M16, L16,
K16, H16,
J16, G16,
F16
11, 12,
13, 14,
55, 56,
58, 59,
75, 76,
77, 78,
119, 120,
122, 124
STOHZ0 - 15
Serial Output Streams High Impedance Control 0 to 15
(5 V-Tolerant Slew-Rate-Limited Three-state Outputs)
These pins are used to enable (or disable) external three-state
buffers. When an output channel is in the high impedance state,
the STOHZ drives high for the duration of the corresponding output
channel. When the STio channel is active, the STOHZ drives low
for the duration of the corresponding output channel. STOHZ
outputs are available for STio0 - 15 only.
B15
141
ODE
Output Drive Enable (5 V-Tolerant Input with Internal Pull-up)
This is the output enable control for STio0 - 31 and the
output-driven-high control for STOHZ0 - 15. When it is high, STio0
- 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are
tristated and STOHZ0 - 15 are driven high.
M4, N6, R6,
P7, R7, N7,
M8, N8, P8,
R8, M9, N9,
R9, N10, P9,
R10
16, 18,
20, 22,
23, 24,
25, 26,
27, 28,
30, 32,
34, 36,
37, 38
D0 - 15
Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state
I/Os)
These pins form the 16-bit data bus of the microprocessor port.
14
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
N12
44
DTA_RDY
Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.
R11
40
CS
Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
N11
39
R/W_WR
Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
R12
42
DS_RD
Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
K13, K15,
K14, J11,
J12, J13,
J15, H11,
J14, H12,
H13, H15,
G12, G13
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
A0 - 13
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
M13
41
MOT_INTEL
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin is
connected to ground, Intel interface should be used.
G2
211
RESET
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 31 drivers and drives the STOHZ0 - 15
outputs to high. It also preloads registers with default values and
clears all internal counters. To ensure proper reset action, the reset
pin must be low for longer than 1 µs. Upon releasing the reset
signal to the device, the first microprocessor access cannot take
place for at least 600 µs due to the time required to stabilize the
device from the power-down state. Refer to Section Section 13.2
on page 33 for details.
15
Zarlink Semiconductor Inc.
ZL50020
3.0
Data Sheet
Device Overview
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31).
STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking
digital switch with 2048 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the
use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Clock mode (CLKM
bit 11 Table 13, Control Register (CR) Bits. In Multiplied Clock mode, the output data streams will be driven by an
internally generated clock, which is multiplied from CKi internally. In Multiplied Clock mode, the output data streams
will be driven by an internally generated clock, which is multiplied from CKi internally. Refer to Application Note
ZLAN-120 for further explanation of the different modes of operation.
There are two clock modes for this device:
The first is the Divided Clock mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps.The second clock mode is called Multiplied
Clock mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by
this internal clock. In Multiplied Clock mode, the data rate of output streams can be any rate, but output jitter may
not be exactly the same as input jitter.
A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0
Data Rates and Timing
The ZL50020 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to
operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32
channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
The output streams can be programmed to operate as bi-directional streams. The output streams are divided into
two groups to be programmed into bi-directional mode. By setting BDL (bit 6) in the Internal Mode Selection (IMS)
register, input streams 0 - 15 (STi0 - 15) are internally tied low, and output streams 0 - 15 (STio0 - 15) are set to
operate in a bi-directional mode. Similarly, when BDH (bit 7) in the Internal Mode Selection (IMS) register is set,
input streams 16 - 31 (STi16 - 31) are internally tied low, and output streams 16 - 31 (STio16 - 31) are set to operate
in bi-directional mode. The groups do not have to be set into the same mode. Therefore it is possible to have half of
the streams operating in bi-directional mode while the other half is operating in normal input/output mode.
The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input
Control Register 0 - 31 (SICR0 - 31). The output data rate is set on a per-stream basis by programming STO[n]DR3
- 0 (bits 3 - 0) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). The output data rates do not have to
match or follow the input data rates. he maximum number of channels switched is limited to 2048 channels. If all 32
16
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels.
Memory limitations prevent the device from operating at this capacity. A maximum capacity of 2048 channels will
occur if eight of the streams are operating at 16.384 Mbps, half of the streams are operating at 8.192 Mbps or all
streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 1024
channels. However, as each stream can be programmed to a different data rate, any combination of data rates can
be achieved, as long as the total channel count does not exceed 2048 channels. It should be noted that only full
stream can be programmed for use. The device does not allow fractional streams. External High Impedance
Control, STOHZ0 - 15.
There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for
per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided
with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot
channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin
is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin,
OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 16 on page 28 for a
diagrammatical explanation.
4.1
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The frequency of the input clock (CKi) for the ZL50020 depends on the operation mode selected. In divided clock
mode, CKi must be at least twice the highest input or output data rate. For example, if the highest input data rate is
4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is
twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In multiplied clock
mode the frequency of CKi must be at least twice the highest input data rate regardless of the output data rate. An
APLL is used to multiple CKi to generate an internal clock that is used to output clocks and STio streams.
Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz,
regardless of the output data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi.
In either mode the user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width
of the input frame pulse and the frequency of the input clock supplied to the device.
Highest Input or Output
Data Rate
CKIN 1-0 Bits
Input Clock Rate (CKi)
Input Frame Pulse (FPi)
8.192 Mbps or 16.384 Mbps
00
16.384 MHz
8 kHz (61 ns wide pulse)
4.096 Mbps
01
8.192 MHz
8 kHz (122 ns wide pulse)
2.048 Mbps
10
4.096 MHz
8 kHz (244 ns wide pulse)
Table 1 - CKi and FPi Configurations for Divided Clock Modes
l
Highest Input Data Rate
CKIN 1-0 Bits
Input Clock Rate (CKi)
Input Frame Pulse (FPi)
8.192 Mbps or 16.384 Mbps
00
16.384 MHz
8 kHz (61 ns wide pulse)
4.096 Mbps
01
8.192 MHz
8 kHz (122 ns wide pulse)
2.048 Mbps
10
4.096 MHz
8 kHz (244 ns wide pulse)
Table 2 - CKi and FPi Configurations for Multiplied Clock Mode
17
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
ST-BUS
The ZL50020 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
GCI-Bus
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
Channel 0
STi
(2.048 Mbps)
0
Channel 31
7
6
1
0
7
ST-BUS
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
FPi (122 ns)
FPINP = 0
FPINPOS = 0
FPi (122 ns)
FPINP = 1
FPINPOS = 0
GCI-Bus
FPi (122 ns)
FPINP = 0
FPINPOS = 1
FPi (122 ns)
FPINP = 1
FPINPOS = 1
CKi
(8.192 MHz)
CKINP = 0
CKi
(8.192 MHz)
CKINP = 1
Channel 0
STi
(4.096 Mbps)
1
0
7
6
Channel 63
5
4
2
1
0
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR
18
Zarlink Semiconductor Inc.
7
6
ST-BUS
ZL50020
Data Sheet
FPi (61 ns)
FPINP = 0
FPINPOS = 0
FPi (61 ns)
FPINP = 1
FPINPOS = 0
GCI-Bus
FPi (61 ns)
FPINP = 0
FPINPOS = 1
FPi (61 ns)
FPINP = 1
FPINPOS = 1
CKi
(16.384 MHz)
CKINP = 0
CKi
(16.384 MHz)
CKINP = 1
Channel N = 127
Channel 0
STi
(8.192 Mbps)
1 0 7 6 5 4 3 2 1
5 4 3 2 1 0 7 6 5
Channel 0
STi
(16.384 Mbps)
Channel N = 255
321076543210765432
321076543210765432
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR
5.0
ST-BUS and GCI-Bus Timing
The ZL50020 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the
device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by
the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge
of CKo while FPo goes high. The data rates define the number of channels that are available in a 125 µs frame
pulse period.
By default, the ZL50020 is configured for ST-BUS input and output timing. To set the input timing to conform to the
GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing
to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse
Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the
polarity (positive-going or negative-going) of the output clocks.
6.0
Output Timing Generation
The ZL50020 generates frame pulse and clock timing. There are four output frame pulse pins (FPo0 - 3) and four
output clock pins (CKo0 - 3). All output frame pulses are 8 kHz output signals. By default, the output frame
boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1,
CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. The
duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 3 on
page 19. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode
Selection (IMS) register.
Pin Name
Output Timing Rate
Table 3 - Output Timing Generation
19
Zarlink Semiconductor Inc.
Output Timing Unit
ZL50020
FPo0 pulse width
CKo0
FPo1 pulse width
CKo1
FPo2 pulse width
CKo2
FPo3 pulse width
CKo3
Data Sheet
244
ns
4.096
MHz
122
ns
8.192
MHz
61
ns
16.384
MHz
244, 122, 61 or 30
ns
4.096, 8.192, 16.384 or 32.768
MHz
Table 3 - Output Timing Generation
The output timing is dependent on the operation mode that is selected. When the device is in Divided Clock mode,
the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is
8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output
a 4.096 MHz or 8.192 MHz clock signal.
The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50020 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.
ST-BUS
The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and
CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing.
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 0
GCI-Bus
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 1
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 1
CKOFPO0EN = 1
CKO0P = 0
CKo0 = 4.096 MHz
CKOFPO0EN = 1
CKO0P = 1
CKo0 = 4.096 MHz
Figure 7 - Output Timing for CKo0 and FPo0
20
Zarlink Semiconductor Inc.
ST-BUS
ZL50020
CKOFPO1EN = 1
FPO1P = 0
FPO1POS = 0
CKOFPO1EN = 1
FPO1P = 1
FPO1POS = 0
GCI-Bus
CKOFPO1EN = 1
FPO1P = 0
FPO1POS = 1
CKOFPO1EN = 1
FPO1P = 1
FPO1POS = 1
CKOFPO1EN = 1
CKO1P = 0
CKo1 = 8.192 MHz
CKOFPO1EN = 1
CKO1P = 1
CKo1 = 8.192 MHz
ST-BUS
Figure 8 - Output Timing for CKo1 and FPo1
CKOFPO2EN = 1
FPO2P = 0
FPO2POS = 0
CKOFPO2EN = 1
FPO2P = 1
FPO2POS = 0
GCI-Bus
CKOFPO2EN = 1
FPO2P = 0
FPO2POS = 1
CKOFPO2EN = 1
FPO2P = 1
FPO2POS = 1
CKOFPO2EN = 1
CKO2P = 0
CKo2 = 16.384 MHz
CKOFPO2EN = 1
CKO2P = 1
CKo2 = 16.384 MHz
Figure 9 - Output Timing for CKo2 and FPo2
21
Zarlink Semiconductor Inc.
Data Sheet
ST-BUS
ZL50020
Data Sheet
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 0
FPO3POS = 0
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 1
FPO3POS = 0
GCI-Bus
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 0
FPO3POS = 1
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
FPO3P = 1
FPO3POS = 1
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
CKO3P = 0
CKo3 = 32.768 MHz
CKOFPO3EN = 1
CKOFPO3SEL1-0 = 11
CKO3P = 1
CKo3 = 32.768 MHz
NOTE:
When CKOFPO3SEL1-0 = “00,” the output for FPo3 and CKo3 follow the same as Figure 7: Output Timing for CKo0 and FPo0
When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1
When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2
Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11”
7.0
Data Input Delay and Data Output Advancement
Various registers are provided to adjust the input delay and output advancement for each input and output data
stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream.
If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The
sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating
at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set
to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate.
The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output
stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2
bit. By default, there is 0 output bit advancement.
Although input delay or output advancement features are available on streams which are operating in bi-directional
mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention
must be given to the timing to ensure contention is minimized.
22
Zarlink Semiconductor Inc.
ZL50020
7.1
Data Sheet
Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.
By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 31 (SICR0 - 31) as described in Table 24 on page 50. The input bit delay can range from
0 to 7 bits.
FPi
Last Channel
STi[n]
Bit Delay = 0
(Default)
Channel 1
Channel 0
Channel 2
4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Bit Delay = 1
Last Channel
STi[n]
Bit Delay = 1
Channel 0
Channel 1
Channel 2
5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, and 8.192 and 16.384 Mbps modes respectively.
Figure 11 - Input Bit Delay Timing Diagram (ST-BUS)
23
Zarlink Semiconductor Inc.
ZL50020
7.2
Data Sheet
Input Bit Sampling Point Programming
In addition to the input bit delay feature, theZL50020 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input
streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the
sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default
sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
FPi
STi[n]
STIN[n]SMP1-0 = 00
(2, 4 or 8 Mbps Default)
1
2
0
1
STi[n]
STIN[n]SMP1-0 = 10
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 00
(16 Mbps - Default)
Sampling Point = 1/4 Bit
Channel 0
0
Sampling Point = 1/2 Bit
Channel 0
0
5
6
7
Sampling Point = 4/4 Bit
Channel 0
Last Channel
2
5
6
7
Last Channel
1
5
6
7
Last Channel
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
STi[n]
STIN[n]SMP1-0 = 11
(2, 4 or 8 Mbps)
STIN[n]SMP1-0 = 10
(16 Mbps)
Sampling Point = 3/4 Bit
Channel 0
Last Channel
1
0
7
6
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 12 - Input Bit Sampling Point Programming
24
Zarlink Semiconductor Inc.
5
ZL50020
Data Sheet
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
Nominal Channel n Boundary
STi[n]
0
7
6
5
Nominal Channel n+1 Boundary
4
3
2
1
000 01
000 10
000 00 (Default)
000 11
001 01
001 10
001 00
001 11
010 01
010 10
010 00
010 11
011 01
011 10
011 00
011 11
0
7
111 11
111 00
111 10
111 01
110 11
110 00
110 10
110 01
101 11
101 00
101 10
101 01
100 11
100 00
100 10
100 01
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset
Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point
Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)
Figure 13 - Input Bit Delay and Factional Sampling Point
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Zarlink Semiconductor Inc.
ZL50020
7.3
Data Sheet
Output Advancement Programming
This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 31 (SOCR0 - 31).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 26 on page 54. The output bit
advancement can vary from 0 to 7 bits.
FPi
Last Channel
STio[n]
Bit Adv = 0
(Default)
Channel 2
4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Bit Advancement = 1
Last Channel
STio[n]
Bit Adv = 1
Channel 1
Channel 0
Channel 1
Channel 0
Channel 2
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50020
7.4
Data Sheet
Fractional Output Bit Advancement Programming
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.
By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.
FPi
Last Channel
STio[n]
STo[n]FA1-0 = 00
(Default 2, 4, 8 or
16Mb/s)
Channel 0
7
0
1
2
5
6
Fractional Bit Advancement = 1/4 Bit
Last Channel
STio[n]
STo[n]FA1-0 = 01
(2, 4 or 8 Mbps)
Channel 0
7
0
1
5
6
4
Fractional Bit Advancement = 1/2 Bit
STio[n]
STo[n]FA1-0 = 10
(2, 4 or 8 Mbps)
STo[n]FA1-0 = 01
(16 Mbps)
Last Channel
Channel 0
7
0
1
5
6
4
Fractional Bit Advancement = 3/4 Bit
STio[n]
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)
Last Channel
1
Channel 0
7
0
6
5
4
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
27
Zarlink Semiconductor Inc.
ZL50020
7.5
Data Sheet
External High Impedance Control Advancement
The external high impedance signals can be programmed to better match the timing required by the external
buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of
their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any
data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by
programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at
16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same
register.
FPi
HiZ
STio[n]
Last
CH0
CH1
CH2
CH3
Last-2
Last-1
Last
CH0
STOHZ Advancement (Programmable in 4 steps of 1/4 bit
for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
Programmable in 2 steps of 1/2 bit for 16.384 Mbps)
STOHZ[n]
(Default = No Advancement)
STOHZ[n]
(with Advancement)
Output Frame Boundary
Note: n = 0 to 15
Note: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.
Figure 16 - Channel Switching External High Impedance Control Timing
8.0
Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
8.1
Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.
28
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.
m = input channel number
n = output channel number
n-m <= 0
0 < n-m < 7
T = Delay between input and output
1 frame - (m-n)
n-m = 7
STio < STi
n-m > 7
STio >= STi
1 frame + (n-m)
n-m
Table 4 - Delay for Variable Delay Mode
For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in
the same 125 µs frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will
appear in the following frame.
Frame N + 1
Frame N
STi4
CH2
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio5
CH9
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STi6
CH1
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio9
CH3
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 17 - Data Throughput Delay for Variable Delay
8.2
Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a
stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when
the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all
output channels.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and
output channel number (n). The data throughput delay (T) is:
T = 2 frames + (n - m)
The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit
is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable
variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay
mode.
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Frame N + 2
Frame N + 1
Frame N
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 18 - Data Throughput Delay for Constant Delay
9.0
Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High
(CM_H). The CM_L is 16 bits wide and is used for channel switching and other special modes. The CM_H is 5 bits
wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low,
µ-law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory
location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor
access cycle. See Table 31 on page 57 for the address mapping of the connection memory. Any unused bits will be
reset to zero on the 16-bit data bus.
For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode
without the µ-law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If
µ-law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information,
the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory
Low.
When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50020 will operate in one of
the special modes described in Table 33 on page 58. When the per-channel message mode is enabled, MSG7 - 0
(bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data.
When the per-channel message mode is enabled, the µ-law/A-law conversion can also be enabled as required.
30
Zarlink Semiconductor Inc.
ZL50020
10.0
Data Sheet
Connection Memory Block Programming
This feature allows for fast initialization of the connection memory after power up.
10.1
Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
into CM_L.
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The values stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
BPD2
BPD1
BPD0
Table 5 - Connection Memory Low After Block Programming
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6 - Connection Memory High After Block Programming
Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.
It takes at least two frame periods (250 µs) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.
11.0
Device Operation in Divided Clock and Multiplied Clock Modes
This device has two main operating modes - Divided Clock mode and Multiplied Clock mode.
In Multiplied Clock mode, output clocks and frame pulses are generated from an internal high-speed clock
synchronized to CKi and FPi. Therefore, all specified output clock rates and data rates are available on CKo0-3 and
STio0-31. In Divided Clock mode, output clocks and frame pulses are directly divided from CKi/FPi. Therefore, the
output clock rate cannot exceed the CKi rate (the output data rates are also limited as per Table 1). The input data
rate cannot exceed the CKi rate in either Multiplied or Divided Clock modes, because input data are always
sampled directly by CKi.
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Table 7, “ZL50020 Operating Modes” on page 32 summarizes the different modes of operation available within the
ZL50020. Each Major mode (explained below) has an associated Minor mode that is determined by setting the
MODE_4M Input Control pins and the OPM bit in the Control Register (Table 13, “Control Register (CR) Bits” on
page 39) indicated in the table.
Device
Input Pins
Operating Mode
Control
CR Register
Output Clock Pins
Data Pins
Signal
Bit
Reference Lock
Enabled
Clock Source
Major
Minor
MODE_4M [1:0]
CKi
OPM
CKo0-3
CKo0-3
STi
STo
Divided
Clock
4M
11
4M
0
CKi
Yes
CKi
8/16 M
00
8/16 M
CKo0-3
(CKi)
1
CKi MULT
Multiplied
Clock
4M
11
4M
8/16 M
00
8/16 M
CKo0-3
(CKi MULT)
Legend:
X
Don’t care or not applicable.
Reference Lock
Refers to what signal the output pins are locked to:
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
Clock Source
Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
Table 7 - ZL50020 Operating Modes
11.1
Divided Clock Mode Operation
When the device is in Divided Clock mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data
rate defined by CKi. For example, if CKi is 4.096 MHz, the input and output data rate cannot be higher than
2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz.
11.2
Multiplied Clock Mode Operation
When the device is in Multiplied Clock mode, device hardware is used to multiply CKi internally. STio0 - are driven
by this internally generated clock. In this mode, the output clocks and data can run at any of the specified rates, but
they may have different jitter characteristics from the input clock (CKi). The input data rates are still limited by the
CKi rate (as per Table 1), as input data are always sampled directly by CKi.
11.3
Output Clock Frequencies
The device can generate a limited number of clock and frame pulse output signals. All signals are synchronous to
each other and are locked to the input CKi and FPi. The device can provide outputs with the following frequencies,
with the exception that when in Divided Clock mode, the output clock rate cannot exceed the input CKi rate.
CKo0
4.096 MHz
CKo1
8.192 MHz
CKo2
16.384 MHz
CKo3
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
FPo0
8 kHz (244 ns wide pulse)
FPo1
8 kHz (122 ns wide pulse)
FPo2
8 kHz (61 ns wide pulse)
FPo3
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
Table 8 - Generated Output Frequencies
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Zarlink Semiconductor Inc.
ZL50020
12.0
Data Sheet
Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 20 on page 63, Figure 21 on page 64, Figure 22 on page 65 and Figure 23 on page 66 for the
microprocessor timing.
13.0
Device Reset and Initialization
The RESET pin is used to reset the ZL50020. When this pin is low, the following functions are performed:
•
synchronously puts the microprocessor port in a reset state
•
tristates the STio0 - 31 outputs
•
drives the STOHZ0 - 15 outputs to high
•
preloads all internal registers with their default values (refer to the individual registers for default values)
•
clears all internal counters
13.1
Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the
power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time
as VDD_IO, but should not “lead” the VDD_IO supply by more than 0.3 V.
13.2
Device Initialization on Reset
Upon power up, the ZL50020 should be initialized as follows:
•
Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high
•
Set the TRST pin to low to disable the JTAG TAP controller
•
Reset the device by pulsing the RESET pin to zero for longer than 1 µs
•
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
•
Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
•
Wait at least 500 µs prior to the next microport access (see Note below)
•
Use the block programming mode to initialize the connection memory
•
Release the ODE pin from low to high after the connection memory is programmed
Note: If CKi is 16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is
4.096 MHz, the waiting time is 2 ms.
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Zarlink Semiconductor Inc.
ZL50020
13.3
Data Sheet
Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset
SRSTSW (bit 1) in the Software Reset Register (SRR).
14.0
Pseudo Random Bit Generation and Error Detection
The ZL50020 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudorandom code (ITU O.151).
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125 µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.
For each input stream, there is a set of registers for the BER test. The registers are as follows:
•
BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register
(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
•
BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the
BER sequence will start to be compared.
•
BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence
will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or
256channels at the data rates of 2.048, 4.096, 8.192or 16.384Mbps, respectively. The minimum length of the
BER test is a single channel. The user must take care to program the correct channel length for the BER test
so that the channel length does not exceed the total number of channels available in the stream.
•
BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When
the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER
(bit 1) in the BER Receiver Control Register is used to reset the BRER register.
For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L). PCC1 - 0 (bits 2 - 1) in
the Connection Memory Low must be programmed to “10” to enable the per-stream based BER transmitters. For
each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the
channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER
receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 µs)
between completion of connection memory programming and starting the BER receiver before the BER receiver
can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.
34
Zarlink Semiconductor Inc.
ZL50020
15.0
Data Sheet
PCM A-law/µ-law Translation
The ZL50020 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or
data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode
and Message Mode.
In order to use this feature, the Connection Memory High (CM_H) entry for the output channel must be
programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the
input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 9.
The different code options are:
Input Coding
(ICL1- 0)
Output Coding
(OCL1 - 0)
Voice Coding
(V/D bit = 0)
00
00
ITU-T G.711 A-law
No code
01
01
ITU-T G.711 µ-law
Alternate Bit Inversion (ABI)
10
10
A-law without Alternate Bit
Inversion (ABI)
Inverted Alternate Bit
Inversion (ABI)
11
11
µ-law without Magnitude
Inversion (MI)
All bits inverted
Data Coding
(V/D bit = 1)
Table 9 - Input and Output Voice and Data Coding
For voice coding options, the ITU-T G.711 A-law and ITU-T G.711 µ-law are the standard rules for encoding. A-law
without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). µ-law
without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3,
2, 1, 0).
When transferring data code, the option “no code” does not invert the bits. The Alternate Bit Inversion (ABI) option
inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When
the “All bits inverted” option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.
The input channel and output channel encoding law are configured independently. If the output channel coding is
set to be different from the input channel, the ZL50020 performs translation between the two standards. If the input
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection
Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data
encoding laws.
16.0
Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
Data Rate
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
2.048 Mbps
Channel 0 - 7
Channel 8 - 15
Channel 16 - 23
Channel 24 - 31
4.096 Mbps
Channel 0 - 15
Channel 16 - 31
Channel 32 - 47
Channel 48 - 63
8.192 Mbps
Channel 0 - 31
Channel 32 - 63
Channel 64 - 95
Channel 96 - 127
16.384 Mbps
Channel 0 - 63
Channel 64 - 127
Channel 128 - 191
Channel 192 - 255
Table 10 - Definition of the Four Quadrant Frames
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to “1”
or “0” as shown by the following table:
STIN[n]Q[y]C[2:0]
Action
0xx
Normal Operation
100
Replaces LSB of every channel in Quadrant y with ‘0’
101
Replaces LSB of every channel in Quadrant y with ‘1’
110
Replaces MSB of every channel in Quadrant y with ‘0’
111
Replaces MSB of every channel in Quadrant y with ‘1’
Note: y = 0, 1, 2, 3
Table 11 - Quadrant Frame Bit Replacement
Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.
17.0
JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
17.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50020 test functions. It consists of three input pins and one output pin
as follows:
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
•
Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to high when it is not driven from an external source.
•
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. The registers are
described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse.
This pin is internally pulled to high when it is not driven from an external source.
•
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is
clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDo driver is set to a high impedance state.
•
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not
driven from an external source.
36
Zarlink Semiconductor Inc.
ZL50020
17.2
Data Sheet
Instruction Register
The ZL50020 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during data register scanning.
17.3
Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50020 JTAG interface contains three test data registers:
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells
arranged to form a scan path around the boundary of the ZL50020 core logic.
•
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
•
The Device Identification Register - The JTAG device ID for the ZL50020 is 0C36414BH
17.4
Version
<31:28>
0000
Part Number
<27:12>
1100 0011 0110 0100
Manufacturer ID
<11:1>
0001 0100 101
LSB
<0>
1
BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE-1149.1 test interface.
37
Zarlink Semiconductor Inc.
ZL50020
18.0
Data Sheet
Register Address Mapping
Address
A13 - A0
CPU
Access
Register
Name
Abbreviation
Reset By
0000H
R/W
Control Register
CR
Switch/Hardware
0001H
R/W
Internal Mode Selection Register
IMS
Switch/Hardware
0002H
R/W
Software Reset Register
SRR
Hardware Only
0003H
R/W
Output Clock and Frame Pulse Control Register
OCFCR
Hardware
0004H
R/W
Output Clock and Frame Pulse Selection
Register
OCFSR
Hardware
0005H
R/W
FPo_OFF0 Register
FPOFF0
Hardware
0006H
R/W
FPo_OFF1 Register
FPOFF1
Hardware
0007H
R/W
FPo_OFF2 Register
FPOFF2
Hardware
0010H
R Only
Internal Flag Register
IFR
Switch/Hardware
0011H
R Only
BER Error Flag Register 0
BERFR0
Switch/Hardware
0012H
R Only
BER Error Flag Register 1
BERFR1
Switch/Hardware
0013H
R Only
BER Receiver Lock Register 0
BERLR0
Switch/Hardware
0014H
R Only
BER Receiver Lock Register 1
BERLR1
Switch/Hardware
0100H 011FH
R/W
Stream Input Control Registers 0 - 31
SICR0 - 31
Switch/Hardware
0120H 013FH
R/W
Stream Input Quadrant Frame Registers 0 - 31
SIQFR0 - 31
Switch/Hardware
0200H 021FH
R/W
Stream Output Control Registers 0 - 31
SOCR0 - 31
Switch/Hardware
0300H 031FH
R/W
BER Receiver Start Registers 0 - 31
BRSR0 - 31
Switch/Hardware
0320H 033FH
R/W
BER Receiver Length Registers 0 - 31
BRLR0 - 31
Switch/Hardware
0340H 035FH
R/W
BER Receiver Control Registers 0 - 31
BRCR0 - 31
Switch/Hardware
0360H 037FH
R Only
BER Receiver Error Registers 0 - 31
BRER0 - 31
Switch/Hardware
Table 12 - Address Map for Registers (A13 = 0)
38
Zarlink Semiconductor Inc.
ZL50020
19.0
Data Sheet
Detailed Register Description
External Read/Write Address: 0000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
OPM
0
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
Bit
Name
Description
15 - 12
Unused
11
OPM
10
Unused
9
FPINPOS
8
CKINP
Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7
FPINP
Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6-5
CKIN1 - 0
Reserved. In normal functional mode, these bits MUST be set to zero.
Operation Mode.
This bit is used to set the device in Master/Slave operation. Refer to Table 7, “ZL50020
Operating Modes” on page 32 for more details.
Reserved. In normal functional mode, this bits MUST be set to zero.
Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0
FPi Active Period
CKi
00
61 ns
16.384 MHz
01
122 ns
8.192 MHz
10
244 ns
4.096 MHz
11
Reserved
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 10,
should also be set to define the input clock mode.
4
VAREN
Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
3
MBPE
Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
Table 13 - Control Register (CR) Bits
39
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
OPM
0
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
Bit
Name
2
OSB
Description
Output Stand By Bit:
This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table
describes the HiZ control of the serial data outputs:
RESET
Pin
SRSTSW
(in SRR)
ODE
Pin
OSB
Bit
0
X
X
X
HiZ
Driven High
1
1
X
X
HiZ
Driven High
1
0
0
X
HiZ
Driven High
1
0
1
0
HiZ
Driven High
1
0
1
1
Active
(Controlled by CM)
Active
(Controlled by CM)
STio0 - 31
STOHZ0 - 15
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to
SOCR0 - 31 (bit2 - 0).
1-0
MS1 - 0
Memory Select Bits
These two bits are used to select connection memory low, connection high or data memory for access by CPU:
MS1 - 0
Memory Selection
00
Connection Memory Low Read/Write
01
Connection Memory High Read/Write
10
Data Memory Read
11
Reserved
Table 13 - Control Register (CR) Bits (continued)
40
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0001H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIO_
PD_EN
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
Bit
Name
15 - 9
Unused
8
STIO_PD_
EN
7
BDH
6
BDL
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
Bi-directional Control for Streams 16-31
BDH
STio16 - 31 Operation
0
normal operation:
STi16-31 are inputs
STio16-31 are outputs
1
bi-directional operation:
STi16-31 tied low internally
STio16-31 are bi-directional
Bi-directional Control for Streams 0-15
BDL
STio0 - 15 Operation
0
normal operation:
STi0-15 are inputs
STio0-15 are outputs
1
bi-directional operation:
STi0-15 tied low internally
STio0-15 are bi-directional
5
RBEREN
PRBS Receiver Enable
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,
this bit MUST be high.
4
TBEREN
PRBS Transmitter Enable
When this bit is low, all the BER transmitters are disabled. To enable any BER
transmitters, this bit MUST be high.
Table 14 - Internal Mode Selection Register (IMS) Bits
41
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0001H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIO_
PD_EN
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
Bit
Name
Description
3-1
BPD2 - 0
Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.
0
MBPS
Memory Block Programming Start:
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has finished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Table 14 - Internal Mode Selection Register (IMS) Bits (continued)
42
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0002H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SRST
SW
0
Bit
Name
15 - 2
Unused
1
SRSTSW
0
Unused
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Software Reset Bit for Switch
When this bit is low, switching blocks are in normal operation. When this bit is high,
switching blocks are in software reset state. Refer to Table 12, “Address Map for
Registers (A13 = 0)” on page 32 for details regarding which registers are affected.
Reserved
In normal functional mode, these bits MUST be set to zero.
Table 15 - Software Reset Register (SRR) Bits
43
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0003H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FPOF2
EN
FPOF1
EN
FPOF0
EN
0
0
CKO
FPO3
EN
CKO
FPO2
EN
CKO
FPO1
EN
CKO
FPO0
EN
Bit
Name
Description
15 - 9
Unused
8
FPOF2EN
FPo_OFF2 Enable
When this bit is high, output frame pulse FPo_OFF2
When this bit is low, output frame pulse FPo_OFF2.
7
FPOF1EN
FPo_OFF1 Enable
When this bit is high, output frame pulse FPo_OFF1 is enabled.
When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.
6
FPOF0EN
FPo_OFF0 Enable
When this bit is high, output frame pulse FPo_OFF0 is enabled.
When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.
5
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
4
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
3
CKOFPO3
EN
CKo3 and FPo3 Enable
When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.
When this bit is low, CKo3 and FPo3 are in high impedance state.
2
CKOFPO2
EN
CKo2 and FPo2 Enable
When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.
When this bit is low, CKo2 and FPo2 are in high impedance state.
1
CKOFPO1
EN
CKo1 and FPo1 Enable
When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.
When this bit is low, CKo1 and FPo1 are in high impedance state.
0
CKOFPO0
EN
CKo0 and FPo0 Enable
When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.
When this bit is low, CKo0 and FPo0 are in high impedance state.
Reserved
In normal functional mode, these bits MUST be set to zero.
Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
44
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0004H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CKO
FPO3
SEL1
CKO
FPO3
SEL0
CKO3
P
FPO3
P
FPO3
POS
CKO2
P
FPO2
P
FPO2
POS
CKO1
P
FPO1
P
FPO1
POS
CKO0
P
FPO0
P
FPO0
POS
Bit
Name
15 - 14
Unused
13 - 12
CKOFPO3
SEL1 - 0
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle
Selection
CKOFPO3
SEL1 - 0
FPo3
CKo3
00
244 ns
4.096 MHz
01
122 ns
8.192 MHz
10
61 ns
16.384 MHz
11
30 ns
32.768 MHz
11
CKO3P
Output Clock (CKo3) Polarity Selection
When this bit is low, the output clock CKo3 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo3 rising edge aligns with the
frame boundary.
10
FPO3P
Output Frame Pulse (FPo3) Polarity Selection
When this bit is low, the output frame pulse FPo3 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo3 has the positive frame pulse format.
9
FPO3POS
8
CKO2P
Output Clock (CKo2) Polarity Selection
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
7
FPO2P
Output Frame Pulse (FPo2) Polarity Selection
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
6
FPO2POS
Output Frame Pulse (FPo3) Position
When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus).
Output Frame Pulse (FPo2) Position
When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus).
Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
45
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0004H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CKO
FPO3
SEL1
CKO
FPO3
SEL0
CKO3
P
FPO3
P
FPO3
POS
CKO2
P
FPO2
P
FPO2
POS
CKO1
P
FPO1
P
FPO1
POS
CKO0
P
FPO0
P
FPO0
POS
Bit
Name
Description
5
CKO1P
Output Clock (CKo1) Polarity Selection
When this bit is low, the output clock CKo1 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo1 rising edge aligns with the
frame boundary.
4
FPO1P
Output Frame Pulse (FPo1) Polarity Selection
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.
3
FPO1POS
2
CKO0P
Output Clock (CKo0) Polarity Selection
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.
1
FPO0P
Output Frame Pulse (FPo0) Polarity Selection
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.
0
FPO0POS
Output Frame Pulse (FPo1) Position
When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus).
Output Frame Pulse (FPo0) Position
When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).
Note: In Divided Clock modes, CKo3 - 1 cannot exceed frequency of CKi.
Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)
46
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0005H - 0007H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FOF[n]
OFF7
FOF[n]
OFF6
FOF[n]
OFF5
FOF[n]
OFF4
FOF[n]
OFF3
FOF[n]
OFF2
FOF[n]
OFF1
FOF[n]
OFF0
FOF[n]
C1
FOF[n]
C0
Bit
Name
15 - 10
Unused
9-2
FOF[n]OFF7 - 0
1-0
FOF[n]C1 - 0
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
FPo_OFF[n] Channel Offset
The binary value of these bits refers to the channel offset from original frame boundary. Permitted channel offset values depend on bits 1-0 of this register.
FPo_OFF[n] Control bits
FOF[n]C
1-0
Data Rate
(Mbps)
FPo_OFF[n]
Pulse Cycle Width
FOF[n]OFF7 - 0
Permitted
Channel Offset
Polarity
Control
Position
Control
00
2.048
one 4.096 MHz clock
0 - 31
FPO0P
FPO0POS
01
4.096
one 8.192 MHz clock
0 - 63
FPO1P
FPO1POS
10
8.192
one 16.384 MHz
clock
0 - 127
FPO2P
FPO2POS
11
16.384
one 16.384 MHz
clock
0 - 255
FPO2P
FPO2POS
Note: [n] denotes output offset frame pulse from 0 to 2.
Table 18 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
47
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read Address: 0010H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT
ERR
IN
ERR
Bit
Name
Description
15 - 2
Unused
1
OUTERR
Output Error (Read Only)
This bit is set high when the total number of output channels is programmed to be
more than the maximum capacity of 2048, in which case the output channels beyond
the maximum capacity should be disabled.
This bit will be cleared automatically after programming is corrected.
0
INERR
Input Error (Read Only)
This bit is set high when the total number of input channels is programmed to be more
than the maximum capacity of 2048, in which case the input channels beyond the
maximum capacity should be disabled.This bit will be cleared automatically after programming is corrected.
Reserved
In normal functional mode, these bits are zero.
Table 19 - Internal Flag Register (IFR) Bits - Read Only
External Read Address: 00011H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
F15
BER
F14
BER
F13
BER
F12
BER
F11
BER
F10
BER
F9
BER
F8
BER
F7
BER
F6
BER
F5
BER
F4
BER
F3
BER
F2
BER
F1
BER
F0
Bit
Name
Description
15 - 0
BERF[n]
BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 0 - 15.
Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only
48
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 00012H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
F31
BER
F30
BER
F29
BER
F28
BER
F27
BER
F26
BER
F25
BER
F24
BER
F23
BER
F22
BER
F21
BER
F20
BER
F19
BER
F18
BER
F17
BER
F16
Bit
Name
Description
15 - 0
BERF[n]
BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 16 - 31.
Table 21 - BER Error Flag Register 1 (BERFR1) Bits - Read Only
External Read Address: 00013H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
L15
BER
L14
BER
L13
BER
L12
BER
L11
BER
L10
BER
L9
BER
L8
BER
L7
BER
L6
BER
L5
BER
L4
BER
L3
BER
L2
BER
L1
BER
L0
Bit
Name
15 - 0
BERL[n]
Description
BER Receiver Lock[n]
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 0 - 15.
Table 22 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
49
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read Address: 00014H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BER
L31
BER
L30
BER
L29
BER
L28
BER
L27
BER
L26
BER
L25
BER
L24
BER
L23
BER
L22
BER
L21
BER
L20
BER
L19
BER
L18
BER
L17
BER
L16
Bit
Name
15 - 0
BERL[n]
Description
BER Receiver Lock[n]:
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 16 - 31.
Table 23 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
External Read/Write Address: 0100H - 011FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
STIN[n]
DR3
STIN[n]
DR2
STIN[n]
DR1
STIN[n]
DR0
Bit
Name
15 - 9
Unused
8-6
STIN[n]BD2 - 0
5-4
STIN[n]SMP1 - 0
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Input Stream[n] Bit Delay Bits.
The binary value of these bits refers to the number of bits that the input stream
will be delayed relative to FPi. The maximum value is 7. Zero means no delay.
Input Data Sampling Point Selection Bits
STIN[n]SMP1-0
Sampling Point
(2.048 Mbps, 4.096 Mbps, 8.192 Mbps
streams)
Sampling Point
(16.384 Mbps
streams)
00
3/4 point
2/4 point
01
1/4 point
10
2/4 point
11
4/4 point
Table 24 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits
50
Zarlink Semiconductor Inc.
4/4 point
ZL50020
Data Sheet
External Read/Write Address: 0100H - 011FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
STIN[n]
DR3
STIN[n]
DR2
STIN[n]
DR1
STIN[n]
DR0
Bit
Name
3-0
STIN[n]DR3 - 0
Description
Input Data Rate Selection Bits:
STIN[n]DR3-0
Data Rate
0000
Stream Unused
0001
2.048 Mbps
0010
4.096 Mbps
0011
8.192 Mbps
0100
16.384 Mbps
0101 - 1111
Reserved
Note: [n] denotes input stream from 0 - 31.
Table 24 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits (continued)
51
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
Name
15 - 12
Unused
11 - 9
STIN[n]Q3C2 - 0
8-6
STIN[n]Q2C2 - 0
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Quadrant Frame 3 Control Bits
These three bits are used to control STi[n]’s quadrant frame 3, which is defined
as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q3C
2-0
Operation
0xx
normal operation
100
LSB of each channel is replaced by “0”
101
LSB of each channel is replaced by “1”
110
MSB of each channel is replaced by “0”
111
MSB of each channel is replaced by “1”
Quadrant Frame 2 Control Bits
These three bits are used to control STi[n]’s quadrant frame 2, which is defined
as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps,
4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q2C
2-0
Operation
0xx
normal operation
100
LSB of each channel is replaced by “0”
101
LSB of each channel is replaced by “1”
110
MSB of each channel is replaced by “0”
111
MSB of each channel is replaced by “1”
Table 25 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
52
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
Name
Description
5-3
STIN[n]Q1C2 - 0
Quadrant Frame 1 Control Bits
these three bits are used to control STi[n]’s quadrant frame 1, which is defined
as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
2-0
STIN[n]Q0C2 - 0
STIN[n]Q1C
2-0
Operation
0xx
normal operation
100
LSB of each channel is replaced by “0”
101
LSB of each channel is replaced by “1”
110
MSB of each channel is replaced by “0”
111
MSB of each channel is replaced by “1”
Quadrant Frame 0 Control Bits
These three bits are used to control STi[n]’s quadrant frame 0, which is defined
as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0
Operation
0xx
normal operation
100
LSB of each channel is replaced by “0”
101
LSB of each channel is replaced by “1”
110
MSB of each channel is replaced by “0”
111
MSB of each channel is replaced by “1”
Note: [n] denotes input stream from 0 - 31.
Table 25 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits (continued)
53
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0200H - 021FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
STOHZ
[n]A2
STOHZ
[n]A1
STOHZ
[n]A0
STO[n]
FA1
STO[n]
FA0
STO[n]
AD2
STO[n]
AD1
STO[n]
AD0
STO[n]
DR3
STO[n]
DR2
STO[n]
DR1
STO[n]
DR0
Bit
Name
15 - 12
Unused
11 - 9
STOHZ[n]A2 - 0
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
STOHZ Additional Advancement Bits
(Valid only for
STio0-15)
STOHZ[n]A2-0
000
001
010
011
100
101-111
8-7
STO[n]FA1 - 0
Additional Advancement
(2.048 Mbps, 4.096 Mbps,
8.192 Mbps)
0 bit
1/4 bit
2/4 bit
3/4 bit
4/4 bit
Reserved
Additional Advancement
(16.384 Mbps streams)
0 bit
2/4 bit
4/4 bit
Reserved
Output Stream[n] Fractional Advancement Bits
STO[n]FA1-0
Advancement
(2.048 Mbps, 4.096 Mbps,
8.192 Mbps streams)
Advancement
(16.384 Mbps streams)
00
0
0
01
1/4 bit
2/4
10
2/4 bit
Reserved
11
3/4 bit
6-4
STO[n]AD2 - 0
Output Stream[n] Bit Advancement Selection Bits
The binary value of these bits refers to the number of bits that the output stream
is to be advanced relative to FPo. The maximum value is 7. Zero means no
advancement.
3-0
STO[n]DR3 - 0
Output Data Rate Selection Bits
STIN[n]DR3 - 0
Data Rate
0000
disabled: STio HiZ
(STOHZ driven high)
0001
2.048 Mbps
0010
4.096 Mbps
0011
8.192 Mbps
0100
16.384 Mbps
0101 - 1111
Reserved
Note: [n] denotes output stream from 0 - 31.
Table 26 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits
54
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0300H - 031FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ST[n]
BRS7
ST[n]
BRS6
ST[n]
BRS5
ST[n]
BRS4
ST[n]
BRS3
ST[n]
BRS2
ST[n]
BRS1
ST[n]
BRS0
Bit
Name
15 - 8
Unused
7-0
ST[n]
BRS7 - 0
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Stream[n] BER Receive Start Bits
The binary value of these bits refers to the input channel in which the BER data starts
to be compared.
Note: [n] denotes input stream from 0 - 31.
Table 27 - BER Receiver Start Register [n] (BRSR[n]) Bits
External Read/Write Address: 0320H - 03FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ST[n]
BL8
ST[n]
BL7
ST[n]
BL6
ST[n]
BL5
ST[n]
BL4
ST[n]
BL3
ST[n]
BL2
ST[n]
BL1
ST[n]
BL0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
8-0
ST[n]
BL8 - 0
Stream[n] BER Length Bits
The binary value of these bits refers to the number of consecutive channels expected
to receive the BER pattern. The maximum number of BER channels is 32, 64, 128 and
256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
respectively. The minimum number of BER channels is 1. If these bits are set to zero,
no BER test will be performed.
Note: [n] denotes input stream from 0 - 31.
Table 28 - BER Receiver Length Register [n] (BRLR[n]) Bits
55
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0340H - 035FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ST[n]
CBER
ST[n]
SBER
Bit
Name
Description
15 - 2
Unused
1
ST[n]
CBER
Stream[n] Bit Error Rate Counter Clear
When this bit is high, it resets the internal bit error counter and the stream BER
Receiver Error Register to zero.
0
ST[n]
SBER
Stream[n] Bit Error Rate Test Start
When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit
error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the
completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set
in the IMS Register first.
Reserved
In normal functional mode, these bits MUST be set to zero.
Note: [n] denotes input stream from 0 - 31
Table 29 - BER Receiver Control Register [n] (BRCR[n]) Bits
External Read Address: 0360H - 037FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST[n]
BC15
ST[n]
BC14
ST[n]
BC13
ST[n]
BC12
ST[n]
BC11
ST[n]
BC10
ST[n]
BC9
ST[n]
BC8
ST[n]
BC7
ST[n]
BC6
ST[n]
BC5
ST[n]
BC4
ST[n]
BC3
ST[n]
BC2
ST[n]
BC1
ST[n]
BC0
Bit
Name
Description
15 - 0
ST[n]
BC15 - 0
Stream[n] BER Count Bits (Read Only)
The binary value of these bits refers to the bit error counts. When it reaches its maximum value of 0xFFFF, the value will be held and will not rollover.
Note: [n] denotes input stream from 0 - 31
Table 30 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
56
Zarlink Semiconductor Inc.
ZL50020
20.0
Memory
20.1
Memory Address Mappings
Data Sheet
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB
(Note 1)
Stream Address
(St0 - 31)
Channel Address
(Ch0 - 255)
A13
A12
A11
A10
A9
A8
Stream [n]
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
1
1
1
1
.
.
.
.
.
1
1
.
.
.
.
1
1
0
0
0
0
0
0
0
0
0
.
.
.
.
.
0
0
.
.
.
.
1
1
0
0
0
0
0
0
0
0
1
.
.
.
.
.
1
1
.
.
.
.
1
1
0
0
0
0
1
1
1
1
0
.
.
.
.
.
1
1
.
.
.
.
1
1
0
0
1
1
0
0
1
1
0
.
.
.
.
.
1
1
.
.
.
.
1
1
0
1
0
1
0
1
0
1
0
.
.
.
.
.
0
1
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
.
.
Stream 14
Stream 15
.
.
.
.
Stream 30
Stream 31
0
0
.
.
0
0
0
0
.
.
0
0
.
.
.
.
0
0
.
.
.
.
1
1
0
0
.
.
0
0
0
0
.
.
0
0
.
.
.
.
1
1
.
.
.
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
.
.
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
0
0
.
.
1
1
0
0
.
.
1
1
.
.
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
.
0
0
.
.
1
1
0
0
1
1
.
.
.
.
1
1
.
.
.
.
1
1
1
1
.
.
.
.
1
1
.
.
.
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
.
.
.
.
0
1
.
.
.
.
0
1
Notes:
1. A13 must
2. Channels
3. Channels
4. Channels
5. Channels
1
1
.
.
.
.
1
1
.
.
.
.
1
1
Channel [n]
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
.
.
.
.
Ch126
Ch 127 (Note 4)
.
.
.
.
Ch 254
Ch 255 (Note 5)
be high for access to data and connection memory positions. A13 must be low to access internal registers.
0 to 31 are used when serial stream is at 2.048 Mbps.
0 to 63 are used when serial stream is at 4.096 Mbps.
0 to 127 are used when serial stream is at 8.192 Mbps.
0 to 255 are used when serial stream is at 16.384 Mbps.
Table 31 - Address Map for Memory Locations (A13 = 1)
20.2
Connection Memory Low (CM_L) Bit Assignment
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 32 on page 57.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
V/C
SSA
4
SSA
3
SSA
2
SSA
1
SSA
0
SCA
7
SCA
6
SCA
5
SCA
4
SCA
3
SCA
2
SCA
1
SCA
0
CMM
=0
Bit
Name
Description
15
UAEN
Conversion between µ-law and A-law Enable
When this bit is low, normal switch without µ-law/A-law conversion. Connection memory high will be ignored.
When this bit is high, switch with µ-law/A-law conversion, and connection
memory high controls the conversion method.
Table 32 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
57
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
V/C
SSA
4
SSA
3
SSA
2
SSA
1
SSA
0
SCA
7
SCA
6
SCA
5
SCA
4
SCA
3
SCA
2
SCA
1
SCA
0
CMM
=0
Bit
Name
Description
14
V/C
Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from constant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.
13 - 9
SSA4 - 0
Source Stream Address
The binary value of these 5 bits represents the input stream number.
8-1
SCA7 - 0
Source Channel Address
The binary value of these 8 bits represents the input channel number.
0
CMM = 0
Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit13 1 are the source stream number and channel number.
Note: For proper µ - law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 32 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits
PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode
as shown in Table 33 on page 58.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
0
0
0
0
MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
Bit
Name
Description
15
UAEN
Conversion between µ-law and A-law Enable (Message mode only)
When this bit is low, message mode has no µ-law/A-law conversion. Connection memory high will be ignored.
When this bit is high, message mode has µ-law/A-law conversion, and connection memory high controls the conversion method.
14 - 11
Unused
10 - 3
MSG7 - 0
Reserved
In normal functional mode, these bits MUST be set to zero.
Message Data Bits
8-bit data for the message mode. Not used in the per-channel tristate and
BER test modes.
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
58
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
0
0
0
0
MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
Bit
Name
2-1
PCC1 - 0
0
Description
Per-Channel Control Bits
These two bits control the corresponding entry’s value on the STio stream.
CMM = 1
PC
C1
PC
C0
Channel Output Mode
0
0
Per Channel Tristate
0
1
Message Mode
1
0
BER Test Mode
1
1
Reserved
Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate, per-channel message mode or per-channel BER
mode.
Note: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
20.3
Connection Memory High (CM_H) Bit Assignment
Connection memory high provides the detailed information required for µ-law and A-law conversion. ICL and OCL
bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected
PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the
class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between
A-law and µ-law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the
ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following
table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are
translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed.
The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections,
variable delay connections and per-channel message mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
V/D
ICL
1
ICL
0
OCL
1
OCL
0
Bit
Name
15 - 5
Unused
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
Table 34 - Connection Memory High (CM_H) Bit Assignment
59
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
V/D
ICL
1
ICL
0
OCL
1
OCL
0
Bit
Name
4
V/D
3-2
ICL1 - 0
Description
Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
Input Coding Law.
ICL1-0
1-0
OCL1 - 0
Input Coding Law
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
CCITT.ITU A-law
No code
01
CCITT.ITU µ-law
ABI
10
A-law w/o ABI
Inverted ABI
11
µ-law w/o Magnitude
Inversion
All Bits Inverted
Output Coding Law
OCL1-0
Output Coding Law
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
00
CCITT.ITU A-law
No code
01
CCITT.ITU µ-law
ABI
10
A-law w/o ABI
Inverted ABI
11
µ-law w/o Magnitude
Inversion
All Bits Inverted
Note 1:
For proper µ - law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
Note 2:
Refer to G.711 standard for detail information of different laws.
Table 34 - Connection Memory High (CM_H) Bit Assignment
60
Zarlink Semiconductor Inc.
ZL50020
21.0
Data Sheet
DC Parameters
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD_IO
-0.5
5.0
V
VDD_CORE
-0.5
2.5
V
1
I/O Supply Voltage
2
Core Supply Voltage
3
Input Voltage
VI_3V
-0.5
VDD + 0.5
V
4
Input Voltage (5 V-tolerant inputs)
VI_5V
-0.5
7.0
V
5
Continuous Current at Digital Outputs
Io
15
mA
6
Package Power Dissipation
PD
7
Storage Temperature
TS
- 55
1.5
W
+125
°C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
TOP
-40
25
+85
°C
1
Operating Temperature
2
Positive Supply
VDD_IO
3.0
3.3
3.6
V
3
Positive Supply
VDD_CORE
1.71
1.8
1.89
V
4
Input Voltage
VI
0
3.3
VDD_IO
V
5
Input Voltage on 5 V-Tolerant Inputs
VI_5V
0
5.0
5.5
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
IDD_CORE
120
mA
IDD_IO
70
mA
Test Conditions
1
Supply Current - VDD_CORE
2
Supply Current - VDD_IO
3
Input High Voltage
VIH
4
Input Low Voltage
VIL
0.8
V
5
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0≤<VIN≤VDD_IO
See Note 1
6
Weak Pullup Current
IPU
-33
µA
Input at 0V
7
Weak Pulldown Current
IPD
33
µA
Input at VDD_IO
3
pF
8
Input Pin Capacitance
9
Output High Voltage
VOH
10 Output Low Voltage
VOL
11 Output High Impedance Leakage
IOZ
12 Output Pin Capacitance
CO
2.0
CL=30pF
V
CI
2.4
5
V
IOH = 8 mA
0.4
V
IOL = 8 mA
5
µA
0 < V < VDD
10
pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
61
Zarlink Semiconductor Inc.
ZL50020
22.0
Data Sheet
AC Parameters
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
Characteristics
Sym.
Level
Units
1
CMOS Threshold
VCT
0.5 VDD_IO
V
2
Rise/Fall Threshold Voltage High
VHM
0.7 VDD_IO
V
3 Rise/Fall Threshold Voltage Low
VLM
0.3 VDD_IO
† Characteristics are over recommended operating conditions unless otherwise stated.
V
Conditions
Timing Reference Points
V HM
V CT
V LM
ALL SIGNALS
Figure 19 - Timing Parameter Measurement Voltage Levels
62
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode - Read Access
Characteristics
Sym.
Min.
Typ.‡
Max.
Test Conditions2
Units
1
CS de-asserted time
tCSD
15
ns
2
DS de-asserted time
tDSD
15
ns
3
CS setup to DS falling
tCSS
0
ns
4
R/W setup to DS falling
tRWS
10
ns
5
Address setup to DS falling
tAS
5
ns
6
CS hold after DS rising
tCSH
0
ns
7
R/W hold after DS rising
tRWH
0
ns
8
Address hold after DS rising
tAH
0
ns
9
Data setup to DTA Low
tDS
8
ns
CL = 50 pF
10 Data hold after DS rising
tDHZ
7
ns
CL = 50 pF, RL = 1 K
(Note 1)
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
Memory
tAKD
12 Acknowledgement hold time.
From DS high to DTA high
tAKH
13 DTA drive high to HiZ
tAKZ
Note 1:
Note 2:
4
75
185
ns
ns
12
ns
8
ns
CL = 50 pF
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to
discharge C L .
A delay of 500 µs to 2 ms (see Section 13.2 on page 33) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
tCSS
tCSH
CS
VCT
tDSD
DS
VCT
tRWS
tRWH
VCT
R/W
tAS
tAH
VCT
VALID ADDRESS
A0-A13
tDHZ
VCT
VALID READ DATA
D0-D15
tDS
tAKZ
VCT
DTA
tAKD
tAKH
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access
63
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode - Write Access
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
CS de-asserted time
tCSD
15
ns
2
DS de-asserted time
tDSD
15
ns
3
CS setup to DS falling
tCSS
0
ns
4
R/W setup to DS falling
tRWS
10
ns
5
Address setup to DS falling
tAS
5
ns
6
Data setup to DS falling
tDS
0
ns
7
CS hold after DS rising
tCSH
0
ns
8
R/W hold after DS rising
tRWH
0
ns
9
Address hold after DS rising
tAH
0
ns
10 Data hold from DS rising
tDH
5
ns
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
Memory
tAKD
12 Acknowledgement hold time.
From DS high to DTA high
tAKH
13 DTA drive high to HiZ
tAKZ
Note 1:
Note 2:
4
55
150
ns
ns
12
ns
8
ns
Test Conditions2
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
CL = 50 pF
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to
discharge C L .
A delay of 500 µs to 2 ms (see Section 13.2 on page 33) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
tCSH
tCSS
CS
VCT
tDSD
DS
VCT
tRWH
tRWS
VCT
R/W
tAH
tAS
VCT
VALID ADDRESS
A0-A13
tDS
tDH
VCT
VALID WRITE DATA
D0-D15
tAKZ
VCT
DTA
tAKD
tAKH
Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access
64
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - Intel Non-Multiplexed Bus Mode - Read Access
Characteristics
Sym.
Min.
Typ.‡
Max.
Test Conditions2
Units
1
CS de-asserted time
tCSD
15
ns
2
RD setup to CS falling
tRS
10
ns
3
WR setup to CS falling
tWS
10
ns
4
Address setup to CS falling
tAS
5
ns
5
RD hold after CS rising
tRH
0
ns
6
WR hold after CS rising
tWH
0
ns
7
Address hold after CS rising
tAH
0
ns
8
Data setup to RDY high
tDS
8
ns
CL = 50 pF
9
Data hold after CS rising
tCSZ
7
ns
CL = 50 pF, RL = 1 K
(Note 1)
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
Memory
tAKD
175
185
ns
ns
CL = 50 pF
CL = 50 pF
11 Acknowledgement hold time.
From CS high to RDY low
tAKH
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
12 RDY drive low to HiZ
tAKZ
8
ns
Note 1:
Note 2:
4
High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge C L .
A delay of 500 µs to 2 ms (see Section 13.2 on page 33) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
VCT
CS
tRH
tRS
VCT
RD
tWH
tWS
VCT
WR
tAH
tAS
VCT
VALID ADDRESS
A0-A13
tCSZ
VCT
VALID READ DATA
D0-D15
tDS
tAKZ
VCT
RDY
tAKD
tAKH
Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access
65
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - Intel Non-Multiplexed Bus Mode - Write Access
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
CS de-asserted time
tCSD
15
ns
2
WR setup to CS falling
tWS
10
ns
3
RD setup to CS falling
tRS
10
ns
4
Address setup to CS falling
tAS
5
ns
5
Data setup to CS falling
tDS
0
ns
6
WR hold after CS rising
tWH
0
ns
7
RD hold after CS rising
tRH
0
ns
8
Address hold after CS rising
tAH
10
ns
9
Data hold after CS rising
tDH
5
ns
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
Memory
tAKD
11 Acknowledgement hold time.
From CS high to RDY low
tAKH
12 RDY drive low to HiZ
tAKZ
Note 1:
Note 2:
4
55
150
ns
ns
12
ns
8
ns
Test Conditions2
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
CL = 50 pF
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to
discharge C L .
A delay of 500 µs to 2 ms (Section 13.2 on page 33) must be applied before the first microprocessor access is performed
after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
VCT
CS
tWH
tWS
VCT
WR
tRH
tRS
VCT
RD
tAH
tAS
VCT
VALID ADDRESS
A0-A13
tDH
tDS
D0-D15
VCT
VALID WRITE DATA
tAKZ
VCT
RDY
tAKD
tAKH
Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access
66
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - JTAG Test Port Timing
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
1
TCK Clock Period
tTCKP
100
ns
2
TCK Clock Pulse Width High
tTCKH
20
ns
3
TCK Clock Pulse Width Low
tTCKL
20
ns
4
TMS Set-up Time
tTMSS
10
ns
5
TMS Hold Time
tTMSH
10
ns
6
TDi Input Set-up Time
tTDIS
20
ns
7
TDi Input Hold Time
tTDIH
60
ns
8
TDo Output Delay
tTDOD
9
TRST pulse width
tTRSTW
30
ns
200
Notes
CL = 30 pF
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tTCKL
tTCKH
tTCKP
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 24 - JTAG Test Port Timing Diagram
67
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz)
Characteristic
Sym.
Min.
Typ.‡
61
Max. Units Notes
1
FPi Input Frame Pulse Width
tFPIW
40
2
FPi Input Frame Pulse Setup Time
tFPIS
20
ns
3
FPi Input Frame Pulse Hold Time
tFPIH
20
ns
4
CKi Input Clock Period
tCKIP
55
5
CKi Input Clock High Time
tCKIH
6
CKi Input Clock Low Time
tCKIL
7
CKi Input Clock Rise/Fall Time
61
115
ns
67
ns
27
34
ns
27
34
ns
3
ns
trCKi, tfCKi
8 CKi Input Clock Cycle to Cycle Variation
tCVC
0
20
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz)
Characteristic
Sym.
Min.
Typ.‡
122
Max. Units Notes
1
FPi Input Frame Pulse Width
tFPIW
90
2
FPi Input Frame Pulse Setup Time
tFPIS
45
ns
3
FPi Input Frame Pulse Hold Time
tFPIH
45
ns
4
CKi Input Clock Period
tCKIP
110
5
CKi Input Clock High Time
tCKIH
6
CKi Input Clock Low Time
tCKIL
7
CKi Input Clock Rise/Fall Time
trCKi, tfCKi
122
220
ns
135
ns
55
69
ns
55
69
ns
3
ns
8 CKi Input Clock Cycle to Cycle Variation
tCVC
0
20
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
68
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz)
Characteristic
Sym.
Min.
Typ.‡
244
Max. Units Notes
1
FPi Input Frame Pulse Width
tFPIW
90
2
FPi Input Frame Pulse Setup Time
tFPIS
110
ns
3
FPi Input Frame Pulse Hold Time
tFPIH
110
ns
4
CKi Input Clock Period
tCKIP
220
5
CKi Input Clock High Time
tCKIH
6
CKi Input Clock Low Time
tCKIL
7
CKi Input Clock Rise/Fall Time
244
420
ns
270
ns
110
135
ns
110
135
ns
3
ns
trCKi, tfCKi
8 CKi Input Clock Cycle to Cycle Variation
tCVC
0
20
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPIW
FPi
tFPIS
tFPIH
tCKIP
tCKIH
tCKIL
CKi
trCKI
tfCKI
Input Frame Boundary
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
tFPIW
FPi
tFPIS
tFPIH
tCKIP
tCKIH
tCKIL
CKi
trCKI
tfCKI
Input Frame Boundary
Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
69
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - ST-BUS/GCI-Bus Input Timing
Characteristic
1
Max.
Units
Min.
tSIS2
tSIS4
tSIS8
tSIS16
5
5
5
5
ns
ns
ns
ns
tSIH2
tSIH4
tSIH8
tSIH16
8
8
8
8
ns
ns
ns
ns
Test Conditions
STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
2
Typ.‡
Sym.
STi Hold Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
tSIS2
tSIH2
STi0 - 31
2.048 Mbps
Bit0
Ch31
Bit6
Ch0
Bit7
Ch0
VCT
tSIS4
tSIH4
STi0 - 31
4.096 Mbps
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
VCT
tSIS8
tSIH8
STi0 - 31
8.192 Mbps
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
Input Frame Boundary
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps
70
Zarlink Semiconductor Inc.
TT
VVCT
ZL50020
Data Sheet
FPi
CKi
(16.384 MHz)
tSIS16
tSIH16
STi0 - 31
16.384 Mbps
Bit1
Ch255
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
TT
VVCT
Input Frame Boundary
Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
tSIS2
tSIH2
STi0 - 31
2.048 Mbps
Bit7
Ch31
Bit1
Ch0
Bit0
Ch0
VCT
tSIS4
tSIH4
STi0 - 31
4.096 Mbps
Bit7
Ch63
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
VCT
tSIS8
tSIH8
STi0 - 31
8.192 Mbps
Bit6
Ch127
Bit7
Ch127
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
Input Frame Boundary
Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps
71
Zarlink Semiconductor Inc.
TT
VVCT
ZL50020
Data Sheet
FPi
CKi
(16.384 MHz)
tSIS16
tSIH16
STi0 - 31
16.384 Mbps
Bit6
Ch255
Bit7
Ch255
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
TT
VVCT
Input Frame Boundary
Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps
AC Electrical Characteristics† - ST-BUS/GCI-Bus Output Timing
Characteristic
1
Sym.
Typ.‡
Min.
Max.
Units
Test Conditions
CL = 30 pF
STio Delay - Active to Active
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
tSOD2
tSOD4
tSOD8
tSOD16
0
0
0
0
6
6
6
6
ns
ns
ns
ns
Multiplied Clock Mode
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
tSOD2
tSOD4
tSOD8
tSOD16
-6
-6
-6
-6
0
0
0
0
ns
ns
ns
ns
Divided Clock Mode
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
72
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
FPo0
CKo0
(4.096 MHz)
tSOD2
STio0 - 31
2.048 Mbps
Bit7
Ch0
Bit0
Ch31
Bit6
Ch0
VCT
tSOD4
STio0 - 31
4.096 Mbps
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
VCT
tSOD8
STio0 - 31
8.192 Mbps
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
VCT
tSOD16
STio0 - 31
16.384 Mbps
Bit2 Bit1
Bit0 Bit7
Ch255 Ch255 Ch255 Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
Bit7
Ch1
Bit6
Ch1
Bit5
Ch1
Bit4
Ch1
Bit3
Ch1
Bit2
Ch1
Bit1
Ch1
VCT
Output Frame Boundary
Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
FPo0
CKo0
(4.096 MHz)
tSOD2
STio0 - 31
2.048 Mbps
Bit0
Ch0
Bit7
Ch31
Bit1
Ch0
VCT
tSOD4
STio0 - 31
4.096 Mbps
Bit7
Ch63
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
VCT
tSOD8
STio0 - 31
8.192 Mbps
Bit7
Ch127
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
VCT
tSOD16
STio0 - 31
16.384 Mbps
Bit5 Bit6
Bit7 Bit0
Ch255 Ch255 Ch255 Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
Bit0
Ch1
Bit1
Ch1
Bit2
Ch1
Bit3
Ch1
Bit4
Ch1
Bit5
Ch1
Bit6
Ch1
Output Frame Boundary
Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
73
Zarlink Semiconductor Inc.
VCT
ZL50020
Data Sheet
AC Electrical Characteristics† - ST-BUS/GCI-Bus Output Tristate Timing
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions*
1
STio Delay - Active to High-Z
tDZ
-3
-8
7
0
ns
ns
Multiplied Clock Mode
Divided Clock Mode
2
STio Delay - High-Z to Active
tZD
-3
-8
7
0
ns
ns
Multiplied Clock Mode
Divided Clock Mode
3
Output Drive Enable (ODE) Delay
- High-Z to Active
77
ns
Multiplied Clock Mode
260
138
77
ns
ns
ns
Divided Clock Mode
tZD_ODE
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to
discharge C L.
VCT
FPo0
VCT
CKo0
tDZ
STio
Valid Data
Tristate
VCT
Valid Data
VCT
tZD
Tristate
STio
Figure 33 - Serial Output and External Control
VCT
ODE
tZD_ODE
STio
HiZ
tDZ_ODE
Valid Data
HiZ
Figure 34 - Output Drive Enable (ODE)
74
Zarlink Semiconductor Inc.
VCT
ZL50020
Data Sheet
AC Electrical Characteristics† - Clock Mode Input/Output Frame Boundary Alignment
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
1
Input and Output Frame Offset in
Divided Clock Mode
tFBOS
5
13
ns
2
Input and Output Frame Offset in
Multiplied Clock Mode
tFBOS
2
10
ns
Notes
Input reference jitter is
equal to zero.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
Input Frame Boundary
tFBOS
Output Frame Boundary
FPo0
CKo0
(4.096 MHz)
Figure 35 - Input and Output Frame Boundary Offset
75
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
tFPW03
VCT
FPo0/3
tFODF03
tFODR03
tCKP03
tCKH03
tCKL03
VCT
CKo0/3
trCK03
tfCK03
Output Frame Boundary
Figure 36 - FPo0 and CKo0 Timing Diagram
AC Electrical Characteristics† - FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Divided Clock Mode and Multiplied Clock
Mode with Less than 10 ns of Input Cycle to Cycle Variation
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
244
249
ns
1
FPo0 Output Pulse Width
tFPW03
239
2
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
tFODF03
117
127
ns
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR03
117
127
ns
4
CKo0 Output Clock Period
tCKP03
239
249
ns
5
CKo0 Output High Time
tCKH03
117
127
ns
6
CKo0 Output Low Time
tCKL03
117
127
ns
7
CKo0 Output Rise/Fall Time
5
ns
244
trCK03, tfCK03
Notes
CL = 30 pF
CL = 30 pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Multiplied Clock Mode with More than 10 ns
of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
244
270
ns
1
FPo0 Output Pulse Width
tFPW03
218
2
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
tFODF03
117
127
ns
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR03
97
146
ns
4
CKo0 Output Clock Period
tCKP03
218
270
ns
5
CKo0 Output High Time
tCKH03
117
127
ns
6
CKo0 Output Low Time
tCKL03
97
146
ns
244
Notes
CL = 30 pF
CL = 30 pF
5
ns
7 CKo0 Output Rise/Fall Time
trCK03, tfCK03
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
76
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
tFPW1
VCT
FPo1/3
tFODF1
tFODR1
tCKP1
tCKH1
tCKL1
VCT
CKo1/3
trCK1
tfCK1
Output Frame Boundary
Figure 37 - FPo1 and CKo1 Timing Diagram
AC Electrical Characteristics† - FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Divided Clock Mode and Multiplied Clock
Mode with Less than 10 ns of Input Cycle to Cycle Variation
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
122
127
ns
1
FPo1 Output Pulse Width
tFPW13
117
2
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
tFODF13
56
66
ns
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR13
56
66
ns
4
CKo1 Output Clock Period
tCKP13
117
127
ns
5
CKo1 Output High Time
tCKH13
56
66
ns
6
CKo1 Output Low Time
tCKL13
56
66
ns
122
Notes
CL = 30 pF
CL = 30 pF
7 CKo1 Output Rise/Fall Time
trCK13, tfCK13
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Multiplied Clock Mode with More than 10 ns
of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
122
127
ns
1
FPo1 Output Pulse Width
tFPW13
106
2
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
tFODF13
56
66
ns
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR13
46
66
ns
4
CKo1 Output Clock Period
tCKP13
106
148
ns
5
CKo1 Output High Time
tCKH13
46
87
ns
6
CKo1 Output Low Time
tCKL13
46
66
ns
122
Notes
CL = 30 pF
CL = 30 pF
7 CKo1 Output Rise/Fall Time
trCK13, tfCK13
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
77
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
tFPW23
VCT
FPo2/3
tFODF23
tFODR23
tCKP23
tCKH23
tCKL23
VCT
CKo2/3
trCK23
tfCK23
Output Frame Boundary
Figure 38 - FPo2 and CKo2 Timing Diagram
†
AC Electrical Characteristics - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Divided Clock Mode and Multiplied Clock
Mode with Less than 10 ns of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
61
66
ns
1
FPo2 Output Pulse Width
tFPW23
56
2
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
tFODF23
25
36
ns
3
FPo2 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR23
25
36
ns
4
CKo2 Output Clock Period
tCKP23
56
66
ns
5
CKo2 Output High Time
tCKH23
25
36
ns
6
CKo2 Output Low Time
tCKL23
25
36
ns
61
Notes
CL = 30 pF
CL = 30 pF
7 CKo2 Output Rise/Fall Time
trCK23, tfCK23
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Multiplied Clock Mode with More than
10 ns of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
61
66
ns
1
FPo2 Output Pulse Width
tFPW23
56
2
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
tFODF23
25
36
ns
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR23
25
36
ns
4
CKo2 Output Clock Period
tCKP2
47
76
ns
5
CKo2 Output High Time
tCKH23
17
43
ns
6
CKo2 Output Low Time
tCKL23
17
43
ns
61
Notes
CL = 30 pF
CL = 30 pF
5
ns
7 CKo2 Output Rise/Fall Time
trCK23, tfCK23
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
78
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
tFPW3
VCT
FPo3
tFODF3
tFODR3
tCKP3
tCKH3
tCKL3
VCT
CKo3
trCK3
tfCK3
Output Frame Boundary
Figure 39 - FPo3 and CKo3 Timing Diagram
AC Electrical Characteristics† - FPo3/CKo3 (32.768 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less
than 10 ns of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
30.5
34
ns
1
FPo3 Output Pulse Width
tFPW3
27
2
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
tFODF3
10
18
ns
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
21
ns
4
CKo3 Output Clock Period
tCKP3
27
34
ns
5
CKo3 Output High Time
tCKH3
12
30.5
19
ns
6
CKo3 Output Low Time
tCKL3
12
19
ns
Notes
CL = 30 pF
CL = 30 pF
7 CKo3 Output Rise/Fall Time
trCK3, tfCK3
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo3/CKo3 (32.768 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Cycle to
Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
30.5
34
ns
1
FPo3 Output Pulse Width
tFPW3
27
2
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
tFODF3
12
19
ns
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
19
ns
4
CKo3 Output Clock Period
tCKP3
17
44
ns
5
CKo3 Output High Time
tCKH3
5
29
ns
6
CKo3 Output Low Time
tCKL3
12
18
ns
7
CKo3 Output Rise/Fall Time
5
ns
trCK3, tfCK3
30.5
Notes
CL = 30 pF
CL = 30 pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
79
Zarlink Semiconductor Inc.
ZL50020
Data Sheet
AC Electrical Characteristics† - Divided Clock Mode Output Timing
Characteristic
Sym.
Min.
Max.
Units
1
CKo0 to CKo1 (8.192 MHz) delay
tC1D
-1
2
ns
2
CKo0 to CKo2 (16.384 MHz) delay
tC2D
-1
3
ns
3
CKo0 to CKo3 (16.384 MHz/8.192 MHz/4.096 MHz) delay
tC3D
-2
2
ns
Sym.
Min.
Max.
Units
† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics† - Multiplied Clock Mode Output Timing
Characteristic
1
CKo0 to CKo1 (8.192 MHz) delay
tC1D
-1
2
ns
2
CKo0 to CKo2 (16.384 MHz) delay
tC2D
-1
3
ns
3
CKo0 to CKo3
(32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay
tC3D
-1
3
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
tFPD
FPo0
VCT
VCT
CKo0
(4.096 MHz)
tC1D
VCT
CKo1
(8.192 MHz)
tC2D
VCT
CKo2
(16.384 MHz)
tC3D
VCT
CKo3
(32.768 MHz)
Figure 40 - Output Timing (ST-BUS Format)
80
Zarlink Semiconductor Inc.
b
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
214440
DATE
26June03
APPRD.
Previous package codes
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
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