ESD8L5.0C Surface Mount TVS For ESD Protection Diode with Ultra-Low Capacitance TRANSIENT VOLTAGE SUPPRESSORS 150 mWATTS 5.0 VOLTS P b Lead(Pb)-Free General Description: The ESD8L is designed to protect voltage sensitive components that require ultra-low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it issuited for use in high frequency designs such as USB 2.0 high speed and antenna lin applications. 1 2 Features: *Ultra Low Capacitance 0.5 pF *Low Clamping Voltage *Small Body Outline Dimensions: 0.039” x 0.024” (1.00 mm x 0.60 mm) *Low Body Height: 0.016” (0.4mm) SOD-882 *Low Leakage *Response Time is Typically < 1.0 ns *IEC61000-4-2 Level 4 ESD Protection 1 2 Pin 1. CATHODE 2. ANODE Mechanical Characteristics: *CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V-0 *LEAD FINISH: 100% Matte Sn (Tin) *QUALIFIED MAX REFLOW TEMPERATURE: 260 ºC *Device Meets MSL 1 Requirements SOD-882 Outline Dimensions Unit:mm MILLIMETERS DIM MIN NOM MAX A B C D E F G H P R W 0.95 0.55 0.33 1.00 0.60 0.35 0.39 0.127 0.0635 0.12 0.20 0.64 0.25 0.49 1.05 0.65 0.37 SOLDERING FOOTPRINT WEITRON http://www.weitron.com.tw 1/4 16-Apr-2013 ESD8L5.0C Maximum Ratings(TA=25˚C Unless Otherwise Noted) Symbol Characteristic IEC61000-4-2(ESD) Value Unit ±8 ±8 KV PD 150 mW TJ ,Tstg -55 to +150 °C TL 260 °C Contact Air Total Power Dissipation on FR-5 Board (Note1) @ Ta=25°C Junction and Storage Temperature Range Lead Solder Temperature -Maximum (10 second Duration) Stresses exceeding Maximum Ratings may damage the device. Maximum Rating are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR-5 = 1.0*0.75*0.62 in. Electrical Characteristics (Ta=25°C VRWM (V) IR ( A) @ VRWM VBR (V) @ IT (Note 2) IT Max Max Min mA Typ 5.0 1.0 5.4 1.0 0.5 Marking Device ESD8L5.0C N unless otherwise noted, VF=1.0V Max. @ IF=10mA for all types) VC (V) @ IPP = 1 A (Note 3) VC Max Max Per IEC61000-4-2 (Note 4) 0.9 12.9 Figures 1 and 2 See Below C (pF) 2. VBR is measured with a pulse test current IT at anambient temperature of 25°C. 3. Surge current waveform per Figure 5. 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Electrical Characteristics (TA = 25°C unless otherwise noted) Characteristics Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IF Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM VC VBR VRWM Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C I V IR VF IT IPP Uni Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. WEITRON http://www.weitron.com.tw 2/4 16-Apr-2013 ESD8L5.0C Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2 WEITRON http://www.weitron.com.tw Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2 3/4 16-Apr-2013 ESD8L5.0C IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 80 Figure 5. 8 X 20 ms Pulse Waveform WEITRON http://www.weitron.com.tw 4/4 16-Apr-2013