RENESAS M32C/8A

REJ09B0385-0100
M32C/8A Group
16/32
Hardware Manual
RENESAS MCU
M16C FAMILY / M32C/80 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date:Jul 15, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1.
Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the M32C/8A Group. Make sure to refer to the latest versions of these documents.
The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type
Datasheet
Description
Document Title
Document No.
REJ03B0213Hardware overview and electrical characteristics M32C/8A Group
Datasheet
0110
M32C/8A Group
This hardware
Hardware manual Hardware specifications (pin assignments,
Hardware Manual manual
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set
M32C/80 Series
REJ09B0319Software Manual 0100
Available from Renesas
Application note Information on using peripheral functions and
Technology Web site.
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1)
Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2)
Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7
b6
b5
b4
b3
*1
b2
b1
b0
0
Symbol
XXX
Address
XXX
Bit Symbol
XXX0
After Reset
00h
Bit Name
XXX bits
XXX1
Function
RW
1 0: XXX
0 1: XXX
1 0: Do not set to this value
1 1: XXX
RW
RW
(b2)
Unimplemented.
Write 0. Read as undefined value.
(b3)
Reserved bit
Set to 0
RW
XXX bits
Function varies depending on each operation
mode
RW
XXX4
*3
XXX5
WO
XXX6
RW
XXX7
XXX bit
*2
b1 b0
0: XXX
1: XXX
*4
RO
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Unimplemented.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Unimplemented.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Unimplemented
Nothing is implemented to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Full Form
Asynchronous Communication Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment bus
Input/Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connection
Phase Locked Loop
Pulse Width Modulation
Special Function Registers
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
IEBus is a registered trademark of NEC Electronics Corporation.
Table of Contents
Special Function Register (SFR) Page Reference ............................................................................ B-1
1.
Overview ......................................................................................................................................... 1
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
2.
Features ..................................................................................................................................................... 1
Applications .......................................................................................................................................... 1
Specifications ........................................................................................................................................ 1
Product List ............................................................................................................................................... 6
Block Diagram .......................................................................................................................................... 7
Pin Assignments ........................................................................................................................................ 8
Pin Functions ........................................................................................................................................... 15
Central Processing Unit (CPU) ..................................................................................................... 18
2.1
General Registers ....................................................................................................................................
2.1.1
Data Registers (R0, R1, R2, and R3) ..................................................................................................
2.1.2
Address Registers (A0 and A1) ..........................................................................................................
2.1.3
Static Base Register (SB) ...................................................................................................................
2.1.4
Frame Base Register (FB) ..................................................................................................................
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..............................................................
2.1.6
Interrupt Table Register (INTB) .........................................................................................................
2.1.7
Program Counter (PC) ........................................................................................................................
2.1.8
Flag Register (FLG) ............................................................................................................................
2.2
High-Speed Interrupt Registers ...............................................................................................................
2.3
DMAC-Associated Registers ..................................................................................................................
19
19
19
19
19
19
19
19
19
20
20
3.
Memory ......................................................................................................................................... 21
4.
Special Function Registers (SFRs) ............................................................................................... 22
5.
Reset ............................................................................................................................................. 33
5.1
5.1.1
5.1.2
5.2
5.3
5.4
5.5
6.
Hardware Reset 1 ....................................................................................................................................
Reset at a Stable Supply Voltage ........................................................................................................
Power-on Reset ...................................................................................................................................
Hardware Reset 2 (Vdet3 detection function) .........................................................................................
Software Reset ........................................................................................................................................
Watchdog Timer Reset ............................................................................................................................
Internal Registers ....................................................................................................................................
33
33
33
35
35
35
36
Power Supply Voltage Detection Function .................................................................................... 37
6.1
Vdet3 Detection Function .......................................................................................................................
6.2
Vdet4 Detection Function .......................................................................................................................
6.2.1
Usage Notes on Vdet4 Detection Interrupt .........................................................................................
6.3
Cold Start/Warm Start Determine Function ............................................................................................
7.
41
42
44
44
Processor Mode ............................................................................................................................ 45
7.1
7.2
8.
Processor Mode ....................................................................................................................................... 45
Setting of Processor Mode ...................................................................................................................... 45
Bus ................................................................................................................................................ 49
8.1
Bus Settings ............................................................................................................................................. 49
A-1
8.1.1
Selecting External Address Bus .........................................................................................................
8.1.2
Selecting External Data Bus ...............................................................................................................
8.1.3
Selecting Separate/Multiplexed Bus ...................................................................................................
8.2
Bus Control .............................................................................................................................................
8.2.1
Address Bus and Data Bus .................................................................................................................
8.2.2
Chip-Select Output .............................................................................................................................
8.2.3
Read/Write Output Signals .................................................................................................................
8.2.4
Bus Timing .........................................................................................................................................
8.2.5
ALE Output ........................................................................................................................................
8.2.6
RDY Input ............................................................................................................................................................
8.2.7
HOLD Input ........................................................................................................................................
8.2.8
External Bus States when Accessing Internal Space ..........................................................................
8.2.9
BCLK Output .....................................................................................................................................
8.3
Page Mode Control Function ..................................................................................................................
9.
50
50
50
52
52
52
54
55
63
63
64
65
65
66
Clock Generation Circuits ............................................................................................................. 69
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.2
9.3
9.3.1
9.3.2
9.3.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.6
Types of the Clock Generation Circuit ...................................................................................................
Main Clock .........................................................................................................................................
Sub Clock ...........................................................................................................................................
On-Chip Oscillator Clock ...................................................................................................................
PLL Clock ...........................................................................................................................................
CPU Clock and BCLK ............................................................................................................................
Peripheral Function Clock .......................................................................................................................
f1, f8, f32, and f2n ..............................................................................................................................
fAD .....................................................................................................................................................
fC32 ....................................................................................................................................................
Clock Output Function ............................................................................................................................
Power Consumption Control ...................................................................................................................
CPU operating mode ..........................................................................................................................
Wait Mode ..........................................................................................................................................
Stop Mode ...........................................................................................................................................
System Clock Protect Function ...............................................................................................................
69
78
79
80
81
83
83
83
83
83
84
85
85
87
90
93
10.
Protection ...................................................................................................................................... 94
11.
Interrupts ....................................................................................................................................... 95
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.3.1
11.3.2
11.3.3
11.4
11.5
11.5.1
Types of Interrupts ..................................................................................................................................
Software Interrupts ..................................................................................................................................
Undefined Instruction Interrupt ..........................................................................................................
Overflow Interrupt ..............................................................................................................................
BRK Interrupt .....................................................................................................................................
BRK2 Interrupt ...................................................................................................................................
INT Instruction Interrupt ....................................................................................................................
Hardware Interrupts ................................................................................................................................
Special Interrupts ................................................................................................................................
DMACII Transfer Complete Interrupt ...............................................................................................
Peripheral Function Interrupt ..............................................................................................................
High-Speed Interrupt ...............................................................................................................................
Interrupts and Interrupt Vectors ..............................................................................................................
Fixed Vector Table .............................................................................................................................
A-2
95
96
96
96
96
96
96
97
97
97
97
98
99
99
11.5.2
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.6.9
11.7
11.8
11.9
11.10
Relocatable Vector Table ................................................................................................................... 99
Interrupt Request Acknowledgement .................................................................................................... 102
I Flag and IPL ................................................................................................................................... 102
Interrupt Control Registers and RLVL Register ............................................................................... 102
Interrupt Sequence ............................................................................................................................ 106
Interrupt Response Time .................................................................................................................. 107
IPL Change when Interrupt Request is Acknowledged .................................................................... 108
Saving a Register .............................................................................................................................. 108
Returning from Interrupt Routine ..................................................................................................... 109
Interrupt Priority ............................................................................................................................... 109
Interrupt Priority Level Select Circuit .............................................................................................. 109
INT Interrupt ......................................................................................................................................... 111
NMI Interrupt ........................................................................................................................................ 114
Key Input Interrupt ................................................................................................................................ 114
Address Match Interrupt ....................................................................................................................... 115
12.
Watchdog Timer .......................................................................................................................... 116
13.
DMAC ......................................................................................................................................... 120
13.1
Transfer Cycles ..................................................................................................................................... 130
13.1.1 Effect of Source and Destination Addresses .................................................................................... 130
13.1.2 Effect of the DS Register .................................................................................................................. 130
13.1.3 Effect of Software Wait State ........................................................................................................... 130
13.1.4 Effect of the RDY Signal .................................................................................................................. 130
13.2
DMA Transfer Time ............................................................................................................................. 131
13.3
Channel Priority and DMA Transfer Timing ........................................................................................ 131
14.
DMACII ....................................................................................................................................... 133
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.2
14.3
14.3.1
14.3.2
14.3.3
14.4
14.4.1
14.4.2
14.4.3
14.5
14.6
14.7
15.
DMACII Settings ..................................................................................................................................
RLVL Register .................................................................................................................................
DMACII Index .................................................................................................................................
Interrupt Control Register for the Peripheral Function ....................................................................
Relocatable Vector Table for the Peripheral Function .....................................................................
DMACII Performance ...........................................................................................................................
Transfer Data .........................................................................................................................................
Memory-to-memory Transfer ...........................................................................................................
Immediate Data Transfer ..................................................................................................................
Calculation Transfer .........................................................................................................................
Transfer Modes .....................................................................................................................................
Single Transfer .................................................................................................................................
Burst Transfer ...................................................................................................................................
Multiple Transfer ..............................................................................................................................
Chain Transfer .......................................................................................................................................
End-of-Transfer Interrupt ......................................................................................................................
Execution Time .....................................................................................................................................
133
133
135
137
137
137
137
137
138
138
138
138
138
138
139
139
140
Timers ......................................................................................................................................... 141
15.1
Timer A ................................................................................................................................................. 143
15.1.1 Timer Mode ...................................................................................................................................... 155
A-3
15.1.2 Event Counter Mode .........................................................................................................................
15.1.3 One-Shot Timer Mode ......................................................................................................................
15.1.4 Pulse Width Modulation Mode .........................................................................................................
15.2
Timer B .................................................................................................................................................
15.2.1 Timer Mode ......................................................................................................................................
15.2.2 Event Counter Mode .........................................................................................................................
15.2.3 Pulse Period Measurement Mode, Pulse Width Measurement Mode ..............................................
16.
Three-Phase Motor Control Timer Function ............................................................................... 178
16.1
Triangular Wave Modulation Mode ......................................................................................................
16.2
Sawtooth Wave Modulation Mode .......................................................................................................
16.3
Short Circuit Prevention Features .........................................................................................................
16.3.1 Prevention Against Upper/Lower Arm Short Circuit by Program Errors ........................................
16.3.2 Arm Short Circuit Prevention Using Dead Time Timer ...................................................................
16.3.3 Forced-Cutoff Function by the NMI Input .......................................................................................
17.
189
193
195
195
195
195
Serial Interfaces .......................................................................................................................... 196
17.1
UART0 to UART4 ................................................................................................................................
17.1.1 Clock Synchronous Mode ................................................................................................................
17.1.2 Clock Asynchronous (UART) Mode ................................................................................................
17.1.3 Special Mode 1 (I2C Mode) .............................................................................................................
17.1.4 Special Mode 2 .................................................................................................................................
17.1.5 Special Mode 3 (GCI Mode) ............................................................................................................
17.1.6 Special Mode 4 (SIM Mode) ............................................................................................................
18.
156
161
163
166
173
174
175
197
207
216
224
236
241
245
A/D Converter ............................................................................................................................. 251
18.1
18.1.1
18.1.2
18.1.3
18.1.4
18.1.5
18.1.6
18.1.7
18.2
18.2.1
18.2.2
18.2.3
18.2.4
18.2.5
18.2.6
18.2.7
18.3
18.4
Mode Descriptions ................................................................................................................................
One-Shot Mode .................................................................................................................................
Repeat Mode .....................................................................................................................................
Single Sweep Mode ..........................................................................................................................
Repeat Sweep Mode 0 ......................................................................................................................
Repeat Sweep Mode 1 ......................................................................................................................
Multi-Port Single Sweep Mode ........................................................................................................
Multi-Port Repeat Sweep Mode 0 ....................................................................................................
Functions ...............................................................................................................................................
Resolution .........................................................................................................................................
Sample and Hold ..............................................................................................................................
Trigger Select Function ....................................................................................................................
DMAC Operating Mode ...................................................................................................................
Extended Analog Input Pins .............................................................................................................
External Operating Amplifier (Op-Amp) Connection Mode ...........................................................
Power Consumption Reduce Function .............................................................................................
Read from the AD0i Register (i = 0 to 7) ..............................................................................................
Output Impedance of Sensor Equivalent Circuit under A/D Conversion .............................................
A-4
259
260
261
262
263
264
266
267
268
268
268
268
268
268
269
269
270
270
19.
D/A Converter ............................................................................................................................. 272
20.
CRC Calculation ......................................................................................................................... 274
21.
X/Y Conversion ........................................................................................................................... 276
22.
Programmable I/O Ports ............................................................................................................. 279
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
Port Pi Direction Register (PDi Register, i = 0 to 15) ...........................................................................
Port Pi Register (Pi Register, i = 0 to 15) ..............................................................................................
Function Select Register A (PSj Register, j = 0 to 3) ............................................................................
Function Select Register B (PSLk Register, k = 0 to 3) ........................................................................
Function Select Register C (PSC Register) ...........................................................................................
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) .................................................................
Port Control Register (PCR Register) ...................................................................................................
Analog Input and Other Peripheral Function Input ...............................................................................
279
279
279
279
279
280
280
280
23.
Electrical Characteristics ............................................................................................................. 299
24.
Usage Notes .............................................................................................................................. 331
24.1
24.1.1
24.1.2
24.1.3
24.2
24.2.1
24.2.2
24.3
24.3.1
24.3.2
24.3.3
24.3.4
24.4
24.5
24.5.1
24.5.2
24.5.3
24.5.4
24.5.5
24.6
24.7
24.7.1
24.7.2
24.7.3
24.8
24.9
24.9.1
24.9.2
24.9.3
24.9.4
24.10
Power Supply ........................................................................................................................................
Power-on ...........................................................................................................................................
Power Supply Ripple ........................................................................................................................
Noise .................................................................................................................................................
Special Function Registers (SFRs) ........................................................................................................
100 Pin-Package ...............................................................................................................................
Register Settings ...............................................................................................................................
Clock Generation Circuits .....................................................................................................................
Main Clock .......................................................................................................................................
Sub Clock .........................................................................................................................................
Clock Dividing Ratio ........................................................................................................................
Power Consumption Control ............................................................................................................
Protection ..............................................................................................................................................
Interrupts ...............................................................................................................................................
ISP Setting ........................................................................................................................................
NMI Interrupt ...................................................................................................................................
INT Interrupt .....................................................................................................................................
Changing Interrupt Control Register ................................................................................................
Changing RLVL Register .................................................................................................................
DMAC ...................................................................................................................................................
Timers ...................................................................................................................................................
Timer A, Timer B .............................................................................................................................
Timer A .............................................................................................................................................
Timer B .............................................................................................................................................
Three-Phase Motor Control Timer Function .........................................................................................
Serial Interfaces .....................................................................................................................................
Changing UiBRG Register (i = 0 to 4) .............................................................................................
Clock Synchronous Mode ................................................................................................................
UART Mode .....................................................................................................................................
Special Mode 1 (I2C Mode) .............................................................................................................
A/D Converter .......................................................................................................................................
A-5
331
331
332
332
333
333
333
334
334
334
334
334
337
338
338
338
338
340
340
341
342
342
342
344
345
346
346
346
346
346
347
24.11
Programmable I/O Ports ........................................................................................................................ 349
Appendix 1. Package Dimensions ................................................................................................. 350
Index ..................................................................................................................................................... 351
A-6
Special Function Register (SFR) Page Reference
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register
Symbol
Page
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
46
47
71, 118
72
Address Match Interrupt Enable Register
Protect Register
External Data Bus Width Control Register
Main Clock Division Register
Oscillation Stop Detection Register
Watchdog Timer Start Register
Watchdog Timer Control Register
AIER
PRCR
DS
MCD
CM2
WDTS
WDC
115
94
49
73
74
40, 119
119
Address Match Interrupt Register 0
RMAD0
115
Processor Mode Register 2
PM2
76
Address Match Interrupt Register 1
RMAD1
115
Voltage Detection Register 2
VCR2
38
Address Match Interrupt Register 2
RMAD2
115
Voltage Detection Register 1
VCR1
38
Address Match Interrupt Register 3
RMAD3
115
PLL Control Register 0
PLL Control Register 1
PLC0
PLC1
75
75
Address Match Interrupt Register 4
RMAD4
115
Address Match Interrupt Register 5
RAMD5
115
Vdet4 Detection Interrupt Register
D4INT
39
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
Address Match Interrupt Register 6
Address Match Interrupt Register 7
Blank spaces are reserved. No access is allowed.
RMAD6
RMAD7
115
115
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Page
External Space Wait Control Register 0
External Space Wait Control Register 1
External Space Wait Control Register 2
External Space Wait Control Register 3
Page Mode Wait Control Register 0
Page Mode Wait Control Register 1
EWCR0
EWCR1
EWCR2
EWCR3
PWCR0
PWCR1
DMA0 Control Register
Timer B5 Interrupt Control Register
DMA2 Control Register
UART2 Receive/ACK Interrupt Control
Register
Timer A0 Interrupt Control Register
UART3 Receive/ACK Interrupt Control
Register
Timer A2 Interrupt Control Register
UART4 Receive/ACK Interrupt Control
Register
Timer A4 Interrupt Control Register
UART0/UART3 Bus Conflict Detection
Interrupt Control Register
UART0 Receive/ACK Interrupt Control
Register
A/D0 Conversion Interrput Control Register
UART1 Receive/ACK Interrupt Control
Register
I
Timer B1 Interrupt Control Register
DM0IC
TB5IC
DM2IC
TB1IC
103
Timer B3 Interrupt Control Register
TB3IC
103
INT5 Interrupt Control Register
INT5IC
104
INT3 Interrupt Control Register
INT3IC
104
INT1 Interrupt Control Register
INT1IC
104
Blank spaces are reserved. No access is allowed.
B-1
Symbol
55
55
55
55
66
67
S2RIC
TA0IC
S3RIC
TA2IC
S4RIC
103
TA4IC
BCN0IC/
BCN3IC
S0RIC
AD0IC
S1RIC
Special Function Register (SFR) Page Reference
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
to
02BFh
Register
Symbol
Page
DMA1 Interrupt Control Register
UART2 Transmit/NACK Interrupt Control
Register
DMA3 Interrupt Control Register
UART3 Transmit/NACK Interrupt Control
Register
Timer A1 Interrupt Control Register
UART4 Transmit/NACK Interrupt Control
Register
Timer A3 Interrupt Control Register
UART2 Bus Conflict Detection Interrupt
Control Register
UART0 Transmit/NACK Interrupt Control
Register
UART1/UART4 Bus Conflict Detection
Interrupt Control Register
UART1 Transmit Complete Interrupt Control
Register
Key Input Interrupt Control Register
Timer B0 Interrupt Control Register
KUPIC
TB0IC
Timer B2 Interrupt Control Register
II/O Interrupt Control Register 3/
CAN2 Interrupt Control Register 1
Timer B4 Interrupt Control Register
TB2IC
IIO3IC/
CAN21IC
TB4IC
103
INT4 Interrupt Control Register
INT4IC
104
INT2 Interrupt Control Register
INT2IC
104
INT0IC
103
104
INT0 Interrupt Control Register
Exit Priority Register
Blank spaces are reserved. No access is allowed.
DM1IC
S2TIC
DM3IC
S3TIC
TA1IC
S4TIC
TA3IC
103
BCN2IC
S0TIC
BCN1IC/
BCN4IC
S1TIC
RLVL
103
105, 134
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
Register
X0R, Y0R
X1 Register, Y1 Register
X1R, Y1R
X2 Register, Y2 Register
X2R, Y2R
X3 Register, Y3 Register
X3R, Y3R
X4 Register, Y4 Register
X4R, Y4R
X5 Register, Y5 Register
X5R, Y5R
X6 Register, Y6 Register
X6R, Y6R
X7 Register, Y7 Register
X7R, Y7R
X8 Register, Y8 Register
X8R, Y8R
X9 Register, Y9 Register
X9R, Y9R
Page
276
X/Y Control Register
X10R,
Y10R
X11R,
Y11R
X12R,
Y12R
X13R,
Y13R
X14R,
Y14R
X15R,
Y15R
XYC
276
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Baud Rate Register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
202
201
200
199
198
204
X10 Register, Y10 Register
X11 Register, Y11 Register
X12 Register, Y12 Register
X13 Register, Y13 Register
X14 Register, Y14 Register
X15 Register, Y15 Register
UART1 Transmit Buffer Register
U1TB
206
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
203
204
UART1 Receive Buffer Register
U1RB
206
UART4 Special Mode Register 4
UART4 Special Mode Register 3
UART4 Special Mode Register 2
UART4 Special Mode Register
UART4 Transmit/Receive Mode Register
UART4 Baud Rate Register
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
202
201
200
199
198
204
UART4 Transmit Buffer Register
U4TB
206
UART4 Transmit/Receive Control Register 0
UART4 Transmit/Receive Control Register 1
U4C0
U4C1
203
204
UART4 Receive Buffer Register
U4RB
206
Timer B3, B4, B5 Count Start Flag
TBSR
171
Timer A11 Register
TA11
Timer A21 Register
TA21
Timer A41 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set
Counter
INVC0
INVC1
IDB0
IDB1
DTT
180
181
187
187
186
ICTB2
185
030Eh
030Fh
Blank spaces are reserved. No access is allowed.
B-2
Symbol
X0 Register, Y0 Register
187
Special Function Register (SFR) Page Reference
Address
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
044Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
Register
Symbol
Page
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
167, 168,
169
External Interrupt Source Select Register
IFSR
113, 205
UART3 Special Mode Register 4
UART3 Special Mode Register 3
UART3 Special Mode Register 2
UART3 Special Mode Register
UART3 Transmit/Receive Mode Register
UART3 Baud Rate Register
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
202
201
200
199
198
204
UART3 Transmit Buffer Register
U3TB
206
UART3 Transmit/Receive Control Register 0
UART3 Transmit/Receive Control Register 1
U3C0
U3C1
203
204
UART3 Receive Buffer Register
U3RB
170
206
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Baud Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
202
201
200
199
198
204
UART2 Transmit Buffer Register
U2TB
206
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
203
204
UART2 Receive Buffer Register
U2RB
206
Count Start Register
TABSR
Clock Prescaler Reset Registe
One-Shot Start Register
Trigger Select Register
Up/Down Flag
CPSRF
ONSF
TRGSR
UDF
152, 171,
188
77
153
151, 184
150
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
Count Source Prescaler Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
149
170
145, 146,
147, 148
167, 168,
169
185
77, 144
Address
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
Register
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Baud Rate Register
B-3
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
Page
202
201
200
199
198
204
UART0 Transmit Buffer Register
U0TB
206
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
203
204
UART0 Receive Buffer Register
U0RB
206
DMA0 Request Source Select Register
DMA1 Request Source Select Register
DMA2 Request Source Select Register
DMA3 Request Source Select Register
DM0SL
DM1SL
DM2SL
DM3SL
122
CRC Data Register
CRCD
274
CRC Input Register
CRCIN
274
A/D0 Register 0
AD00
A/D0 Register 1
AD01
A/D0 Register 2
AD02
A/D0 Register 3
AD03
A/D0 Register 4
AD04
A/D0 Register 5
AD05
A/D0 Register 6
AD06
A/D0 Register 7
AD07
A/D0 Control Register 4
AD0CON4
258
A/D0 Control Register 2
A/D0 Control Register 3
A/D0 Control Register 0
A/D0 Control Register 1
D/A Register 0
AD0CON2
AD0CON3
AD0CON0
AD0CON1
DA0
256
257
254
255
273
D/A Register 1
DA1
273
D/A Control Register
DACON
273
Function Select Register C
PSC
290
258
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
Symbol
Special Function Register (SFR) Page Reference
Address
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
Register
Function Select Register A0
Function Select Register A1
Function Select Register B0
Function Select Register B1
Function Select Register A2
Function Select Register A3
Function Select Register B2
Function Select Register B3
Symbol
PS0
PS1
PSL0
PSL1
PS2
PS3
PSL2
PSL3
Page
286
286
288
288
287
287
289
289
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Port P14 Register
Port P15 Register
Port P14 Direction Register
Port P15 Direction Register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
P14
P15
PD14
PD15
285
285
284
284
285
285
284
284
285
285
284
284
285
285
284
284
285
285
284
284
Pull-Up Control Register 2
Pull-Up Control Register 3
Pull-Up Control Register 4
PUR2
PUR3
PUR4
292
293
294
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
285
285
284
284
285
285
284
284
285
285
284
284
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
291
291
Port Control Register
PCR
295
Blank spaces are reserved. No access is allowed.
B-4
M32C/8A Group
RENESAS MCU
1.
Overview
1.1
Features
The M32C/8A Group is a single-chip control MCU, fabricated using high-performance silicon gate CMOS
technology, embedding the M32C/80 Series CPU core. The M32C/8A Group is housed in 144-pin and 100-pin
plastic molded LQFP packages.
With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process
complex instructions by less bytes and execute instructions at higher speed.
The M32C/8A Group has a multiplier and DMAC adequate for office automation, communication devices and
industrial equipment, and other high-speed processing applications.
The M32C/8A Group is ROMless device.
Use the M32C/8A Group in microprocessor mode after reset.
1.1.1
Applications
Audio, cameras, office/communication/portable equipment, etc.
1.1.2
Specifications
Tables 1.11.3 to 1.4 lists the specifications of the M32C/8A Group.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 1 of 352
M32C/8A Group
Table 1.1
Item
CPU
1. Overview
Specifications (144-Pin Version) (1)
Function
Central processing unit
Specification
M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,
multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns ( f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V)
41.7 ns ( f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V)
• Operating mode: microprocessor mode
Memory
ROM, RAM
See Table 1.5 Product List.
Power Supply Voltage Detection
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
External
Bus / memory expansion • Address space: 16 Mbyte
Bus
function
• External bus interface: 1 to 7 wait states can be inserted,
Expansion
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate and multiplexed bus
formats, switchable data bus width (8-bit or 16-bit)
Clock
Clock generation circuits • 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detection function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
Interrupts
• Interrupt vectors: 70
• External interrupt inputs:
NMI × 1
INT × 3 (16-bit external bus width)
INT × 6 (8- bit external bus width)
Key input × 4
• Interrupt priority levels: 7
Watchdog Timer
15-bit × 1 (with prescaler)
DMA
DMAC
• 4 channels, cycle steal method
• Trigger sources: 31
• Transfer modes: 2 (single transfer and repeat transfer)
DMAC II
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode)
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
Timer function for
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
3-phase motor control
and timer B2)
On-chip dead time timer
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 2 of 352
M32C/8A Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications (144-Pin Version) (2)
Function
UART0 to UART4
A/D Converter
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous / asynchronous × 5
I2C bus (optional)(2), special mode 2, GCI mode, SIM mode
IEBus (optional)(1)(2)
10-bit resolution x 18 channels, includes sample and hold
function
8-bit resolution × 2 channels
CRC-CCITT (X16 + X12 + X5 + 1) compliant
X/Y Converter
16 bits x 16 bits
I/O Ports
Programmable I/O ports • Input only: 1
• CMOS I/O:
81 (8-bit external bus width)
73 (16-bit external bus width)
with selectable pull-up resistor
• N channel open drain ports: 2
Operating Frequency /
32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC1
24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1
Supply Voltage
Current Consumption
28 mA (32 MHz / VCC1 = VCC2 = 5 V)
22 mA (24 MHz / VCC1 = VCC2 = 3.3 V)
45 μA (approx. 1 MHz / VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode → wait mode)
0.8 μA (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)(2)
Package
144-pin LQFP (PLQP0144KA-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Please contact a Renesas sales office to use the optional feature.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 3 of 352
M32C/8A Group
Table 1.3
Item
CPU
1. Overview
Specifications (100-Pin Version) (1)
Function
Central processing unit
Specification
M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,
multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHZ / VCC1 = 4.2 to 5.5 V)
41.7 ns (f(CPU) = 24 MHZ / VCC1 = 3.0 to 5.5 V)
• Operating mode: microprocessor mode
Memory
ROM, RAM
See Table 1.5 Product List.
Power Supply Voltage Detection
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
External
Bus / memory expansion • Address space: 16 Mbyte
Bus
function
• External bus interface: 1 to 7 wait states can be inserted,
Expansion
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
Clock
Clock generation circuits • 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detection function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
Interrupts
• Interrupt vectors: 70
• External interrupt inputs:
NMI × 1
INT × 3 (16-bit external bus width)
INT × 6 (8- bit external bus width)
Key input × 4
• Interrupt priority levels: 7
Watchdog Timer
15-bit × 1 (with prescaler)
DMA
DMAC
• 4 channels, cycle steal method
• Trigger sources: 31
• Transfer modes: 2 (single transfer and repeat transfer)
DMACII
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
Timer function for
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
3-phase motor control
and timer B2)
On-chip dead time timer
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 4 of 352
M32C/8A Group
Table 1.4
Item
Serial
Interface
1. Overview
Specifications (100-Pin Version) (2)
Function
UART0 to UART4
A/D Converter
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous / asynchronous × 5
I2C bus (optional)(2), special mode 2, GCI mode, SIM mode
IEBus (optional)(1)(2)
10-bit resolution x 10 channels, includes sample and hold
function
8-bit resolution × 2 channels
CRC-CCITT (X16 + X12 + X5 + 1) compliant
X/Y Converter
16 bits x 16 bits
I/O Ports
Programmable I/O ports • Input only: 1
• CMOS I/O:
45 (8-bit external bus width)
37 (16-bit external bus width)
with selectable pull-up resistor
• N channel open drain ports: 2
Operating Frequency /
32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 to VCC1
24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 to VCC1
Supply Voltage
Current Consumption
28 mA (32 MHz / VCC1 = VCC2 = 5 V)
22 mA (24 MHz / VCC1 = VCC2 = 3.3 V)
45 μA (approx. 1 MHz / VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode → wait mode)
0.8 μA (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)(2)
Package
100-pin LQFP (PLQP0100KB-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Please contact a Renesas sales office for optional features.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 5 of 352
M32C/8A Group
1.2
1. Overview
Product List
Table 1.5 lists product information. Figure 1.1 shows product numbering system.
Table 1.5
Product List (M32C/8A)
Type No.
M308A0SGP
M308A3SGP
M308A5SGP
Package
PLQP0100KB-A (100P6Q-A)
(P) PLQP0100KB-A (100P6Q-A)
(P) PLQP0144KA-A (144P6Q-A)
Current as of July. 2007
ROM
Capacity
−
RAM
Capacity
12KB
24KB
24KB
Remarks
ROMless
ROMless
ROMless
(P): Under planning
Part No.
M30 8A x S GP
Package type option
GP: Package PLQP0100KB-A (100P6Q-A)
Package PLQP0144KA-A (144P6Q-A)
Memory type
S: ROMless version
Shows RAM capacity, pin count, etc.
(The value itself has no specific meaning)
M32C/8A Group
M16C Family
Figure 1.1
Product Numbering System
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 6 of 352
M32C/8A Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a M32C/8A Group block diagram.
8
8
(2)
8
(2)
Port P0
8
(2)
Port P1
Port P2
8
(2)
8
(2)
Port P3
Port P4
8
8
Port P6
Port P7
(2)
Port P5
<VCC2>
<VCC1>
Internal peripheral functions
10-bit A/D converter:
1 circuit, 18 input (3)
Timers (16-bit)
Output (timer A): 5
Input (timer B): 6
Clock generation circuits:
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
8-bit D/A converters:
2 circuits
Three-phase motor
control circuit
DMAC: 4 channels
DMAC II
Watchdog timer (15 bits)
M32C/80 Series CPU core
Serial Interface: 5 channels
clock synchronous/
asynchronous
R0H
R0L
R1H
R1L
FLG
ISP
R3
USP
A0
PC
A1
X/Y converter:
16 bits × 16 bits
(1)
<VCC2>
Port P13
8
(1)
Port P12
8
(1)
Port P11
5
SVF
FB
SVP
SB
VCT
(1)
Port P15
8
RAM
INTB
R2
CRC calculation circuit
X16 + X12 + X5 + 1 (CCITT)
Memory
(1)
Port P14
7
Multiplier
<VCC1>
Port P10
8
Port P9
8
P8_5
Port P8
7
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Ports P0 to P5 function as bus control pins when using in microprocessor mode .
Port P1 can function as I/O port when using with 8-bit external bus width only.
3. 18 channels are available in the 144-pin package. 10 channels are available in the 100-pin package.
Figure 1.2
M32C/8A Group Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 7 of 352
M32C/8A Group
1.4
1. Overview
Pin Assignments
Figures 1.3 and 1.4 show a pin assignment (top view).
A19
A18
A9 , [ A9 / D9 ]
A10 , [ A10 / D10
A11 , [ A11 / D11
A12 , [ A12 / D12
A13 , [ A13 / D13
A14 , [ A14 / D14
A15 , [ A15 / D15
A16
A17
73
74
75
76
77
78
79
80
81
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
82
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
<VCC2>
M32C/8A Group
PLQP0144KA-A
(144P6Q-A)
(top view)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
2
1
<VCC1>
P4_4 / CS3 / A20
P4_5 / CS2 / A21
P4_6 / CS1 / A22
P4_7 / CS0 / A23
P12_5
P12_6
P12_7
P5_0 / WRL / WR
P5_1 / WRH / BHE
P5_2 / RD
P5_3 / CLKOUT / BCLK / ALE
P13_0
P13_1
VCC2
P13_2
VSS
P13_3
P5_4 / HLDA / ALE
P5_5 / HOLD
P5_6 / ALE
P5_7 / RDY
P13_4
P13_5
P13_6
P13_7
P6_0 / CTS0 / RTS0 / SS0
P6_1 / CLK0
P6_2 / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1
P6_5 / CLK1
VSS
P6_6 / RXD1 / SCL1 / STXD1
VCC1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
ANEX1 / TXD4 / SDA4 / SRXD4
ANEX0 / CLK4
DA1 / SS4 / RTS4 / CTS4 / TB4IN
DA0 / SS3 / RTS3 / CTS3 / TB3IN
SRXD3 / SDA3 / TXD3 / TB2IN
STXD3 / SCL3 / RXD3 / TB1IN
CLK3 / TB0IN
/ P9_6
/ P9_5
/ P9_4
/ P9_3
/ P9_2
/ P9_1
/ P9_0
P14_6
P14_5
P14_4
P14_3
P14_2
P14_1
P14_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
U / TA4IN / P8_1
U / TA4OUT / P8_0
TA3IN / P7_7
TA3OUT / P7_6
W / TA2IN / P7_5
W / TA2OUT / P7_4
SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
CLK2 / V / TA1OUT / P7_2
(1) STXD2 / SCL2 / RXD2 / TB5IN / TA0IN / P7_1
( note 2 )
98
99
100
101
102
103
104
105
106
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
11
D8 / P1_0
D7 / P0_7
D6 / P0_6
D5 / P0_5
D4 / P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
D3 / P0_3
D2 / P0_2
D1 / P0_1
D0 / P0_0
AN15_7 / P15_7
AN15_6 / P15_6
AN15_5 / P15_5
AN15_4 / P15_4
AN15_3 / P15_3
AN15_2 / P15_2
AN15_1 / P15_1
VSS
AN15_0 / P15_0
VCC1
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
107
108
P1_1 /
P1_2 /
P1_3 /
P1_4 /
P1_5 /
P1_6 /
P1_7 /
P2_0 /
P2_1 /
P2_2 /
P2_3 /
P2_4 /
P2_5 /
P2_6 /
P2_7 /
VSS
P3_0 /
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1 /
P3_2 /
P3_3 /
P3_4 /
P3_5 /
P3_6 /
P3_7 /
P4_0 /
P4_1 /
VSS
P4_2 /
VCC2
P4_3 /
D9
D10
D11
D12
INT3 / D13
INT4 / D14
INT5 / D15
A0 , [ A0 / D0
A1 , [ A1 / D1
A2 , [ A2 / D2
A3 , [ A3 / D3
A4 , [ A4 / D4
A5 , [ A5 / D5
A6 , [ A6 / D6
A7 , [ A7 / D7
A8 , [ A8 / D8 ]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
( note 3 )
NOTES:
1. P7_0 and P7_1 are N-channel open drain output.
2. Confirm the pin 1 position on the package by referring to Package Dimensions.
3. Pin names in square brackets [ ] correspond to signal function names.
Figure 1.3
Pin Assignment for 144-pin Package
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 8 of 352
M32C/8A Group
Table 1.6
Pin
No.
1. Overview
144-Pin Version List of Pin Names (1)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
1
2
3
P9_6
P9_5
P9_4
TB4IN
CTS4/RTS4/SS4
4
P9_3
TB3IN
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P9_2
P9_1
P9_0
P14_6
P14_5
P14_4
P14_3
P14_2
P14_1
P14_0
TB2IN
TB1IN
TB0IN
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
RXD3/SCL3/STXD3
CLK3
BYTE
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
TXD4/SDA4/SRXD4
CLK4
P8_7
P8_6
P8_5
NMI
25
P8_4
INT2
26
P8_3
INT1
27
P8_2
INT0
28
P8_1
TA4IN/U
29
P8_0
TA4OUT/U
30
P7_7
TA3IN
31
P7_6
TA3OUT
32
P7_5
TA2IN/W
33
P7_4
TA2OUT/W
34
P7_3
TA1IN/V
35
P7_2
TA1OUT/V
CTS2/RTS2/SS2
CLK2
36
P7_1
TA0IN/TB5IN
RXD2/SCL2/STXD2
37
P7_0
TA0OUT
TXD2/SDA2/SRXD2
38
39
40
41
42
43
P6_7
TXD1/SDA1/SRXD1
P6_6
RXD1/SCL1/STXD1
P6_5
P6_4
CTS1/RTS1/SS1
44
P6_3
TXD0/SDA0/SRXD0
45
P6_2
RXD0/SCL0/STXD0
46
P6_1
CLK0
47
P6_0
CTS0/RTS0/SS0
48
49
50
P13_7
P13_6
P13_5
VCC1
VSS
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
CLK1
Page 9 of 352
Analog Pin
ANEX1
ANEX0
DA1
DA0
Bus Control Pin
M32C/8A Group
Table 1.7
Pin
No.
1. Overview
144-Pin Version List of Pin Names (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
52
P13_4
P5_7
RDY
53
P5_6
ALE
54
P5_5
HOLD
55
P5_4
HLDA/ALE
56
57
58
59
60
61
62
63
P13_3
VSS
P13_2
VCC2
CLKOUT
P13_1
P13_0
P5_3
P5_2
BCLK/ALE
RD
64
P5_1
WRH/BHE
65
P5_0
WRL/WR
66
67
68
69
P12_7
P12_6
P12_5
P4_7
CS0/A23
70
P4_6
CS1/A22
71
P4_5
CS2/A21
72
P4_4
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P4_3
CS3/A20
A19
P4_2
A18
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
A17
A16
A15,[A15/D15]
A14,[A14/D14]
A13,[A13/D13]
A12,[A12/D12]
A11,[A11/D11]
A10,[A10/D10]
A9,[A9/D9]
P3_0
A8,[A8/D8]
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
A7,[A7/D7]
A6,[A6/D6]
A5,[A5/D5]
A4,[A4/D4]
A3,[A3/D3]
A2,[A2/D2]
A1,[A1/D1]
VCC2
VSS
VCC2
VSS
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 10 of 352
M32C/8A Group
Table 1.8
Pin
No.
1. Overview
144-Pin Version List of Pin Names (3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
101
102
P2_0
P1_7
INT5
A0,[A0/D0]
D15
103
P1_6
INT4
D14
104
P1_5
INT3
D13
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130 VSS
131
132 VCC1
133
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
P0_3
P0_2
P0_1
P0_0
P15_7
P15_6
P15_5
P15_4
P15_3
P15_2
P15_1
AN15_7
AN15_6
AN15_5
AN15_4
AN15_3
AN15_2
AN15_1
P15_0
AN15_0
P10_7
KI3
AN_7
134
P10_6
KI2
AN_6
135
P10_5
KI1
AN_5
136
P10_4
KI0
137
138
139
140 AVSS
141
142 VREF
143 AVCC
144
P10_3
P10_2
P10_1
AN_3
AN_2
AN_1
P10_0
AN_0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P9_7
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
AN_4
RXD4/SCL4/STXD4
Page 11 of 352
ADTRG
M32C/8A Group
1. Overview
A9 / D9 ]
[ A10 / D10
[ A11 / D11
[ A12 / D12
[ A13 / D13
[ A14 / D14
[ A15 / D15
A9 ,
A10
A11
A12
A13
A14
A15
A16
A17
[
,
,
,
,
,
,
A8 , [ A8 / D8 ]
]
]
]
]
]
]
D2
D3
D4
D5
D6
D7
/
/
/
/
/
/
A2
A3
A4
A5
A6
A7
[
[
[
[
[
[
,
,
,
,
,
,
A2
A3
A4
A5
A6
A7
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
50
<VCC2>
77
49
78
48
79
47
80
46
81
45
82
44
83
43
M32C/8A Group
84
85
42
41
86
40
87
39
88
38
PLQP0100KB-A
(100P6Q-A)
(top view)
89
90
91
92
37
36
35
34
93
33
94
32
95
31
96
30
97
29
98
28
<VCC1>
99
27
100
P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2(1)
P7_2 / TA1OUT / V / CLK2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NMI
INT2
INT1
INT0
U / TA4IN
U / TA4OUT
TA3IN
TA3OUT
W / TA2IN
W / TA2OUT
SS2 / RTS2 / CTS2 / V / TA1IN
11
P4_2 / A18
P4_3 / A19
P4_4 / CS3 / A20
P4_5 / CS2 / A21
P4_6 / CS1 / A22
P4_7 / CS0 / A23
P5_0 / WRL / WR
P5_1 / WRH / BHE
P5_2 / RD
P5_3 / CLKOUT / BCLK / ALE
P5_4 / HLDA / ALE
P5_5 / HOLD
P5_6 / ALE
P5_7 / RDY
P6_0 / CTS0 / RTS0 / SS0
P6_1 / CLK0
P6_2 / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2(1)
VSS
XIN
VCC1
/ P8_5
/ P8_4
/ P8_3
/ P8_2
/ P8_1
/ P8_0
/ P7_7
/ P7_6
/ P7_5
/ P7_4
/ P7_3
10
9
8
7
6
5
4
3
2
DA1 / SS4 / RTS4 / CTS4
DA0 / SS3 / RTS3 / CTS3
SRXD3 / SDA3 / TXD3
STXD3 / SCL3 / RXD3
CLK3
/
/
/
/
/
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
/
/
/
/
/
P9_4
P9_3
P9_2
P9_1
P9_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
(note 2)
26
1
D10 / P1_2
D9 / P1_1
D8 / P1_0
D7 / P0_7
D6 / P0_6
D5 / P0_5
D4 / P0_4
D3 / P0_3
D2 / P0_2
D1 / P0_1
D0 / P0_0
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
ANEX1 / SRXD4 / SDA4 / TXD4 / P9_6
ANEX0 / CLK4 / P9_5
74
75
P1_3 /
P1_4 /
P1_5 /
P1_6 /
P1_7 /
P2_0 /
P2_1 /
P2_2 /
P2_3 /
P2_4 /
P2_5 /
P2_6 /
P2_7 /
VSS
P3_0 /
VCC2
P3_1 /
P3_2 /
P3_3 /
P3_4 /
P3_5 /
P3_6 /
P3_7 /
P4_0 /
P4_1 /
D11
D12
INT3 / D13
INT4 / D14
INT5 / D15
A0 , [ A0 / D0 ]
A1 , [ A1 / D1 ]
]
]
]
]
]
]
(note 3)
NOTES:
1. P7_0 and P7_1 are N-channel open drain output.
2. Confirm the pin 1 position on the package by referring to Package Dimensions.
3. Pin names in square brackets [ ] correspond to signal function names.
Figure 1.4
Pin Assignment for 100-pin Package
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 12 of 352
M32C/8A Group
Table 1.9
Pin
No.
1. Overview
100-Pin Version List of Pin Names (1)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
1
P9_4
TB4IN
CTS4/RTS4/SS4
DA1
2
P9_3
TB3IN
DA0
3
4
5
6
7
8
9
10
P9_2
P9_1
P9_0
TB2IN
TB1IN
TB0IN
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
RXD3/SCL3/STXD3
CLK3
11
12
13
14
BYTE
CNVSS
XCIN
XCOUT
Bus Control Pin
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
15
P8_5
NMI
16
P8_4
INT2
17
P8_3
INT1
18
P8_2
INT0
19
P8_1
TA4IN/U
20
P8_0
TA4OUT/U
21
P7_7
TA3IN
22
P7_6
TA3OUT
23
P7_5
TA2IN/W
24
P7_4
TA2OUT/W
25
P7_3
TA1IN/V
CTS2/RTS2/SS2
26
P7_2
TA1OUT/V
CLK2
27
P7_1
TA0IN/TB5IN
RXD2/SCL2/STXD2
28
P7_0
TA0OUT
TXD2/SDA2/SRXD2
29
P6_7
TXD1/SDA1/SRXD1
30
P6_6
RXD1/SCL1/STXD1
31
P6_5
CLK1
32
P6_4
CTS1/RTS1/SS1
33
P6_3
TXD0/SDA0/SRXD0
34
P6_2
RXD0/SCL0/STXD0
35
P6_1
CLK0
36
P6_0
CTS0/RTS0/SS0
37
P5_7
RDY
38
P5_6
ALE
39
P5_5
HOLD
40
P5_4
HLDA/ALE
P5_3
BCLK/ALE
42
P5_2
RD
43
P5_1
WRH/BHE
44
P5_0
WRL/WR
45
P4_7
CS0/A23
46
P4_6
CS1/A22
47
P4_5
CS2/A21
48
P4_4
CS3/A20
49
P4_3
A19
50
P4_2
A18
41
CLKOUT
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 13 of 352
M32C/8A Group
Table 1.10
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1. Overview
100-Pin Version List of Pin Names (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A17
A16
A15,[A15/D15]
A14,[A14/D14]
A13,[A13/D13]
A12,[A12/D12]
A11,[A11/D11]
A10,[A10/D10]
A9,[A9/D9]
P3_0
A8,[A8/D8]
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
INT5
A7,[A7/D7]
A6,[A6/D6]
A5,[A5/D5]
A4,[A4/D4]
A3,[A3/D3]
A2,[A2/D2]
A1,[A1/D1]
A0,[A0/D0]
D15
72
P1_6
INT4
D14
73
P1_5
INT3
D13
74
75
76
77
78
79
80
81
82
83
84
85
86
87
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
KI3
AN_7
88
P10_6
KI2
AN_6
89
P10_5
KI1
AN_5
90
P10_4
KI0
91
92
93
94
95
96
97
98
P10_3
P10_2
P10_1
AN_3
AN_2
AN_1
P10_0
AN_0
99
100
VCC2
VSS
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AN_4
AVSS
VREF
AVCC
P9_7
RXD4/SCL4/STXD4
P9_6
P9_5
TXD4/SDA4/SRXD4
CLK4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 14 of 352
ADTRG
ANEX1
ANEX0
M32C/8A Group
1.5
1. Overview
Pin Functions
Table 1.11
Item
Power supply
Analog power
supply input
Reset input
Pin Functions (1) (100-Pin Package and 144-Pin Package)
Pin Name
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
CNVSS
External data
bus width
select input
Bus control
Pins
BYTE
D0 to D7
D8 to D15
A0 to A22
A23
A0/D0 to
A7/D7
I/O
Supply
Description
Type Voltage
−
−
Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin.
The input condition of VCC1 ≥ VCC2 must be met.
−
VCC1 Power supply input pins to the A/D converter and D/A converter.
Connect the AVCC pin to VCC1, and the AVSS pin to VSS.
I
VCC1 The MCU is placed in a reset state when applying an “L” signal to
the RESET pin.
I
VCC1 This pin switches processor mode. Apply an “H” signal to the
CNVSS pin to start up in microprocessor mode.
I
VCC1 This pin switches data bus width in external memory space 3. A
data bus is 16 bits wide when the BYTE pin is held “L” and 8 bits
wide when it is held “H”.
I/O
VCC2 Data (D0 to D7) input/output pins while accessing an external
memory space with separate bus.
I/O
VCC2 Data (D8 to D15) inputs/output pins while accessing an external
memory space with 16-bit separate bus.
O
VCC2 Address bits (A0 to A22) output pins.
O
VCC2 Inverted address bit (A23) output pin.
I/O
VCC2
A8/D8 to
A15/D15
I/O
VCC2
CS0 to CS3
O
VCC2
WRL/WR
WRH/BHE
RD
O
VCC2
ALE
O
VCC2
HOLD
I
VCC2
HLDA
O
VCC2
RDY
I
VCC2
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 15 of 352
Data (D0 to D7) input/output and 8 low-order address bits (A0 to
A7) output are performed by time-sharing these pins while
accessing an external memory space with multiplexed bus.
Data (D8 to D15) input/output and 8 middle-order address bits (A8
to A15) output are performed by time-sharing these pins while
accessing an external memory space with 16-bit multiplexed bus.
Chip-select signal output pins used to specify external devices.
WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH
can be switched with WR and BHE by program.
• WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is written to an even
address in external memory space while an “L” is output from the
WRL pin. Data is written to an odd address while an “L” is output
from the WRH pin.
Data is read while an “L” is output from the RD pin.
• WR, BHE and RD are selected:
Data is written while an “L” is output from the WR pin.
Data is read while an “L” is output from the RD pin.
Data in odd address is accessed while an “L” is output from the
BHE pin. Select WR, BHE and RD when an external data bus is
8 bits wide.
ALE signal is used for the external devices to latch address signals
when the multiplexed bus is selected.
The MCU is placed in a hold state while an “L” signal is applied to
the HOLD pin.
The HLDA pin outputs an “L” while the MCU is placed in a hold
state
Bus is placed in a wait state while an “L” signal is applied to the
RDY pin.
M32C/8A Group
Table 1.12
Item
Main clock
input
Main clock
output
Sub clock
input
Sub clock
output
BCLK output
Clock output
1. Overview
Pin Functions (2) (100-Pin Package and 144-Pin Package)
Pin Name
XIN
XOUT
I/O
Supply
Description
Type Voltage
I
VCC1 Input/output pins for the main clock oscillation circuit. Connect a
ceramic resonator or crystal oscillator between XIN and XOUT. To
O
VCC1 apply an external clock, apply it to XIN and leave XOUT open
XCIN
I
VCC1
XCOUT
O
VCC1
BCLK
CLKOUT
O
O
VCC2
VCC2
Bus clock output pin
The CLKOUT pin outputs the clock having the same frequency as
fC, f8, or f32
INT interrupt
input
INT0 to INT2
I
VCC1
INT interrupt input pins
NT3 to INT5
I
VCC2
NMI interrupt
input
Timer A
NMI
I
VCC1
TA0OUT to
TA4OUT
TA0IN to
TA4IN
TB0IN to
TB5IN
I/O
VCC1
I
VCC1
NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor
when the NMI interrupt is not used.
Timer A0 to A4 input/output pins
(TA0OUT is N-channel open drain output)
Timer A0 to A4 input pins
I
VCC1
Timer B0 to B5 input pins
U, U, V, V,
W, W
O
VCC1
Three-phase motor control timer output pins
CTS0 to
CTS4
I
VCC1
Input pins to control data transmission
RTS0 to
RTS4
CLK0 to CLK4
RXD0 to
RXD4
TXD0 to
TXD4
SDA0 to
SDA4
SCL0 to SCL4
O
VCC1
Output pins to control data reception
I/O
I
VCC1
VCC1
Serial clock input/output pins
Serial data input pins
O
VCC1
I/O
VCC1
I/O
VCC1
O
VCC1
I
VCC1
Serial data output pins
(TXD2 is N-channel open drain output)
Serial data input/output pins
(SDA2 is N-channel open drain output)
Serial clock input/output pins
(SCL2 is N-channel open drain output)
Serial data output pins when slave mode is selected
(STXD2 is N-channel open drain output)
Serial data input pins when slave mode is selected
I
VCC1
Control input pins used in the serial interface special mode.
Timer B
Three-phase
motor control
timer output
Serial
interface
I2C mode
STXD0 to
Serial
STXD4
interface
special function SRXD0 to
SRXD4
SS0 to SS4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 16 of 352
Input/output pins for the sub clock oscillation circuit. Connect a
crystal oscillator between XCIN and XCOUT. To apply an external
clock, apply it to XCIN and leave XCOUT open.
M32C/8A Group
Table 1.13
Item
Reference
voltage input
A/D converter
1. Overview
Pin Functions (3) (100-Pin Package and 144-Pin Package)
Pin Name
VREF
AN_0 to AN_7
ADTRG
ANEX0
D/A converter
I/O port
Input port
Key input
interrupt input
I/O Supply
Type Voltage
I
−
I
I
VCC1
VCC1
I/O
VCC1
ANEX1
I
DA0, DA1
O
P0_0 to P0_7, I/O(1)
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7
P6_0 to P6_7, I/O
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7
P8_0 to P8_4
P8_6, P8_7
P8_5
I
KI0 to KI3
I
VCC1
VCC1
VCC2
VCC1
Description
The VREF pin supplies the reference voltage to the A/D converter
and D/A converter.
Analog input pins for the A/D converter.
External trigger input pin for the A/D converter.
Extended analog input pin for the A/D converter or output pin in
external op-amp connection mode.
Extended analog input pin for the A/D converter.
Output pins for the D/A converter.
8-bit CMOS I/O ports. The Port Pi Direction Register determines
if each pin is used as an input port or an output port. The Pull-up
Control Register determines if the input ports, divided into groups
of four, are pulled up or not.
These 8-bit I/O ports are functionally equivalent to P0.
(P7_0 and P7_1 are N-channel open drain output.)
These I/O ports are functionally equivalent to P0.
VCC1
VCC1
Shares the pin with NMI. Input port to read NMI pin level.
Key input interrupt input pins
NOTE:
1. P0 to P5 function as bus control pins and cannot be used as I/O ports. P1_0 to P1_7 can be used as I/O ports
when using with 8-bit external bus width only.
Table 1.14
Item
A/D converter
I/O ports
Pin Functions (4) (144-Pin Package Only)
Pin Name
AN15_0 to
AN15_7
P11_0 to
P11_4,
P12_0 to
P12_7,
P13_0 to
P13_7
P14_0 to
P14_6,
P15_0 to
P15_7
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
I/O
Supply
Description
Type Voltage
I
VCC1 Analog input pins for the A/D converter
I/O
VCC2
I/O
VCC1
Page 17 of 352
These I/O ports are functionally equivalent to P0.
M32C/8A Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There
are two sets of register banks.
b31
b15
R2
R2
R3
R3
General registers
b0
R0H
R0H
R1H
R1H
R0L
R0L
R1L
R1L
Data registers(1)
R2
R2
R3
R3
b23
A0
A0
A1
A1
SB
SB
FB
FB
Static base register(1)
Frame base register(1)
USP
ISP
INTB
PC
User stack pointer
Interrupt stack pointer
Interrupt table register
Program counter
Address registers(1)
FLG
b15
Flag register
b8 b7
IPL
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved
Processor interrupt priority level
Reserved
b15
High-speed interrupt registers
b0
SVF
b23
Flag save register
PC save register
Vector register
SVP
VCT
b7
b0
DMD0
DMD1
DMAC-associated registers
b15
DCT0
DCT1
DRC0
DRC1
b23
DMA0
DMA1
DRA0
DRA1
DSA0
DSA1
DMA mode registers
DMA transfer count registers
DMA transfer count reload registers
DMA memory address registers
DMA memory address reload registers
DMA SFR address registers
NOTE:
1. These registers comprise a register bank.
There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 18 of 352
M32C/8A Group
2.1
2. Central Processing Unit (CPU)
General Registers
2.1.1
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into
high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers.
R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer,
arithmetic and logic operations.
2.1.3
Static Base Register (SB)
SB is a 24-bit register used for SB-relative addressing.
2.1.4
Frame Base Register (FB)
FB is a 24-bit register used for FB-relative addressing.
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP.
Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
2.1.6
Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
2.1.7
Program Counter (PC)
PC is 24 bits wide and indicates the address of the next instruction to be executed.
2.1.8
Flag Register (FLG)
FLG is a 16-bit register indicating the CPU state.
2.1.8.1
Carry Flag (C)
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 19 of 352
M32C/8A Group
2.1.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when
an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.
The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying
software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are follows:
• Save flag register (SVF)
• Save PC register (SVP)
• Vector register (VCT)
Refer to 11.4 High-Speed Interrupt for details.
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows:
• DMA mode register (DMD0, DMD1)
• DMA transfer count register (DCT0, DCT1)
• DMA transfer count reload register (DRC0, DRC1)
• DMA memory address register (DMA0, DMA1)
• DMA memory address reload register (DRA0, DRA1)
• DMA SFR address register (DSA0, DSA1)
Refer to 13. DMAC for details.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 20 of 352
M32C/8A Group
3.
3. Memory
Memory
Figure 3.1 is a memory map of the M32C/8A Group.
The M32C/8A Group has 16-Mbyte address space from addresses 000000h to FFFFFFh.
The fixed interrupt vectors are allocated addresses FFFFDCh to FFFFFFh. They store the starting address of each
interrupt routine. Refer to 11. Interrupts for details.
The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 12-Kbyte internal
RAM area is allocated addresses 000400h to 0033FFh. The internal RAM is used not only for storing data but for the
stacks when subroutines are called or when interrupt requests are acknowledged.
SFRs are allocated address 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D
converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be
accessed by users.
The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and
JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h
SFR
000400h
Internal RAM
XXXXXXh
010000h
Reserved
FFFE00h
FFFFDCh
Special page
vector table
Undefined instruction
Overflow
BRK instruction
Address match
External Space
Watchdog timer (1)
NMI
FFFFFFh
FFFFFFh
Reset
Internal RAM
Capacity
XXXXXXh
12 Kbytes
0033FFh
24 Kbytes
0063FFh
NOTE:
1. The watchdog timer interrupt, oscillation stop detection interrupt , and Vdet4 detection interrupt use the same vector.
Figure 3.1
Memory Map
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 21 of 352
M32C/8A Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.11 list SFR address
maps.
Table 4.1
SFR Address Map (1)
Address
Register
Symbol
After Reset
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0(1)
PM0
0000 0011b(CNVSS=”H”)
0005h
Processor Mode Register 1
PM1
00h
0006h
System Clock Control Register 0
CM0
0000 1000b
0007h
System Clock Control Register 1
CM1
0010 0000b
0009h
Address Match Interrupt Enable Register
AIER
00h
000Ah
Protect Register
PRCR
XXXX 0000b
DS
XXXX 1000b(BYTE=”L”)
XXXX 0000b(BYTE=”H”)
0008h
000Bh
External Data Bus Width Control Register
000Ch
Main Clock Division Register
MCD
XXX0 1000b
000Dh
Oscillation Stop Detection Register
CM2
00h
000Eh
Watchdog Timer Start Register
WDTS
XXh
000Fh
Watchdog Timer Control Register
WDC
00XX XXXXb
Address Match Interrupt Register 0
RMAD0
000000h
Processor Mode Register 2
PM2
00h
Address Match Interrupt Register 1
RMAD1
000000h
Voltage Detection Register 2
VCR2
00h
Address Match Interrupt Register 2
RMAD2
000000h
Voltage Detection Register 1
VCR1
0000 1000b
Address Match Interrupt Register 3
RMAD3
000000h
0026h
PLL Control Register 0
PLC0
0001 X010b
0027h
PLL Control Register 1
PLC1
000X 0000b
Address Match Interrupt Register 4
RMAD4
000000h
Address Match Interrupt Register 5
RMAD5
000000h
Vdet4 Detection Interrupt Register
D4INT
XX00 0000b
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTE:
1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been
performed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 22 of 352
M32C/8A Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Address Map (2)
Address
Register
Symbol
After Reset
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
Address Match Interrupt Register 6
RMAD6
000000h
Address Match Interrupt Register 7
RMAD7
000000h
0048h
External Space Wait Control Register 0
EWCR0
X0X0 0011b
0049h
External Space Wait Control Register 1
EWCR1
X0X0 0011b
004Ah
External Space Wait Control Register 2
EWCR2
X0X0 0011b
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
004Bh
External Space Wait Control Register 3
EWCR3
X0X0 0011b
004Ch
Page Mode Wait Control Register 0
PWCR0
0001 0001b
004Dh
Page Mode Wait Control Register 1
PWCR1
0001 0001b
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 23 of 352
M32C/8A Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Address Map (3)
Address
Register
Symbol
After Reset
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
DMA0 Interrupt Control Register
DM0IC
XXXX X000b
0069h
Timer B5 Interrupt Control Register
TB5IC
XXXX X000b
006Ah
DMA2 Interrupt Control Register
DM2IC
XXXX X000b
006Bh
UART2 Receive/ACK Interrupt Control Register
S2RIC
XXXX X000b
006Ch
Timer A0 Interrupt Control Register
TA0IC
XXXX X000b
006Dh
UART3 Receive/ACK Interrupt Control Register
S3RIC
XXXX X000b
006Eh
Timer A2 Interrupt Control Register
TA2IC
XXXX X000b
006Fh
UART4 Receive/ACK Interrupt Control Register
S4RIC
XXXX X000b
0070h
Timer A4 Interrupt Control Register
TA4IC
XXXX X000b
0071h
UART0/UART3 Bus Conflict Detection Interrupt Control Register
BCN0IC/BCN3IC
XXXX X000b
0072h
UART0 Receive/ACK Interrupt Control Register
S0RIC
XXXX X000b
0073h
A/D0 Conversion Interrupt Control Register
AD0IC
XXXX X000b
0074h
UART1 Receive/ACK Interrupt Control Register
S1RIC
XXXX X000b
Timer B1 Interrupt Control Register
TB1IC
XXXX X000b
Timer B3 Interrupt Control Register
TB3IC
XXXX X000b
INT5 Interrupt Control Register
INT5IC
XX00 X000b
INT3 Interrupt Control Register
INT3IC
XX00 X000b
INT1 Interrupt Control Register
INT1IC
XX00 X000b
0088h
DMA1 Interrupt Control Register
DM1IC
XXXX X000b
0089h
UART2 Transmit/NACK Interrupt Control Register
S2TIC
XXXX X000b
008Ah
DMA3 Interrupt Control Register
DM3IC
XXXX X000b
008Bh
UART3 Transmit/NACK Interrupt Control Register
S3TIC
XXXX X000b
008Ch
Timer A1 Interrupt Control Register
TA1IC
XXXX X000b
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
008Dh
UART4 Transmit/NACK Interrupt Control Register
S4TIC
XXXX X000b
008Eh
Timer A3 Interrupt Control Register
TA3IC
XXXX X000b
008Fh
UART2 Bus Conflict Detection Interrupt Control Register
BCN2IC
XXXX X000b
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 24 of 352
M32C/8A Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Address Map (4)
Address
Register
Symbol
After Reset
0090h
UART0 Transmit/NACK Interrupt Control Register
S0TIC
XXXX X000b
0091h
UART1/UART4 Bus Conflict Detection Interrupt Control Register
BCN1IC/BCN4IC
XXXX X000b
0092h
UART1 Transmit/NACK Interrupt Control Register
S1TIC
XXXX X000b
0093h
Key Input Interrupt Control Register
KUPIC
XXXX X000b
0094h
Timer B0 Interrupt Control Register
TB0IC
XXXX X000b
Timer B2 Interrupt Control Register
TB2IC
XXXX X000b
Timer B4 Interrupt Control Register
TB4IC
XXXX X000b
INT4 Interrupt Control Register
INT4IC
XX00 X000b
INT2 Interrupt Control Register
INT2IC
XX00 X000b
009Eh
INT0 Interrupt Control Register
INT0IC
XX00 X000b
009Fh
Exit Priority Register
RLVL
XXXX 0000b
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
to
02BFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 25 of 352
M32C/8A Group
Table 4.5
4. Special Function Registers (SFRs)
SFR Address Map (5)
Address
02C0h
Register
Symbol
After Reset
X0 Register, Y0 Register
X0R, Y0R
XXXXh
X1 Register, Y1 Register
X1R, Y1R
XXXXh
X2 Register, Y2 Register
X2R, Y2R
XXXXh
X3 Register, Y3 Register
X3R, Y3R
XXXXh
X4 Register, Y4 Register
X4R, Y4R
XXXXh
X5 Register, Y5 Register
X5R, Y5R
XXXXh
X6 Register, Y6 Register
X6R, Y6R
XXXXh
X7 Register, Y7 Register
X7R, Y7R
XXXXh
X8 Register, Y8 Register
X8R, Y8R
XXXXh
X9 Register, Y9 Register
X9R, Y9R
XXXXh
X10 Register, Y10 Register
X10R, Y10R
XXXXh
X11 Register, Y11 Register
X11R, Y11R
XXXXh
X12 Register, Y12 Register
X12R, Y12R
XXXXh
X13 Register, Y13 Register
X13R, Y13R
XXXXh
X14 Register, Y14 Register
X14R, Y14R
XXXXh
X15 Register, Y15 Register
X15R, Y15R
XXXXh
X/Y Control Register
XYC
XXXX XX00b
02E4h
UART1 Special Mode Register 4
U1SMR4
00h
02E5h
UART1 Special Mode Register 3
U1SMR3
00h
02E6h
UART1 Special Mode Register 2
U1SMR2
00h
02E7h
UART1 Special Mode Register
U1SMR
00h
02E8h
UART1 Transmit/Receive Mode Register
U1MR
00h
02E9h
UART1 Baud Rate Register
U1BRG
XXh
UART1 Transmit Buffer Register
U1TB
XXXXh
02ECh
UART1 Transmit/Receive Control Register 0
U1C0
0000 1000b
02EDh
UART1 Transmit/Receive Control Register 1
U1C1
0000 0010b
UART1 Receive Buffer Register
U1RB
XXXXh
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02EAh
02EBh
02EEh
02EFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 26 of 352
M32C/8A Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Address Map (6)
Address
Register
Symbol
After Reset
02F0h
02F1h
02F2h
02F3h
02F4h
UART4 Special Mode Register 4
U4SMR4
00h
02F5h
UART4 Special Mode Register 3
U4SMR3
00h
02F6h
UART4 Special Mode Register 2
U4SMR2
00h
02F7h
UART4 Special Mode Register
U4SMR
00h
02F8h
UART4 Transmit/Receive Mode Register
U4MR
00h
02F9h
UART4 Baud Rate Register
U4BRG
XXh
UART4 Transmit Buffer Register
U4TB
XXXXh
02FCh
UART4 Transmit/Receive Control Register 0
U4C0
0000 1000b
02FDh
UART4 Transmit/Receive Control Register 1
U4C1
0000 0010b
UART4 Receive Buffer Register
U4RB
XXXXh
Timer B3, B4, B5 Count Start Register
TBSR
000X XXXXb
Timer A11 Register
TA11
XXXXh
Timer A21 Register
TA21
XXXXh
Timer A41 Register
TA41
XXXXh
0308h
Three-Phase PWM Control Register 0
INVC0
00h
0309h
Three-Phase PWM Control Register 1
INVC1
00h
030Ah
Three-Phase Output Buffer Register 0
IDB0
XX11 1111b
02FAh
02FBh
02FEh
02FFh
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
030Bh
Three-Phase Output Buffer Register 1
IDB1
XX11 1111b
030Ch
Dead Time Timer
DTT
XXh
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
XXh
Timer B3 Register
TB3
XXXXh
Timer B4 Register
TB4
XXXXh
Timer B5 Register
TB5
XXXXh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
Timer B3 Mode Register
TB3MR
00XX 0000b
031Ch
Timer B4 Mode Register
TB4MR
00XX 0000b
031Dh
Timer B5 Mode Register
TB5MR
00XX 0000b
External Interrupt Source Select Register
IFSR
00h
031Eh
031Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 27 of 352
M32C/8A Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Address Map (7)
Address
Register
Symbol
After Reset
0320h
0321h
0322h
0323h
0324h
UART3 Special Mode Register 4
U3SMR4
00h
0325h
UART3 Special Mode Register 3
U3SMR3
00h
0326h
UART3 Special Mode Register 2
U3SMR2
00h
0327h
UART3 Special Mode Register
U3SMR
00h
0328h
UART3 Transmit/Receive Mode Register
U3MR
00h
0329h
UART3 Baud Rate Register
U3BRG
XXh
UART3 Transmit Buffer Register
U3TB
XXXXh
032Ch
UART3 Transmit/Receive Control Register 0
U3C0
0000 1000b
032Dh
UART3 Transmit/Receive Control Register 1
U3C1
0000 0010b
UART3 Receive Buffer Register
U3RB
XXXXh
0334h
UART2 Special Mode Register 4
U2SMR4
00h
0335h
UART2 Special Mode Register 3
U2SMR3
00h
0336h
UART2 Special Mode Register 2
U2SMR2
00h
0337h
UART2 Special Mode Register
U2SMR
00h
032Ah
032Bh
032Eh
032Fh
0330h
0331h
0332h
0333h
0338h
UART2 Transmit/Receive Mode Register
U2MR
00h
0339h
UART2 Baud Rate Register
U2BRG
XXh
UART2 Transmit Buffer Register
U2TB
XXXXh
033Ch
UART2 Transmit/Receive Control Register 0
U2C0
0000 1000b
033Dh
UART2 Transmit/Receive Control Register 1
U2C1
0000 0010b
UART2 Receive Buffer Register
U2RB
XXXXh
0340h
Count Start Register
TABSR
00h
0341h
Clock Prescaler Reset Register
CPSRF
0XXX XXXXb
0342h
One-Shot Start Register
ONSF
00h
033Ah
033Bh
033Eh
033Fh
0343h
Trigger Select Register
TRGSR
00h
0344h
Up/Down Select Register
UDF
00h
Timer A0 Register
TA0
XXXXh
Timer A1 Register
TA1
XXXXh
Timer A2 Register
TA2
XXXXh
Timer A3 Register
TA3
XXXXh
Timer A4 Register
TA4
XXXXh
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
044Ch
034Dh
034Eh
034Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 28 of 352
M32C/8A Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Address Map (8)
Address
0350h
Register
Symbol
After Reset
Timer B0 Register
TB0
XXXXh
Timer B1 Register
TB1
XXXXh
Timer B2 Register
TB2
XXXXh
0356h
Timer A0 Mode Register
TA0MR
00h
0357h
Timer A1 Mode Register
TA1MR
00h
0358h
Timer A2 Mode Register
TA2MR
00h
0359h
Timer A3 Mode Register
TA3MR
00h
035Ah
Timer A4 Mode Register
TA4MR
00h
035Bh
Timer B0 Mode Register
TB0MR
00XX 0000b
035Ch
Timer B1 Mode Register
TB1MR
00XX 0000b
0351h
0352h
0353h
0354h
0355h
035Dh
Timer B2 Mode Register
TB2MR
00XX 0000b
035Eh
Timer B2 Special Mode Register
TB2SC
XXXX XXX0b
035Fh
Count Source Prescaler Register(1)
TCSPR
0XXX 0000b
0364h
UART0 Special Mode Register 4
U0SMR4
00h
0365h
UART0 Special Mode Register 3
U0SMR3
00h
0366h
UART0 Special Mode Register 2
U0SMR2
00h
0367h
UART0 Special Mode Register
U0SMR
00h
0360h
0361h
0362h
0363h
0368h
UART0 Transmit/Receive Mode Register
U0MR
00h
0369h
UART0 Baud Rate Register
U0BRG
XXh
UART0 Transmit Buffer Register
U0TB
XXXXh
036Ch
UART0 Transmit/Receive Control Register 0
U0C0
0000 1000b
036Dh
UART0 Transmit/Receive Control Register 1
U0C1
0000 0010b
UART0 Receive Buffer Register
U0RB
XXXXh
0378h
DMA0 Request Source Select Register
DM0SL
0X00 0000b
0379h
DMA1 Request Source Select Register
DM1SL
0X00 0000b
037Ah
DMA2 Request Source Select Register
DM2SL
0X00 0000b
037Bh
DMA3 Request Source Select Register
DM3SL
0X00 0000b
CRC Data Register
CRCD
XXXXh
CRC Input Register
CRCIN
XXh
036Ah
036Bh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
037Ch
037Dh
037Eh
037Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTE:
1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 29 of 352
M32C/8A Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Address Map (9)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
Register
Symbol
After Reset
A/D0 Register 0
AD00
00XXh
A/D0 Register 1
AD01
00XXh
A/D0 Register 2
AD02
00XXh
A/D0 Register 3
AD03
00XXh
A/D0 Register 4
AD04
00XXh
A/D0 Register 5
AD05
00XXh
A/D0 Register 6
AD06
00XXh
A/D0 Register 7
AD07
00XXh
A/D0 Control Register 4
AD0CON4
XXXX 00XXb
0390h
0391h
0392h
0393h
0394h
A/D0 Control Register 2
AD0CON2
XX0X X000b
0395h
A/D0 Control Register 3
AD0CON3
XXXX X000b
0396h
A/D0 Control Register 0
AD0CON0
00h
0397h
A/D0 Control Register 1
AD0CON1
00h
0398h
D/A Register 0
DA0
XXh
D/A Register 1
DA1
XXh
D/A Control Register
DACON
XXXX XX00b
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 30 of 352
M32C/8A Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Address Map (10)
Address
Register
Address
Register
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
Function Select Register C
PSC
00X0 0000b
03B0h
Function Select Register A0
PS0
00h
03B1h
Function Select Register A1
PS1
00h
03B2h
Function Select Register B0
PSL0
00h
03B3h
Function Select Register B1
PSL1
00h
03B4h
Function Select Register A2
PS2
00X0 0000b
03B5h
Function Select Register A3
PS3
00h
03B6h
Function Select Register B2
PSL2
00X0 0000b
03B7h
Function Select Register B3
PSL3
00h
03C0h
Port P6 Register
P6
XXh
03C1h
Port P7 Register
P7
XXh
03C2h
Port P6 Direction Register
PD6
00h
03C3h
Port P7 Direction Register
PD7
00h
03C4h
Port P8 Register
P8
XXh
03C5h
Port P9 Register
P9
XXh
03C6h
Port P8 Direction Register
PD8
00X0 0000b
03C7h
Port P9 Direction Register
PD9
00h
03C8h
Port P10 Register
P10
XXh
03C9h
Port P11 Register(1)
P11
XXh
03CAh
Port P10 Direction Register
PD10
00h
03CBh
Port P11 Direction Register(1)(2)
PD11
XXX0 0000b
03CCh
Port P12 Register(1)
P12
XXh
03CDh
Port P13 Register(1)
P13
XXh
03CEh
Port P12 Direction Register(1)(2)
PD12
00h
03CFh
Port P13 Direction Register(1)(2)
PD13
00h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTES:
1. These registers cannot be used in the 100-pin package.
2. Set to FFh in the 100-pin package.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 31 of 352
M32C/8A Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Address Map (11)
Address
Register
Address
Register
03D0h
Port P14 Register(1)
P14
XXh
03D1h
Port P15 Register(1)
P15
XXh
03D2h
Port P14 Direction Register(1)(2)
PD14
X000 0000b
03D3h
Port P15 Direction Register(1)(2)
PD15
00h
03DAh
Pull-Up Control Register 2
PUR2
00h
03DBh
Pull-Up Control Register 3
PUR3
00h
03DCh
Pull-Up Control Register 4(1)(3)
PUR4
XXXX 0000b
03E0h
Port P0 Register
P0
XXh
03E1h
Port P1 Register
P1
XXh
03E2h
Port P0 Direction Register
PD0
00h
03E3h
Port P1 Direction Register
PD1
00h
03E4h
Port P2 Register
P2
XXh
03E5h
Port P3 Register
P3
XXh
03E6h
Port P2 Direction Register
PD2
00h
03E7h
Port P3 Direction Register
PD3
00h
03E8h
Port P4 Register
P4
XXh
03E9h
Port P5 Register
P5
XXh
03EAh
Port P4 Direction Register
PD4
00h
03EBh
Port P5 Direction Register
PD5
00h
03F0h
Pull-Up Control Register 0
PUR0
00h
03F1h
Pull-Up Control Register 1
PUR1
XXXX 0000b
Port Control Register
PCR
XXXX XXX0b
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DDh
03DEh
03DFh
03ECh
03EDh
03EEh
03EFh
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTES:
1. These registers cannot be used in the 100-pin package.
2. Set to FFh in the 100-pin package.
3. Set to 00h in the 100-pin package.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 32 of 352
M32C/8A Group
5.
5. Reset
Reset
Hardware reset 1, hardware reset 2 (Vdet3 detection function), software reset and watchdog timer reset are
implemented to reset the MCU.
5.1
Hardware Reset 1
Pins, CPU, and SFRs are reset by using the RESET pin. When a low-level (“L”) signal is applied to the RESET pin
while the supply voltage meets the recommended operating conditions, ports and I/O pins for peripheral functions
are reset. (Refer to Table 5.1 Pin states while RESET pin is held “L”.) Also, the oscillation circuit is reset and the
main clock starts oscillating. CPU and SFRs are reset when the signal applied to the RESET pin changes from “L”
to high-level (“H”), and then the MCU executes a program beginning with the address indicated by the reset vector.
The WDC5 bit in the WDC register and the internal RAM are not reset by hardware reset 1. When an “L” signal is
applied to the RESET pin while writing data to the internal RAM, the value written to the internal RAM becomes
undefined.
Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin states while
the RESET pin is held “L”.
5.1.1
Reset at a Stable Supply Voltage
(1) Apply an “L” signal to the RESET pin.
(2) Input 20 clock cycles or more into the XIN pin.
(3) Apply an “H” signal to the RESET pin.
5.1.2
Power-on Reset
(1) Apply an “L” signal to the RESET pin.
(2) Increase the supply voltage until it meets the recommended operating condition.
(3) Wait for td(P-R) (internal power supply stabilization time) or more to allow the internal power supply to
stabilize.
(4) Inputs 20 clock cycles or more into the XIN pin.
(5) Apply an “H” signal to the RESET pin.
Recommended
operating volatage
VCC1
VCC1
0V
RESET
RESET
0.2VCC1 or below
0.2VCC1 or below
0V
Input td(P-R) + 20 clock cycles or more
to the XIN pin
NOTE:
1. If operating at VCC1 > VCC2, VCC2 voltage must be lower than VCC1 voltage when powering up and down.
Figure 5.1
Example of Reset Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 33 of 352
M32C/8A Group
5. Reset
VCC1, VCC2
XIN
Td(P-R) ms or
more is required
20 or more clock
cycles are required
RESET
40 to 45 BCLK cycles
BCLK
Microprocessor mode
BYTE = "H"
Content of reset vector
Address
A23
RD
WR
FFFFFCh
FFFFFDh
“L”
“H”
“L”
“H”
“L”
Content of reset vector
Address
RD
WR
Figure 5.2
FFFFFFh
“H”
Microprocessor mode
BYTE = "L"
A23
FFFFFEh
FFFFFCh
“H”
“L”
“H”
“L”
“H”
“L”
Reset Sequence
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 34 of 352
FFFFFEh
M32C/8A Group
Table 5.1
5. Reset
Pin States while RESET Pin is Held “L”(2)
Microprocessor Mode
Pin Name
CNVSS = “H”
BYTE = “L”
BYTE = “H”
P0
Data input (high-impedance)
P1
Data input (high-impedance)
P2 to P4
Address output (undefined)
P5_0
WR signal output (“H”)(3)
P5_1
BHE signal output (“H”)
P5_2
RD signal output (“H”)(3)
P5_3
BCLK output(3)
P5_4
HLDA signal output (output level depends on an input level to
the HOLD pin)(3)
P5_5
HOLD signal input (high-impedance)
P5_6
“H” signal output(3)
P5_7
RDY signal input (high-impedance)
P6 to P15(1)
Input port (high-impedance)
Input port (high-impedance)
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. The availability of the pull-up resistors is undefined until the internal supply voltage stabilizes.
3. These pin states are defined after the power is turned on and the internal supply voltage stabilizes. Until then,
the pin states are undefined.
5.2
Hardware Reset 2 (Vdet3 detection function)
Pins, CPU, and SFRs are reset by the Vdet3 detection function, when the voltage applied to the VCC1 pin drops to
Vdet3 (V) or below. The states of the pins, CPU, and SFRs after reset are the same as the hardware reset 1. Refer
to 6. Power Supply Voltage Detection Function for details on Vdet3 detection function.
5.3
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU is reset), the MCU resets the CPU, SFRs, ports, and I/O
pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector.
Set the PM03 bit to 1 while the main clock is selected as the clock source for the CPU clock and the main clock
oscillation is stable.
The software reset does not reset the following SFRs; bits PM01 and PM11 in the PM0 register, the WDC5 bit in
the WDC register, and the TCSPR register.
Processor mode remains unchanged since bits PM01 and PM00 are not reset.
5.4
Watchdog Timer Reset
When the CM06 bit in the CM0 register is set to 1 (reset) and the watchdog timer underflows, the MCU resets the
CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address
indicated by the reset vector.
The watchdog timer reset does not reset the following SFRs; bits PM01 and PM11 in the PM0 register, the WDC5
bit in the WDC register, and the TCSPR register.
Processor mode remains unchanged since bits PM01 and PM00 are not reset.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 35 of 352
M32C/8A Group
5.5
5. Reset
Internal Registers
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states
after reset.
0: 0 after reset
X: Undefined after reset
General registers
High-speed interrupt registers
b15
b0
b15
Flag register (FLG)
b15
b8 b7
b0
X 0 0 0 X X X X 0 0 0 0 0 0 0 0
U I O B S Z D C
IPL
b15
b0
XXXXh
b23
Flag save register (SVF)
XXXXXXh
PC save register (SVP)
XXXXXXh
Vector register (VCT)
DMAC-associated registers
b0
00h
R0H
00h
R0L
Data register (R0H/R0L)
00h
R1H
00h
R1L
Data register (R1H/R1L)
b7
b0
00h
DMA mode register (DMD0)
00h
DMA mode register (DMD1)
0000h
R2
Data register (R2)
0000h
R3
Data register (R3)
XXXXh
DMA transfer count register (DCT0)
000000h
A0
Address register (A0)
XXXXh
DMA transfer count register (DCT1)
000000h
A1
Address register (A1)
XXXXh
DMA transfer count reload register (DRC0)
000000h
SB
Static base register (SB)
XXXXh
DMA transfer count reload register (DRC1)
b23
000000h
FB
Frame base register (FB)
b15
b23
XXXXXXh
DMA memory address register (DMA0)
XXXXXXh
DMA memory address register (DMA1)
000000h
User stack pointer (USP)
XXXXXXh
DMA memory address reload register (DRA0)
000000h
Interrupt stack pointer (ISP)
XXXXXXh
DMA memory address reload register (DRA1)
Interrupt table register (INTB)
XXXXXXh
DMA SFR address register (DSA0)
Program counter (PC)
XXXXXXh
DMA SFR address register (DSA1)
000000h
Contents of addresses
FFFFFEh to FFFFFCh
Figure 5.3
CPU Register States after Reset
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 36 of 352
M32C/8A Group
6.
6. Power Supply Voltage Detection Function
Power Supply Voltage Detection Function
The power supply voltage detection function has the Vdet3 detection function, Vdet4 detection function, and cold
start/warm start determination function. The Vdet3 detection function and Vdet4 detection function detect the changes
in voltage and trigger the events. The cold start/warm start determination function determines whether the MCU is
reset at power-on or reset while running.
The power supply voltage detection function is available only with VCC1 = 4.2V to 5.5V standard.
Figure 6.1 shows a block diagram of the voltage detection circuit. Figures 6.2 to 6.4 show voltage detection-associated
registers.
Vdet3 detection fucntion
Wait time to release hardware reset 2:
td(S-R)
1 shot
VCC1
＋
T
Q
≥Vdet3
Internal reset signal
(active "L")
E
VC26
CM10
Vdet4 detection function
VC13
＋
≥Vdet3
Analog Filter
E
(rejection range: 200 ns)
VC27
Vdet4 detection signal(1)
DF1 to DF0
00b
01b
10b
CPU clock
1/8
1/2
1/2
1/2
Digital filter
CM10
WAIT instruction (wait mode)
11b
D42 bit
Output one-shot pulse when the
D42 bit becomes 0 to 1.
Vdet4 detection
interrupt signal
Latch
D41
D40
WDC5
S
Hardware reset 1
at power-on
R
Oscillation stop
detection
interrupt signal
Watchdog timer
interrupt signal
Cold start/warm start determination function
Write a given value to
the WDC register
Watchdog timer
interrupt request
Q
COLD/WARM
(Cold start, warm start)
CM10: bit in the CM1 register
VC13: bit in the VCR1 register
VC26, VC27: bits in the VCR2 register
DF1 and DF0, D40, D41, D42: bits in the D4INT register
WDC5: bit in the WDC register
NOTE:
1. When the VC27 bit in the VCR2 register is set to 0 (Vdet4 detection function not used), the Vdet4 detection signal becomes "H".
Figure 6.1
Power Supply Voltage Detection Function Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 37 of 352
M32C/8A Group
6. Power Supply Voltage Detection Function
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
VCR1
Address
001Bh
Bit Symbol
−
(b2-b0)
VC13
−
(b7-b4)
Bit Name
After Reset
0000 1000b
Function
RW
Reserved bits
Set to 0
RW
Voltage change monitor flag(1)
0: VCC1 < Vdet4
1: VCC1 ≥ Vdet4
RO
Reserved bits
Set to 0
RW
NOTE:
1. The VC13 bit is enabled when the VC27 bit in the VCR2 register is set to 1 (Vdet4 detection function used).
The VC13 bit becomes 1 when the VC27 bit is set to 0 (Vdet4 detection function not used).
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
VCR2
Address
0017h
Bit Symbol
−
(b5-b0)
Bit Name
After Reset
00h
Function
RW
Reserved bits
Set to 0
RW
VC26
Vdet3 detection function
select bit(2, 4, 5)
0: Vdet3 detection function not used
1: Vdet3 detection function used
RW
VC27
Vdet4 detection function
select bit(3, 4)
0: Vdet4 detection function not used
1: Vdet4 detection function used
RW
NOTES:
1. Set the VCR2 register after the PRC3 bit in the PRCR register is set to 1 (write enable).
2. To use the hardware reset 2 (Vdet3 detection function), set the VC26 bit to 1.
3. To use the Vdet4 detection function, set the VC27 bit to 1 and the D40 bit in the D4INT register to 1 (Vdet4 detection interrupt
used). The VC13 bit in the VCR1 register and the D42 bit in the D4INT register are enabled when the VC27 bit is set to 1.
4. After the VC26 or VC27 bit is set to 1, the detection circuit waits for td(E-A) to elapse before starting operation.
5. The VC26 bit is disabled when the MCU is in stop mode. (The hardware reset 2 is not performed even if the voltage applied to
the VCC1 pin drops below Vdet3.)
Figure 6.2
VCR1 Register, VCR2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 38 of 352
M32C/8A Group
6. Power Supply Voltage Detection Function
Vdet4 Detection Interrupt Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
After Reset
XX00 0000b
Address
002Fh
Bit Symbol
Bit Name
Function
RW
D40
Vdet4 detection interrupt
enable bit(2)
0: Vdet4 detection interrupt disabled
1: Vdet4 detection interrupt enabled
RW
D41
Wait mode/Stop mode exit
control bit(3)
0: Vdet4 detection interrupt is not used to exit
wait/stop mode
1: Vdet4 detection interrupt is used to exit
wait/stop mode
RW
D42
Voltage change detect flag(4, 5)
0: Not detected
1: Voltage crosses Vdet4
RW
D43
WDT underflow detect flag (5)
0: Not detected
1: Detected
RW
b5 b4
RW
DF0
Sampling clock select bits
DF1
−
(b7-b6)
Unimplemented.
Read as undefined value.
0 0: CPU clock divided-by-8
0 1: CPU clock divided-by-16
1 0: CPU clock divided-by-32
1 1: CPU clock divided-by-64
RW
−
NOTES:
1. Set the D4INT register after the PRC3 bit in the PRCR register is set to 1 (write enable).
2. Use the following procedure to set the D40 bit to 1:
(1) Set the VC27 bit in the VCR2 register to 1
(2) Wait for td(E-A) before the voltage detection circuit starts operating
(3) Wait for required sampling time (See Table "Sampling Period")
(4) Set the D40 bit to 1
3. If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set it to 1 to use the
Vdet4 detection interrupt again to exit these modes.
4. The D42 bit is enabled when the VC27 bit is set to 1 (Vdet4 detection function used ). The D42 bit becomes 0 when the VC27 bit
is set to 0 (Vdet4 detection function not used).
5. The D43 bit can be set to 0 by program. Writing a 0 has no effect.
Figure 6.3
D4INT Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 39 of 352
M32C/8A Group
6. Power Supply Voltage Detection Function
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
WDC
Address
000Fh
Bit Symbol
Bit Name
After Reset
00XX XXXXb
Function
−
(b4-b0)
High-order bits of watchdog timer
WDC5
Cold start/warm start determine
flag(1)
0: Cold start
1: Warm start
RW
Reserved bit
Set to 0
RW
Prescaler select bit
0: Divide-by-16
1: Divide-by-128
RW
−
(b6)
WDC7
RO
NOTE:
1. The WDC5 bit is 0 after power-on. It can be set to 1 only by program. The bit becomes 1 by writing either a 0 or 1.
The bit remains a value set before reset, even after reset has been performed.
Figure 6.4
WDC Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 40 of 352
M32C/8A Group
6.1
6. Power Supply Voltage Detection Function
Vdet3 Detection Function
The hardware reset 2 is performed if the voltage applied to the VCC1 pin drops to Vdet3 (V) or below.
Set the VC26 bit in the VCR2 register to 1 to use this Vdet3 detection function.
When the hardware reset 2 occurs, ports and I/O pins for peripheral functions are reset. The CPU and SFRs are
reset when td(S-R) elapses after the voltage applied to the VCC1 pin reaches Vdet3r (V) or above. Then, the MCU
executes a program in an address indicated by the reset vector. The states of pins and SFRs after reset are the same
as the hardware reset 1.
Use the Vdet3 detection function while operating at or above Vdet3s. If the applied voltage drops below Vdet3s,
perform the hardware reset 1 (refer to 5.1.1 Reset at a Stable Supply Voltage). The Vdet3 detection function
cannot be used while the MCU is in stop mode.
Figure 6.5 shows a Vdet3 detection function operation example.
5.0 V
5.0 V
3.1 V(1)
Vdet3r
3.0 V
Vdet3
VCC1
(1)
Vdet3s
2.0V(2)
VSS
“H”
RESET
Set to 1 (Vdet3 detection function used) by program.
“L”
“1”
VC26 bit in the
VCR2 register
“0”
Internal reset signal
Undefined
“H”
“L”
NOTES:
1. Typical value.
2. Minimum value.
Figure 6.5
Wait time to release
hardware reset 2: td(S-R)
Vdet3 Detection Function Operation Example
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 41 of 352
M32C/8A Group
6.2
6. Power Supply Voltage Detection Function
Vdet4 Detection Function
Vdet4 detection interrupt is generated if the voltage applied to the VCC1 pin crosses the Vdet4 (V) level, either by
dropping below or by rising above Vdet4. Set the VC27 bit in the VCR2 register to 1 (Vdet4 detection function
used) and the D40 bit in the D4INT register to 1 (Vdet4 detection interrupt enabled) to use the Vdet4 detection
function.
The D42 bit becomes 1 (voltage crosses Vdet4) as soon as the applied voltage crosses Vdet4. When the D42 bit
changes from 0 to 1, a Vdet4 detection interrupt request is generated. The D42 bit does not become 0 automatically
when the interrupt is acknowledged. Set it to 0 (not detected) by program. Whether the voltage has dropped below
Vdet4 or risen above Vdet4 can be determined by reading the VC13 bit in the VCR1 register.
Set the D41 bit in the D4INT register to 1 to use the Vdet4 detection interrupt to exit wait mode or stop mode. The
MCU exits wait mode or stop mode if the Vdet4 detection signal is generated even if the D42 bit is 1.
The Vdet4 detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop
detection interrupt. When using the Vdet4 detection interrupt simultaneously with these interrupts, determine
whether the Vdet4 detection interrupt is generated by reading the D42 bit in the interrupt routine.
Table 6.1 shows conditions to generate Vdet4 detection interrupt request. Figure 6.6 shows a Vdet4 detection
function operation example.
Bits DF1 and DF0 in the D4INT register determine the sampling clock which is used to detects if the voltage
applied to the VCC1 pin crosses Vdet4. Table 6.2 shows the sampling periods.
Table 6.1
Conditions to Generate Vdet4 Detection Interrupt Request
Operating Mode
CPU operating mode(3)
VC27 Bit
D40 Bit
1
1
Wait mode, Stop mode(4)
D41 Bit
D42 Bit(1)
VC13 Bit(2)
−
0 to 1
0 to 1
1 to 0
1
−
0 to 1
− : either 0 or 1
NOTES:
1. Set to 0 by program before generating an interrupt.
2. An interrupt request is generated when the sampling period elapses after the value of the bit is changed. See
Figure 6.6 Vdet4 Detection Function Operation Example for details.
3. CPU operating mode includes main clock mode, PLL mode, low speed mode, low-power consumption mode,
on-chip oscillator mode, on-chip oscillator low-power consumption mode. (Refer to 9. Clock Generation
Circuits.)
4. Refer to 6.2.1 Usage Notes on Vdet4 Detection Interrupt.
Table 6.2
Sampling Periods
Sampling Clock (μs)
CPU Clock
(MHz)
Divided-by-8
Divided-by-16
Divided-by-32
Divided-by-64
16
3.0
6.0
12.0
24.0
24
2.0
4.0
8.0
16.0
NOTE:
1. Set the CPU clock below 24 MHz to use the voltage detection function.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 42 of 352
M32C/8A Group
6. Power Supply Voltage Detection Function
Voltage applied to VCC1
Vdet4 (V)
3 (V)
Time
RESET
“H”
“L”
VC27 bit
1
0
VC13 bit
1
(note 1)
0
<When wait mode/stop mode is not used>
Sampling period
Output from digital filter
“H”
“L”
Set to 0 by program
D42 bit
Vdet4 detection
interrupt request signal
from D42 bit
1
0
(note 2)
“H”
“L”
<When wait mode/stop mode is used>
Sampling period
Output from digital filter
D42 bit
Vdet4 detection
interrupt request signal
from D42 bit
D41 bit
Vdet4 detection
interrupt request signal
when D41 bit is 1
“H”
“L”
Set to 0 by program
1
0
“H”
“L”
1
0
(note 3)
“H”
“L”
VC27 bit: bit in the VCR2 register
VC13 bit: bit in the VCR1 register
VC41 bit, VC42 bit: bits in the D4INT register
Wait mode or
stop mode
Wait mode or
stop mode
NOTES:
1. Apply an "L" to the RESET pin when the voltage input to the VCC1 pin drops to 3.0 V or below. When the
voltage rises above 3.0 V, and the voltage of the internal VDC and the main clock oscillation stabilize, apply an
"H" to the RESET pin.
2. When the D42 bit is set to 1, the Vdet4 detection interrupt request signal is not generated even if the Vdet4
detection signal is output from the digital filter.
3. If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set
it back to 1 to use the Vdet4 detection interrupt again to exit wait/stop mode.
Figure 6.6
Vdet4 Detection Function Operation Example
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 43 of 352
M32C/8A Group
6.2.1
6. Power Supply Voltage Detection Function
Usage Notes on Vdet4 Detection Interrupt
When all the conditions below are met, the Vdet4 detection interrupt is generated and the MCU exits wait mode
as soon as the WAIT instruction is executed or exits stop mode as soon as the CM10 bit in the CM1 register is
set to 1 (all clocks stopped).
•
•
•
•
the VC27 bit in the VCR2 register is set to 1 (Vdet4 detection function used)
the D40 bit in the D4INT register is set to 1 (Vdet4 detection interrupt enabled)
the D41 bit in the D4INT register is set to 1 (Vdet4 detection interrupt is used to exit wait/stop mode)
the voltage applied to the VCC1 pin is Vdet4 or above (the VC13 bit in the VCR1 register is 1)
Execute the WAIT instruction or set the CM10 bit to 1 (all clocks stopped) while the VC13 bit is 0
(VCC1 < Vdet4), if the MCU is configured to enter wait/stop mode when voltage applied to the VCC1 pin
drops Vdet4 or below and to exit wait/stop mode when the voltage applied rises to Vdet4 or above.
If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set it
back to 1 to use the Vdet4 detection interrupt again to exit wait/stop mode.
6.3
Cold Start/Warm Start Determine Function
The WDC5 bit in the WDC register determines whether it is a reset process when power-on (cold start) or a reset
process when the RESET signal is input during MCU running (warm start). Default value of the WDC5 bit is 0
(cold start) when power-on, and the bit is set to 1 (warm start) by writing given values to the WDC register. The
WDC5 bit does not become 0 even if the hardware reset 1, hardware reset2, software reset, or watchdog timer reset
is performed.
Figure 6.7 shows an example of cold start/warm start determine function operation.
5V
VCC1
0V
5V
Pch transistor ON (Approx. 4 V)
CPU comes out of reset
RESET
0V
Set to 1 by program
T1
T2
1
T > 100 μs
WDC5 bit
0
Program starts running
Reset sequence (Approx.20 μs@16 MHz)
The WDC5 bit remains set
to 1 even if voltage applied
to RESET becomes 0 V.
NOTE:
1. If the time difference between T1 and T2 is greater, it may take longer to set the WDC5 bit to 1.
Figure 6.7
Cold Start/Warm Start Determine Function Operation
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 44 of 352
M32C/8A Group
7.
7. Processor Mode
Processor Mode
7.1
Processor Mode
Microprocessor mode can be selected as the processor mode. Table 7.1 lists the features of the processor mode.
Table 7.1
Processor Mode Features
Processor Mode
Microprocessor mode(1)
Accessible Space
SFR, internal RAM, external space
Pins assigned to I/O Port
P0 to P5 become bus control pins
NOTE:
1. Refer to 8. Bus for details.
7.2
Setting of Processor Mode
Input an “H” signal to the CNVSS pin and release the RESET signal to start up in microprocessor mode. Bits
PM01 and PM00 are set to 11b (microprocessor mode) after reset. Do not set to values other than 11b.
Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in microprocessor
mode.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 45 of 352
M32C/8A Group
7. Processor Mode
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1 1
Symbol
Address
After Reset
PM0
0004h
0000 0011b (CNVSS = "H")
Bit Symbol
Bit Name
PM00
Processor mode bits(2)
PM01
Function
RW
b1 b0
RW
Do not set to values other than the above.
RW
1 1: Microprocessor mode
PM02
R/W mode select bit
0: RD/BHE/WR
1: RD/WRH/WRL
RW
PM03
Software reset bit
The MCU is reset when this bit is set to 1.
Read as 0.
RW
PM04
b5 b4
Multiplexed bus space
select bits(3)
PM05
ー
(b6)
PM07
0 0: Multiplexed bus is not used
0 1: Access the CS2 area using multiplexed bus
1 0: Access the CS1 area using multiplexed bus
1 1: Do not set to this value.
RW
RW
Reserved bit
Set to 0
RW
BCLK output function select bit
0: BCLK output (4)
1: No BCLK output
RW
NOTES:
1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
2. Bits PM01 and PM00 maintain values set before reset, even after software reset or watchdog timer reset has performed.
3. The PM05 and PM04 bits setting is enabled in microprocessor mode. Set these bits in the combination with bits PM11 and PM10
in the PM 1 register. Refer to the Table "Multiplexed Bus Settings and Chip-Select Areas" in the Bus chapter.
4. To output BCLK from P5_3 in microprocessor mode, set the PM07 bit to 0, bits CM01 and CM00 in the CM0 register to "00b" (I/O
port P5_3), and bits PM15 and PM14 in the PM1 register to 00b, 10b, or 11b.
Figure 7.1
PM0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 46 of 352
M32C/8A Group
7. Processor Mode
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
PM1
After Reset
Address
0005h
Bit Symbol
Bit Name
00h
Function
RW
0 0: Mode 0 (A20 to A23 for P4_4 to P4_7)
0 1: Mode 1 (A20 for P4_4,
CS2 to CS0 for P4_5 to P4_7)
1 0: Mode 2 (A20 and A21 for P4_4 and P4_5,
CS1 and CS0 for P4_6 and P4_7)
1 1: Mode 3 (CS3 to CS0 for P4_4 to P4_7)
RW
b1 b0
PM10
External space mode bits
PM11
RW
PM12
Internal memory wait bit
0: No wait state
1: 1 wait state
RW
PM13
SFR area wait bit
0: 1 wait state
1: 2 wait states
RW
b5 b4
RW
PM14
ALE pin select bits
PM15
−
(b7-b6)
Reserved bits
0 0: No ALE
0 1: P5_3(2)
1 0: P5_6
1 1: P5_4
Set to 0
RW
RW
NOTES:
1. Set the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
2. To output ALE signal from P5_3, set bits PM15 and PM14 to 01b, and bits CM01 and CM00 in the CM0 register to 00b (I/O port
P5_3).
Figure 7.2
PM1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 47 of 352
M32C/8A Group
7. Processor Mode
Microprocessor mode
000000h
000400h
Mode 0
Mode 1
Mode 2
SFR
SFR
SFR
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Reserved
Reserved
Reserved
Reserved
External space 0
CS1
2-Mbyte
external space 0(1)
010000h
100000h
200000h
300000h
Mode 3
SFR
External space 1
CS2
2-Mbyte
external space 1
External space 2
Not used
Not used
CS1
4-Mbyte
external space 0(2)
CS1 1-Mbyte　external space 0
CS2 1-Mbyte　external space 1
400000h
Not used
Not used
C00000h
D00000h
E00000h
External space 3
CS0
2-Mbyte
external space 3
F00000h
FFFFFFh
CS area controlled by the EWCRi register:
CS0 controlled by EWCR3
CS1 controlled by EWCR0
CS2 controlled by EWCR1
CS3 controlled by EWCR2
Figure 7.3
Page 48 of 352
CS0
4-Mbyte
external space 3
Not used
CS0 1-Mbyte　external space 3
NOTES:
1. 200000h to 010000h = 1984 Kbytes. 64K bytes less than 2 Mbytes.
2. 400000h to 010000h = 4032 Kbytes. 64K bytes less than 4 Mbytes.
Memory Map in Microprocessor Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
CS3 1-Mbyte　external space 2
Not used
M32C/8A Group
8.
8. Bus
Bus
In microprocessor mode, the following pins become bus control pins: D0 to D15, A0 to A22, A23, CS0 to CS3, WRL/
WR, WRH/BHE, RD, CLKOUT/BCLK/ALE, HLDA/ALE, HOLD, ALE, RDY.
8.1
Bus Settings
Bus setting is determined by the BYTE pin, the DS register, the PM05 and PM04 bits in the PM0 register, and bits
PM11 and PM10 in the PM1 register.
Table 8.1 lists how to change bus settings. Figure 8.1 shows the DS register.
Table 8.1
Bus Settings
Bus Setting
Selecting external data bus width
Setting bus width after reset
Selecting separate bus or multiplexed bus
Number of chip-select pins
Pin & Registers Used for Setting
DS register
BYTE pin (for external space 3 only)
Bits PM05 and PM04 in the PM0 register
Bits PM11 and PM10 in the PM1 register
External Data Bus Width Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DS
Address
000Bh
Bit Symbol
RW
External space 0
data bus width select bit
0: 8 bits wide
1: 16 bits wide
RW
DS1
External space 1
data bus width select bit
0: 8 bits wide
1: 16 bits wide
RW
DS2
External space 2
data bus width select bit
0: 8 bits wide
1: 16 bits wide
RW
DS3
External space 3
data bus width select bit (1)
0: 8 bits wide
1: 16 bits wide
RW
Unimplemented.
Write 0. Read as undefined value.
DS Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
DS0
−
(b7-b4)
Figure 8.1
Bit Name
After Reset
XXXX 1000b (BYTE pin = "L")
XXXX 0000b (BYTE pin = "H")
Page 49 of 352
−
M32C/8A Group
8.1.1
8. Bus
Selecting External Address Bus
The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space
(CS area) vary in each external space mode. Bits PM11 and PM10 in the PM1 register select external space
mode.
8.1.2
Selecting External Data Bus
The DS register selects either external 8-bit data bus or 16-bit data bus per each external space. The data bus in
the external space 3, after reset, becomes 16 bits wide when a low-level (“L”) signal is applied to the BYTE pin
and 8 bits wide when a high-level (“H”) signal is applied. Keep the BYTE pin level while the MCU is
operating. Internal bus is always 16 bits wide.
8.1.3
Selecting Separate/Multiplexed Bus
Bits PM05 and PM04 in the PM0 register select either the separate bus or multiplexed bus. The MCU starts up
with the separate bus after reset.
8.1.3.1
Separate Bus
With the separate bus format, the MCU performs data input/output and address output using individual buses.
The DS register selects 8-bit or 16-bit external data bus for each external space. If all DSi bits in the DS register
(i = 0 to 3) are set to 0 (8-bit data bus), port P0 functions as the data bus and port P1 as the programmable I/O
port.
If any of the DSi bits is set to 1 (16-bit data bus), ports P0 and P1 function as the data bus. Port P1 output is
undefined when the MCU accesses the space where its DSi bit is set to 0.
8.1.3.2
Multiplexed Bus
With the multiplexed bus format, the MCU performs data input/output and address output using the same bus
by time-sharing. D0 to D7 are time-multiplexed with A0 to A7 in the space accessed by the 8-bit data bus. D0
to D15 are time-multiplexed with A0 to A15 in the space accessed by the 16-bit data bus.
Table 8.2 lists multiplexed bus settings and chip-select areas. Table 8.3 lists a processor mode and pin function.
Table 8.2
Multiplexed Bus Settings and Chip-Select Areas
PM05 and PM04
bits setting(1)
00b
(external space
mode 0
00b
(multiplexed bus not used)
01b
(access the CS2 area
using multiplexed bus)
10b
(access the CS1 area
using multiplexed bus)
PM11 and PM10 Bits Setting
01b
10b
(external space
(external space
mode 1)
mode 2)
Separate bus
Do not set to
these values
CS2
Do not set to
this value
CS2
CS1
CS1
CS1
NOTE:
1. In microprocessor mode, do not set bits PM05 and PM04 in the PM0 register to 11b.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
11b
(external space
mode 3)
Page 50 of 352
M32C/8A Group
Table 8.3
8. Bus
Processor Mode and Pin Function
Processor Mode
Microprocessor Mode
PM05 and PM04 bits 00b (Multiplexed bus not used)
setting(1)
01b (Access CS2 area using multiplexed bus)
10b (Access CS1 area using multiplexed bus)
Data bus width
Access all external
Access any external
spaces with 8-bit data spaces with 16-bit
bus
data bus
Access all external
Access any external
spaces with 8-bit data spaces with 16-bit
bus
data bus
P0_0 to P0_7
Data bus (D0 to D7)
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
I/O port
Data bus
(D8 to D15)
Address bus (A0 to A7)
I/O port
Data bus
(D8 to D15)
Address bus/data bus (A0/D0 to A7/D7)(2)
Address bus (A8 to A15)
Address bus/data bus
(A8/D8 to A15/D15)(2)
P4_0 to P4_3
Address Bus (A16 to A19)
P4_4 to P4_6
CS or address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(6)
P4_7
CS or address bus (A23) (Refer to 8.2 Bus Control for details)(6)
P5_0 to P5_2
RD, WRL, WRH outputs or RD, BHE, WR outputs (Refer to 8.2 Bus Control for details)(4)
P5_3
CLKOUT/BCLK/ALE(7)
P5_4
HLDA/ALE(3)
P5_5
HOLD
P5_6
ALE(3)(5)
P5_7
RDY
NOTES:
1. Do not set bits PM05 and PM04 in the PM0 register to 11b in microprocessor mode since the MCU starts up
with the separate bus after reset.
2. These pins are used as address bus when selecting separate bus.
3. Bits PM15 and PM14 in the PM1 register determine which pin is used to output the ALE signal.
4. The PM02 bit in the PM0 register selects either “RD, WRL, WRH” or “RD, BHE, WR” combination.
5. P5_6 outputs undefined value when bits PM15 and PM14 are set to 00b (no ALE). In this case, it cannot be
used as an I/O port.
6. Bits PM11 and PM10 in the PM1 register determine whether these pins are used as chip-select outputs or
address bus.
7. Use bits CM01 and CM00 in the CM0 register, bits PM15 and PM14 in the PM1 register, and the PM07 bit in
the PM0 register to select among CLKOUT, BCLK, and ALE function.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 51 of 352
M32C/8A Group
8.2
8. Bus
Bus Control
Described below are the signals required to access external devices. The signals are available in microprocessor
mode only.
8.2.1
Address Bus and Data Bus
Address bus is the signals to access 16-Mbyte space, and consists of 24 control pins; A0 to A22 and A23. A23
is an inverse output signal of the highest-order address bit.
Data bus is the signals for data input and output. The DS register selects either an 8-bit data bus width from D0
to D7 or a 16-bit data bus width from D0 to D15 for each external space. When a high-level (“H”) signal is
applied to the BYTE pin, the data bus accessing the external space 3 is 8 bits wide after reset.
When a low-level (“L”) signal is applied to the BYTE pin, the data bus accessing the external space 3 is 16 bits
wide.
8.2.2
Chip-Select Output
Chip-select outputs share pins with address bus, A20 to A22 and A23. Bits PM11 and PM10 in the PM1 register
determine the CS areas to be accessed and the number of chip-select outputs. Maximum of four chip-select
outputs are provided.
In microprocessor mode, no chip-select signal is output after reset. Only A23, however, can perform as a chipselect output.
The CSi pin (i=0 to 3) outputs an “L” signal while accessing its corresponding external space. An “H” signal is
output while the MCU is accessing other external spaces. Figure 8.2 shows an example of address bus and
chip-select outputs (separate bus).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 52 of 352
M32C/8A Group
8. Bus
Example 1:
After accessing the external space, both address bus
and chip-select output change
Example 2:
After accessing an external space, the chip-select
output changes but the address bus does not.
When the MCU accesses the external space j
specified by another chip-select output in the next
cycle after having accessed the external space i, both
address bus and chip-select output change.
When the MCU accesses SFR or internal RAM area
in the next cycle after having accessed an external
space, the chip-select signal changes but the
address bus does not.
Access
Access another
external
external space j
space i
Data bus
Data
Address bus
Address
Access
external
space
Data bus
Data
Address bus
Chip-select: CSk
Access SFR,
internal RAM
Data
Address
Chip-select: CSk
Chip-select: CSp
Example 3:
After accessing the external space, the address bus
changes but the chip-select output does not.
Example 4:
After accessing an external space, neither address
bus nor chip-select signal changes.
When the MCU accesses the space i specified by the
same chip-select output in the next cycle after having
accessed the external space i, the address bus
changes but the chip-select output does not.
When the MCU does not access any spaces in the
next cycle after having accessed an external space
(no instruction prefetch is performed), neither
address bus nor chip-select signal changes.
Access
Access the same
external
external space i
space i
Data bus
Data
Address bus
Address
Data bus
Data
Chip-select: CSk
i = 0 to 3
j = 0 to 3, excluding i
k = 0 to 3
p = 0 to 3, excluding k
Access
external
space
Address bus
Address
NOTE:
1. The above examples show the address bus and chip-select output in two consecutive bus cycles.
Depending on the combination, the chip-select signal can be more than two bus cycles.
Address Bus and Chip-Select Outputs (Separate Bus)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Data
Chip-select: CSk
CS1 outputs an "L" signal while accessing the external space 0.
CS2 outputs an "L" signal while accessing the external space 1.
CS3 outputs an "L" signal while accessing the external space 2.
CS0 outputs an "L" signal while accessing the external space 3.
Figure 8.2
No accesss to
external space
Page 53 of 352
M32C/8A Group
8.2.3
8. Bus
Read/Write Output Signals
When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the “RD, WR,
and BHE” outputs or the “RD, WRL, and WRH” outputs to determine the read/write output signals. When the
DS3 to DS0 in the DS register are set to 0 (8-bit external data bus width), set the PM02 bit to 0 (RD/WR/BHE).
When any of the DS3 to DS0 bits are set to 1 (16-bit external data bus width) to access an 8-bit space, the
combination of “RD, WR, and BHE” is automatically selected regardless of the PM02 bit setting. Table 8.4
lists RD, WRL, and WRH outputs. Table 8.5 list RD, WR, and BHE outputs.
The RD, WR, and BHE outputs are selected for the read/write output signals after reset. When changing to
“RD, WRL, and WRH” outputs, set the PM02 bit first to write data to an external memory.
Table 8.4
Data Bus Width
16 bits
8 bits
RD, WRL, and WRH Outputs
RD
WRL
WRH
A0
CPU Processing on External Space
L
H
H
Not used
Read data
H
L
H
Not used
Write 1-byte data to even address
H
H
L
Not used
Write 1-byte data to odd address
Write data to both even and odd addresses
H
L
L
Not used
H
L(1)
Not used
H/L
Write 1-byte data
L
H(1)
Not used
H/L
Read 1-byte data
NOTE:
1. These become WR output.
Table 8.5
Data Bus Width
16 bits
8 bits
RD, WR, and BHE Outputs
RD
WR
BHE
A0
H
L
L
H
Write 1-byte data to odd address
L
H
L
H
Read 1-byte data from odd address
H
L
H
L
Write 1-byte data to even address
CPU Processing on External Space
L
H
H
L
Read 1-byte data from even address
H
L
L
L
Write data to both even and odd addresses
L
H
L
L
Read data from both even and odd addresses
H
L
Not used
H/L
Write 1-byte data
L
H
Not used
H/L
Read 1-byte data
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 54 of 352
M32C/8A Group
8.2.4
8. Bus
Bus Timing
Software wait states for the internal RAM can be set using the PM12 bit in the PM1 register, for the SFR area
using the PM13 bit, and for external spaces using the EWCRi register (i = 0 to 3). Table 8.6 lists a software
wait state and bus cycle.
The basic bus cycle for the internal RAM and SFR area is one bus clock (BCLK) cycle. A read or write to the
internal RAM takes the basic bus cycle. When the PM12 bit in the PM1 register to 1 (1 wait state), an access to
the internal RAM takes two BCLK cycles.
A read or write to the SFR area takes two BCLK cycles (1 wait state). When the PM13 bit in the PM1 register
is set to 1 (2 wait states), an access takes three BCLK cycles.
The external bus cycle is divided into two phases: the number of BCLK cycles in the period from the beginning
of the bus access until the read or write output signal becomes “L” (first φ), and the number of BCLK cycles in
the period from the read or write output signal becomes “L” until the signal changes to “H” (second φ).
The minimum read or write cycle for the external bus is two BCLK clock cycles (1 φ + 1 φ). The EWCRi
register (i = 0 to 3) selects an external bus cycle from 12 types for the separate bus and seven types for the
multiplexed bus. For example, when bits EWCRi4 to EWCRi0 in the EWCRi register are set to 00011b
(1 φ+3 φ), the external bus cycle is four BCLK cycles.
Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show external bus timings.
External Space Wait Control Register i (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
EWCR0 to EWCR3
Bit Symbol
Address
0048h, 0049h, 004Ah, 004Bh
Bit Name
Function
b4 b3 b2 b1 b0 (1)
EWCRi0
EWCRi1
EWCRi2
Bus cycle select bits (3)
EWCRi3
EWCRi4
−
(b5)
EWCRi6
−
(b7)
After Reset
X0X0 0011b
(2)
0 0 0 0 1: 1 φ + 1 φ
0 0 0 1 0: 1 φ + 2 φ
0 0 0 1 1: 1 φ + 3 φ
0 0 1 0 0: 1 φ + 4 φ
0 0 1 0 1: 1 φ + 5 φ
0 0 1 1 0: 1 φ + 6 φ
0 1 0 1 0: 2 φ + 2 φ
0 1 0 1 1: 2 φ + 3 φ
0 1 1 0 0: 2 φ + 4 φ
0 1 1 0 1: 2 φ + 5 φ
1 0 0 1 1: 3 φ + 3 φ
1 0 1 0 0: 3 φ + 4 φ
1 0 1 0 1: 3 φ + 5 φ
1 0 1 1 0: 3 φ + 6 φ
Do not set to values other than the above
Unimplemented.
Write 0. Read as undefined value.
Recovery cycle insert
select bit
Unimplemented.
Write 0. Read as undefined value.
RW
RW
RW
RW
RW
RW
−
0: Insert no recovery cycle when accessing
external space i
1: Insert a recovery cycle when accessing
external space i
RW
−
NOTES:
1. The number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L".
2. The number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H".
Figure 8.3
EWCR0 to EWCR3 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 55 of 352
M32C/8A Group
Table 8.6
8. Bus
Software Wait State and Bus Cycle
PM1 Register
Space
External Bus Status
PM13 Bit
PM12 Bit
EWCRi Register
(i=0 to 3)
EWCRi4 to
EWCRi0 Bits
SFR area
−
0
1
−
−
Internal RAM
−
−
0
1
−
Separate bus
−
−
Multiplexed bus
−
−
External
memory
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 56 of 352
00001b
00010b
00011b
00100b
00101b
00110b
01010b
01011b
01100b
10011b
10100b
10110b
01010b
01011b
01101b
10011b
10100b
10101b
10110b
Bus Cycle
2 BCLK cycles
3 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
5 BCLK cycles
6 BCLK cycles
7 BCLK cycles
4 BCLK cycles
5 BCLK cycles
6 BCLK cycles
6 BCLK cycles
7 BCLK cycles
9 BCLK cycles
4 BCLK cycles
5 BCLK cycles
7 BCLK cycles
6 BCLK cycles
7 BCLK cycles
8 BCLK cycles
9 BCLK cycles
M32C/8A Group
8. Bus
• Bus cycle 1 φ + 1 φ
• Bus cycle 1 φ + 2 φ
1 bus cycle = 2 φ
1 bus cycle = 3 φ
BCLK
BCLK
Address
Address
CSi
(1)
CSi
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
(1)
• Bus cycle 1 φ + 4 φ
• Bus cycle 1 φ + 3 φ
1 bus cycle = 4 φ
1 bus cycle = 5 φ
BCLK
BCLK
Address
Address
CSi
CSi
(1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
• Bus cycle 1 φ + 5 φ
• Bus cycle 1 φ + 6 φ
1 bus cycle = 6 φ
1 bus cycle = 7 φ
BCLK
BCLK
Address
Address
CSi
(1)
CSi
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.4
Bus Cycles when Separate Bus is Selected (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
(1)
Page 57 of 352
(1)
M32C/8A Group
8. Bus
• Bus cycle 2 φ + 2 φ
• Bus cycle 2 φ + 3 φ
1 bus cycle = 4 φ
1 bus cycle = 5 φ
BCLK
BCLK
Address
Address
CSi
CSi
(1)
Read data
Read data
RD
RD
Write data
Write data
WR, WRL, WRH
WR, WRL, WRH
• Bus cycle 2 φ + 4 φ
1 bus cycle = 6 φ
BCLK
Address
CSi
(1)
Read data
RD
Write data
WR, WRL, WRH
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.5
Bus Cycles when Separate Bus is Selected (2)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 58 of 352
(1)
M32C/8A Group
8. Bus
• Bus cycle 3 φ + 3 φ
1 bus cycle = 6 φ
BCLK
Address
CSi
(1)
Read data
RD
Write data
WR, WRL, WRH
• Bus cycle 3 φ + 4 φ
1 bus cycle = 7 φ
BCLK
Address
CSi
(1)
Read data
RD
Write data
WR, WRL, WRH
• Bus cycle 3 φ + 6 φ
1 bus cycle = 9 φ
BCLK
Address
CSi
(1)
Read data
RD
Write data
WR, WRL, WRH
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.6
Bus Cycle with Separate Bus is Selected(3)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 59 of 352
M32C/8A Group
8. Bus
• Bus cycle 2 φ + 2 φ
• Bus cycle 2 φ + 3 φ
1 bus cycle = 4 φ
1 bus cycle = 5 φ
BCLK
BCLK
(1)
CSi
Read data
LA
Read data
RD
RD
LA
RD
RD
Write data
LA
Write data
WD
WR (WRL)
WR (WRL)
ALE
ALE
• Bus cycle 2 φ + 5 φ
1 bus cycle = 7 φ
BCLK
(1)
CSi
LA
Read data
RD
RD
LA
Write data
WD
WR (WRL)
ALE
? Bus cycle 3 φ + 3 φ
1 bus cycle = 6 φ
BCLK
(1)
CSi
LA
Read data
RD
RD
LA
Write data
WD
WR (WRL)
ALE
LA: Latch address
RD: Read data
WD: Write data
i=0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.7
(1)
CSi
Bus Cycles when Multiplexed Bus is Selected (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 60 of 352
LA
WD
M32C/8A Group
8. Bus
• Bus cycle 3 φ + 4 φ
1 bus cycle = 7 φ
BCLK
(1)
CSi
LA
Read data
RD
RD
LA
Write data
WD
WR (WRL)
ALE
• Bus cycle 3 φ + 5 φ
1 bus cycle = 8 φ
BCLK
CSi
(1)
Read data
LA
RD
RD
Write data
LA
WD
WR (WRL)
ALE
• Bus cycle 3 φ + 6 φ
1 bus cycle = 9 φ
BCLK
(1)
CSi
LA
Read data
RD
RD
LA
Write data
WD
WR (WRL)
ALE
LA: Latch address
RD: Read data
WD: Write data
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.8
Bus Cycles when Multiplexed Bus is Selected (2)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 61 of 352
M32C/8A Group
8.2.4.1
8. Bus
Bus Cycle with Recovery Cycle Inserted
The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not.
Address output or data output is held during the recovery cycle (only when using the separate bus). Devices,
which require longer address hold time or data hold time, are connectable.
- Recovery cycle when separate bus is selected (bus cycle is 1 φ + 2 φ)
Recovery cycle
BCLK
A
Address
Address is held
CSi
(1)
Read data
RD
RD
Write data
WD
Data is held
WR, WRL, WRH
- Recovery cycle when multiplexed bus is selected (bus cycle is 2 φ + 3 φ)
Recovery cycle
BCLK
(1)
CSi
LA
Read data
RD
RD
LA
Write data
WD
Data is held
WR (WRL)
ALE
A: address
LA: Latch address
RD: Read data
WD: Write data
i = 0 to 3
NOTE:
1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.9
Recovery Cycle
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 62 of 352
M32C/8A Group
8.2.5
8. Bus
ALE Output
The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus.
Latch the address at the falling edge of the ALE output. Bits PM15 and PM14 in the PM1 register determine to
what pin the ALE output is assigned.
The ALE signal is output even when accessing the internal space.
(1) 8-bit data bus
(2) 16-bit data bus
ALE
D0/A0 to D7/A7
ALE
Address
A8 to A15
Address
A16 to A19
Address
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Data(1)
Address or CS
D0/A0 to D15/A15
Address
A16 to A19
A20/CS3
A21/CS2
A22/CS1
A23/CS0
Data(1)
Address
Address or CS
NOTE:
1. D0/A0 to D15/A15 are placed in high-impedance states when read.
Figure 8.10
8.2.6
ALE Output and Address/Data Bus
RDY Input
The RDY signal facilitates access to external devices requiring longer access time. When RDY input is “L” at
the falling edge of the last BCLK cycle, wait states are inserted into the bus cycle. Then, when an “H” signal is
input to the RDY pin at the falling edge of BCLK, the MCU resumes executing the remaining bus clock.
Table 8.7 lists MCU states when placed in wait state by RDY input. Figure 8.11 shows an example of the RD
signal that is extended by the RDY signal.
Table 8.7
MCU States while “L” is Input to the RDY Pin
Item
State
Clock generation circuits
Operating (oscillating)
RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, ALE,
HLDA, programmable I/O ports
Maintains the same state as when “L” is input to RDY pin.
Internal peripheral circuits
Operating
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 63 of 352
M32C/8A Group
8. Bus
- Separate bus (bus cycle is 1φ + 2φ)
- Multiplexed bus (bus cycle is 1φ + 2φ)
BCLK
BCLK
CSi(1)
CSi(1)
RD
RD
RDY
RDY
tsu(RDY-BCLK)
tsu(RDY-BCLK)
Timing to input RDY signal
Timing to input RDY signal
i = 0 to 3
: Wait states inserted by RDY input
tsu(RDY-BCLK): RDY input setup time
NOTE:
1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.
Figure 8.11
8.2.7
RD Output Signal Extended by RDY Input
HOLD Input
The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a lowlevel (“L”) signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is
completed. While the HOLD pin is held “L”, the MCU remains in a hold state and the HLDA pin outputs an
“L” signal. Table 8.8 lists the MCU states in hold state.
Bus is used in the following priority order: HOLD, DMAC, CPU.
Table 8.8
MCU States in Hold State
Item
State
Clock generation circuits
Operating (oscillating)
CPU
Stopped
Internal peripheral circuits
Operating
(Watchdog timer is stopped)(1)
RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE
High-impedance
HLDA
Outputs “L”
ALE
Outputs “L”
Programmable I/O ports
Maintains the same state as when “L” is input to HOLD pin.
NOTE:
1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the
watchdog timer), watchdog timer does not stop.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 64 of 352
M32C/8A Group
8.2.8
8. Bus
External Bus States when Accessing Internal Space
Table 8.9 lists external bus states when the internal space is accessed.
Table 8.9
External Bus States when Accessing Internal Space
Item
State when Accessing SFR and Internal RAM
A0 to A22, A23
Hold the last accessed address in the external space
D0 to D15
High-impedance
RD, WR, WRL, WRH
Outputs “H”
BHE
Holds the output level at the time when the MCU accessed the external
space or SFR area for the last time
CS
Outputs “H”
ALE
Outputs ALE signal
8.2.9
BCLK Output
The bus clock can be output from the BCLK pin in microprocessor mode. To output the bus clock, set the
PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O
port P5_3).
Refer to 9. Clock Generation Circuits for details.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 65 of 352
M32C/8A Group
8.3
8. Bus
Page Mode Control Function
The page mode control function allows high-speed read access to the external memory compatible with the page
mode control. While the MCU accesses data within the eight-byte block of consecutive addresses which have the
same 21 high-order bits, less cycles are required for the subsequent bus accesses than the first bus access.
The EWCRi register (i = 0 to 3) determines how many wait states are inserted for the first bus access. Registers
PWCR0 and PWCR1 determine how many wait states are inserted for the subsequent bus accesses. Use the
following procedure to enable the page mode control.
(1) Set bits EWCRi4 to EWCRi0 in the EWCRi register.
(2) Set bits PWCRj02 to PWCRj00 and bits PWCRj06 to PWCRj04 in the PWCRj register (j = 0, 1).
(3) Set bits PWCRj03 and PWCRj07 to 1 (page mode control enabled).
When using the page mode control function, access all the external spaces using page mode control. It is not
allowed to combine the page mode controlled access and the normal access to external spaces.
Set bits PM05 and PM04 to 00b (multiplexed bus is not used). The page mode control function and multiplexed
bus cannot be used at the same time.
Figure 8.12 and 8.13 show registers PWCR0 and PWCR1. Figure 8.14 shows a diagram of external bus timing with
page mode function.
Page Mode Wait Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PWCR0
004Ch
0001 0001b
Bit Symbol
Bit Name
PWCR000
PWCR001
b2 b1 b0
External space 0
subsequent access
wait select bits
PWCR002
PWCR003
External space 0
page mode control enable bit
PWCR004
PWCR005
0
0
0
1
0
1
1
0
1: 1 φ + 1φ
0: 1 φ + 2φ
1: 1 φ + 3φ
0: 1 φ + 4φ
External space 1
subsequent access
wait select bits
External space 1
page mode control enable bit
PWCR0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 66 of 352
RW
RW
RW
0: Page mode control disabled
1: Page mode control enabled (1)
RW
0
0
0
1
0
1
1
0
1: 1 φ + 1φ
0: 1 φ + 2φ
1: 1 φ + 3φ
0: 1 φ + 4φ
RW
RW
Do not set to values other than the above.
RW
0: Page mode control disabled
1: Page mode control enabled (1)
RW
NOTE:
1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery
cycle when accessing external space i ).
Figure 8.12
RW
Do not set to values other than the above.
b6 b5 b4
PWCR006
PWCR007
Function
M32C/8A Group
8. Bus
Page Mode Wait Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PWCR1
004Dh
0001 0001b
Bit Symbol
Bit Name
PWCR100
PWCR101
b2 b1 b0
External space 2
subsequent access
wait select bits
External space 2
page mode control enable bit
PWCR104
PWCR105
External space 3
subsequent access
wait select bits
0
1
1
0
1: 1φ + 1φ
0: 1φ + 2φ
1: 1φ + 3φ
0: 1φ + 4φ
External space 3
page mode control enable bit
PWCR1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 67 of 352
RW
RW
RW
RW
b6 b5 b4
RW
0
0
0
1
0
1
1
0
1: 1φ + 1φ
0: 1φ + 2φ
1: 1φ + 3φ
0: 1φ + 4φ
0: Page mode control disabled
1: Page mode control enabled (1)
NOTE:
1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery
cycle when accessing external space i ).
Figure 8.13
RW
0: Page mode control disabled
1: Page mode control enabled (1)
Do not set to values other than the above.
PWCR106
PWCR107
0
0
0
1
Do not set to values other than the above.
PWCR102
PWCR103
Function
RW
RW
RW
M32C/8A Group
8. Bus
8-bit data bus width
Set using bits EWCR34 to EWCR30
Set using bits PWCR106 to PWCR104
3φ + 3 φ
1φ + 2 φ
1φ + 2φ
FFF000h
FFF001h FFF002h
1φ + 2 φ
3φ + 3 φ
1φ + 2 φ
FFF007h
FFF008h
FFF009h
BCLK
Address
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions:
- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).
- The DS3 bit in the DS regiter is set to 0 (8 bits wide).
- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3φ).
- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).
- Bits PWCR106 to PWCR104 are set to 010b (1 φ + 2φ).
- The PWCR107 bit is set to 1 (page mode control enabled).
If the MCU accesses data in other than the eight-byte block of consecutive addresses, the page mode controlled access
is started over from the first bus access.
16-bit data bus width
Set using bits EWCR34 to EWCR30
Set using bits PWCR106 to PWCR104
3φ + 3 φ
1φ + 2 φ
1φ + 2φ
1φ + 2 φ
FFF000h
FFF002h FFF004h FFF006h
3φ + 3 φ
1φ + 2 φ
1φ + 2 φ
FFF008h
FFF00Ah FFF00Ch
BCLK
Address
Data
CS0 (CE)
RD (OE)
The above applies under the following conditions:
- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).
- The DS3 bit in the DS regiter is set to 1 (16 bits wide).
- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3φ).
- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).
- Bits PWCR106 to PWCR104 are set to 010b (1 φ + 2φ).
- The PWCR107 bit is set to 1 (page mode control enabled).
Figure 8.14
External Bus Timing with Page Mode Control Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 68 of 352
M32C/8A Group
9.
9. Clock Generation Circuits
Clock Generation Circuits
9.1
Types of the Clock Generation Circuit
The MCU has four on-chip clock generation circuits to generate system clock signals.
• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer
Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock
generation circuit. Figures 9.2 to 9.8 show clock-associated registers.
Table 9.1
Clock Generation Circuit Specifications
Item
Applications
Clock frequency
Connectable
oscillator or
resonator
Oscillator or
resonator
connect pins
Oscillation stop/
restart function
Oscillator state
after reset
Other
Main Clock Oscillation Sub Clock Oscillation
On-chip Oscillator
Circuit
Circuit
• CPU clock source
• CPU clock source
• CPU clock source
• Peripheral function
• Count source for
• Peripheral function
clock source
timer A and timer B
clock source
Up to 32 MHz
32.768 kHz
Approx. 1 MHz
• Ceramic resonator
• Crystal oscillator
Crystal oscillator
−
PLL Frequency
Synthesizer
• CPU clock source
• Peripheral function
clock source
Up to 32 MHz
(see Table 9.3)
−
XIN, XOUT
XCIN, XCOUT
−
−
Available
Available
Available
Available
Oscillating
Stopped
Stopped
Stopped
Externally generated
clock can be used.
Externally generated
clock can be used.
Oscillation stop detect 30 MHz or 20 MHz:
Input 10 MHz to the
function:
main clock
When the main clock
32 MHz or 21.3 MHz
stops, the on-chip
Input 8 MHz to the
oscillator starts
main clock
oscillating
automatically and
becomes the CPU
and peripheral
function clock source
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 69 of 352
M32C/8A Group
9. Clock Generation Circuits
PM21
Interrupt request level
determination output
CM10
SQ
Logic 1 write signal
to CM10 bit
Stop mode
R
Vdet4 detection
interrupt signal
S
NMI
WAIT instruction
RQ
CM02
Clock stop signal in wait mode
RESET
Software reset
Watchdog timer reset
Hardware reset 2
Main clock oscillation circuit
XIN
CM05
CM21
Stop mode
XOUT
fXIND
CM05
Main clock
Stop mode
PM26
CM17
0
0
1
PLL frequency
synthesizer fPLL
Clock stop signal
in wait mode
PM22
On-chip
oscillator
PM26
PM27
Reset the
divider (divideby-8 mode)
Divider
0
(divide-by-m)
CM21
fROC
1
Clock stop signal
in wait mode
1
Peripheral function
clock source: fPFC
MCD register(2) CM07
fAD
f1
CM21
f8
Enable oscillation
Stop mode
1/8
Clock stop signal
in wait mode
Sub clock oscillation circuit
XCIN
CPU clock
(bus clock)
fCPU
VC27
XCOUT
1/4
CST
00
01
fXIND
fROC 10
PM27～ PM26
f32
1/2n
1/32
CPSR=1
fC
f2n(1)
fC32
Reset the divider
CM04
Oscillation stop detection circuit
Main clock
Clock edge detect/
charge and discharge
circuit control
Charge and
discharge circuit
Oscillation stop detection
interrupt request
generation circuit
Oscillation stop detection
interrupt request
(non-maskable interrupt requst)
Watchdog timer
interrupt request signal
Vdet4 detection
interrupt request signal
CM21
PLL frequency synthesizer
VCO clock (fVCO)
Programmable
counter
Main clock
Reference
frequency counter
Phase
comparator
Charge
pump
Voltage
controlled
oscillator
(VCO)
1/2
PLL clock (fPLL)
1/3
PLC12
PLC12: bit in the PLC1 register
VC27: bit in the VCR2 register
CM02, CM04, CM05, and CM07: bits in the CM0 register
CM10 and CM17: bits in the CM1 register
CM21: bit in the CM2 regsiter
PM21, PM22, PM26, and PM27: bits in the PM2 register
CST: bit in the TCSPR register
CPSR: bit in the CPSRF register
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16).
Figure 9.1
Clock Generation Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 70 of 352
M32C/8A Group
9. Clock Generation Circuits
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
After Reset
0000 1000b
Address
0006h
Bit Symbol
Bit Name
Function
b1 b0
CM00
Clock output function select bits (2)
CM01
0 0: I/O port P5_3(2)
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
RW
RW
RW
CM02
Peripheral function clock stop in
wait mode bit(9)
0: Peripheral clocks do not stop in wait mode
1: Peripheral clocks stop in wait mode (3)
RW
CM03
XCIN-XCOUT drive capability
select bit(10)
0: Low
1: High
RW
CM04
Port XC switch bit
0: I/O port function
1: XCIN-XCOUT oscillation function (4)
RW
CM05
Main clock (XIN-XOUT)
stop bit(5, 9)
0: Main clock oscillates
1: Main clock stops (6)
RW
CM06
Watchdog timer
function select bit
0: Watchdog timer interrupt
1: Reset(7)
RW
CM07
CPU clock select bit 0 (8, 9)
0: Clock selected by the CM21 bit divided by
the MCD register
1: Sub clock
RW
NOTES:
1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. The BCLK, ALE, or "L" signal is output from the P5_3 pin in microprocessor mode. The P5_3 does not function as an I/O port.
3. fC32 does not stop running.
4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the
PU25 bit in the PUR2 register to 0 (no pull-up).
5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power
consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock
oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21
bit in the CM2 register to 1 (on-chip oscillator clock).
When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled
up to the XOUT pin via the feedback resistor.
6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip
oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1.
7. Once the CM06 bit is set to 1, it cannot be set to 0 by program.
8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes.
Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes.
Do not change the CM07 bit simultaneously with the CM04 or CM05 bit.
9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect.
10. When stop mode is entered, the CM03 bit becomes 1.
Figure 9.2
CM0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 71 of 352
M32C/8A Group
9. Clock Generation Circuits
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 0
Symbol
CM1
Address
0007h
Bit Symbol
Bit Name
After Reset
0010 0000b
Function
RW
CM10
All clock stop control bit (2, 3, 5)
0: Clock oscillates
1: All clocks stop (stop mode)
RW
−
(b4-b1)
Reserved bits
Set to 0
RW
−
(b5)
Reserved bit
Set to 1
RW
−
(b6)
Reserved bit
Set to 0
RW
CPU clock select bit 1 (4, 5)
0: Main clock
1: PLL clock
RW
CM17
NOTES:
1. Set the CM1 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. When the CM10 bit is set to 1, the XOUT pin outputs "H" and the built-in feedback resistor is disconnected. Pins XIN, XCIN,
and XCOUT are placed in high-impedance states.
3. When the CM10 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode).
Do not set the CM10 bit to 1, when the CM20 bit in the CM2 register is set to 1 (oscillation stop detect function enabled) or the
CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock selected).
4. Set the CM17 bit to 1 after the PLL clock oscillation stablilizes.
5. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), writes to bits CM10 and CM17 have no effect.
If the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock as watchdog timer count source), a write to the CM10 bit
has no effect.
Figure 9.3
CM1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 72 of 352
M32C/8A Group
9. Clock Generation Circuits
Main Clock Division Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
MCD
000Ch
XXX0 1000b
Bit Symbol
Bit Name
MCD0
b4 b3 b2 b1 b0
MCD1
MCD2
Main clock division
select bits(2)
MCD3
1 0 0 1 0: Divide-by-1 (no division) mode
0 0 0 1 0: Divide-by-2 mode
0 0 0 1 1: Divide-by-3 mode
0 0 1 0 0: Divide-by-4 mode
0 0 1 1 0: Divide-by-6 mode
0 1 0 0 0: Divide-by-8 mode
0 1 0 1 0: Divide-by-10 mode
0 1 1 0 0: Divide-by-12 mode
0 1 1 1 0: Divide-by-14 mode
0 0 0 0 0: Divide-by-16 mode
Do not set to values other than the above
MCD4
−
(b7-b5)
Function
Reserved bits
Read as undefined value
RW
RW
RW
RW
RW
RW
−
NOTES:
1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b.
In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit in the CM0 register is set to 1 (main
clock stops).
Figure 9.4
MCD Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 73 of 352
M32C/8A Group
9. Clock Generation Circuits
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
CM2
After Reset
00h
Address
000Dh
Bit Symbol
Bit Name
Function
RW
CM20
Oscillation stop detection
enable bit(2)
0: Oscillation stop detect function not used
1: Oscillation stop detect function used
RW
CM21
CPU clock select bit 2 (3, 4)
0: Clock selected by the CM17 bit
1: On-chip oscillator clock
RW
CM22
Oscillation stop detection flag (5)
0: Loss of main clock not detected
1: Loss of main clock detected
RW
CM23
Main clock monitor flag(6)
0: Main clock oscillates
1: Main clock stops
RO
−
(b7-b4)
Reserved bits
Set to 0
RW
NOTES:
1. Set the CM2 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the CM20 bit has no effect.
3. When a loss of the main clock is detected while the CM20 bit is set to 1, the CM21 bit becomes 1.
Although the main clock restarts oscillating, the CM21 bit does not become 0. To use the main clock as the CPU clock source
after the main clock restarts oscillating, set the CM21 bit to 0 by program.
4. When both the CM20 and CM22 bits are set to 1, do not set the CM21 bit to 0.
5. When a loss of the main clock is detected, the CM22 bit becomes 1. The CM22 bit can only be set to 0, not 1, by program.
If the CM22 bit is set to 0 by program while the main clock is stopped, the CM22 bit does not become 1 until another loss of the
main clock is detected after the main clock restarts oscillating.
6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop detection interrupt is generated.
Figure 9.5
CM2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 74 of 352
M32C/8A Group
9. Clock Generation Circuits
PLL Control Register 0 (1, 2, 5)
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1
Symbol
Address
PLC0
0026h
Bit Symbol
Bit Name
PLC00
After Reset
0001 X010b
Function
RW
The VCO clock is the main clock multiplied by
the following variables.
RW
b2 b1 b0
Programmable counter
select bits(3)
PLC01
0 1 1: Multiply-by-6
1 0 0: Multiply-by-8
RW
Do not set to values other than the above
PLC02
RW
−
(b3)
Reserved bit
Read as undefined value
−
(b4)
Reserved bit
Set to 1
RW
−
(b5)
Reserved bit
Set to 0
RW
−
(b6)
Reserved bit
Set to 1
RW
Operation enable bit(4)
0: PLL stops
1: PLL runs
RW
PLC07
−
NOTES:
1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. If the PM21 bit in the PM2 register is set to 1 (disables a clock chang), a write to the PLC0 register has no effect.
3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once.
4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0.
5. Set registers PLC0 and PLC1 simultaneously in 16-bit units .
PLL Control Register 1(1, 2, 3, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0
1 0
Syambol
PLC1
Address
0027h
Bit Symbol
Bit Name
After Reset
000X 0000b
Function
−
(b0)
Reserved bit
Set to 0
RW
−
(b1)
Reserved bit
Set to 1
RW
PLC12
PLL clock division select bit
0: Divide-by-2
1: Divide-by-3
−
(b3)
Reserved bit
Set to 0
−
(b4)
Reserved bit
Read as undefined value
−
(b7-b5)
Reserved bits
Set to 0
NOTES:
1. Set the PLC1 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the the PLC1 register has no effect.
3. Set the PLC1 register while the PLC07 bit is 0 (PLL stopped).The PLC1 register can be written only once.
4. Set registers PLC0 and PLC1 simultaneously in 16-bit units.
Figure 9.6
PLC0 Register, PLC1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 75 of 352
RW
RW
−
RW
M32C/8A Group
9. Clock Generation Circuits
Processor Mode Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0
Symbol
PM2
Bit Symbol
−
(b0)
After Reset
00h
Address
0013h
Bit Name
Function
Reserved bit
Set to 0
RW
PM21
System clock protect bit (2, 3)
0: Protects a clock by the PRCR register
1: Disables a clock change
RW
PM22
WDT count source protect bit (2, 4)
0: CPU clock as count source for the watchdog
timer
1: On-chip oscillator clock as count source for
the watchdog timer
RW
Reserved bits
Set to 0
RW
b7 b6
RW
−
(b5-b3)
PM26
f2n clock source select bits
PM27
0 0: Clock selected by the CM21 bit
0 1: XIN clock (fXIND)
1 0: On-chip oscillator clock (fROC)
1 1: Do not set to this value
NOTES:
1. Set the PM2 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
2. Once bits PM22 and PM21 are set to 1, they cannot be set to 0 by program.
3. When the PM21 bit is set to 1,
• the CPU clock does not stop, even if the WAIT instruction is executed;
• writes to the following bits have no effect.
- the CM02 bit in the CM0 register
- the CM05 bit in the CM0 register
- the CM07 bit in the CM0 register (CPU clock source is not changed)
- the CM10 bit in the CM1 register (the MCU does not enter stop mode)
- the CM17 bit in the CM1 register (CPU clock source is not changed)
- the CM20 bit in the CM2 register (oscillation stop detect function setting is not changed)
- all bits in registers PLC0 and PLC1 (PLL frequency synthesizer setting is not changed)
4. When the PM22 bit is set to 1,
• the on-chip oscillator starts oscillating and the on-chip oscillator clock becomes the count source for the watchdog timer;
• write to the CM10 bit in the CM1 register is disabled (writing a 1 has no effect and the MCU does not enter stop mode);
• the watchdog timer keeps operating when the MCU is in wait mode or in hold state.
Figure 9.7
PM2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 76 of 352
RW
M32C/8A Group
9. Clock Generation Circuits
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSPR
After Reset(2)
0XXX 0000b
Address
035Fh
Bit Symbol
Bit Name
Function
RW
CNT0
RW
CNT1
If the setting value is n, f2n is the main clock,
on-chip oscillator clock, or PLL clock divided
by 2n.
When n is set to 0, no division is selected
Division rate select bits (1)
CNT2
CNT3
−
(b6-b4)
CST
RW
RW
RW
Reserved bits
Read as undefined value
Operation enable bit
0: Divider stops
1: Divider operates
−
RW
NOTES:
1. Set bits CNT3 to CNT0 after the CST bit is set to 0.
2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.
Clock Prescaler Reset Register
b7 b6 b5 b4 b3 b2 b1 b0
Figure 9.8
Symbol
CPSRF
Address
0341h
Bit Symbol
Bit Name
−
(b6-b0)
Unimplemented.
Write 0. Read as undefined value.
CPSR
Clock prescaler reset bit
TCSPR Register, CPSRF Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 77 of 352
After Reset
0XXX XXXXb
Function
RW
−
When the CPSR bit is set to 1, a divider for
fC32 is reset. Read as 0.
RW
M32C/8A Group
9.1.1
9. Clock Generation Circuits
Main Clock
Main clock oscillation circuit generates the main clock. The main clock is used as the clock source for the CPU
clock and peripheral function clocks.
The main clock oscillation circuit is configured by connecting an oscillator between the XIN and XOUT pins.
The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the oscillation circuit in
stop mode to reduce power consumption. The main clock oscillation circuit may also be configured by feeding
an externally generated clock to the XIN pin. Figure 9.9 shows examples of main clock circuit connection.
Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator
manufacturer.
The main clock divided-by-eight becomes the CPU clock source after reset.
To reduce power consumption, set the CM05 bit in the CM0 register to 1 (main clock stopped) after the sub
clock or on-chip oscillator clock is selected as the CPU clock sources. In this case, the XOUT pin outputs an
“H” signal. The XIN pin is pulled up to the XOUT pin via the feedback resistor which remains on. When an
external clock is input to the XIN pin, do not set the CM05 bit to 1.
All clocks, including the main clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU
(On-chip feedback resistor)
CIN
XIN
MCU
(On-chip feedback resistor)
XIN
Externally generated clock
VCC
Oscillator
VSS
XOUT
Rd(1)
COUT
XOUT
VSS
Open
NOTE:
1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values
recommended by the oscillator manufacturer.
If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback
resistor between XIN and XOUT following the instructions.
Figure 9.9
Main Clock Circuit Connection
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 78 of 352
M32C/8A Group
9.1.2
9. Clock Generation Circuits
Sub Clock
Sub clock oscillation circuit generates the sub clock. The sub clock is used as the clock source for the CPU
clock and for timer A and timer B. fC, which has the same frequency as the sub clock can be output from the
CLKOUT pin.
The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and
XCOUT pins. The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the
oscillation circuit in stop mode to reduce power consumption. The sub clock oscillation circuit may also be
configured by feeding an externally generated clock to the XCIN pin. Figure 9.10 shows an example of sub
clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant
recommended by each oscillator manufacturer.
The sub clock is stopped after reset, and the feedback resistor is disconnected from the oscillation circuit. To
start oscillating the sub clock oscillation circuit, set both the PD8_7 and PD8_6 bits in the PD8 register to 0
(input mode), the PU25 bit in the PUR2 register to 0 (no pull-up), and then the CM04 bit in the CM0 register to
1 (XCIN-XCOUT oscillation function). To input the externally generated clock to the XCIN pin, set the PD8_7
bit to 0, the PU25 bit to 0, and then the CM04 bit to 1. A clock input to the XCIN pin becomes the clock source
for the sub clock.
When the CM07 bit in the CM0 register is set to 1 (sub clock) after the sub clock oscillation stabilizes, the sub
clock becomes the CPU clock source.
All clocks, including the sub clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU
(On-chip feedback resistor)
CCIN
XCIN
MCU
(On-chip feedback resistor)
XCIN
Externally generated clock
VCC
Oscillator
VSS
XCOUT
RCd(1)
CCOUT
XCOUT
VSS
Open
NOTE:
1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values
recommended by the oscillator manufacturer.
If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback
resistor between XCIN and XCOUT following the instructions.
Figure 9.10
Sub Clock Circuit Connection
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 79 of 352
M32C/8A Group
9.1.3
9. Clock Generation Circuits
On-Chip Oscillator Clock
On-chip oscillator generates the 1-MHz on-chip oscillator clock. The on-chip oscillator clock is used as the
clock source for the CPU clock and peripheral function clocks.
The on-chip oscillator clock is stopped after reset. When the CM21 bit in the CM2 register is set to 1 (on-chip
oscillator clock), the on-chip oscillator starts oscillating and becomes the clock source for the CPU clock and
peripheral function clocks in place of the main clock.
Table 9.2 lists on-chip oscillator start conditions.
Table 9.2
On-Chip Oscillator Start Condition
CM2 Register
PM2 Register
Applications
CM21
PM22
PM27, PM26
1
0
00b
Clock source for the CPU clock and peripheral function clock
0
1
00b
Count source for the watchdog timer
(The clock keeps running in stop mode.)
0
0
10b
Clock source for f2n
9.1.3.1
Oscillation Stop Detect Function
When the main clock is terminated running by an external factor, the on-chip oscillator automatically starts
oscillating.
When the CM 20 bit in the CM2 register is set to 1 (oscillation stop detect function used), an oscillation stop
detection interrupt request is generated as soon as the main clock is lost. Simultaneously, the on-chip oscillator
starts oscillating. The on-chip oscillator clock takes the place of the main clock as the clock source for the CPU
clock and peripheral function clocks. Associated bits in the CM2 register are changed as follows:
• CM21 bit becomes 1 (on-chip oscillator clock becomes the CPU clock)
• CM22 bit becomes 1 (loss of main clock stop is detected)
• CM23 bit becomes 1 (main clock stops)
The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt and the Vdet4
detection interrupt. When these interrupts are used simultaneously, verify the CM22 bit within an interrupt
routine to determine if an oscillation stop detection interrupt request has been generated.
When the main clock resumes its operation after a loss of the main clock is detected, the main clock can be
selected as the clock source for the CPU clock and peripheral function clocks by program. Figure 9.11 shows
the procedure to switch the clock source from the on-chip oscillator clock to the main clock.
In low-speed mode, when the main clock is lost while the CM20 bit is set to 1, an oscillation stop detection
interrupt request is generated, and the on-chip oscillator starts oscillating. The sub clock remains as the source
for the CPU clock. The on-chip oscillator clock becomes the source for the peripheral function clocks.
When the peripheral function clocks are stopped, the oscillation stop detect function cannot be used. To enter
wait mode while using the oscillation stop detect function, set the CM02 bit in the CM0 register to 0 (peripheral
clocks do not stop in wait mode).
The oscillation stop detect function is a precaution against the unintended termination of the main clock by an
external factor. Set the CM20 bit to 0 (oscillation stop detect function not used) when the main clock is stopped
by program, i.e., entering stop mode or setting the CM05 bit in the CM0 register to 1 (main clock stops).
When the main clock frequency is 2 MHz or lower, the oscillation stop detect function is not available. In this
case, set the CM20 bit to 0.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 80 of 352
M32C/8A Group
9. Clock Generation Circuits
Start
Read the CM23 bit in the
CM2 register
1 (Main clock stops)
0 (Main clock oscillates)
Verified several times?
NO
YES
PRCR register: PRC0 bit = 1
MCD register: bits MCD4 to MCD0 = 01000b
Enable writing to registers associated with clocks
Divide-by-8 mode
CM2 register: CM22 bit = 0
Loss of the main clock is not detected
CM2 register: CM21 bit = 0
Select the main clock as the CPU clock source
PRC0 bit = 0
Disable writing to registers associated with clocks
End
Figure 9.11
9.1.4
Procedure to Switch from On-chip Oscillator Clock to Main Clock
PLL Clock
The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be
used as the clock source for the CPU clock and peripheral function clocks.
The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL
runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock
is stabilized.
The PLL clock is the VCO clock divided by either 2 or 3. When the PLL clock is used as the clock source for
the CPU clock or peripheral function clocks, set each bit as shown in Table 9.3. Figure 9.12 shows the
procedure to use the PLL clock as the CPU clock source.
Set the CM17 bit in the CM1 register to 0 (main clock as CPU clock source) and the PLC07 bit to 0 (PLL stops)
before stopping the CPU clock or the main clock.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 81 of 352
M32C/8A Group
9. Clock Generation Circuits
Table 9.3
Bit Settings to Use PLL Clock as CPU Clock Source
Multiplication
factor
PLC0 Register
PLC1 Register
PLC02 bit
PLC01 bit
PLC00 bit
2
3
0
1
1
8/3
4
1
0
0
PLL Clock
PLC12 bit
1
fPLL = 2 × fXIN
0
fPLL = 3 × fXIN
1
fPLL = 8/3 × fXIN
0
fPLL = 4 × fXIN
Start
PRCR register: PRC0 bit = 1
CM2 register: CM21 bit = 0
CM0 register: CM07 bit = 0
Enable writing to registers associated with clocks
Select the main clock as the CPU clock source
(※Set after a main clock oscillation stabilizes)
Set registers PLC0 and PLC1
Select the multiplication factor for the PLL clock
(※Set registers PLC0 and PLC1 simultaneously in 16-bit units)
PLC1
PLC0
Multiplication factor for PLL clock
00000010 01010011b
× 6/2 = 3
00000010 01010100b
× 8/2 = 4
00000110 01010011b
× 6/3 = 2
00000110 01010100b
× 8/3 = 2.66
PLC0 register: PLC07 bit = 1
PLL runs
Wait for tsu(PLL)
CM1 register : CM17 bit = 1
PRC0 bit = 0
Wait for PLL frequency synthesizer to stabilize
Select the PLL clock as the clock source for the CPU clock
and peripheral function clock
Disable writing to registers associated with clocks
End
Figure 9.12
Procedure to Use PLL Clock as CPU Clock Source
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 82 of 352
M32C/8A Group
9.2
9. Clock Generation Circuits
CPU Clock and BCLK
The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset,
the CPU clock is the main clock divided by eight. The bus clock (BCLK) has the same frequency as the CPU clock
and can be output from the BCLK pin in microprocessor mode. Refer to 9.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock, or PLL clock can be selected as the clock source for the CPU
clock.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the clock source for the CPU clock, the
selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the CPU clock. Bits MCD4
to MCD0 in the MCD register select the clock division. When the MCU enters stop mode or low-power
consumption mode, bits MCD4 to MCD0 are set to 01000b (divide-by-8 mode). Therefore, when the CPU clock
source is switched to the main clock next time, the CPU clock is the main clock divided by eight. Refer to 9.5
Power Consumption Control for details.
9.3
Peripheral Function Clock
The peripheral function clocks are used to operate the peripheral functions excluding the watchdog timer. The
clock selected by the CM17 bit in the CM1 register and the CM21 bit in the CM2 register (any of the main clock,
PLL clock, or on-chip oscillator clock) becomes the peripheral function clock source (fPFC).
9.3.1
f1, f8, f32, and f2n
f1, f8 and f32 are fPFC divided by 1, 8, or 32.
Bits PM27 and PM 26 in the PM2 register select a f2n clock source from fPFC, XIN clock (fXIND), and the onchip oscillator clock (fROC). Bits CNT3 to CNT0 in the TCSPR register select a f2n division. (n = 1 to 15. No
division when n = 0.)
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fPFC
stops. When bits PM27 and PM26 in the PM2 register are set to 10b (on-chip oscillator is selected for the f2n
clock source), f2n does not stop in wait mode.
f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer A and
timer B.
The CLKOUT pin outputs f8 and f32. Refer to 9.4 Clock Output Function for details.
9.3.2
fAD
fAD is used to operate the A/D converter and has the same frequency as fPFC.
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fAD stops.
9.3.3
fC32
fC32 is the sub clock divided by 32. fC32 is used as the count source for timer A and timer B. fC32 is available
if the sub clock is running.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 83 of 352
M32C/8A Group
9.4
9. Clock Generation Circuits
Clock Output Function
The CLKOUT pin outputs fC, f8, or f32.
The BCLK clock, which has the same frequency as the CPU clock, can be output from the BCLK pin in
microprocessor mode.
Table 9.4 lists CLKOUT pin function in microprocessor mode.
Table 9.4
CLKOUT Pin Function in Microprocessor Mode
CM0 Register(1)
PM1 Register(2)
Bits CM01 and CM00 Bits PM15 and PM14
PM0 Register(2)
PM07 bit
CLKOUT/BCLK/ALE Pin Function
0
Outputs BCLK
1
Outputs “L”
(does not function as P5_3)
00b
00b
10b
11b
−
Outputs ALE
01b
01b
−
−
Outputs fC
10b
−
−
Outputs f8
11b
−
−
Outputs f32
−: Can be set to either 0 or 1
NOTES:
1. Change the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enable).
2. Change registers PM0 and PM1 after setting the PRC1 bit in the PRCR register to 1 (write enable).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 84 of 352
M32C/8A Group
9.5
9. Clock Generation Circuits
Power Consumption Control
The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock
frequency is, the more the processing power is available. The lower the CPU clock frequency is, the less power is
consumed. When unnecessary oscillation circuits are stopped, power consumption is further reduced.
CPU operating mode, wait mode, and stop mode are provided as the power consumption control. CPU operating
mode is further separated into the following modes; main clock mode, PLL mode, low-speed mode, low-power
consumption mode, on-chip oscillator mode, and on-chip oscillator low-power consumption mode.
Figure 9.13 shows a mode transition diagram.
Reset
PLL clock
(note 1)
Stop mode
Wait mode
CM10 = 1
Interrupt
PLL mode
Main clock mode
T
A I ion
W uct
r
st
in
pt
rr u
e
t
In
WAIT
instruction
On-chip
oscillator mode
Low-speed
mode
Interrupt
Sub clock
On-chip oscillator
clock
On-chip oscillator
low-power
consumption mode
Low-power
consumption
mode
WAIT instruction
Interrupt
CM10: bit in the CM1 register
NOTE:
1. Bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) after reset.
Figure 9.13
9.5.1
Mode Transition
CPU operating mode
The CPU clock can be selected from the main clock, sub clock, on-chip oscillator clock, or PLL clock. When
switching the CPU clock source, wait until the new CPU clock source stabilizes. To change the CPU clock
source from the sub clock, on-chip oscillator clock, or PLL clock, set it to the main clock once and then switch
it to another clock.
To switch the CPU clock source from the on-chip oscillator clock to the main clock, set bits MCD4 to MCD0 in
the MCD register to 01000b (divided-by-8 mode) in on-chip oscillator mode.
Table 9.5 lists bit setting and operation mode associated with clocks.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 85 of 352
M32C/8A Group
9.5.1.1
9. Clock Generation Circuits
Main Clock Mode
The main clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock.
The main clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the
count source for timer A and timer B.
9.5.1.2
PLL Mode
The PLL clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock.
The PLL clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the
count source for timer A and timer B.
9.5.1.3
Low-Speed Mode
The sub clock is used as the source for the CPU clock. The main clock, PLL clock, or on-chip oscillator clock is
used as the source for fPFC. fC32 can be used as the count source for timer A and timer B.
9.5.1.4
Low-Power Consumption Mode
The MCU enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock is
used as the source for the CPU clock, and the on-chip oscillator clock is used as the source for fPFC. fC32 can
be used as the count source for timer A and timer B. In low-power consumption mode, bits MCD4 to MCD0 in
the MCD register become 01000b (divide-by-8 mode). Therefore, next time the CPU clock source is switched
to the main clock, the CPU clock is the main clock divided by eight.
9.5.1.5
On-Chip Oscillator Mode
The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for
the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running,
fC32 can be used as the count source for timer A and timer B.
9.5.1.6
On-Chip Oscillator Low-power Consumption Mode
The MCU enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip
oscillator mode. The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as
the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub
clock is running, fC32 can be used as the count source for timer A and timer B.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 86 of 352
M32C/8A Group
Table 9.5
9. Clock Generation Circuits
Operation Mode Setting
Oscillation Control
CPU Clock
Source
Operating Mode
CM0 Register
CM05
CM04
PLC0
Register
CM2
Register
PLC07
CM21(1)
Selector
CM0
CM1
Register
Register
CM17
CM07
Main clock
Main clock mode
0
−
−
0
0
0
PLL clock
PLL mode
0
−
1
0
1
0
Low-speed mode
0
1
−
−
−
1
Low power
consumption mode
1
1
0
−
0
1
0
−
−
1
−
0
1
−
0
1
0
0
Sub clock
On-chip oscillator mode
On-chip
On-chip oscillator lowoscillator clock power consumption
mode
−: Can be set to either 0 or 1
NOTE:
1. The CM21 bit in the CM2 register has both the oscillation control and selector functions.
9.5.2
Wait Mode
In wait mode, the CPU and watchdog timer stop operating. If the PM22 bit in the PM2 register is set to 1 (onchip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Since the main
clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their
clock source also continue to operate.
9.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode), fAD, f1, f8, and f32 stop in
wait mode. f2n, which uses the clock selected by the CM21 bit in the CM2 register as its clock source, also
stops in wait mode. Power consumption can be reduced by stopping these peripheral clocks. f2n, which uses
the XIN clock (fXIND) or on-chip oscillator clock as its clock source, and fC32 do not stop even in wait mode.
9.5.2.2
Entering Wait Mode
To enter wait mode with the CM02 bit in the CM0 register set to 1, set bits MCD4 to MCD0 in the MCD
register for the CPU clock frequency to be 10 MHz or less after dividing the main clock.
Figure 9.14 shows a procedure to enter wait mode.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 87 of 352
M32C/8A Group
9. Clock Generation Circuits
Start
(1) Initial setting
RLVL register: bits RLVL2 to RLVL0 = 7
Initial setting for the wait/stop mode
exit interrupt priority level
Set an interrupt priority level of each interrupt
(2) Before entering wait mode
I flag = 0
Set the interrupt priority level (ILVL2 to ILVL0) of
the interrupt used to exit wait mode
Interrupt disabled
(ILVL2 to ILVL0) > IPL* = (RLVL2 to RLVL0)*
Set the interrupt priority level of the interrupts,
which are not used to exit wait mode, to 0
FLG register: set IPL
Bits RLVL2 to RLVL0 = the same level as IPL
Select the operating mode from the following:
-main clock mode
-low-speed mode
-on-chip oscillator mode
-on-chip oscillator low-power consumption mode
I flag = 1
Execute the WAIT instruction
Set the processor interrupt priority level (IPL)*
Set the exit interrupt priority level (RLVL2 to RLVL0)*
When the CM02 bit in the CM0 register is 1,
set bits MCD4 to MCD0 in the MCD register
for the CPU frequency to be 10 MHz or less.
Interrupt enabled
(note) Insert at least 4 NOP's after WAIT instruction.
Wait mode
(3) After exiting wait mode
RLVL register: bits RLVL2 to RLVL0 = 7
End
Figure 9.14
Procedure to Enter Wait Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 88 of 352
Set the exit priority level as soon as exiting wait mode
M32C/8A Group
9.5.2.3
9. Clock Generation Circuits
Pin States in Wait Mode
Table 9.6 lists pin states in wait mode.
Table 9.6
Pin States in Wait Mode
Pin
States
Address bus, data bus, CS0 to CS3, BHE
Maintain the state immediately before entering wait mode
RD, WR, WRL, WRH
“H”
HLDA, BCLK
“H”
ALE
“L”
Ports
Maintain the state immediately before entering wait mode
CLKOUT
9.5.2.4
When fC is selected
Continue to output the clock
When f8, f32 are selected • When the CM02 bit in the CM0 register is 0 (peripheral clocks
do not stop in wait mode): Continue to output the clock
• When the CM02 bit is 1 (peripheral clocks stop in wait mode):
The clock is stopped and holds the level immediately before
entering wait mode
Exiting Wait Mode
Wait mode is exited by the hardware reset 1, hardware reset 2, NMI interrupt, Vdet4 detection interrupt, or
peripheral function interrupts.
As for a peripheral function interrupt that is not used to exit wait mode, set bits ILVL2 to ILVL0 in the Interrupt
Control Register for the peripheral function interrupt to 000b (interrupt disabled) before executing the WAIT
instruction.
The CM02 bit setting in the CM0 register affects the use of the peripheral function interrupts to exit wait mode.
When the CM02 bit is set to 0 (peripheral clocks do not stop in wait mode), any peripheral function interrupts
can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral clocks stop in wait mode), the
peripheral functions clocked by the peripheral function clocks stop, and therefore, the peripheral function
interrupts cannot be used to exit wait mode. However, the peripheral functions clocked by the external clock
and fC32 do not stop regardless of the CM02 bit setting. Also, f2n, which uses the XIN clock (fXIND) or onchip oscillator clock as its clock source does not stop. The interrupts generated by the peripheral functions
which operate using these clocks can be used to exit wait mode.
When the MCU exits wait mode by the peripheral function interrupts or NMI interrupt, the CPU clock does not
change before and after the WAIT instruction is executed.
Table 9.7 lists interrupts to be used to exit wait mode and usage conditions.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 89 of 352
M32C/8A Group
Table 9.7
9. Clock Generation Circuits
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt
When CM02 = 0
When CM02 = 1
NMI interrupt
Available
Available
Vdet4 detection interrupt
Available
Available
Serial interface interrupt
Available when the source clock is the
internal clock or clock input to the CLKi
pin.
Available when the source clock is the
clock input to the CLKi pin or f2n (when
fXIND or on-chip oscillator clock is
selected).
Key input interrupt
Available
Available
A/D conversion interrupt
Available in one-shot mode or singlesweep mode
Not available
Timer A interrupt
Timer B interrupt
Available in all modes
Available in event counter mode or when
the count source is fC32 or f2n (when
fXIND or on-chip oscillator clock is
selected)
INT interrupt
Available
Available
9.5.3
Stop Mode
In stop mode, all clocks are stopped. Since the CPU clock and peripheral function clocks are stopped, the CPU
and the peripheral functions which are operated by these clocks stop their operation. The least power is required
to operate the MCU in stop mode. Enter stop mode from main clock mode.
9.5.3.1
Entering Stop Mode
Stop mode is entered when setting the CM10 bit in the CM1 register to 1 (all clocks stop) while the NMI pin is
held “H”. Also, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) by setting the
CM10 bit to 1.
Figure 9.15 shows a procedure to enter stop mode.
When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction queue,
and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit
interrupt routine is handled.
Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1.
fset I
bset 0, cm1
jmp.b LABEL_001
LABEL_001:
nop
nop
nop
nop
mov.b #0, prcr
.
.
.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
; I flag is set to 1
; all clocks stopped (stop mode)
; jmp.b instruction executed (no instruction between jmp.b and LABEL.)
; nop(1)
; nop(2)
; nop(3)
; nop(4)
; protection set
Page 90 of 352
M32C/8A Group
9. Clock Generation Circuits
Start
(1) Initial setting
RLVL register: bits RLVL2 to RLVL0 = 7
Set the wait/stop mode
exit interrupt priority level to 7.
Set an interrupt priority level of each interrupt
(2) Before entering stop mode
I flag = 0
Set the interrupt priority level (ILVL2 to ILVL0) of
the interrupt used to exit stop mode
Interrupt disabled
(ILVL2 to ILVL0) > IPL* = (RLVL2 to RLVL0)*
Set the interrupt priority level of the interrupts,
which is not used to exit stop mode, to 0
FLG register: set IPL
Bits RLVL2 to RLVL0 = the same level as IPL
PRCR register: PRC0 bit = 1
PRC1 bit = 1
CM1 register: CM17 bit = 0
CM2 register: CM21 bit = 0
CM0 register: CM07 bit = 0
Set the processor interrupt priority level (IPL)*
Set the exit interrupt priority level (RLVL2 to RLVL0)*
Enable writing to registers associated with clocks
Select the main clock as the CPU clock source
(※Set after a main clock oscillation stabilizes)
When the oscillation stop detect function is used
CM2 register: CM20 bit = 0
Disable oscillation stop detect function
I flag = 1
Interrupt enabled
CM1 register: CM10 bit = 1
All clocks stop (1)
Stop mode
(3) After exiting wait mode
RLVL register: bits RLVL2 to RLVL0 = 7
Set the exit priority level as soon as exiting wait mode
End
NOTE:
1. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1.
bset 0,
cm1
jmp.b LABEL_001
LABEL_001:
nop
nop
nop
nop
mov.b #0, prcr
.
.
.
Figure 9.15
; all clocks stopped (stop mode)
; jmp.b instruction executed (no instruction
; between jmp.b and LABEL.)
; nop(1)
; nop(2)
; nop(3)
; nop(4)
; protection set
Procedure to Enter Stop Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 91 of 352
M32C/8A Group
9.5.3.2
9. Clock Generation Circuits
Pin States in Stop Mode
Table 9.8 lists pin states in stop mode.
Table 9.8
Pin States in Stop Mode
Pin
States
Address Bus, Data Bus, CS0 to CS3, BHE
Maintain the state immediately before entering stop mode
RD, WR, WRL, WRH
“H”
HLDA, BCLK
“H”
ALE
“H”
Ports
Maintain the state immediately before entering stop mode
CLKOUT
When fC is selected
“H”
When f8, f32 are selected
The clock is stopped and holds the level immediately before
entering stop mode
XIN
Placed in a high-impedance state
XOUT
“H”
XCIN, XCOUT
Placed in a high-impedance state
9.5.3.3
Exiting Stop Mode
Stop mode is exited by the hardware reset 1, NMI interrupt, Vdet4 detection interrupt, or peripheral function
interrupts. The following are the peripheral function interrupts that can be used to exit stop mode.
• Key input interrupt
• INT interrupt
• Timer A and timer B interrupts
(Available when the timer counts external pulse having 100-Hz frequency or below in event counter mode)
When only the hardware reset 1, NMI interrupt, or Vdet4 detection interrupt are used to exit stop mode, set bits
ILVL2 to ILVL0 in the Interrupt Control Registers for all the peripheral function interrupts to 000b (interrupt
disabled) before setting the CM10 bit in the CM1 register to 1 (all clocks stop).
If the voltage applied to pins VCC1 and VCC2 drops below 3.0 V in stop mode, exit stop mode by the hardware
reset 1 after the voltage has satisfied the recommended operating conditions.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 92 of 352
M32C/8A Group
9.6
9. Clock Generation Circuits
System Clock Protect Function
The system clock protect function prohibits changing the CPU clock source when the main clock is selected as the
CPU clock source. With this function, the CPU clock can continue running even if the program runs out of control.
When the PM21 bit in the PM2 register is set to 1 (disables a clock change), the following bits cannot be written:
• Bits CM02, CM05, and CM07 in the CM0 register
• Bits CM10 and CM17 in the CM1 register
• The CM20 bit in the CM2 register
• All bits in registers PLC0 and PLC1
The CPU clock continues running when the WAIT instruction is executed.
Figure 9.16 shows a procedure to use the system clock protect function. Follow the procedure while the CM05 bit
in the CM0 register is set to 0 (main clock oscillates) and the CM07 bit to 0 (main clock as CPU clock source).
Start
PRCR register: PRC1 bit = 1
Enable writing to registers associated with clocks
PM2 register: PM21 bit = 1 (1)
Disable a clock change
PRCR register: PRC1 bit = 0
Disable writing to registers associated with clocks
End
NOTE:
1. Execute the WAIT instruction when the PM21 bit in the PM2 register is set to 0.
Figure 9.16
Procedure to Use System Clock Protect Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 93 of 352
M32C/8A Group
10. Protection
10. Protection
The function protects important registers from being inadvertently overwritten in case of a program crash. Figure 10.1
shows the PRCR register.
The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to 1
(write enable). Set the PD9 or PS3 register immediately after the PRC2 bit is set to 1. Do not generate an interrupt or
a DMA or DMACII transfer between these two instructions. Bits PRC0, PRC1, and PRC3 do not become 0
automatically even after a write to the SFR area. Set bits PRC0, PRC1, and PRC3 to 0 by program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000Ah
Bit Symbol
Bit Name
After Reset
XXXX 0000b
Function
RW
PRC0
Protect bit 0(1)
Writing to registers CM0, CM1, CM2, MCD,
PLC0, and PLC1 is enabled
0: Write disable
1: Write enable
RW
PRC1
Protect bit 1(1)
Writing to registers PM0, PM1, PM2, INVC0,
and INVC1 is enabled
0: Write disable
1: Write enable
RW
PRC2
Protect bit 2(2)
Writing to registers PD9 and PS3 is enabled
0: Write disable
1: Write enable
RW
PRC3
Protect bit 3(1)
Writing to registers VCR2 and D4INT is enabled
0: Write disable
1: Write enable
RW
−
(b7-b4)
Unimplemented.
Write 0. Read as undefined value.
−
NOTES:
1. Bits PRC0, PRC1, and PRC3 do not become 0 automatically even after a write to the SFR area. Set bits PRC0, PRC1, and
PRC3 to 0 by program.
2. The PRC2 bit becomes 0 by a write to the SFR area after the PRC2 bit is set to 1.
Figure 10.1
PRCR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 94 of 352
M32C/8A Group
11. Interrupts
11. Interrupts
11.1
Types of Interrupts
Figure 11.1 shows the types of interrupts.
Undefined instruction (UND instruction)
Software
(Non-maskable interrupts)
Overflow (INTO instruction)
BRK instruction
BRK2 instruction(2)
INT instruction
NMI
Watchdog timer
Interrupts
Oscillation stop detection
Special
(Non-maskable interrupts)
Hardware
Vdet4 detection
Single step(2)
Address match
Peripheral function(1)
(Maskable interrupts)
DMACII transfer complete
NOTES:
1. Peripheral function interrupts are generated by the on-chip peripheral functions in the MCU.
2. Do not use these interrupts. They are for use with development tool only.
Figure 11.1
Interrupts
• Maskable interrupts
The I flag and IPL can enable and disable these interrupts.
The interrupt priority order can be changed based on interrupt priority level.
• Non-maskable interrupt
These interrupts cannot be disabled regardless of the I flag and IPL settings.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 95 of 352
M32C/8A Group
11.2
11. Interrupts
Software Interrupts
Software interrupts occur when particular instructions are executed. Software interrupts are non-maskable.
11.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
11.2.2
Overflow Interrupt
The overflow interrupt occurs when the INTO instruction is executed while the O flag in the FLG register is 1
(arithmetic operation overflow). Instructions that can set the O flag are: ABS, ADC, ADCF, ADD, ADDX,
CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
11.2.3
BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
11.2.4
BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. This is for use with development support tool only.
11.2.5
INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can specify
software interrupt numbers 0 to 63. Software interrupt numbers 8 to 43 are assigned to the vector table used for
the peripheral function interrupt. This means that the MCU is able to execute the peripheral function interrupt
routine by executing the INT instruction. When the INT instruction is executed, values in the FLG register and
PC are saved to the stack. The relocatable vector of the specified software interrupt number is stored in PC.
The stack, where the data is saved, varies depending on a software interrupt number.
ISP is selected for software interrupt numbers 0 to 31. (The U flag in the FLG register becomes 0.) For
software interrupt numbers 32 to 63, SP which is selected immediately before executing the INT instruction is
used. (The U flag does not change.)
For the peripheral function interrupt, the FLG register value is saved and the U flag becomes 0 (ISP selected)
when an interrupt request is acknowledged. Therefore, for software interrupt numbers 32 to 43, SP to be used
can differ depending on whether an interrupt is generated by a peripheral function or by the INT instruction.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 96 of 352
M32C/8A Group
11.3
11. Interrupts
Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1
Special Interrupts
Special interrupts are non-maskable.
11.3.1.1
NMI Interrupt
The NMI interrupt occurs when a signal applied to the NMI pin changes from high level (“H”) to low level
(“L”). Refer to 11.8 NMI Interrupt for details.
11.3.1.2
Watchdog Timer Interrupt
The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog
Timer for details.
11.3.1.3
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9.
Clock Generation Circuits for details.
11.3.1.4
Vdet4 Detection Interrupt
The Vdet4 detection interrupt occurs when the voltage applied to VCC1 rises above or drops below Vdet4.
Refer to 6.2 Vdet4 Detection Function for details.
11.3.1.5
Single-Step Interrupt
Do not use the single-step interrupt. This is for use with development support tool only.
11.3.1.6
Address Match Interrupt
When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match
interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi
register (i = 0 to 7) .
Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if
a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address
Match Interrupt for details.
11.3.2
DMACII Transfer Complete Interrupt
The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for
details.
11.3.3
Peripheral Function Interrupt
The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function
interrupts and software interrupt numbers 8 to 43 for the INT instruction use the same interrupt vector table.
The peripheral function interrupt is maskable.
See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual
peripheral functions for details.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 97 of 352
M32C/8A Group
11.4
11. Interrupts
High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt routine in
three cycles. When the FSIT bit in the RLVL register is set to 1 (interrupt priority level 7 is used for the highspeed interrupt), the interrupt that bits ILVL2 to ILVL0 in the Interrupt Control Register are set to 111b (level 7)
becomes the high-speed interrupt.
Only one interrupt can be set as the high-speed interrupt. To use the high-speed interrupt, do not set multiple
interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to 0 (interrupt priority level 7 is
used for interrupt) to use the high-speed interrupt.
Set the starting address of a high-speed interrupt routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register value is saved into the SVF register and the
PC value is saved into the SVP register. A program is executed from an address indicated by the VCT register.
Use the FREIT instruction to return from a high-speed interrupt routine. Values saved into registers SVF and
SVP are restored to the FLG register and PC by executing the FREIT instruction.
The high-speed interrupt, and DMA2 and DMA3 share some of the registers. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can still be used.
Figure 11.2 shows a procedure to use high-speed interrupt.
Start
I flag = 0
RLVL register: FSIT bit = 1
DMAII bit = 0
Interrupt disabled
Interrupt priority level 7 is used for the high-speed interrupt
Interrupt priority level 7 is used for interrupt
VCT regsiter: Set the starting address of
the high-speed interrupt routine
Set the peripheral function used for the high-speed
interrupt source
Interrupt Control Register:
Bits ILVL2 to ILVL0 = 111b (level 7)
I flag = 1
Set the interrupt priority level in the Interrupt Control Register
for the peripheral function used for the high-speed
interrupt source.
Interrupt enabled
Operate peripheral functions
End
Figure 11.2
Procedure to Use High-Speed Interrupt
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 98 of 352
M32C/8A Group
11.5
11. Interrupts
Interrupts and Interrupt Vectors
There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector.
When an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt
vector. Figure 11.3 shows an interrupt vector.
MSB
Figure 11.3
11.5.1
LSB
Vector address+0
8 Low-order bits of address
Vector address+1
8 Middle-order bits of address
Vector address+2
8 High-order bits of address
Vector address+3
00h
Interrupt Vector
Fixed Vector Table
The fixed vector table is allocated addresses FFFFDCh to FFFFFFh. Table 11.1 lists the fixed vector table.
Table 11.1
Fixed Vector Table
Interrupt
Source
Vector Addresses
Address (L) to Address (H)
Remarks
Reference
Undefined
instruction
FFFFDCh to FFFFDFh
Overflow
FFFFE0h to FFFFE3h
BRK instruction
FFFFE4h to FFFFE7h
Address match
FFFFE8h to FFFFEBh
−
FFFFECh to FFFFEFh
Reserved space
Watchdog timer
FFFFF0h to FFFFF3h
These addresses are used for Reset,
the watchdog timer interrupt,
clock generation circuit,
oscillation stop detection
watchdog timer
interrupt, and Vdet4 detection
interrupt.
−
FFFFF4h to FFFFF7h
Reserved space
NMI
FFFFF8h to FFFFFBh
Reset
FFFFFCh to FFFFFFh
11.5.2
M32C/80 series
software manual
If the content of the address
FFFFE7h is FFh, the CPU
executes from the address
stored into software interrupt
number 0 in the relocatable
vector table.
Reset
Relocatable Vector Table
The relocatable vector table occupies 256 bytes beginning from the address set in the INTB register. Tables
11.2 and 11.3 list the relocatable vector table.
Set an even address to the starting address of the vector set in the INTB register to increase the interrupt
sequence execution rate.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 99 of 352
M32C/8A Group
Table 11.2
11. Interrupts
Relocatable Vector Tables (1)
Vector Table Address
Address (L) to Address (H)(1)
Interrupt Source
Software
Interrupt Number
Reference
BRK instruction(2)
+0 to +3 (0000h to 0003h)
0
Reserved space
+4 to +31 (0004h to 001Fh)
1 to 7
M32C/80 Series
Software Manual
DMA0
+32 to +35 (0020h to 0023h)
8
DMAC
DMA1
+36 to +39 (0024h to 0027h)
9
DMA2
+40 to +43 (0028h to 002Bh)
10
DMA3
+44 to +47 (002Ch to 002Fh)
11
Timer A0
+48 to +51 (0030h to 0033h)
12
Timer A1
+52 to +55 (0034h to 0037h)
13
Timer A2
+56 to +59 (0038h to 003Bh)
14
Timer A3
+60 to +63 (003Ch to 003Fh)
15
+64 to +67 (0040h to 0043h)
16
+68 to +71 (0044h to 0047h)
17
+72 to +75 (0048h to 004Bh)
18
+76 to +79 (004Ch to 004Fh)
19
Timer A4
UART0 transmission,
UART0 reception,
ACK(3)
UART1 transmission,
UART1 reception,
NACK(3)
NACK(3)
ACK(3)
Timer A
Serial interfaces
+80 to +83 (0050h to 0053h)
20
Timer B0
+84 to +87 (0054h to 0057h)
21
Timer B1
+88 to +91 (0058h to 005Bh)
22
Timer B2
+92 to +95 (005Ch to 005Fh)
23
Timer B3
+96 to +99 (0060h to 0063h)
24
Timer B4
+100 to +103 (0064h to 0067h)
25
INT5
+104 to +107 (0068h to 006Bh)
26
INT4
+108 to +111 (006Ch to 006Fh)
27
INT3
+112 to +115 (0070h to 0073h)
28
INT2
+116 to +119 (0074h to 0077h)
29
INT1
+120 to +123 (0078h to 007Bh)
30
INT0
+124 to +127 (007Ch to 007Fh)
31
+128 to +131 (0080h to 0083h)
32
Timer B
+132 to +135 (0084h to 0087h)
33
Serial interfaces
+136 to +139 (0088h to 008Bh)
34
+140 to +143 (008Ch to 008Fh)
35
Timer B5
UART2 transmission,
UART2 reception,
NACK(3)
ACK(3)
UART3 transmission,
NACK(3)
ACK(3)
+144 to +147 (0090h to 0093h)
36
UART4 transmission, NACK(3)
+148 to +151 (0094h to 0097h)
37
UART4 reception, ACK(3)
+152 to +155 (0098h to 009Bh)
38
UART3 reception,
NOTES:
1. These are the address offset from the base address set in the INTB register.
2. The I flag does not disable this interrupt.
3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 100 of 352
Timer B
Interrupts
M32C/8A Group
Table 11.3
11. Interrupts
Relocatable Vector Tables (2)
Interrupt Source
Vector Table Address
Address (L) to Address (H)(1)
Software
Interrupt Number
Bus conflict detection,
Start condition detection/
Stop condition detection
(UART2)(3)
+156 to +159 (009Ch to 009Fh)
39
Bus conflict detection,
Start condition detection/
Stop condition detection
(UART3 or UART0)(4)
+160 to +163 (00A0h to 00A3h)
40
Bus conflict detection,
Start condition detection/
Stop condition detection
(UART4 or UART1)(4)
+164 to +167 (00A4h to 00A7h)
41
A/D0
+168 to +171 (00A8h to 00ABh)
42
Reference
Serial interfaces
A/D converter
Key input
+172 to +175 (00ACh to 00AFh)
43
Interrupts
Reserved space
+176 to +255 (00B0h to 00FFh)
44 to 63
-
INT instruction(2)
+0 to +3 (0000h to 0003h) to
+252 to +255 (00FCh to 00FFh)
0 to 63
Interrupts
NOTES:
1. These are the address offset from the base address set in the INTB register.
2. The I flag does not disable this interrupt.
3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources.
4. The IFSR6 bit in the IFSR register selects either UART0 or UART3. The IFSR7 bit selects either UART1 or
UART4.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 101 of 352
M32C/8A Group
11.6
11. Interrupts
Interrupt Request Acknowledgement
Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however,
requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests
are generated.
For the peripheral function interrupts to be acknowledged, the following conditions must be met:
• I flag = 1
• IR bit = 1
• Bits ILVL2 to ILVL > IPL
The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG
register. The IR bit and bits ILVL2 to ILVL0 are in the Interrupt Control Register.
11.6.1
I Flag and IPL
The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts
are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag is automatically set to 0 after
reset.
IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt
has higher priority level than IPL, the interrupt is acknowledged.
Table 11.4 lists interrupt priority levels associated with IPL.
Table 11.4
Interrupt Priority Levels
IPL2 to IPL0
11.6.2
Required Interrupt Priority Levels to Be Acknowledged
for Maskable Interrupts
0
Level 1 and above
1
Level 2 and above
2
Level 3 and above
3
Level 4 and above
4
Level 5 and above
5
Level 6 and above
6
Level 7 and above
7
All maskable interrupts are disabled
Interrupt Control Registers and RLVL Register
The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5
show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 102 of 352
M32C/8A Group
11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TA0IC to TA4IC
TB0IC to TB5IC
S0TIC to S4TIC
S0RIC to S4RIC
BCN0IC to BCN4IC
DM0IC to DM3IC
AD0IC
KUPIC
006Ch, 008Ch, 006Eh, 008Eh, 0070h
0094h, 0076h, 0096h, 0078h, 0098h, 0069h
0090h, 0092h, 0089h, 008Bh, 008Dh
0072h, 0074h, 006Bh, 006Dh, 006Fh
0071h, 0091h, 008Fh, 0071h(1), 0091h(2)
0068h, 0088h, 006Ah, 008Ah
0073h
0093h
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Bit Symbol
Bit Name
b2 b1 b0
ILVL0
ILVL1
Interrupt priority level select bits
ILVL2
IR
−
(b7-b4)
Interrupt request bit(3)
Unimplemented.
Write 0. Read as undefined value.
NOTES:
1. The BCN0IC register shares the address with the BCN3IC register.
2. The BCN1IC register shares the address with the BCN4IC register.
3. The IR bit can be set to 0 only. (Do not set to 1.)
Figure 11.4
Interrupt Control Register (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
Page 103 of 352
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt not requested
1: Interrupt requested
X000b
X000b
X000b
X000b
X000b
X000b
X000b
X000b
RW
RW
RW
RW
RW
−
M32C/8A Group
11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
INT0IC to INT2IC
INT3IC to INT5IC(1)
009Eh, 007Eh, 009Ch
007Ch, 009Ah, 007Ah
XX00 X000b
XX00 X000b
Bit Symbol
Bit Name
b2 b1 b0
ILVL0
ILVL1
Function
Interrupt priority level
select bits
ILVL2
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
RW
RW
RW
RW
Interrupt request bit(2)
0: Interrupt not requested
1: Interrupt requested
RW
POL
Polarity switch bit(3)
0: Falling edge / "L" level selected
1: Rising edge / "H" level selected
RW
LVS
Level sensitive/
edge sensitive switch bit (4)
0 : Edge sensitive
1 : Level sensitive
RW
IR
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
−
NOTES:
1. When a 16-bit data bus is used in microprocessor mode, pins INT3 to INT5 are used as data bus. In this case, set bits ILVL2 to
ILVL0 in registers INT3IC to INT5IC to 000b.
2. The IR bit can be set to 0 only. (Do not set to 1.)
3. Set the POL bit to 0 when its corresponding bit in the IFSR register is set to 1 (both edges).
4. When the LVS bit is set to 1, set its corresponding bit in the IFSR register to 0 (one edge).
Figure 11.5
11.6.2.1
Interrupt Control Register (2)
Bits ILVL2 to ILVL0
Bits ILVL2 to ILVL0 determine an interrupt priority level. The higher the interrupt priority level is, the higher
priority the interrupt has.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is enabled
only when its interrupt priority level is higher than IPL. When bits ILVL2 to ILVL0 are set to 000b (level 0),
the interrupt is disabled.
11.6.2.2
IR Bit
The IR bit is automatically set to 1 (interrupt requested) by hardware when an interrupt request is generated.
After an interrupt request is acknowledged and an interrupt sequence in the corresponding interrupt vector is
executed, the IR bit is automatically set to 0 (interrupt not requested) by hardware.
The IR bit can be set to 0 by program. Do not set it to 1.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 104 of 352
M32C/8A Group
11. Interrupts
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
RLVL
009F
XXXX 0000b
Bit Symbol
Bit Name
b2 b1 b0
RLVL0
RLVL1
Function
Exit wait mode/stop mode
interrupt priority level
control bits(1)
RLVL2
FSIT
High-speed interrupt select bit
−
(b4)
Unimplemented.
Write 0. Read as undefined value.
DMAII
DMACII select bit (4)
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
0 0 0: Level 0
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt priority level 7 is used for normal
interrupt
1: Interrupt priority level 7 is used for high-speed
interrupt(2)(3)
RW
RW
RW
RW
RW
−
0: Interrupt priority level 7 is used for interrupt
1: Interrupt priority level 7 is used for DMACII
transfer (2)
RW
−
NOTES:
1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits
RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register.
2. Do not set both the FSIT and DMAII bits to 1.
Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b.
3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt.
4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt
Control Register.
Figure 11.6
11.6.2.3
RLVL Register
Bits RLVL2 to RLVL0
When using an interrupt to exit wait mode or stop mode, refer to 9.5.2 Wait Mode and 9.5.3 Stop Mode for
details.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 105 of 352
M32C/8A Group
11.6.3
11. Interrupts
Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority after the instruction in progress is completed. Then, the CPU starts the interrupt sequence from the
following cycle. However, for the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT, and RMPA
instructions, if an interrupt request is generated while one of these instructions is being executed, the MCU
suspends the instruction execution to start the interrupt sequence.
The interrupt sequence is performed as indicated below:
(1) The CPU obtains the interrupt number by reading the address 000000h (address 000002h for the highspeed interrupt). Then, the corresponding IR bit to the interrupt becomes 0 (interrupt not requested).
(2) The FLG register value, immediately before the interrupt sequence, is saved to a temporary register(1) in
the CPU.
(3) Each bit in the FLG register becomes as follows:
The I flag becomes 0 (interrupt disabled)
The D flag becomes 0 (single-step interrupt disabled)
The U flag becomes 0 (ISP selected)
(4) The internal register value (the FLG register value saved in (2)) in the CPU is saved to the stack; or to
the SVF register for the high-speed interrupt.
(5) The PC value is saved to the stack; or to the SVP register for the high-speed interrupt.
(6) The interrupt priority level of the acknowledged interrupt becomes the IPL level.
(7) An interrupt vector corresponding to the acknowledged interrupt is stored into PC.
After the interrupt sequence is completed, the CPU executes the instruction from the starting address of the
interrupt routine.
NOTE:
1. Temporary register cannot be accessed by users.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 106 of 352
M32C/8A Group
11.6.4
11. Interrupts
Interrupt Response Time
Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt
request generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the
period between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure
11.7), and the period required to perform the interrupt sequence ((b) in Figure 11.7).
Interrupt request is
generated
Interrupt request is
acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in interrupt routine
(b)
Interrupt response time
(a) Period between an interrupt request generation and the end of instruction execution.
(b) Period required to perform an interrupt sequence.
Figure 11.7
Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require
the longest time (a), which is at the maximum of 42 cycles.
Table 11.5 lists time (b).
Table 11.5
Interrupt Sequence Execution Time(1)
Interrupts
Execution Time
(in terms of CPU clock)
Peripheral function
16 cycles
INT instruction
14 cycles
NMI
Watchdog timer
Undefined instruction
Address match
15 cycles
Overflow
16 cycles
BRK instruction (relocatable vector table)
19 cycles
BRK instruction (fixed vector table)
21 cycles
High-speed interrupt
5 cycles
NOTE:
1. The values when interrupt vectors are allocated in even addresses in the external ROM, and when the external
bus cycle is two CPU clock cycles. This does not apply to the high-speed interrupt.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 107 of 352
M32C/8A Group
11.6.5
11. Interrupts
IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, the priority level for the acknowledged interrupt
becomes the IPL level.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt that has no interrupt
priority level occurs, the value shown in Table 11.6 becomes the IPL level.
Table 11.6
Interrupts without Interrupt Priority Levels and IPL
Interrupt Source
IPL level
Watchdog timer, NMI, oscillation stop detection, Vdet4 detection
7
Software, address match
11.6.6
Not changed
Saving a Register
In the interrupt sequence, values of the FLG register and PC are saved to the stack.
Figure 11.8 shows the stack states before and after an interrupt request is acknowledged.
The other necessary registers are saved by program at the beginning of the interrupt routine. The PUSHM
instruction can save multiple registers(1) in the register bank currently used.
Refer to 11.4 High-Speed Interrupt for the high-speed interrupt.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Address
Address
MSB
Stack
LSB
MSB
Stack
m-6
m-6
PCL
m-5
m-5
PCM
m-4
m-4
PCH
m-3
m-3
00h
m-2
m-2
FLGL
m-1
FLGH
m-1
m
Previous stack
contents
m+1
Previous stack
contents
[SP]
SP value before
an interrupt is
generated
Stack state before an interrupt
request is acknowledged
Figure 11.8
m
Previous stack
contents
m+1
Previous stack
contents
LSB
[SP]
New SP value
PCL: 8 low-order bits of PC
PCM: 8 middle-order bits of PC
PCH: 8 high-order bits of PC
FLGL: 8 low-order bits of FLG
FLGH: 8 high-order bits of FLG
Stack state before an interrupt
request is acknowledged
Stack States Before and After Acknowledgement of Interrupt Request
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 108 of 352
M32C/8A Group
11.6.7
11. Interrupts
Returning from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC,
which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And
then, the program that was running before an interrupt request was acknowledged, resumes its process. The
high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details.
Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved
by program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched
back to the bank used immediately before the interrupt sequence.
11.6.8
Interrupt Priority
If two or more interrupt requests are detected at the same sampling points (a timing to detect whether any
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable
interrupts (peripheral function interrupts).
Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure
11.9 shows the priority of hardware interrupts.
The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt
causes the MCU to execute an interrupt routine.
Reset
H
NMI
Watchdog timer
Oscillation stop detection
Vdet4 detection
Peripheral function
Address match
Figure 11.9
11.6.9
L
Interrupt Priority of Hardware Interrupts
Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt
requests are generated at the same sampling point.
Figure 11.10 shows the interrupt priority level select circuit.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 109 of 352
M32C/8A Group
High
11. Interrupts
Interrupt priority level
Level 0 (initial value)
DMA0
DMA1
DMA2
DMA3
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
UART0 transmission/NACK
UART0 reception/ACK
UART1 transmission/NACK
UART1 reception/ACK
Timer B0
Timer B1
Timer B2
Interrupt priority level
Timer B3
Bus conflict/
start or stop condition detection
(UART0, UART3)
Timer B4
INT5
INT4
Bus conflict/
start or stop condition detection
(UART1, UART4)
INT3
A/D0
INT2
Key input interrupt
INT1
INT0
Bits RLVL2 to RLVL0
Timer B5
Interrupt request priority
level detection result outputs
(to the clock generation
circuit)
UART2 transmission/NACK
UART2 reception/ACK
IPL
UART3 transmission/NACK
UART3 reception/ACK
I flag
UART4 transmission/NACK
UART4 reception/ACK
Low
Bus conflict/
start or stop condition detection
(UART2)
Watchdog timer,
oscillation stop detection,
Vdet4 detection
NMI
DMACII
Peripheral function interrupt priority
(if priority levels are the same)
Figure 11.10
Address match
Interrupt Priority Level Select Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 110 of 352
Interrupt request
acknowledged
(to CPU)
M32C/8A Group
11.7
11. Interrupts
INT Interrupt
External input to pins INT0 to INT5 generate the INT0 to INT5 interrupts. INT interrupts can select either edge
sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input signal level
to the INTi pin (i = 0 to 5) triggers an interrupt request.
To use INT interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and select a
rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the IFSR
register. When the IFSRi bit is set to 1 (both edges), set the corresponding POL bit to 0 (falling edge). When the
selected edge is detected at the INTi pin, the corresponding IR bit becomes 1.
To use INT interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either “L” level or “H”
level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the INTi pin,
the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as the
selected level is detected to the INTi pin. When the input signal is changed to the inactive level, the IR bit becomes
0 by the interrupt request acknowledgement or writing a 0 by program.
Interrupts can be enabled or disabled using bits ILVL2 toILVL0 in the INTiIC register.
Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows the IFSR register.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 111 of 352
M32C/8A Group
11. Interrupts
< Procedure for Edge Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit
Select either one edge or both edge
INTiIC register: POL bit
LVS bit = 0
Select polarity (Set to 0 when both edges are selected)
Select edge sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
< Procedure for Level Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit = 0
Select one edge
INTiIC register: POL bit
LVS bit = 1
Select polarity
Select level sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
Figure 11.11
INTi Interrupt Setting Procedures (i = 0 to 5)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 112 of 352
i = 0 to 5
M32C/8A Group
11. Interrupts
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
031Fh
Bit Symbol
Bit Name
After Reset
00h
Function
IFSR0
INT0 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR1
INT1 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR2
INT2 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR3
INT3 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR4
INT4 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR5
INT5 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR6
UART0, UART3
interrupt source select bit
0: UART3 bus conflict, start condition detection,
stop condition detection
1: UART0 bus conflict, start condition detection,
stop condition detection
RW
IFSR7
UART1, UART4
interrupt source select bit
0: UART4 bus conflict, start condition detection,
stop condition detection
1: UART1 bus conflict, start condition detection,
stop condition detection
RW
NOTE:
1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the
corresponding INTilC register to 0 (falling edge).
Figure 11.12
IFSR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 113 of 352
M32C/8A Group
11.8
11. Interrupts
NMI Interrupt
The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes
from “H” level to “L” level. A read from the P8_5 bit in the P8 register returns the input level of the NMI pin.
When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor (pull-up). “H” level or “L” level
width of the signal applied to the NMI pin must be 2 CPU clock cycles + 300 ns or more.
11.9
Key Input Interrupt
The IR bit in the KUPIC register becomes 1 when an falling edge is detected at any of the pins P10_4 to P10_7 set
to input mode. The key input interrupt can also be used as key-on wake-up function to exit wait mode or stop
mode. To use the key input interrupt, do not use pins P10_4 to P10_7 as A/D input. Figure 11.13 shows a block
diagram of the key input interrupt. When an “L” signal is applied to one of the pins P10_4 to P10_7 in input mode,
an falling edge detected at the other pins is not recognized as an interrupt request signal.
When the PSC_7 bit in the PSC register is set to 1 (AN_4 to AN_7), the input buffer for ports or the key input
interrupt is disconnected. Therefore, the pin level cannot be obtained by reading the Port P10 register in input
mode. Also, the IR bit in the KUPIC register does not become 1 even if a falling edge is detected at pins KI0 to
KI3.
PU31 bit
Pull-up
transistor
PD10_7 bit
PSC_7 bit
PD10_7 bit
P10_7/KI3
PD10_6 bit
Pull-up
transistor
Key input interrupt request
P10_6/KI2
Pull-up
transistor
PD10_5 bit
Pull-up
transistor
PD10_4 bit
P10_5/KI1
PD10_4 to PD10_7: Bits in the PD10 register
PSC_7: Bit in the PSC register
PU31: Bit in the PUR3 register
P10_4/KI0
Figure 11.13
Key Input Interrupt
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 114 of 352
M32C/8A Group
11. Interrupts
11.10 Address Match Interrupt
The address match interrupt is non-maskable. This interrupt occurs immediately before executing the instruction
stored in the address specified by the RMADi register (i=0 to 7). Eight addresses can be set for the address match
interrupt. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled.
Figure 11.14 shows registers associated with the address match interrupt.
Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if a
table data or any address other than the starting address of the instruction is set.
Address Match Interrupt Register i (i = 0 to 7)
b23
b16 b15
b8 b7
b0
Symbol
Address
RMAD0
RMAD1
RMAD2
RMAD3
RMAD4
RMAD5
RMAD6
RMAD7
0012h to 0010h
0016h to 0014h
001Ah to 0018h
001Eh to 001Ch
002Ah to 0028h
002Eh to 002Ch
003Ah to 0038h
003Eh to 003Ch
After Reset
000000h
000000h
000000h
000000h
000000h
000000h
000000h
000000h
Function
Addressing register for the address match interrupt
Setting Range
RW
000000h to FFFFFFh
RW
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
AIER
0009h
00h
Bit Symbol
Figure 11.14
Bit Name
Function
AIER0
Address match interrupt 0
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER1
Address match interrupt 1
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER2
Address match interrupt 2
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER3
Address match interrupt 3
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER4
Address match interrupt 4
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER5
Address match interrupt 5
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER6
Address match interrupt 6
enable bit
0: interrupt disabled
1: interrupt enabled
RW
AIER7
Address match interrupt 7
enable bit
0: interrupt disabled
1: interrupt enabled
RW
RMAD0 to RMAD7 Registers, AIER Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 115 of 352
M32C/8A Group
12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit freerunning counter. If a write to the WDTS register is not performed due to a program running out of control, the freerunning counter underflows, which results in the watchdog timer interrupt generation or the MCU reset. When
operating the watchdog timer, write to the WDTS register in a shorter cycle than the watchdog timer cycle in such as
the main routine.
Tables 12.1 and 12.2 list specifications of the watchdog timer. Figure 12.1 shows a block diagram of the watchdog
timer. Figures 12.2 and 12.3 show registers associated with the watchdog timer.
Table 12.1
Watchdog Timer Specifications (1)
Items
Count operation
Count start condition
When underflows
After underflows
Read from watchdog timer
Specifications
The free-running counter decrements
Writing to the WDTS register:
A write to the WDTS register initializes a free-running counter and the counter
decrements from 7FFFh
One of the following occurs (selectable using the CM06 bit in the CM0 register):
• Watchdog timer interrupt generation(1)
• MCU reset
The counter continues decrementing
(when the watchdog timer interrupt is selected)
A read from bit 4 to bit 0 in the WDC register returns bit 14 to bit 10 of the free-running
counter
NOTE:
1. The watchdog timer shares the same vector with the oscillation stop detection interrupt and Vdet4 detection
interrupt. When using the watchdog timer interrupt simultaneously with these interrupts, determine whether the
watchdog timer interrupt is generated by reading the D43 bit in the D4INT register in the interrupt rouine.
Table 12.2
Watchdog Timer Specifications (2)
Item
PM22 bit in PM2 register(1)
CM07 bit in CM0 register
WDC7 bit in WDC register
Clock source
Prescaler
Count source for counter
Bit Setting and Specifications
0
0
0
0
0
1
1
0
−
CPU clock
Clock divided by MCD register
Sub clock
Divide-by-16
Divide-by-128
Divide-by-2
1
−
−
On-chip oscillator
not available
1
× 16
fCPU
1
fCPU × 128
1
×2
fCPU
1
fROC
Time-out period (formula)(2)
1
× 524288
fCPU
1
fCPU × 4194304
1
× 65536
fCPU
1
fROC × 32768
Time-out period (reference)
Approx. 16.4 ms
fCPU = 32 MHz
Approx. 131.1 ms
fCPU = 32 MHz
Approx. 2 s
fCPU = 32 kHz
Approx. 32.8 ms
fROC = 1 MHz
Operation in wait mode,
stop mode, and hold state
Stops
Operates(3)
−: either 0 or 1
fCPU: CPU clock frequency
fROC: On-chip oscillator clock frequency
NOTES:
1. Once the PM22 bit is set to 1, it cannot be set to 0 by program.
2. Difference between the calculation result and actual period can be one count source cycle of the counter.
3. A write to the CM10 bit in the CM1 register is disabled. Writing a 1 has no effect and the MCU does not enter
stop mode. The watchdog timer interrupt cannot be used to exit wait mode.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 116 of 352
M32C/8A Group
12. Watchdog Timer
Prescaler
1/16
CPU clock
Wait mode signal
HOLD
1/128
1/2
CM07=0
WDC7=0
CM07=0
WDC7=1
CM07=1
PM22
CM06
0
1
Write signal to the WDTS register
1
D43
Figure 12.1
Watchdog Timer Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 117 of 352
Reset
Vdet4
detection
interrupt signal
Oscillation stop
detection
interrupt signal
Internal reset signal
CM06, CM07: bits in the CM0 register
WDC7: bit in the WDC register
PM22: bit in the PM2 register
D43: bit in the D4INT register
Watchdog timer interrupt signal
Watchdog timer
Set to
7FFFh
On-chip oscillator clock
0
Watchdog timer
interrupt request
(non-maskable)
M32C/8A Group
12. Watchdog Timer
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
After Reset
0000 1000b
Address
0006h
Bit Symbol
Bit Name
Function
b1 b0
CM00
Clock output function select bits (2)
CM01
0 0: I/O port P5_3(2)
0 1: Outputs fC
1 0: Outputs f8
1 1: Outputs f32
RW
RW
RW
CM02
Peripheral function clock stop in
wait mode bit(9)
0: Peripheral clocks do not stop in wait mode
1: Peripheral clocks stop in wait mode (3)
RW
CM03
XCIN-XCOUT drive capability
select bit(10)
0: Low
1: High
RW
CM04
Port XC switch bit
0: I/O port function
1: XCIN-XCOUT oscillation function (4)
RW
CM05
Main clock (XIN-XOUT)
stop bit(5, 9)
0: Main clock oscillates
1: Main clock stops (6)
RW
CM06
Watchdog timer
function select bit
0: Watchdog timer interrupt
1: Reset(7)
RW
CM07
CPU clock select bit 0 (8, 9)
0: Clock selected by the CM21 bit divided by
the MCD register
1: Sub clock
RW
NOTES:
1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. The BCLK, ALE, or "L" signal is output from the P5_3 pin in microprocessor mode. The P5_3 does not function as an I/O port.
3. fC32 does not stop running.
4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the
PU25 bit in the PUR2 register to 0 (no pull-up).
5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power
consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock
oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21
bit in the CM2 register to 1 (on-chip oscillator clock).
When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled
up to the XOUT pin via the feedback resistor.
6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip
oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1.
7. Once the CM06 bit is set to 1, it cannot be set to 0 by program.
8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes.
Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes.
Do not change the CM07 bit simultaneously with the CM04 or CM05 bit.
9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect.
10. When stop mode is entered, the CM03 bit becomes 1.
Figure 12.2
CM0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 118 of 352
M32C/8A Group
12. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
WDC
Address
000Fh
After Reset
00XX XXXXb
Bit Symbol
Bit Name
−
(b4-b0)
High-order bits of watchdog timer
WDC5
Cold start/warm start determine
flag(1)
0: Cold start
1: Warm start
RW
Reserved bit
Set to 0
RW
Prescaler select bit
0: Divide-by-16
1: Divide-by-128
RW
−
(b6)
WDC7
Function
RW
RO
NOTES:
1. The WDC5 bit is 0 after power-on. It can be set to 1 only by program. The bit becomes 1 by writing either a 0 or 1.
The bit maintains a value set before reset, even after reset has been performed.
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000Eh
Address
Undefined
Function
The counter is initialized and starts decrementing by a write instruction to the WDTS register.
7FFFh is the default value after initialization no matter what value is written.
Figure 12.3
WDC Register, WDTS Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 119 of 352
RW
WO
M32C/8A Group
13. DMAC
13. DMAC
DMAC allows data to be sent to and from memory without involving the CPU. The M32C/8A Group has four DMAC
channels. DMAC transfers a 8- or 16-bit data from a source address to a destination address for each transfer request.
DMA0 and DMA1 must be prioritized when using DMAC. DMA2 and DMA3 share the registers with the high-speed
interrupts. The high-speed interrupts cannot be used when three or more DMAC channels are used.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. DMAC
employing the cycle-steal method enables a high-speed operation from a transfer request to a completion of 16-bit
(word) or 8-bit (byte) data transfer.
Figure 13.1 shows a mapping of DMAC-associated registers. Table 13.1 lists specifications of DMAC. Figures 13.2
to 13.6 show DMAC-associated registers. Figures 13.7 and 13.8 show register settings.
Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to set the registers.
To set registers DCT2, DCT3, DRC2, DRC3, DMA2, and DMA3, set the B flag to 1 (register bank 1) and write to
registers R0 to R3, A0, and A1 with the MOV instruction.
To set registers DSA2 and DSA3, set the B flag to 1 and write to registers SB and FB with the LDC instruction.
To set registers DRA2 and DRA3, write to registers SVP and VCT with the LDC instruction.
DMAC-Associated Registers
DMD0
DMA mode register 0
DMD1
DMA mode register 1
DCT0
DMA0 transfer count register
DCT1
DMA1 transfer count register
DRC0
DMA0 transfer count reload register(1)
DRC1
DMA1 transfer count reload register(1)
DMA0
DMA0 memory address register
DMA1
DMA1 memory address register
DSA0
DMA0 SFR Address register
DSA1
DMA1 SFR Address register
DRA0
DMA0 memory address reload register(1)
DRA1
DMA1 memory address reload register(1)
When three or more DMAC channels are used,
the register bank 1 is employed as DMAC registers.
When three or more DMAC channels are used,
the high-speed interrupt registers are employed as DMAC
registers.
DCT2(R0)
DMA2 transfer count register
SVF
DCT3(R1)
DMA3 transfer count register
DRA2(SVP)
DMA2 memory address reload register(1)
DRC2(R2)
DMA2 transfer count reload register(1)
DRA3(VCT)
DMA3 memory address reload register(1)
DRC3(R3)
register(1)
DMA3 transfer count reload
DMA2(A0)
DMA2 memory address register
DMA3(A1)
DMA3 memory address register
DSA2(SB)
DMA2 SFR Address register
DSA3(FB)
DMA3 SFR Address register
NOTE:
1. These registers are used for repeat transfer, not for single transfer.
Figure 13.1
Register Mapping for DMAC
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 120 of 352
Flag save register
When using DMA2 and DMA3, use the CPU registers shown in
parentheses ( ).
M32C/8A Group
13. DMAC
A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request
source. Bits DSEL 4 to DSEL0 in the DMiSL register determine which source is selected. When a software trigger is
selected, a DMA transfer is started by setting the DSR bit in the DMiSL register to 1. When a peripheral function
interrupt request is selected, a DMA transfer is started by an interrupt request occurrence. The DMA transfer is
performed even if interrupts are disabled by the I flag, IPL, or Interrupt Control Register, since DMAC is free from
these affects. When an interrupt request (DMA request) is generated, the IR bit in the Interrupt Control Register
becomes 1. The IR bit, however, does not become 0 even if the DMA transfer is performed.
Table 13.1
DMAC Specifications
Item
Specification
Number of Channels
4 channels (cycle-steal method)
Transfer memory space
From a given address in a 16-Mbyte space to a fixed address in a 16-Mbyte space
From a fixed address in a 16-Mbyte space to a given address in a 16-Mbyte space
Maximum bytes transferred
128 Kbytes (when a 16-bit data is transferred)
64 Kbytes (when an 8-bit data is transferred)
DMA request source
Falling edge or both edges of signals applied to pins INT0 to INT3
Timer A0 to A4 interrupt requests
Timer B0 to B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D0 interrupt request
Software trigger
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority)
Transfer unit
8 bits, 16 bits
Transfer address
Fixed address: one specified address
Incremented address: address which is incremented by a transfer unit on each
successive access.
(Source address and destination address cannot be both fixed nor both
incremented.)
Transfer
mode
Single transfer
Transfer is completed when the DCTi register (i = 0 to 3) becomes 0000h
Repeat transfer
When the DCTi register becomes 0000h, values of the DRCi register are reloaded
into the DCTi register and the DMA transfer continues.
DMA interrupt request
generation timing
When the DCTi register becomes from 0001h to 0000h, a DMA interrupt request
is generated.
DMA startup Single transfer
DMAC starts a data transfer when a DMA request is generated after bits MDi1 and
MDi0 in the DMDj register (j = 0 to 1) are set to 01b (single transfer), while the DCTi
register is set to 0001h or higher value.
DMA stop
Repeat transfer
DMAC starts a data transfer when a DMA request is generated after bits MDi1 and
MDi0 are set to 11b (repeat transfer), while the DCTi register is set to 0001h or
higher value.
Single transfer
When bits MDi1 and MDi0 are set to 00b (DMA disabled)
DMAC stops when the DCTi register becomes 0000h (0 DMA transfer) by a DMA
transfer completion or by writing.
Repeat transfer
When bits MDi1 and MDi0 are set to 00b (DMA disabled)
DMAC stops when the DCTi register becomes 0000h (0 DMA transfer) by a DMA
transfer completion or writing and the DRCi register is 0000h.
Reload timing to registers DCTi
and DMAi
Values are reloaded when the DCTi register becomes from 0001h to 0000h in
repeat transfer mode.
DMA transfer time
Between SFR area and internal RAM transfer: minimum 3 bus clock cycles
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 121 of 352
M32C/8A Group
13. DMAC
DMAi Request Source Select Register (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0SL to DM3SL
Bit Symbol
Address
0378h, 0379h, 037Ah, 037Bh
Bit Name
After Reset
0X00 0000b
Function
RW
DSEL0
RW
DSEL1
RW
See Table "DMiSL register function (i = 0 to 3)"
DSEL2
DMA request source
select bits(1)
Do not set to values other than specified in the
Table.
DSEL3
RW
DSEL4
RW
DSR
Software DMA request bit (2)
When a software trigger is selected, a DMA
request is generated by setting this bit to 1
(Read as 0)
−
(b6)
Reserved bit
Read as undefined value
DRQ
DMA request bit(2, 3)
0: Not requested
1: Requested
NOTES:
1. Change settings of bits DSEL4 to DSEL0 while bits MDi1 and MDi0 in the DMD0 or DMD1 register are set to 00b (DMA
disabled). Also, when bits DSEL4 to DSEL0 are change, set the DRQ bit to 1 at the same time.
e.g., MOV.B #083h, DMiSL ; Select timer A0
2. When the DSR bit is set to 1, set the DRQ bit to 1 at the same time.
e.g., OR.B #0A0h, DMiSL
3. Do not write a 0 to the DRQ bit.
Figure 13.2
DM0SL to DM3SL Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 122 of 352
RW
−
RW
M32C/8A Group
Table 13.2
13. DMAC
DMiSL Register (i = 0 to 3) Function
Setting Value
DMA Request Source
b4 b3 b2 b1 b0
DMA0
0
0
0
0
0
Software trigger
0
0
0
0
1
Falling edge of INT0
DMA1
Falling edge of INT1
0
0
0
1
0
Both edges of INT0
0
0
0
1
1
Timer A0 interrupt request
Both edges of INT1
0
0
1
0
0
Timer A1 interrupt request
0
0
1
0
1
Timer A2 interrupt request
0
0
1
1
0
Timer A3 interrupt request
0
0
1
1
1
Timer A4 interrupt request
0
1
0
0
0
Timer B0 interrupt request
0
1
0
0
1
Timer B1 interrupt request
0
1
0
1
0
Timer B2 interrupt request
0
1
0
1
1
Timer B3 interrupt request
0
1
1
0
0
Timer B4 interrupt request
0
1
1
0
1
Timer B5 interrupt request
0
1
1
1
0
UART0 transmit interrupt request
0
1
1
1
1
UART0 receive interrupt or ACK interrupt request(3)
1
0
0
0
0
UART1 transmit interrupt request
1
0
0
0
1
UART1 receive interrupt or ACK interrupt request(3)
1
0
0
1
0
UART2 transmit interrupt request
1
0
0
1
1
UART2 receive interrupt or ACK interrupt request(3)
1
0
1
0
0
UART3 transmit interrupt request
1
0
1
0
1
UART3 receive interrupt or ACK interrupt request(3)
1
0
1
1
0
UART4 transmit interrupt request
1
0
1
1
1
UART4 receive interrupt or ACK interrupt request(3)
1
1
0
0
0
A/D0 interrupt request
DMA2
Falling edge of INT2
Both edges of INT2
DMA3
Falling edge of INT3(1)
Both edges of
INT3(1)
(Note 2)
(Note 2)
NOTES:
1. When the INT3 pin is used for data bus in microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to
the INT3 pin.
2. The falling edge or both edges of input signal to the INTi pin can be a DMA request source. It is not affected by the INT interrupts (bits
POL and LVS in the INTiIC register, the IFSR register) and vice versa.
3. To switch between the UARTj receive interrupt and ACK interrupt (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on
the UiSMR2 register. To use the ACK interrupt, set the IICM bit to 1 (I2C mode) and the IICM2 bit to 0 (NACK/ACK interrupt).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 123 of 352
M32C/8A Group
13. DMAC
DMAi Memory Address Register (i = 0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
Address
After Reset
DMA0(2)
DMA1(2)
DMA2 (bank1:A0)(3)
DMA3 (bank1:A1)(4)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
XXXXXXh
XXXXXXh
000000h
000000h
Function
Set an incremented source address or incremented destination
address(1)
Setting Range
RW
000000h to FFFFFFh
(16 Mbytes)
RW
NOTES:
1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a destination
address is selected. When the RWk bit is set to 1 (incremented address to fixed address), a source address is selected.
2. Use the LDC instruction to set registers DMA0 and DMA1.
3. To set the DMA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the A0 register.
4. To set the DMA3 register, set the B flag to 1 and write to the A1 register.
DMAi SFR Address Register (i = 0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
Address
After Reset
DSA0(2)
DSA1(2)
DSA2 (bank1:SB)(3)
DSA3 (bank1:FB)(4)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
XXXXXXh
XXXXXXh
000000h
000000h
Function
Set a fixed source address or fixed destination address (1)
Setting Range
RW
000000h to FFFFFFh
(16 Mbytes)
RW
NOTES:
1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a source address
is selected. When the RWk bit is set to 1 (incremented address to fixed address), a destination address is selected.
2. Use the LDC instruction to set registers DSA0 and DSA1.
3. To set the DSA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the SB register using the LDC
instruction.
4. To set the DSA3 register, set the B flag to 1 and write to the FB register using the LDC instruction.
Figure 13.3
DMA0 to DMA3 Registers, DSA0 to DSA3 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 124 of 352
M32C/8A Group
13. DMAC
DMAi Memory Address Reload Register(1) (i = 0 to 3)
b23
b16 b15
b8 b7
b0
Symbol
Address
After Reset
DRA0
DRA1
DRA2 (SVP)(2)
DRA3 (VCT)(3)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
XXXXXXh
XXXXXXh
XXXXXXh
XXXXXXh
Function
Set an incremented source address or incremented destination
address
Setting Range
RW
000000h to FFFFFFh
(16 Mbytes)
RW
NOTES:
1. Use the LDC instruction to set registers DRA0 to DRA3.
2. To set the DRA2 register, write to the SVP register.
3. To set the DRA3 register, write to the VCT register.
DMAi Transfer Count Register (i = 0 to 3)
b15
b8 b7
b0
Symbol
Address
After Reset
DCT0(2)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
XXXXh
XXXXh
0000h
0000h
DCT1(2)
DCT2 (bank1:R0)(3)
DCT3 (bank1:R1)(4)
Function
Set the number of transfers
Setting Range
RW
0000h to FFFFh(1)
RW
NOTES:
1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation.
2. Use the LDC instruction to set registers DCT0 and DCT1.
3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register.
4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.
DMAi Transfer Count Reload Register (i = 0 to 3)
b15
b8 b7
b0
Symbol
Address
After Reset
DRC0(1)
DRC1(1)
DRC2 (bank1:R2)(2)
DRC3 (bank1:R3)(3)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
XXXXh
XXXXh
0000h
0000h
Function
Set the number of transfers
Setting Range
RW
0000h to FFFFh
RW
NOTES:
1. Use the LDC instruction to set registers DRC0 and DRC1.
2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register.
3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.
Figure 13.4
DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 125 of 352
M32C/8A Group
13. DMAC
DMA Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMD0
Address
(CPU internal register)
Bit Symbol
Bit Name
Channel 0
transfer mode select bits
MD01
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
RW
BW0
Channel 0
transfer unit select bit
0: 8 bits
1: 16 bits
RW
RW0
Channel 0
transfer direction select bit
0: Fixed address to incremented address
1: Incremented address to fixed address
RW
b5 b4
MD10
Channel 1
transfer mode select bits
MD11
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
BW1
Channel 1
transfer unit select bit
0: 8 bits
1: 16 bits
RW
RW1
Channel 1
transfer direction select bit
0: Fixed address to incremented address
1: Incremented address to fixed address
RW
NOTE:
1. Use the LDC instruction to set the DMD0 register.
DMD0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
b1 b0
MD00
Figure 13.5
After Reset
00h
Page 126 of 352
M32C/8A Group
13. DMAC
DMA Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
DMD1
(CPU internal register)
00h
Bit Symbol
Bit Name
b1 b0
MD20
Channel 2
transfer mode select bits
MD21
RW
RW
Channel 2
transfer unit select bit
0: 8 bits
1: 16 bits
RW
RW2
Channel 2
transfer direction select bit
0: Fixed address to incremented address
1: Incremented address to fixed address
RW
b5 b4
Channel 3
transfer mode select bits
MD31
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
RW
BW3
Channel 3
transfer unit select bit
0: 8 bits
1: 16 bits
RW
RW3
Channel 3
transfer direction select bit
0: Fixed address to incremented address
1: Incremented address to fixed address
RW
NOTE:
1. Use the LDC instruction to set the DMD1 register.
DMD1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
0 0: DMA disabled
0 1: Single transfer
1 0: Do not set to this value
1 1: Repeat transfer
RW
BW2
MD30
Figure 13.6
Function
Page 127 of 352
M32C/8A Group
13. DMAC
Start
Set the peripheral function
used as DMAi request source
Set the control registers of the peripheral function,
but do not yet start.
DMD0 register: bits MD01 and MD00 = 00b
bits MD11 and MD10 = 00b
DMA disabled for channel 0
DMA disabled for channel 1
DMiSL register: bits DSEL4 to DSEL0
DSR bit = 0
DRQ bit = 1
DMA request source select bits
DMA requested
DMAi register
Set an incremented source address or
incremented destination address
DSAi register
Set a fixed source address or
fixed destination address
Write with LDC instruction
(note 1)
Write with LDC instruction
<When using repeat transfer>
DRAi register
Set an incremented source address or
incremented destination address
Write with LDC instruction
DCTi register
Set the number of transfers (2)
Write with LDC instruction
DRCi register
Set the number of transfers, which is to be
reloaded
Write with LDC instruction
DMD0 register: bits MD01 and MD00
BW0 bit
RW0 bit
bits MD11 and MD10
BW1 bit
RW1 bit
Transfer mode select bits for channel 0
Transfer unit select bit for channel 0
Transfer direction select bit for channel 0
Transfer mode select bits for channel 1
Transfer unit select bit for channel 1
Transfer direction select bit for channel 1
<When using repeat transfer>
Start the peripheral function
used as DMAi request source
Write with LDC instruction
(note 3)
(note 4)
End
i = 0 and 1
NOTES:
1. When setting the DMiSL register, write a 1 to the DRQ bit.
2. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is
1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.
3. Wait six CPU clock cycles or more by program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.
4. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the
same time.
Figure 13.7
Register Settings When Using DMA0 or DMA1
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 128 of 352
M32C/8A Group
13. DMAC
Start
Set the peripheral function
used as DMAi request source
Set the control registers of the peripheral function,
but do not yet start.
DMD1 register: bits MD21 and MD20 = 00b
bits MD31 and MD30 = 00b
DMA disabled for channel 2
DMA disabled for channel 3
DMiSL register: bits DSEL4 to DSEL0
DSR bit = 0
DRQ bit = 1
DMA request source select bits
B flag = 1
DMA requested
Write with LDC instruction
(note 1)
Select register bank 1 (2)
DMA2 (A0) register or DMA3 (A1) register
Set an incremented source address or
incremented destination address
Write with MOV instruction
DSA2 (SB) register or DSA3 (FB) register
Set a fixed source address or
fixed destination address
Write with LDC instruction
DRA2 (SVP) register or DRA3 (VCT) register
Set an incremented source address or
incremented destination address
Write with LDC instruction
DCT2 (R0) register or DCT3 (R1) register
Set the number of transfer (3)
Write with MOV instruction
Set the number of transfer, which is to be
reloaded
Write with MOV instruction
<When using repeat transfer>
<When using repeat transfer>
DRC2 (R2) register or DRC3 (R3) register
B flag = 0
DMD1 register: bits MD21 and MD20
BW2 bit
RW2 bit
bits MD31 and MD30
BW3 bit
RW3 bit
Start the peripheral function
used as DMAi request source
Select register bank 0 (2)
Transfer mode select bits for channel 2
Transfer unit select bit for channel 2
Transfer direction select bit for channel 2
Transfer mode select bits for channel 3
Transfer unit select bit for channel 3
Transfer direction select bit for channel 3
Write with LDC instruction
(note 4)
(note 5)
End
i = 2 and 3
NOTES:
1. When setting the DMiSL register, write a 1 to the DRQ bit.
2. The register bank 1 and high-speed interrupt cannot be used when using DMA2 and DMA3.
3. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is
1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.
4. Wait six CPU clock cycles or more by program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.
5. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the
same time.
Figure 13.8
Register Settings When Using DMA2 or DMA3
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 129 of 352
M32C/8A Group
13.1
13. DMAC
Transfer Cycles
The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write
data to destination address (destination write). The number of read and write bus cycles depends on the locations
of source and destination addresses. In microprocessor mode, the number of read and write bus cycles also depends
on DS register setting. Software wait state insertion and the RDY signal can extend a bus cycle.
13.1.1
Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the
source-read cycle is added by one bus cycle, compared to a source address starting with an even address.
When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd address, the
destination-write cycle is added by one bus cycle, compared to a destination address starting with an even
address.
13.1.2
Effect of the DS Register
In an external space in microprocessor mode, the transfer cycle varies depending on the data bus width of the
source and destination addresses. See Figure 8.1 for details about the DS register.
• When a 16-bit data is transferred accessing both source address and destination address with an 8-bit data
bus (the DSi bit in the DS register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. Therefore,
two bus cycles are required for reading and another two bus cycles for writing.
• When a 16-bit data is transferred accessing a source address with an 8-bit data bus (the DSi bit is set to 0)
and a destination address with a 16-bit data bus, an 8-bit data will be read twice but be written once as 16bit data. Therefore, two bus cycles are required for reading and one bus cycle for writing.
• When a 16-bit data is transferred accessing a source address with a 16-bit data bus (the DSi bit is set to 1)
and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be
written twice. Therefore, one bus cycle is required for reading and two bus cycles for writing.
13.1.3
Effect of Software Wait State
When accessing the SFR area or memory space that require wait states, the number of bus clocks (BCLK) is
increased by software wait states.
13.1.4
Effect of the RDY Signal
In microprocessor mode, the RDY signal affects a bus cycle if a source address or destination address is in an
external space. Refer to 8.2.6 RDY Signal for details.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 130 of 352
M32C/8A Group
13.2
13. DMAC
DMA Transfer Time
The DMA transfer time can be calculated as follows. (in terms of bus clock)
Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the
number of bus clock).
Transfer time = source read bus cycle × j + destination write bus cycle × k
Table 13.3
Source Read Cycle and Destination Write Cycle
Transfer Unit
Accessing Internal Space
Accessing External Space
Read Cycle
Write Cycle
Read Cycle
Write Cycle
Even
1
1
1
1
Odd
1
1
1
1
Even
−
−
1
1
Odd
−
−
1
1
Even
1
1
1
1
Odd
2
2
2
2
Even
−
−
2
2
Odd
−
−
2
2
Access
Address
Bus Width
8-bit transfer
16 bits
(BWi bit in the DMDp
register = 0)
8 bits
16-bit transfer
(BWi bit = 1)
16 bits
8 bits
i=0 to 3, p=0 and 1
Table 13.4
Coefficient j, k
Internal Space
External Space
Internal RAM
Internal RAM
SFR area
with no wait state
j=1
k=1
with wait state
j=2
k=2
j=2
k=2
13.3
j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9).
Add one cycle to j or k cycles when inserting a recovery
cycle
Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and
the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period
between each DMA transfer request generation on the same channel.
DMA request interval ≥ (number of channels set for DMA transfer - 1) × 5 BCLK cycles
Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling
period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts.
In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority
is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of
the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1
transfer is completed, bus ownership is again returned to the CPU.
DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are
generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership
is acquired. Bus ownership is returned to the CPU after one transfer is completed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 131 of 352
M32C/8A Group
13. DMAC
Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously
and DMA transfers (SFR to RAM) are performed in minimum time.
BCLK
DMA0
Bus
privilege
acquired
DMA1
CPU
INT0
DRQ bit in
DMA0
INT1
DRQ bit in
DMA1
Figure 13.9
DMA Transfers Triggered by INT Interrupt Requests
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 132 of 352
M32C/8A Group
14. DMACII
14. DMACII
DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a
result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral
functions.
Table 14.1 lists specifications of DMACII.
Table 14.1
DMACII Specifications
Item
Specification
DMACII request source
Interrupt requests generated by any peripheral functions with bits ILVL2 to ILVL0
in the Interrupt Control Register set to 111b (level 7)
Transfer data
- Data in a memory location is transferred to another memory location
(memory-to-memory transfer)
- Immediate data is transferred to a memory location (immediate data transfer)
- Data in a memory location (or immediate data) + data in another memory location
is transferred to the other memory location (calculation transfer)
Transfer unit
8 bits or 16 bits
Transfer space
64-Kbyte space in addresses 00000h to 0FFFFh(1)(2)
Transfer address
Fixed address: one specified address
Incremented address: address which is incremented by the transfer unit on each
successive access.
(Selectable for source address and destination address individually)
Transfer mode
Single transfer, burst transfer, multiple transfer
Chain transfer function
Address indicated by an interrupt vector for DMACII index is replaced when a
transfer counter reaches zero
End-of-transfer interrupt
Interrupt occurs when a transfer counter reaches zero
NOTES:
1. When a destination address is 0FFFFh and a 16-bit data is transferred, it is transferred to addresses 0FFFFh
and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is
transferred to a given destination address.
2. The actual transferable space varies depending on internal RAM capacity.
14.1
DMACII Settings
Set up the following registers and tables to activate DMACII.
• RLVL register
• DMACII Index
• Interrupt Control Register of the peripheral functions triggering DMACII requests
• The relocatable vector table of the peripheral functions triggering DMACII requests
14.1.1
RLVL Register
When the DMAII bit is set to 1 (interrupt priority level 7 is used for DMACII transfer) and the FSIT bit to 0
(interrupt priority level 7 is used for normal interrupt), DMACII is activated by an interrupt request from any
peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7).
Figure 14.1 shows the RLVL register.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 133 of 352
M32C/8A Group
14. DMACII
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
RLVL
009F
XXXX 0000b
Bit Symbol
Bit Name
b2 b1 b0
RLVL0
RLVL1
Function
Exit wait mode/stop mode
interrupt priority level
control bits(1)
RLVL2
FSIT
High-speed interrupt select bit
−
(b4)
Unimplemented.
Write 0. Read as undefined value.
DMAII
DMACII select bit (4)
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
0 0 0: Level 0
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt priority level 7 is used for normal
interrupt
1: Interrupt priority level 7 is used for high-speed
interrupt(2)(3)
RW
RW
RW
RW
RW
−
0: Interrupt priority level 7 is used for interrupt
1: Interrupt priority level 7 is used for DMACII
transfer (2)
RW
NOTES:
1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits
RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register.
2. Do not set both the FSIT and DMAII bits to 1.
Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b.
3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt.
4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt
Control Register.
Figure 14.1
RLVL Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 134 of 352
−
M32C/8A Group
14.1.2
14. DMACII
DMACII Index
The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination address, chain
transfer address, and end-of-transfer interrupt address.
The DMACII index must be located on the RAM area.
Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the
DMACII index.
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
Multiple Transfer
16 bits
16 bits
DMACII Index
Starting Address
(BASE)
BASE+2
Transfer mode (MOD)
BASE
Transfer mode (MOD)
Transfer counter (COUNT)
BASE+2
Transfer counter (COUNT)
BASE+4
Transfer source address (or immediate data) (SADR)
BASE+4
Transfer source address (SADR1)
BASE+6
Operation address(1) (OADR)
BASE+6
Transfer destination address (DADR1)
BASE+8
Transfer destination address (DADR)
BASE+8
Transfer source address (SADR2)
BASE+10 Chain Transfer Address (lower byte) (2) (CADR0)
BASE+10 Transfer destination address (DADR2)
BASE+12 Chain Transfer Address (higher byte) (2) (CADR1)
(3)
BASE+14 End-of-Transfer Interrupt Address (lower byte)
(IADR0)
End-of-Transfer Interrupt Address (higher byte) (3)
BASE+16
(IADR1)
to
BASE+28 Transfer source address (SADR7)
BASE+30 Transfer destination address (DADR7)
NOTES:
1. This data is not needed unless using the calculation transfer function.
2. This data is not needed unless using the chain transfer function.
3. This data is not needed unless using the end-of-transfer interrupt.
Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the
calculation transfer function, assign a transfer destination address to BASE+6.
The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering
a DMACII request.
Figure 14.2
DMACII Index
Details of the DMACII index are described below. Set these parameters in the specified order listed in Table
14.2, depending on DMACII transfer mode.
• Transfer mode (MOD)
MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.
• Transfer counter (COUNT)
COUNT is two-byte data and required to set the number of transfer.
• Transfer source address (SADR)
SADR is two-byte data and required to set a source memory address or immediate data.
• Operation address (OADR)
OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using
the calculation transfer function.
• Transfer destination address (DADR)
DADR is two-byte data and required to set a destination memory address.
• Chain transfer address (CADR)
CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set
this data only when using the chain transfer function.
• End-of-transfer interrupt address (IADR)
IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data
only when using the end-of-transfer interrupt.
The abbreviations shown in parentheses( ) for each parameter are used in this section.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 135 of 352
M32C/8A Group
14. DMACII
Table 14.2
DMACII Index Configuration in Transfer Mode
Memory-to-Memory Transfer/
Immediate Data Transfer
Transfer data
Multiple
Transfer
Calculation Transfer
Chain transfer
Not used
Used
Not used
Used
Not used
Used
Not used
Used
Cannot used
End-ofTransfer
Interrupt
Not used
Not used
Used
Used
Not used
Not used
Used
Used
Cannot used
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
COUNT
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR
SADR1
DADR1
DMAC II index
DADR
DADR
DADR
DADR
OADR
OADR
OADR
OADR
8 bytes
CADR0
IADR0
CADR0
DADR
DADR
DADR
DADR
CADR1
IADR1
CADR1
10 bytes
CADR0
IADR0
CADR0
12 bytes
12 bytes
IADR0
CADR1
IADR1
CADR1
IADR1
14 bytes
14 bytes
IADR0
DADRi
IADR1
i = 1 to 7
max. 32 bytes
(when i = 7)
16 bytes
18 bytes
SADRi
Transfer Mode (MOD)(1)
b15
b0
b8 b7
Bit Symbol
Function
(MULT = 0)
Bit Name
Function
(MULT = 1)
SIZE
Transfer unit select bit
0: 8 bits
1: 16 bits
IMM
Transfer data select bit
0: Immediate data
1: Memory
UPDS
Transfer source direction
select bit
0: Fixed address
1: Incremented address
RW
UPDD
Transfer destination
direction select bit
0: Fixed address
1: Incremented address
RW
OPER/
CNT0(2)
Calculation transfer
function select bit
0: Not used
1: Used
BRST/
CNT1(2)
Burst transfer select bit
0: Single transfer
1: Burst transfer
INTE/
CNT2(2)
End-of-transfer interrupt
select bit
0: Interrupt not used
1: Interrupt used
CHAIN
Chain transfer
select bit
0: Chain transfer not
used
1: Chain transfer used
−
(b14-b8)
MULT
RW
Set to 1
b6 b5 b4
RW
Set to 0
RW
Unimplemented.
Write 0. Read as undefined value.
Multiple transfer
select bit
0: Multiple transfer not
used
MOD
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 136 of 352
RW
0 0 0: Do not set to this
value
0 0 1: Once
0 1 0: Twice
:
:
1 1 0: 6 times
1 1 1: 7 times
RW
RW
−
1: Multiple transfer used
NOTES:
1. MOD must be located in the RAM.
2. When the MULT bit is set to 0, bits 6 to 4 function as bits OPER, BRST, and INTE. When the MULT bit is set to 1, bits 6 to 4
function as bits CNT2 to CNT0.
Figure 14.3
RW
RW
M32C/8A Group
14.1.3
14. DMACII
Interrupt Control Register for the Peripheral Function
To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7).
14.1.4
Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMACII index in an interrupt vector for the peripheral function interrupt used as
a DMACII request source. When using the chain transfer, the relocatable vector table must be located in the
RAM.
14.2
DMACII Performance
The DMACII function is selected by setting the DMAII bit to 1 (interrupt priority level 7 is used for DMACII
transfer). DMACII transfer request is generated by interrupt requests from any peripheral function with bits ILVL2
to ILVL0 set to 111b (level 7). These peripheral function interrupt requests are used as DMACII transfer requests
and the peripheral function interrupts cannot be used.
When an interrupt request with bits ILVL2 to ILVL0 set to 111b (level 7) is generated, DMACII is activated
regardless of the I flag and IPL settings.
14.3
Transfer Data
DMACII transfers data in 8-bit unit or 16-bit unit.
• Memory-to-memory transfer: data is transferred from a given memory location in the 64-Kbyte space
(addresses 00000h to 0FFFFh) to another given memory location in the same space.
• Immediate data transfer: immediate data is transferred to a given memory location in the 64-Kbyte space.
• Calculation transfer: two 8-bit or two 16-bit data are added together and the result is transferred to a given
memory location in the 64-Kbyte space.
When a 16-bit data is transferred to a destination address 0FFFFh, it is transferred to addresses 0FFFFh and
10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred
to a given destination address.
The actual transferable space varies depending on internal RAM capacity. Refer to Figure 3.1 for the internal
memory.
14.3.1
Memory-to-memory Transfer
Data transfer between any two memory locations in the 64-Kbyte space can be:
• a transfer from a fixed address to another fixed address;
• a transfer from a fixed address to an incremented address;
• a transfer from an incremented address to a fixed address;
• a transfer from an incremented address to another incremented address.
When an incremented address is selected, DMACII increments an address after every transfer for the following
transfer. In a 8-bit data transfer, a transfer address is incremented by one. In a 16-bit data transfer, a transfer
address is incremented by two.
When a source or destination address exceeds 0FFFFh as a result of address incrementation, the source or
destination address returns to 00000h and continues incrementation. Maintain source and destination address at
0FFFFh or below.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 137 of 352
M32C/8A Group
14.3.2
14. DMACII
Immediate Data Transfer
DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected
as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate data, write data in the
low-order byte of SADR. (The high-order byte is ignored.)
14.3.3
Calculation Transfer
After two memory data, or an immediate data and a memory data, are added together, DMACII transfers the
calculated result to a given memory location. Set a memory address or immediate data to be calculated in
SADR. Set another memory address to be calculated in OADR. To use a “memory + memory” calculation
transfer, a fixed or incremented address can be selected as a source or destination address. If a source address is
incremented, an operation address also becomes incremented. To use an “immediate data + memory”
calculation transfer, a fixed or incremented address can be selected as a destination address.
14.4
Transfer Modes
In DMACII, a single transfer, burst transfer, and multiple transfer are available. The BRST bit in MOD selects
either a single transfer or burst transfer, and the MULT bit in MOD selects a multiple transfer. COUNT determines
how many transfers occur. No transfer occurs when COUNT is set to 0000h.
14.4.1
Single Transfer
For one transfer request, DMACII transfers an 8-bit or 16-bit data once. When an incremented address is
selected for a source or destination address, DMACII increments the address after every transfer for the
following transfer.
COUNT is decremented every time a transfer occurs. If using the end-of-transfer interrupt, an interrupt occurs
when COUNT reaches zero.
14.4.2
Burst Transfer
For one transfer request, DMACII continuously transfers data the number of times determined by COUNT.
COUNT is decremented every time DMACII transfers one transfer unit, and when it reaches zero, a burst
transfer is completed. If using the end-of-transfer interrupt, an interrupt occurs at the end of the burst transfer.
While the burst transfer is taking place, no interrupt can be acknowledged.
14.4.3
Multiple Transfer
When using the multiple transfer, select the memory-to-memory transfer. For one transfer request, DMACII
transfers data multiple times. Bits CNT2 to CNT0 in MOD selects the number of transfers from 001b (once) to
111b (7 times). Do not set bits CNT2 to CNT0 to 000b.
Source and destination addresses enough for all transfers must be allocated alternately in addresses following
MOD and COUNT in DMACII index.
While the transfers are taking place the number of times set using bits CNT2 to CNT0, no interrupt can be
acknowledged. When the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and
end-of-transfer interrupt cannot be used.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 138 of 352
M32C/8A Group
14.5
14. DMACII
Chain Transfer
The chain transfer can be selected with the CHAIN bit in MOD.
The chain transfer is performed as follows.
(1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to
the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request,
either a single transfer or burst transfer selected by the BRST bit in MOD occurs.
(2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and
CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1.
(3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of
the DMACII index specified by the interrupt vector which has been replaced in (2).
Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer.
For the chain transfer, the relocatable vector table must be located in the RAM.
RAM
INTB
Relocatable
Vector
Interrupt vector of the peripheral function triggering
DMACII request. Default value is BASE (a).
BASE (a)
DMACII index (a)
(CADR1,
CADR0)
BASE (b)
When COUNT reaches zero, the above interrupt
vector is replaced with BASE (b), which is the
address written in CADR1 and CADR0.
When the next request occurs, a transfer starts
according to the contents of the DMACII index at
BASE (b).
BASE (b)
DMACII index (b)
(CADR1,
CADR0)
Figure 14.4
14.6
BASE (c)
When COUNT reaches zero, the interrupt vector
is replaced wtih BASE (c).
Relocatable Vector and DMACII Index When using the Chain Transfer
End-of-Transfer Interrupt
The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-oftransfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 139 of 352
M32C/8A Group
14.7
14. DMACII
Execution Time
DMACII execution time is calculated by the following equations (single-speed mode):
Multiple transfers: t [bus clock] = 21+ (11 + b + c) × k
Other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) × m + (4 + e) × n
a: If IMM = 0 (source is immediate data), a = 0; if IMM = 1 (source is data in memory location), a = -1.
b: If UPDS = 1 (source address is incremented), b = 0; if UPDS = 0 (source address is fixed), b = 1.
c: If UPDD = 1 (destination address is incremented), c = 0; if UPDD = 0 (destination address is fixed), c = 1.
d: If OPER = 0 (calculation function is not selected), d = 0;
if OPER = 1 (calculation function is selected) and UPDS = 0 (source is immediate data or fixed address in
memory location), d = 7;
if OPER = 1 (calculation function is selected) and UPDS = 1 (source is incremented address in memory
location), d = 8.
e: If CHAIN = 0 (chain transfer is not selected), e = 0; if CHAIN = 1 (chain transfer is selected), e = 4.
m: If BRST = 0 (single transfer), m = 1; if BRST = 1 (burst transfer), m = a value set in COUNT.
n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1.
k: The number of transfers set in bits CNT2 to CNT0 in MOD.
The above equations are approximations. The execution time varies depending on CPU state, bus wait states, and
DMACII index allocation.
The first instruction of the end-of-transfer interrupt routine is executed in the eighth bus clock after the DMACII
transfer is completed.
Conditions of the example below:
-memory-to-memory transfer (a = -1)
-incremented source address (b = 0)
-fixed destination address (c = 1)
-no calculation function (d = 0)
-no chain transfer (e = 0)
-single transfer (m = 1)
-the end-of-transfer interrupt (transfer counter = 2) occurs
First DMACII transfer
t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks
Second DMACII transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks
DMACII transfer
requested
Program
DMACII transfer
requested
First
DMACII transfer
Program
36 clocks
32 clocks
End-of-transfer interrupt
routine executed
7 clocks
Transfer counter = 1
Transfer counter = 2
Transfer counter is decremented.
Transfer counter = 1
Figure 14.5
Second
DMACII transfer
Transfer counter is decremented.
Transfer counter = 0
Transfer Time
When a DMACII transfer request is generated simultaneously with another request having a higher priority (e.g.,
NMI or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending DMACII transfer
starts after the interrupt sequence of the higher priority interrupt has been completed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 140 of 352
M32C/8A Group
15. Timers
15. Timers
The M32C/8A Group has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their
functions. Individual timers function independently. The count source for each timer is used to operate the timer for
counting and reloading, etc.
Figures 15.1 and 15.2 show block diagrams of timer A and timer B configurations.
Clock Prescaler
fC32
1/32
XCIN
Set the CPSR bit in the
CPSRF register to 1
Reset
f1 f8 f2n fC32
00
01
10
11
TCK1 and TCK0
10
Noise
filter
TA0IN
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A0
01
00
Timer A0 interrupt
01: Event counter mode
11 TA0TGH and TA0TGL
00
01
10
11
TCK1 and TCK0
10
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A1 interrupt
Timer A1
Noise
filter
TA1IN
01
00
01: Event counter mode
11 TA1TGH and TA1TGL
00
01
10
11
TCK1 and TCK0
10
Noise
filter
TA2IN
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A2
01
00
Timer A2 interrupt
01: Event counter mode
11 TA2TGH and TA2TGL
00
01
10
11
TCK1 and TCK0
10
Noise
filter
TA3IN
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A3 interrupt
Timer A3
01
00
01: Event counter mode
11 TA3TGH and TA3TGL
00
01
10
11
TCK1 and TCK0
10
Noise
filter
TA4IN
TMOD1 and TMOD0
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A4 interrupt
Timer A4
01
00
01: Event counter mode
11 TA4TGH and TA4TGL
Timer B2 overflow
or underflow signal
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register
TAiGH, TAiGL: Bits in the ONSF register or the TRGSR register (i = 0 to 4)
Figure 15.1
Timer A Configuration
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 141 of 352
M32C/8A Group
15. Timers
Clock prescaler
1/32
XCIN
Set the CPSR bit in the
CPSRF register to 1
f1 f8 f2n fC32
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
01: Event counter mode
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
1
0
01: Event counter mode
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
01: Event counter mode
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
TCK1 and TCK0
01: Event counter mode
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
TCK1 and TCK0
Timer B4
1
Noise
filter
TB4IN
00
01
10
11
0
01: Event counter mode
TCK1 and TCK0
Noise
filter
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
0
Timer B5
TCK1
01: Event counter mode
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register (i = 0 to 5)
Figure 15.2
Timer B Configuration
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Timer B4 interrupt
TCK1
1
TB5IN
Timer B3 interrupt
Timer B3
1
0
Timer B2 interrupt
Timer B2
1
0
Timer B1 interrupt
Timer B1
TCK1 and TCK0
Noise
filter
TB3IN
1
0
Timer B0 interrupt
Timer B0
TCK1 and TCK0
Noise
filter
TB2IN
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
TCK1 and TCK0
Noise
filter
TB1IN
Reset
Timer B2 overflow or underflow signal
(to the count source of timer A)
Noise
filter
TB0IN
fC32
Page 142 of 352
Timer B5 interrupt
M32C/8A Group
15.1
15. Timers (Timer A)
Timer A
Timer A contains the following four modes. Except in event counter mode, all timers A0 to A4 have the same
functionality. Bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) determine which mode is used.
• Timer mode: The timer counts the internal count source.
• Event counter mode: The timer counts overflow/underflow signal of another timer or the external pulses.
• One-shot timer mode: The timer operates only once for one trigger.
• Pulse width modulation mode: The timer continuously outputs given pulse widths.
Figure 15.3 shows a block diagram of timer A. Figures 15.4 to 15.13 show the registers associated with timer A.
Table 15.1 lists TAiOUT pin settings to use in output mode. Table 15.2 lists TAiIN and TAiOUT pin settings to use
in input mode.
Clock select
Clock source select
High-order bits of data bus
TCK1 and TCK0
f1 00
f8 01
f2n(1) 10
11
fC32
· Timer mode
· One-shot timer mode TMOD1 and TMOD0, MR2
· Pulse width modulation mode
Low-order bits of data bus
8 low-order
bits
Reload register
· Timer Mode (Gate Function)
8 high-order
bits
· Event counter mode
TAiIN
Polarity
Selector
Counter
TAiS
Increment/decrement
TB2 Overflow(2)
TAj Overflow(2)
TAk Overflow(2)
Always decrement except
in event counter mode
00
01
10
11 11
Decrement
TAiTGH to TAiTGL
00
10
11
01
TAiUD
TMOD1 and TMOD0
0
1
MR2
Function select register
Toggle flip flop
TAiOUT
i = 0 to 4
j = i - 1, except j = 4 if i = 0
k = i + 1, except k = 0 if i = 4
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or
divide-by-2n (n = 1 to 15).
2. Overflow signal or underflow signal.
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
TCK1 and TCK0, TMOD1 and TMOC0, MR2 and MR1: Bits in the TAiMR register
TAiTGH to TAiTGL: Bits in the ONSF register if i = 0 or bits in the TRGSR register if i = 1 to 4
TAiS: Bit in the TABSR register
TAiUD: Bit in the UDF register
Figure 15.3
Timer A Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 143 of 352
Addresses
0347h 0346h
0349h 0348h
034Bh 034Ah
034Dh 034Ch
034Fh 034Eh
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
M32C/8A Group
15. Timers (Timer A)
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSPR
Bit Symbol
Address
After Reset(2)
035Fh
0XXX 0000b
Function
Bit Name
CNT0
RW
RW
CNT1
Divide ratio select bits
(1)
If the setting value is n, f2n is the main clock,
on-chip oscillator, or PLL clock divided by 2n.
No division if n = 0
RW
CNT2
RW
CNT3
RW
−
(b6-b4)
CST
Reserved bits
Read as undefined value
Operation enable bit
0: Divider stops
1: Divider stars
−
RW
NOTES:
1. Set the CST bit to 0 before bits CNT3 to CNT0 are rewritten.
2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
Figure 15.4
TCSPR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 144 of 352
M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 0
Symbol
Address
After Reset
TA0MR to TA4MR
0356h, 0357h, 0358h, 0359h, 035Ah
00h
Bit Symbol
Bit Name
Function
TMOD0
RW
Operating mode select bits
b1 b0
0 0: Timer mode
TMOD1
−
(b2)
RW
RW
Reserved bit
Set to 0
RW
b4 b3
MR1
Gate function select bits
MR2
MR3
0 0:
Gate function disabled
0 1:
(TAiIN pin is a programmable I/O port)
1 0: Timer counts only while an "L" signal is input
to the TAiIN pin
1 1: Timer counts only while an "H" signal is
input to the TAiIN pin
Set to 0 in timer mode
Count source select bits
TCK1
0 0: f1
0 1: f8
1 0: f2n(1)
1 1: fC32
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divided-by-2n (n = 1 to 15). To select f2n, set the
CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.5
TA0MR to TA4MR Registers in Timer Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 145 of 352
RW
RW
b7 b6
TCK0
RW
RW
RW
M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 1
Symbol
Address
After Reset
TA0MR to TA4MR
0356h, 0357h, 0358h, 0359h, 035Ah
00h
Bit Symbol
Bit Name
Function
Function
(When not processing
two-phase pulse signals)
(When processing
two-phase pulse signals)
TMOD0
RW
RW
Operating mode select bits
b1 b0
0 1: Event counter mode (1)
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
MR1
Count polarity select bit (2)
0: Falling edges of an
external signal counted
1: Rising edges of an
external signal counted
Set to 0
RW
MR2
Increment/decrement
switching source select bit
0: UDF registser setting
1: Signal applied to the
TAiOUT pin (3)
Set to 1
RW
MR3
Set to 0 in event counter mode
TCK0
Count operation type
select bit
TCK1
Two-phase pulse signal
processing operation
select bit(4,5)
RW
RW
0: Reload
1: Free running
Set to 0
RW
0: Normal processing
operation
1: Multiply-by-4
processing operation
RW
NOTES:
1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode.
2. The MR1 bit is enabled only when counting external signals.
3. The counter decrements when an "L" signal is applied to the TAiOUT pin. The counter increments when an "H" signal is applied
to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing
function enabled). Also, set bits TAjTGH and TAjTGL in the TRGSR register to 00b (input to the TAjIN pin).
Figure 15.6
TA0MR to TA4MR Registers in Event Counter Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 146 of 352
M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(One-Shot Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 1 0
Symbol
Address
After Reset
TA0MR to TA4MR
0356h, 0357h, 0358h, 0359h, 035Ah
00h
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
Operating mode select bits
b1 b0
1 0: One-shot timer mode
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
RW
MR1
External trigger select bit(1)
0: Falling edge of signal applied to the TAiIN pin
1: Rising edge of signal applied to the TAiIN pin
RW
MR2
Trigger select bit
0: The TAiOS bit enabled
1: Selected by bits TAiTGH and TAiTGL
RW
MR3
Set to 0 in one-shot timer mode
RW
b7 b6
TCK0
Count source select bits
TCK1
0 0: f1
0 1: f8
1 0: f2n(2)
1 1: fC32
RW
RW
NOTES:
1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN
pin).
The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj
(j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow).
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.7
TA0MR to TA4MR Registers in One-Shot Timer Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 147 of 352
M32C/8A Group
15. Timers (Timer A)
Timer Ai Mode Register (i = 0 to 4)(Pulse Width Modulation Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1
Symbol
Address
After Reset
TA0MR to TA4MR
0356h, 0357h, 0358h, 0359h, 035Ah
00h
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
Operating mode select bits
b1 b0
1 1: Pulse width modulation (PWM) mode
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
RW
MR1
External trigger select bit(1)
0: Falling edge of signal applied to the TAiIN pin
1: Rising edge of signal applied to the TAiIN pin
RW
MR2
Trigger select bit
0: The TAiS bit is enabled
1: Selected by bits TAiTGH and TAiTGL
RW
MR3
16/8-bit PWM mode select bit
0: Functions as 16-bit pulse width modulator
1: Functions as 8-bit pulse width modulator
RW
b7 b6
TCK0
Count source select bits
TCK1
0 0: f1
0 1: f8
1 0: f2n (2)
1 1: fC32
RW
RW
NOTES:
1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN
pin).
The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj
(j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow).
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.8
TA0MR to TA4MR Registers in Pulse Width Modulation Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 148 of 352
M32C/8A Group
15. Timers (Timer A)
Timer Ai Register(1) (i = 0 to 4)
b15
b8 b7
b0
Symbol
TA0 to TA2
TA3, TA4
Mode
Address
0347h - 0346h, 0349h - 0348h, 034Bh - 034Ah
034Dh - 034Ch, 034Fh - 034Eh
After Reset
Undefined
Undefined
Function
Setting Range
RW
Timer mode
If a count source frequency is fj and the
setting value of TAi register is n, the counter
cycle is (n + 1) / fj
0000h to FFFFh
RW
Event counter mode
If the setting value is n, the count times are
(FFFFh - n+1) when the counter increments,
and (n+1) when the counter decrements (2)
0000h to FFFFh
RW
One-shot timer mode
If the setting value is n, the counter counts
n times and stops.
0000h to FFFFh (3, 4)
WO
Pulse width
modulation mode
(16-bit PWM)
If a count source frequency is fj and
the setting value of the TAi register is n,
PWM cycle: (216 - 1) / fj
"H" width of PWM pulse: n / fj
0000h to FFFEh (3, 5)
WO
Pulse width
modulation mode
(8-bit PWM)
If a count source frequency is fj, the setting
value of high-order bits in the TAi register is
n, and the setting value of low-order bits in
the TAi register is m,
PWM cycle: (28 -1) x (m+1) / fj
"H" width of PWM pulse: (m+1) n / fj
00h to FEh (3, 6)
(High-order address bits)
00h to FFh (3, 6)
(Low-order address bits)
fj: f1, f8, f2n, fC32
NOTES:
1. Read and write this register in 16-bit units.
2. The TAi register counts external pulses or another timer overflows or underflows.
3. Read-modify-write instructions cannot be used to set the TAi register. Refer to Usage Notes for details.
4. When the TAi register is set to 0000h, the counter does not start and a timer Ai interrupt request is not generated.
5. When the TAi register is set to 0000h, the pulse width modulator does not operate and the TAiOUT pin output is held "L".
A timer Ai interrupt request is not generated. When the TAi register is set to FFFFh, the pulse width modulator does
not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated.
6. When 8 high-order bits are set to 00h, the pulse width modulator does not operate and the TAiOUT pin output is held "L".
A timer Ai interrupt request is not generated. When 8 high-order bits are set to FFh, the pulse width modulator does
not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated.
Figure 15.9
TA0 to TA4 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 149 of 352
WO
M32C/8A Group
15. Timers (Timer A)
Up/Down Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
UDF
0344h
00h
Bit Symbol
Bit Name
Function
RW
TA0UD
Timer A0 up/down select bit (2)
0: Decrement
1: Increment
RW
TA1UD
Timer A1 up/down select bit (2)
0: Decrement
1: Increment
RW
TA2UD
Timer A2 up/down select bit (2)
0: Decrement
1: Increment
RW
TA3UD
Timer A3 up/down select bit (2)
0: Decrement
1: Increment
RW
TA4UD
Timer A4 up/down select bit (2)
0: Decrement
1: Increment
RW
TA2P
Timer A2
two-phase pulse signal
processing function select bit (3)
0: Two-phase pulse signal processing function
disabled
1: Two-phase pulse signal processing function
enabled
WO
TA3P
Timer A3
two-phase pulse signal
processing function select bit (3)
0: Two-phase pulse signal processing function
disabled
1: Two-phase pulse signal processing function
enabled
WO
TA4P
Timer A4
two-phase pulse signal
processing function select bit (3)
0: Two-phase pulse signal processing function
disabled
1: Two-phase pulse signal processing function
enabled
WO
NOTES:
1. Read-modify-write instructions cannot be used to set the UDF register. Refer to Usage Notes for details.
2. This bit is enabled when the MR2 bit in the TAiMR register (i = 0 to 4) is set to 0 (the UDF register causes increment/decrement
switching) in event counter mode.
3. Set these bits to 0 when not using the two-phase pulse signal processing function.
Figure 15.10
UDF Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 150 of 352
M32C/8A Group
15. Timers (Timer A)
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRGSR
0343h
00h
Bit Symbol
Bit Name
TA1TGL
b1 b0
Timer A1 trigger select bits
TA1TGH
Timer A2 trigger select bits
TA2TGH
0 0: Input to the TA2IN pin selected
0 1: TB2 overflows selected (1)
1 0: TA1 overflows selected (1)
1 1: TA3 overflows selected (1)
b5 b4
TA3TGL
Timer A3 trigger select bits
TA3TGH
0 0: Input to the TA3IN pin selected
0 1: TB2 overflows selected (1)
1 0: TA2 overflows selected (1)
1 1: TA4 overflows selected (1)
b7 b6
TA4TGL
Timer A4 trigger select bits
TA4TGH
NOTE:
1. Overflow or underflow.
TRGSR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
0 0: Input to the TA1IN pin selected
0 1: TB2 overflows selected (1)
1 0: TA0 overflows selected (1)
1 1: TA2 overflows selected (1)
b3 b2
TA2TGL
Figure 15.11
Function
Page 151 of 352
0 0: Input to the TA4IN pin selected
0 1: TB2 overflows selected (1)
1 0: TA3 overflows selected (1)
1 1: TA0 overflows selected (1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
M32C/8A Group
15. Timers (Timer A)
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TABSR
0340h
00h
Bit Symbol
Figure 15.12
Bit Name
0: Count stops
1: Count starts
RW
TA0S
Timer A0 count start bit
TA1S
Timer A1 count start bit
0: Count stops
1: Count starts
RW
TA2S
Timer A2 count start bit
0: Count stops
1: Count starts
RW
TA3S
Timer A3 count start bit
0: Count stops
1: Count starts
RW
TA4S
Timer A4 count start bit
0: Count stops
1: Count starts
RW
TB0S
Timer B0 count start bit
0: Count stops
1: Count starts
RW
TB1S
Timer B1 count start bit
0: Count stops
1: Count starts
RW
TB2S
Timer B2 count start bit
0: Count stops
1: Count starts
RW
TABSR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
Page 152 of 352
RW
M32C/8A Group
15. Timers (Timer A)
One-Shot Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
ONSF
0342h
00h
Bit Symbol
Bit Name
Timer A0 one-shot start bit (1)
0: In an idle state
1: Timer starts
RW
TA1OS
Timer A1 one-shot start bit (1)
0: In an idle state
1: Timer starts
RW
TA2OS
Timer A2 one-shot start bit (1)
0: In an idle state
1: Timer starts
RW
TA3OS
Timer A3 one-shot start bit (1)
0: In an idle state
1: Timer starts
RW
TA4OS
Timer A4 one-shot start bit (1)
0: In an idle state
1: Timer starts
RW
TAZIE
Z-phase input enable bit
0: Z-phase input disabled
1: Z-phase input enabled
RW
b7 b6
Timer A0 trigger select bits
TA0TGH
NOTES:
1. Read as 0.
2. Overflow or underflow.
ONSF Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
TA0OS
TA0TGL
Figure 15.13
Function
Page 153 of 352
0 0: Input to the TA0IN pin selected
0 1: TB2 overflows selected (2)
1 0: TA4 overflows selected (2)
1 1: TA1 overflows selected (2)
RW
RW
M32C/8A Group
Table 15.1
15. Timers (Timer A)
TAiOUT Pin Settings in Output Mode (i = 0 to 4)
Bit Setting
Pin
Function
PSC
Register
PSL1, PSL2
Registers
PS1, PS2
Registers(1)
P7_0(2)
TA0OUT
−
PSL1_0 = 1
PS1_0 = 1
P7_2
TA1OUT
−
PSL1_2 = 1
PS1_2 = 1
P7_4
TA2OUT
PSC_4 = 0
PSL1_4 = 0
PS1_4 = 1
P7_6
TA3OUT
−
PSL1_6 = 1
PS1_6 = 1
P8_0
TA4OUT
−
PSL2_0 = 0
PS2_0 = 1
NOTES:
1. Set registers PS1and PS2 after setting registers PSC, PSL1, and PSL2.
2. P7_0 is an N-channel open drain output port.
Table 15.2
TAiIN and TAiOUT Pin Settings in Input Mode (i = 0 to 4)
Bit Setting
Pin
Function
PD7, PD8
Registers
PS1, PS2
Registers
P7_0
TA0OUT
PD7_0 = 0
PS1_0 = 0
P7_1
TA0IN
PD7_1 = 0
PS1_1 = 0
P7_2
TA1OUT
PD7_2 = 0
PS1_2 = 0
P7_3
TA1IN
PD7_3 = 0
PS1_3 = 0
P7_4
TA2OUT
PD7_4 = 0
PS1_4 = 0
P7_5
TA2IN
PD7_5 = 0
PS1_5 = 0
P7_6
TA3OUT
PD7_6 = 0
PS1_6 = 0
P7_7
TA3IN
PD7_7 = 0
PS1_7 = 0
P8_0
TA4OUT
PD8_0 = 0
PS2_0 = 0
P8_1
TA4IN
PD8_1 = 0
PS2_1 = 0
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 154 of 352
M32C/8A Group
15.1.1
15. Timers (Timer A)
Timer Mode
In timer mode, the timer counts an internally generated count source.
Table 15.3 lists specifications of timer mode. Figure 15.14 shows a timer mode operation (Timer A).
Table 15.3
Specifications of Timer Mode
Item
Specification
f2n(1),
Count source
f1, f8,
Count operation
• Counter decrements
When the timer underflows, the contents of the reload register are reloaded
into the counter and the count continues.
Counter cycle
n+1
fj
fC32
fj: count source frequency
n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh
Count start condition
The TAiS bit in the TABSR register is set to 1 (count starts)
Count stop condition
The TAiS bit is set to 0 (count stops)
Interrupt request generation timing When the timer underflows
TAiIN pin function
Input for gate function
TAiOUT pin function
Pulse output
Read from timer
A read from the TAi register returns a counter value
Write to timer
• A write to the TAi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TAi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(2)
• Gate function
A signal applied to the TAiIN pin determines whether the count starts or stops.
• Pulse output function
The polarity of the TAiOUT pin is inverted whenever the timer underflows.
The TAiOUT pin outputs an “L” signal while the TAiS bit is 0 (count stops).
Selectable function
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Wait for one count source cycle or more to write after the count starts.
FFFFh
Count starts
Underflow
Underflow
n
Contents of the counter
n = contents of the reload
register
Reload
Count stops
Reload
0000h
TAiS bit in the
TABSR register
1
IR bit in the TAiIC
register
1
0
TAiOUT pin (output)
i = 0 to 4
Figure 15.14
Set to 0 by an interrupt request acknowledgement or by program
0
“H”
“L”
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode).
Bits MR2 and MR1 are set to 00b (gate function disabled).
Operation in Timer Mode (Timer A)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 155 of 352
M32C/8A Group
15.1.2
15. Timers (Timer A)
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulse input.
Timers A2, A3, and A4 can count externally generated two-phase signals.
Table 15.4 lists specifications of event counter mode when not handling two-phase pulse signals.
Table 15.5 lists specifications of event counter mode when handling two-phase pulse signals with timers A2,
A3, and A4. Figure 15.15 shows a event counter mode operation when not handling two-phase pulse signals.
Figure 15.16 shows a event counter mode operation when handling two-phase pulse signals with timers A2, A3,
and A4.
Table 15.4
Specifications of Event Counter Mode When Not Handling Two-Phase Pulse Signals
Item
Specification
Count source
• External signal applied to the TAiIN pin (i = 0 to 4) (valid edge is selectable by
program)
• Timer B2 overflows or underflows
• Timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0)
• Timer Ak overflows or underflows (k = i + 1 except k = 0 if i = 4)
Count operation
• Count direction (increment or decrement) can be selected by external signal or
by program.
• Reload/Free-run type can be selected.
Reload function: The contents of the reload register are reloaded into the
counter and the count continues when the timer underflows or overflows.
Free-running function: The counter continues running without reloading when
the timer underflows or overflows.
Number of counting
(FFFFh - n + 1): when incrementing
n + 1: when decrementing
n: setting value of the TAi register, 0000h to FFFFh
Count start condition
The TAiS bit in the TABSR Register is set to 1 (count starts)
Count stop condition
The TAiS bit is set to 0 (count stops)
Interrupt request generation timing When the timer overflows or underflows
TAiIN pin function
Count source input
TAiOUT pin function
Pulse output, or input to select the count direction
Read from timer
A read from the TAi register returns a counter value
Write to timer
• A write to the TAi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TAi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(1)
Pulse output function
The polarity of the TAiOUT pin is inverted whenever the timer overflows or
underflows. The TAiOUT pin outputs “L” signal while the TAiS bit is 0 (count
stops).
Selectable function
NOTE:
1. Wait for one count source cycle or more to write after the count starts.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 156 of 352
M32C/8A Group
15. Timers (Timer A)
Overflow
FFFFh
Count resumes
Reload
Decrement to increment
Underflow
Count starts
n
Contents of the counter
n = contents of the reload
register
Count stops
Reload
0000h
Input to TAiIN pin
“H”
“L”
TAiS bit in the
TABSR register
1
TAiUD bit in the
UDF register
1
IR bit in the TAiIC
register
1
0
0
Set to 1 by program
0
i = 0 to 4
Set to 0 by an interrupt request acknowledgement or by program
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)
The MR1 bit is set to 1 (rising edges of an external signal counted)
The MR2 bit is set to 0 (UDF register setting)
Bits TCK1 to TCK0 bit are set to 00b (reload)
Figure 15.15
Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 157 of 352
M32C/8A Group
Table 15.5
15. Timers (Timer A)
Specifications of Event Counter Mode When Handling Two-Phase Pulse Signals on
Timers A2, A3, and A4
Item
Count source
Count operation
Specification
Two-phase pulse signals applied to pins TAiIN and TAiOUT (i = 2 to 4)
• Count direction (increment or decrement) is set by a two-phase pulse signal.
• Reload/Free-run type can be selected.
Reload function: The contents of the reload register are reloaded into the
counter and the count continues when the timer underflows or overflows.
Free-running function: The counter continues running without reloading when
the timer underflows or overflows.
Number of counting
(FFFFh - n + 1): when incrementing
n + 1: for decrementing
n: setting value of the TAi register, 0000h to FFFFh
Count start condition
The TAiS bit in the TABSR Register is set to 1 (count starts)
Count stop condition
The TAiS bit is set to 0 (count stops)
Interrupt request generation timing When the timer overflows or underflows
TAiIN pin function
Two-phase pulse input
TAiOUT pin function
Two-phase pulse input
Read from timer
A read from the TAi register returns a counter value
Write to timer
• A write to the TAi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TAi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(1)
• Normal processing operation (Timers A2 and A3)
While a high-level (“H”) signal is applied to the TAjOUT pin (j = 2, 3), the timer
increments a counter value at the rising edge of the TAjIN pin or decrements a
counter value at the falling edge.
• Multiply-by-4 processing operation (Timers A3 and A4)
The timer increments the counter value in the following timings:
-at the rising edge of TAkIN while TAkOUT is “H” (k = 3, 4)
-at the falling edge of TAkIN while TAkOUT is “L”
-at the rising edge of TAkOUT while TAkIN is “L”
-at the falling edge of TAkOUT while TAkIN is “H”
The timer decrements the counter in the following timings:
-at the rising edge of TAkIN while TAkOUT is “L”
-at the falling edge of TAkIN while TAkOUT is “H”
-at the rising edge of TAkOUT while TAkIN is “H”
-at the falling edge of TAkOUT while TAkIN is “L”
• Counter reset by a Z-phase pulse signal input (Timer A3)
The counter value is cleared to 0 by a Z-phase pulse signal input
Selectable function(2)
NOTES:
1. Wait for one count source cycle or more to write after the count starts.
2. Any operation can be selected for timer A3. Timer A2 is used only for the normal processing operation. Timer
A4 is used only for the multiply-by-4 operation.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 158 of 352
M32C/8A Group
15. Timers (Timer A)
Normal processing operation (Timer A2 and timer A3)
While an "H" is applied to the TAjOUT pin (j = 2, 3), the counter increments at the rising edge of the TAjIN pin and decrements at
the falling edge.
TAjOUT
TAjIN
<Free-running function>
m
Counter value
m+1
m+2
m+1
m
m-1
1
0
FFFF
FFFE
FFFF
0
IR bit in the
TAjIC register
Set to 0 by an interrupt request acknowledgement or by program.
<Reload function>
m
Counter value
m+1
m+2
m+1
m
m-1
1
0
FFFF
m-1
m
m+1
IR bit in the
TAjIC register
Set to 0 by an interrupt request acknowledgement or by program.
Multiply-by-4 processing operation (Timer A3 and timer A4)
The counter increments at the following timings:
-at the rising edge of TAkIN while TAkOUT is “H”
-at the falling edge of TAkIN while TAkOUT is “L”
-at the rising edge of TAkOUT while TAkIN is “L”
-at the falling edge of TAkOUT while TAkIN is “H”
The counter decrements at the following timings:
-at the rising edge of TAkIN while TAkOUT is “L”
-at the falling edge of TAkIN while TAkOUT is “H”
-at the rising edge of TAkOUT while TAkIN is “H”
-at the falling edge of TAkOUT while TAkIN is “L”
TAkOUT
TAkIN
<Free-running function>
m
Counter value
m+1
m+2
m+1
m
m-1
1
0
FFFF
FFFE
FFFF
0
IR bit in the
TAkIC register
Set to 0 by an interrupt request acknowledgement or by program.
<Reload function>
m
Counter value
m+1
m+2
m+1
m
m-1
1
0
FFFF
m-1
m
m+1
IR bit in the
TAkIC register
Set to 0 by an interrupt request acknowledgement or by program.
: increment
:decrement
Figure 15.16
Operation in Event Counter Mode When Handling Two-Phase Pulse Signals on
Timers A2, A3, and A4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 159 of 352
M32C/8A Group
15.1.2.1
15. Timers (Timer A)
Counter Reset by Two-Phase Pulse Signal Processing
The counter value of timer can be set to 0 by a Z-phase pulse signal input (counter reset) when processing
two-phase pulse signals.
This function can be used when all the following conditions are met; timer A3 event counter mode, two-phase
pulse signal processing, free-running count operation type, and multiply-by-4 processing. The Z-phase pulse
signal is applied to the INT2 pin.
When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), Z-phase pulse input is enabled to
reset the counter. To reset the counter by a Z-phase pulse input, set the TA3 register to 0000h beforehand.
A Z-phase pulse input is enabled when the edge of a signal applied to the INT2 pin is detected. The POL bit in
the INT2IC register can determine the edge polarity. The Z-phase pulse must have a pulse width of one timer
A3 count source cycle or more. Figure 15.17 shows relations between two-phase pulses (A-phase and B-phase)
and the Z-phase pulse.
Z-phase pulse input resets the counter in the next count source timing followed a Z-phase pulse input.
A timer A3 interrupt request is generated twice in a row if a timer A3 overflow or underflow, and the counter
reset by an INT2 input occur at the same time. Do not generate a timer A3 interrupt request when this function
is used.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
INT2(1)
(Z phase)
Pulse width of one count source cycle or more is required
Counter value
m
m+1
1
2
3
4
5
6
NOTE:
1. Example when the rising edge of INT2 is selected.
Figure 15.17
Relations between Two-Phase Pulses (A-Phase and B-Phase) and Z-Phase Pulse
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 160 of 352
M32C/8A Group
15.1.3
15. Timers (Timer A)
One-Shot Timer Mode
When a trigger occurs, the counter decrements until underflows. Then, the counter is reloaded and stops until
the next trigger occurs.
Table 15.6 lists specifications of one-shot timer mode. Figure 15.18 shows a one-shot timer mode operation.
Table 15.6
Specifications of One-Shot Timer Mode
Item
Specification
f2n(1),
fC32
Count source
f1, f8,
Count operation
• Counter decrements
When the counter reaches 0000h, the counter is reloaded and stops until the
next trigger occurs.
If a trigger occurs while counting, the contents of the reload register are
reloaded into the counter and the count continues.
Number of counting
n times
Count start condition
A trigger, selectable from the following, occurs while the TAiS bit in the TABSR
register is set to 1 (count starts):
• the TAiOS bit in the ONSF register is set to 1 (timer starts)
• an external trigger is applied to TAiIN pin
• timer B2 overflows or underflows,
• timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0),
• timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4)
Count stop condition
• After the counter reaches 0000h and the counter value is reloaded
• When the TAiS bit is set to 0 (count stops)
n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh
(but the counter does not run if n = 0000h)
Interrupt request generation timing When the counter reaches 0000h
TAiIN pin function
Trigger input
TAiOUT pin function
Pulse output
Read from timer
A read from the TAi register returns undefined value
Write to timer
• A write to the TAi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TAi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(2)
Selectable function
Pulse output function
“L” is output while the count stops. “H” is output while counting.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Wait for one count source cycle or more to write after the count starts.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 161 of 352
M32C/8A Group
15. Timers (Timer A)
Count stops
Count stops
FFFFh
Count starts
Count starts
Re-trigger input
m
Contents of the
counter
m = contents of
the reload register
Reload
Count stops
Count starts
Reload
Reload
0000h
TAiS bit in the
TABSR register
1
0
Write signal to
TAiOS bit in the
ONSF register
1 / fj x m
One-shot pulse
output from the
TAiOUT pin
1 / fj x (m + 1)
“H”
“L”
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the
TAiIC register
1
0
fj: Frequency of the count source (f1, f8, f2n (1), fC32)
i = 0 to 4
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 10b (one-shot timer mode).
The MR2 bit is set to 0 (The TAiOS bit in the ONSF register is enabled).
Figure 15.18
Operation in One-Shot Timer Mode (Timer A)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 162 of 352
M32C/8A Group
15.1.4
15. Timers (Timer A)
Pulse Width Modulation Mode
In pulse width modulation mode, the timer outputs pulse signals of a given width repeatedly. The counter
functions as an 8-bit pulse width modulator or 16-bit pulse width modulator.
Table 15.7 lists specifications of pulse width modulation mode. Figures 15.19 and 15.20 show examples of a
16-bit pulse width modulator and 8-bit pulse width modulator operations.
Table 15.7
Specifications of Pulse Width Modulation Mode
Item
Specification
f2n(1),
fC32
Count source
f1, f8,
Count operation
• Counter decrements
(The counter functions as the 8-bit or 16-bit pulse width modulator.)
The contents of the reload register are reloaded at the rising edge of the PWM
pulse and the counter decrements. The count continues even if the re-trigger
occurs while counting.
16-bit PWM
• “H” width = n / fj
n: setting value of the TAi register (i = 0 to 4), 0000h to FFFEh
fj: count source frequency
• Cycle = (216 - 1) / fj
The cycle is fixed to this value
8-bit PWM
• “H” width = n x (m + 1) / fj
• Cycle = (28 - 1) x (m + 1) / fj
m: setting value of low-order bit address of the TAi register, 00h to FFh
n: setting value of high-order bit address of the TAi register, 00h to FEh
Count start condition
When a trigger is not used (the MR2 bit in the TAiMR register is 0):
Set the TAiS bit in the TABSR register to 1
When a trigger is used (the MR2 bit in the TAiMR register is 1):
A trigger, selectable from the following occurs while the TAiS bit in the TABSR
register is set to 1(count starts):
• an external trigger is applied to TAiIN pin
• timer B2 overflows or underflows
• timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0)
• timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4)
Count stop condition
The TAiS bit is set to 0 (count stops)
Interrupt request generation timing At the falling edge of the PWM pulse
TAiIN pin function
Trigger input
TAiOUT pin function
Pulse output
Read from timer
A read from the TAi register returns undefined value
Write to timer
• A write to the TAi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TAi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(2)
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Wait for one count source cycle or more to write after the count starts.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 163 of 352
M32C/8A Group
15. Timers (Timer A)
Count stops
Count starts
End of 1 cycle
1 / fj × (216 - 1)
Count source
Input to the TAiIN pin
"H"
No trigger is generated
by this signal
"L"
TAiS bit in the TABSR
register
1
PWM pulse output
from the TAiOUT pin
"H"
Set to 1 by program
Set to 0 by program
0
1 / fj × m
"L"
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the
TAiIC register
1
0
i = 0 to 4
fj: Count source frequency (f1, f8, f2n (1), fC32)
m: Setting value of the TAi register (0000h to FFFEh)
When the TAiS bit is set to 0 (count stops) while the
TAiOUT output is "H", the TAiOUT output becomes
"L" and the IR bit is set to 1 (interrupt requested).
(Conditions) TAi register is set to 0005h.
TAiMR register: MR1 bit is set to 1 (rising edge of signal applied to the TAiIN pin)
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 15.19
16-Bit Pulse Width Modulator Operation (Timer A)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 164 of 352
M32C/8A Group
15. Timers (Timer A)
Count starts
End of 1 cycle
Count stops
Count source
Signal applied
to TAiIN pin
TAiS bit in the
TABSR register
1 / fj x (m+1) x (2 8-1)
“H”
“L”
Set to 1 by program
Set to 0 by program
1
0
Underflow signal of
8-bit prescaler
1 / fj x (m+1) x n
PWM pulse output
from TAiOUT pin
“H”
“L”
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the
TAiIC register
1
0
i = 0 to 4
fj: Count source frequency (f1, f8, f2n (1), fC32)
n: high-order bits in the TAi register (00h to FEh)
m: low-order bits in the TAi register (00h to FFh)
When the TAiS bit is set to 0 (count stops) while the TAiOUT
output is "H", the TAiOUT output becomes "L" and the IR bit
becomes 1 (interrupt requested).
(Conditions) High-order bits in the TAi register are set to 02h.
Low-order bits in the TAi register are set to 02h.
TAiMR register: The MR1 bit is set to 0 (falling edge of signal applied to the TAiIN pin.)
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. The 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
Figure 15.20
8-bit Pulse Width Modulator Operation (Timer A)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 165 of 352
M32C/8A Group
15.2
15. Timers (Timer B)
Timer B
Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5)
determine which mode is used.
• Timer mode: The timer counts the internal count source.
• Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses.
• Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or
pulse width of the external signal.
Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B.
Table 15.8 shows TBiIN pin settings (i = 0 to 5).
High-order bits of data bus
Low-order bits of data bus
Clock source select
TCK1 and TCK0
00
f1
f8 01
f2n(1) 10
fC32 11
TBj overflow(2)
Polarity switching
TBiIN
and edge pulse
1
TCK1
8 high-order
bits
8 low-order
bits
TMOD1 and TMOD0
00: Timer mode
10: Pulse period and pulse
width measurement mode
Reload register
Counter
01: Event counter mode
0
TBiS
Counter reset circuit
i= 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or
divide-by-2n (n = 1 to 15).
2. Overflow signal or underflow signal.
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register
TBiS: Bit in the TABSR register or the TBSR register
Figure 15.21
Timer B Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 166 of 352
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Addresses
0351h
0350h
0353h
0352h
0355h
0354h
0311h
0310h
0313h
0312h
0315h
0314h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
M32C/8A Group
15. Timers (Timer B)
Timer Bi Mode Register (i = 0 to 5)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
After Reset
TB0MR to TB5MR
035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
00XX 0000b
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
Operating mode select bits
b1 b0
0 0: Timer mode
TMOD1
RW
MR0
RW
Disabled in timer mode.
Can be set to either 0 or 1
MR1
RW
Registers TB0MR and TB3MR:
Set to 0 in timer mode.
MR2
MR3
RW
Registers TB1MR, TB2MR, TB4MR, and TB5MR:
Unimplemented.
Write 0. Read as undefined value.
−
Disabled in timer mode.
Write 0. Read as undefined value.
−
b7 b6
TCK0
Count source select bits
TCK1
0 0: f1
0 1: f8
1 0: f2n(1)
1 1: fC32
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n,
set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.22
TB0MR to TB5MR Registers in Timer Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 167 of 352
RW
RW
M32C/8A Group
15. Timers (Timer B)
Timer Bi Mode Register (i = 0 to 5)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 1
Symbol
Address
After Reset
TB0MR to TB5MR
035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
00XX 0000b
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
Operating mode select bits
b1 b0
0 1: Event counter mode
TMOD1
RW
b3 b2
MR0
Count polarity select bits
0 0: Falling edges of an external signal counted
0 1: Rising edges of an external signal counted
1 0: Falling and rising edges of an external
signal counted
1 1: Do not set to this value
(1)
MR1
Registers TB0MR and TB3MR:
Set to 0 in event counter mode.
MR2
RW
RW
RW
Registers TB1MR, TB2MR, TB4MR, and TB5MR:
Unimplemented.
Write 0. Read as undefined value.
−
MR3
Disabled in event counter mode.
Write 0. Read as undefined value.
−
TCK0
Disabled in event counter mode.
Can be set to either 0 or 1
TCK1
Event clock select bit
RW
0: Signal applied to the TBiIN pin
1: TBj overflows or underflows (2)
RW
NOTES:
1. Bits MR1 and MR0 are enabled when the TCK1 bit is set to 0. Bits MR1 and MR0 can be set to either 0 or 1 when the TCK1 bit
is set to 1.
2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3.
Figure 15.23
TB0MR to TB5MR Registers in Event Counter Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 168 of 352
M32C/8A Group
15. Timers (Timer B)
Timer Bi Mode Register (i = 0 to 5)
(Pulse Period Measurement Mode, Pulse Width Measurement Mode)
b7 b6 b5 b4 b3 b2 b1 b0
1 0
Symbol
Address
After Reset
TB0MR to TB5MR
035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
00XX 0000b
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
b1 b0
Operating mode select bits
TMOD1
1 0: Pulse period measurement mode
Pulse width measurement mode
b3 b2
MR0
Measurement mode
select bits(1)
MR1
0 0: Pulse period measurement 1
0 1: Pulse period measurement 2
1 0: Pulse width measurement
1 1: Do not set to this value
Registers TB0MR and TB3MR:
Set to 0 in pulse period measurement mode, pulse width measurement mode.
MR2
MR3
Registers TB1MR, TB2MR, TB4MR, and TB5MR:
Unimplemented.
Write 0. Read as undefined value.
Timer Bi overflow flag (2)
TCK0
Count source select bits
TCK1
RW
RW
RW
RW
−
0: No overflow has occurred
1: Overflow has occurred (3)
RO
b7 b6
RW
0 0: f1
0 1: f8
1 0: f2n(4)
1 1: fC32
RW
NOTES:
1. Bits MR1 and MR0 determine the following measurement modes:
Pulse period measurement 1 (bits MR1 and MR0 are set to 00b):
Measures the width between the falling edges of a pulse
Pulse period measurement 2 (bits MR1 and MR0 bits are set to 01b):
Measures the width between the rising edges of a pulse
Pulse width measurement (bits MR1 and MR0 bits are set to 10b):
Measures the width between a falling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse
2. The MR3 bit is undefined when reset.
3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write a 0 to the TBiMR register after the MR3 bit
becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts).
4. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the
TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.24
TB0MR to TB5MR Registers in Pulse Period Measurement Mode, Pulse Width
Measurement Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 169 of 352
M32C/8A Group
15. Timers (Timer B)
Timer Bi Register(1) (i = 0 to 5)
b15
b8 b7
b0
Symbol
TB0 to TB2
TB3 to TB5
Mode
Address
0351h - 0350h, 0353h - 0352h, 0355h - 0354h
0311h - 0310h, 0313h - 0312h, 0315h - 0314h
Function
RW
If a count source frequency is fj, and the
setting value of the TBi register is n, the
counter cycle is (n+1).
0000h to FFFFh
RW
Event Counter Mode
If the setting value of the TBi register is n,
the count times are (n+1)(2)
0000h to FFFFh
RW
Pulse Period
Measurement Mode,
Pulse Width
Measurement Mode
Increment the counter between one valid
edge and another valid edge of a pulse
applied to the TBiIN pin
−
RO
TB0 to TB5 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Setting Range
Timer Mode
NOTES:
1. Read and write this register in 16-bit units.
2. Timer Bi counts overflows/underflows of another timer, or the external pulses.
Figure 15.25
After Reset
Undefined
Undefined
Page 170 of 352
M32C/8A Group
15. Timers (Timer B)
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TABSR
0340h
00h
Bit Symbol
Bit Name
Function
RW
TA0S
Timer A0 count start bit
0: Count stops
1: Count starts
RW
TA1S
Timer A1 count start bit
0: Count stops
1: Count starts
RW
TA2S
Timer A2 count start bit
0: Count stops
1: Count starts
RW
TA3S
Timer A3 count start bit
0: Count stops
1: Count starts
RW
TA4S
Timer A4 count start bit
0: Count stops
1: Count starts
RW
TB0S
Timer B0 count start bit
0: Count stops
1: Count starts
RW
TB1S
Timer B1 count start bit
0: Count stops
1: Count starts
RW
TB2S
Timer B2 count start bit
0: Count stops
1: Count starts
RW
Timer B3, B4, B5 Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TBSR
0300h
000X XXXXb
Bit Symbol
−
(b4-b0)
Figure 15.26
Bit Name
Unimplemented.
Write 0. Read as undefined value.
RW
−
TB3S
Timer B3 count start bit
0: Count stops
1: Count starts
RW
TB4S
Timer B4 count start bit
0: Count stops
1: Count starts
RW
TB5S
Timer B5 count start bit
0: Count stops
1: Count starts
RW
TABSR Register, TBSR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
Page 171 of 352
M32C/8A Group
Table 15.8
15. Timers (Timer B)
TBiIN Pin Settings (i=0 to 5)
Bit Setting
Pin
Function
PD9(1)
PD7,
Registers
PS1, PS3(1)
Registers
P7_1
TB5IN
PD7_1 = 0
PS1_1 = 0
P9_0
TB0IN
PD9_0 = 0
PS3_0 = 0
P9_1
TB1IN
PD9_1 = 0
PS3_1 = 0
P9_2
TB2IN
PD9_2 = 0
PS3_2 = 0
P9_3
TB3IN
PD9_3 = 0
PS3_3 = 0
P9_4
TB4IN
PD9_4 = 0
PS3_4 = 0
NOTE:
1. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 172 of 352
M32C/8A Group
15.2.1
15. Timers (Timer B)
Timer Mode
In timer mode, the timer counts an internally generated count source.
Table 15.9 lists specifications of timer mode. Figure 15.27 shows a timer mode operation (Timer B).
Table 15.9
Specifications of Timer Mode
Item
Specification
f2n(1),
fC32
Count source
f1, f8,
Count operation
• Counter decrements
When the timer underflows, the contents of the reload register are reloaded
into the counter and the count continues.
Counter cycle
n+1
fj
fj: count source frequency
n: setting value of the TBi register (i=0 to 5), 0000h to FFFFh
Count start condition
The TBiS bit in the TABSR or TBSR register is set to 1 (count starts)
Count stop condition
The TBiS bit is set to 0 (count stops)
Interrupt request generation timing When the timer underflows
TBiIN pin function
Programmable I/O port
Read from timer
A read from the TBi register returns a counter value.
Write to timer
• A write to the TBi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TBi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(2)
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Wait for one count source cycle or more to write after the count starts.
FFFFh
Count resumes
Count starts
Underflow
Underflow
n
Contents of the counter
n = contents of the reload
register
TBiS bit in the
TABSR or TBSR
register
Count stops
Reload
0000h
IR bit in the TBiIC
register
1
0
1
0
Set to 0 by an interrupt request acknowledged or by program
i = 0 to 5
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode).
Figure 15.27
Reload
Operation in Timer Mode (Timer B)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 173 of 352
M32C/8A Group
15.2.2
15. Timers (Timer B)
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulses.
Table 15.10 lists specifications of event counter mode. Figure 15.28 shows an event counter mode operation.
Table 15.10
Specifications of Event Counter Mode
Item
Specification
Count source
• External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected
by program)
• TBj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3)
Count operation
• Counter decrements
When the timer underflows, the contents of the reload register are reloaded into
the counter and the count continues.
Number of counting
(n + 1) times
Count start condition
The TBiS bit in the TABSR or TBSR register is set to 1 (count starts)
Count stop condition
The TBiS bit is set to 0 (count stops)
n: Setting value of the TBi register 0000h to FFFFh
Interrupt request generation timing When the timer underflows
TBiIN pin function
Count source input
Read from timer
A read from the TBi register returns a counter value.
Write to timer
• A write to the TBi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TBi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).(1)
NOTE:
1. Wait for one count source cycle or more to write after the count starts.
FFFFh
Count starts
Underflow
n
Count resumes
Count stops
Reload
Contents of the counter
n = contents of the reload
register
0000h
“H”
Input to the TBiIN pin
“L”
TBiS bit in the TABSR or TBSR
regsiter
IR bit in the TBiIC regsiter
1
0
1
0
i = 0 to 5
Set to 0 by an interrupt request acknowledgement or by program
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)
Bits MR1 and MR0 are set to 00b (count the falling edge of the external signal)
The TCK1 bit is set to 0 (signal input to TBiIN pin)
Figure 15.28
Operation in Event Counter Mode (Timer B)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 174 of 352
M32C/8A Group
15.2.3
15. Timers (Timer B)
Pulse Period Measurement Mode, Pulse Width Measurement Mode
In pulse period measurement mode and pulse width measurement mode, the timer measures pulse period or
pulse width of the external signal.
Table 15.11 shows specifications in pulse period measurement mode and pulse width measurement mode.
Figure 15.29 shows a pulse period measurement operation. Figure 15.30 shows a pulse width measurement
operation.
Table 15.11
Specifications of Pulse Period Measurement Mode, Pulse Width Measurement Mode
Item
Specification
f2n(1),
fC32
Count source
f1, f8,
Count operation
• Counter increments
The counter value is transferred to the reload register when the valid edge of a
pulse is detected. Then the counter becomes 0000h and the
count continues.
Count start condition
The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 1 (count starts)
Count stop condition
The TBiS bit is set to 0 (count stops)
Interrupt request generation timing • When the valid edge of a pulse is input(2)
• When the timer overflows(3)
The MR3 bit in the TBiMR register is set to 1 (overflow) simultaneously.
TBiIN pin function
Pulse input
Read from timer
A read from the TBi register returns the contents of the reload register
(measurement results)(4)
Write to timer
The TBi register cannot be written
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. An interrupt request is not generated when the first valid edge is input after the count starts.
3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register
after the MR3 bit becomes 1, while the TBiS bit is set to 1.
4. A value read from the TBi register is undefined until the second valid edge is detected after the count starts.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 175 of 352
M32C/8A Group
15. Timers (Timer B)
1st valid edge
“H”
Pulse input
to TBiIN pin(2)
2nd valid edge
“L”
FFFFh
n
Contents of the counter
(n = contents of the
reload register)
(note 1)
0000h
TBiS bit in the TABSR register
or TBSR register
1
0
1
IR bit in the TBiIC
register
Set to 0 by an interrupt request acknowledgement or by program
0
Transfer timing from counter
to reload register
TBi register
Transfer (undefined value)
Transfer (measured value n)
Undefined value
n
i = 0 to 5
NOTES:
1. Counter is reset due to the completion of the measurement.
2. If an overflow and a valid edge input occur simultaneously, an interrupt request is generated only once,
which results in the valid edge not being recognized. Do not let an overflow occur.
Figure 15.29
Operation in Pulse Period Measurement Mode (Timer B)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 176 of 352
M32C/8A Group
15. Timers (Timer B)
1st valid edge
Pulse input
to TBiIN pin
“H”
2nd valid edge
10000h + n
“L”
FFFFh
n
Contents of the counter
n = contents of the
reload register
(note1)
(note2)
(note1)
0000h
TBiS bit in the TABSR or
TBSR register
1
MR3 bit in the
TBiMR register
1
0
(note 3)
0
(note 4)
1
IR bit in the TBiIC register
(note 4)
0
Set to 0 by an interrupt acknowledgement or by program
Transfer timing from counter
to reload register
Transfer
(measured value n)
Transfer
(undefined value)
TBi register
Undefined value
n
i = 0 to 5
NOTES:
1. Counter is reset due to the completion of the measurement.
2. Overflow
3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write a 0 to the TBiMR register
after the MR3 bit becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts).
4. Determine whether an interrupt source is a valid edge input or an overflow by reading the port level
in the TBi interrupt routine.
Figure 15.30
Operation in Pulse Width Measurement Mode (Timer B)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 177 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
16. Three-Phase Motor Control Timer Function
The PWM waveform can be output by using timers B2, A1, A2, and A4. Timer B2 is used for the carrier wave control,
and timers A4, A1, and A2 for the U-, V-, and W-phase PWM control.
Table 16.1 lists specifications of the three-phase motor control timer functions. Table 16.2 lists pin settings. Figure
16.1 shows a block diagram. Figures 16.2 to 16.10 show registers associated with the three-phase motor control timer
function.
Table 16.1
Specifications of Three-Phase Motor Control Timers
Item
Specification
Control method
Three-phase full wave method
Modulation modes
• Triangular wave modulation mode
• Sawtooth wave modulation mode
Active level
Selectable either active High or active Low
Timers to be used
• Timer B2 (Carrier wave cycle control: used in timer mode)
• Timers A4, A1, and A2
(U-, V-, W-phase PWM control: used in one-shot timer mode):
Short circuit prevention features
• Prevention function against upper and lower arm short circuit caused by
program errors
• Arm short circuit prevention function using dead time timer
• Forced cutoff function by NMI input
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 178 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
TB2
register
PWCON
0
1
Reload
register
Timer A1 reload
control signal
ICTB2
register
INV02
f1
Timer A1 reload
control signal
Value written to INV03 bit
Write signal to INV03 bit
"1" write signal to
INV07 bit
RESET
NMI
INV05
INV06
INV06
Write signal to
IDBi register
SQ
R
V-Phase Output
Control Circuit
INV03
DQ
T
R
INV02
INV04
U-phase
W-phase
DTT
register
Transfer
trigger(1)
Start
trigger
V-phase upper/
lower arm short
circuit detection
signal
Reload
register
INV16
0
1
Dead timer
timer
fDT
Dead timer timer
start trigger
Interrupt request
Timer B2
interrupt request
INV00
INV10
Write signal to
TB2 register
1
0
Counter
INV01
INV11
Timer B2
INV15
Data Bus
Timer A1 reload
control signal
INV14
0
1
INV11
DQ
T
DQ
TQ
TA1
register
TA11
register
DQ
DQ
T
T
DQ
Three-phase output
D Q shift register
DV1
DV0
Data Bus
V
INV14
0
1
V
DQ
T
Dead timer timer
start trigger
Data Bus
D
TQ
Start
trigger
f1
Reload
register
DQ
T
Timer A1
DQ
DQ
DVB1
DVB0
DQ
D
T
TQ
fDT
Three-phase output
shift register
Data Bus
Transfer trigger
Start trigger
DTT register
U-Phase Output Control Circuit
Transfer trigger
Start trigger
DTT register
W-Phase Output Control Circuit
INV00 to INV07: bits in the INVC0 register
INV10 to INV15: bits in the INVC1 register
DVi, DVBi: bits in the IDBi register (i = 0, 1)
PWCON: bit in the TB2SC register
NOTE:
1. When the INV06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated at the first timer B2
underflow after writing to the IDBi register (i = 0, 1).
Figure 16.1
Three-Phase Motor Control Timer Function Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 179 of 352
U
U
W
W
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
After Reset
00h
Address
0308h
Bit Symbol
Bit Name
Function
RW
b1 b0
INV00
ICTB2 count condition
select bits
INV01
0 0:
Timer B2 underflow
0 1:
1 0: Timer B2 underflow at the rising edge of the
timer A1 reload control signal(2)
(every odd-numbered timer B2 underflow)
1 1: Timer B2 underflow at the falling edge of the
timer A1 reload control signal(2)
(every even-numbered timer B2 underflow)
RW
RW
INV02
Three-phase motor control timer
function enable bit(3)
0: Three-phase motor control timer function not used
1: Three-phase motor control timer function used(4,5)
RW
INV03
Three-phase motor control timer
output control bit
0: Three-phase motor control timer output disabled(5,6)
1: Three-phase motor control timer output enabled
RW
INV04
Upper and lower arm
simultaneous turn-on disable bit
0: Simultaneous turn-on enabled
1: Simultaneous turn-on disabled
RW
INV05
Upper and lower arm
simultaneous turn-on detect flag
0: Not detected
1: Detected (7)
RO
INV06
Modulation mode select bit (9)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode (10)
RW
INV07
Software trigger select bit
Transfer trigger is generated when the INV07 bit
is set to 1. Trigger for the dead time timer is also
generated when the INV06 bit is set to 1.
This bit is read as 0.
RW
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set bits INV06 and INV02 to INV00
while timers A1,A2, A4, and B2 are stopped.
2. Set the INV01 bit to 1 after setting a value to the ICTB2 register. Also, when the INV01 bit is set to 1, set the timer A1 count start
bit to 1 prior to the first timer B2 underflow.
3. Set pins after the INV02 bit is set to 1. Refer to the table, Pin settings when using three-phase motor control timer function .
4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits, and ICTB2 counter.
5. When the INV03 bit is set to 0 and the INV02 bit to 1, pins U, U, V, V, W, and W (including when other output functions are
assiged to these pins) are all placed in high-impedance states.
6. The INV03 bit becomes 0 when one of the following occurs:
-Reset
-The both upper and lower arms output the active level signals at the same time while the INV04 bit is set to 1
-The INV03 bit is set to 0 by program
-Signal applied to the NMI pin changes from "H" to "L" (while an "L" is applied to the NMI pin, the INV03 bit cannot be set to 1).
7. The INV05 bit cannot be set to 1 by program. To set the INV05 bit to 0, write a 0 to the INV04 bit.
Figure 16.2
INVC0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 180 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INVC1
Address
0309h
Bit Symbol
Bit Name
After Reset
00h
Function
RW
INV10
Timers A1, A2, and A4
start trigger select bit
0: Timer B2 underflow
1: Timer B2 underflow and a write to the TB2
register
RW
INV11
Timers A11, A21, and A41
control bit
0: Timers A11, A21, and A41 not used
(Three-phase mode 0)
1: Timers A11, A21, and A41 used
(Three-phase mode 1)
RW
INV12
Dead time timer
count source (fDT) select bit
0: f1
1: f1 divided by 2
RW
INV13
Carrier wave rise/fall
detect flag(2)
0: Timer B2 underflow occurred an even number
of times
1: Timer B2 underflow occurred an odd number
of times
RO
INV14
Active level control bit
0: Active Low
1: Active High
RW
INV15
Dead time disable bit
0: Dead time enabled
1: Dead time disabled
RW
INV16
Dead time timer trigger
select bit
0: Falling edge of one-shot pulse of timer
(A4, A1, and A2 (3))
1: Rising edge of the three-phase output shift
register (U-, V-, W-phase)
RW
Reserved bit
Set to 0
RW
−
(b7)
NOTES:
1. Set the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set the INVC1 register while timers A1,
A2, A4, and B2 are stopped.
2. The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1.
3. If the following conditions are all met, set the INV16 bit to 1.
- The INV15 bit is set to 0
- Bits Dij (i = U, V or W, j = 0, 1) and DiBj in the IDBj register always have different values when the INV03 bit in the INVC0
register is set to 1 (three-phase control timer output enabled).
(The upper arm and lower arm always output opposite level signals at any time except dead time.)
If any of the above conditions is not met, set the INV16 bit to 0.
Figure 16.3
INVC1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 181 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
After Reset
TB2MR
035Dh
00XX 0000b
Bit Symbol
Bit Name
Function
TMOD0
RW
RW
Operating mode select bits
Set to 00b (timer mode) to use the three-phase
motor control timer function
TMOD1
RW
MR0
RW
Disabled to use the three-phase motor control timer function.
Can be set to either 0 or 1.
MR1
RW
MR2
Set to 0 to use the three-phase motor control timer function
MR3
Unimplemented.
Write 0. Read as undefined value.
−
TCK0
RW
Count source select bits
Set to 00b (f1) to use the three-phase motor
control timer function
TCK1
Figure 16.4
TB2MR Register when Using Three-Phase Motor Control Timer Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 182 of 352
RW
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 1 0
Symbol
Address
After Reset
TA1MR, TA2MR, TA4MR
0357h, 0358h, 035Ah
00h
Bit Symbol
Bit Name
Function
TMOD0
RW
Operating mode select bits
Set to 01b (one-shot timer mode) to use the
three-phase motor control timer function
TMOD1
RW
−
(b2)
Reserved bit
Set to 0
RW
MR1
External trigger select bit
Set to 0 to use the three-phase motor control
timer function
RW
MR2
Trigger select bit
Set to 1 (selected by the TRGSR register) to use
the three-phase motor control timer function
RW
MR3
Set to 0 to use the three-phase motor control timer function
TCK0
RW
RW
Count source select bits
TCK1
Figure 16.5
RW
Set to 00b (f1) to use the three-phase motor
control timer function
RW
TA1MR, TA2MR, and TM4MR Registers when Using Three-Phase Motor Control Timer
Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 183 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRGSR
0343h
00h
Bit Symbol
Bit Name
Function
TA1TGL
RW
Timer A1 trigger select bits
Set to 01b (TB2 underflow) to use the V-phase
output control circuit
TA1TGH
RW
TA2TGL
RW
Timer A2 trigger select bits
Set to 01b (TB2 underflow) to use the W-phase
output control circuit
TA2TGH
RW
b5 b4
TA3TGL
Timer A3 trigger select bits
TA3TGH
0 0: Input to the TA3IN pin selected
0 1: TB2 overflow selected (1)
1 0: TA2 overflow selected (1)
1 1: TA4 overflow selected (1)
TA4TGL
RW
RW
Timer A4 trigger select bits
NOTE:
1. Overflow or underflow.
TRGSR Register when Using Three-Phase Motor Control Timer Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Set to 01b (TB2 underflow) to use the U-phase
output control circuit
TA4TGH
Figure 16.6
RW
Page 184 of 352
RW
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer B2 Special Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0 0 0 0 0 0
TB2SC
035Eh
00h
Bit Symbol
PWCON
−
(b7-b1)
Bit Name
Function
RW
Timer B2
reload timing switch bit
0: Timer B2 underflow
1: Timer B2 underflow at the rising edge of the
timer A1 reload control signal
(every odd-numbered timer B2 underflow)
RW
Reserved bits
Set to 0
RW
NOTE:
1. Set the TB2SC register after the PRC1 bit in the PRCR register is set to 1 (write enable).
Timer B2 Interrupt Generation Frequency Set Counter(1, 2)
b7 b6 b5 b4 b3
b0
Symbol
Address
After Reset
ICTB2
030Dh
Undefined
Function
Setting Range
RW
-When the INV01 bit in the INVC0 register is set to 0 (the ICTB2
counter increments at every timer B2 underflows) and a setting
value is n, the timer B2 interrupt request is generated every n-th
timer B2 underflow.
-When bits INV01 and INV00 are set to 10b (the ICTB2 counter
increments when the timer B2 underflow at the rising edge of the
timer A1 reload control signal) and a setting value is n, the first
timer B2 interrupt request is generated at the (2n-1)th timer B2
underflow. From the 2nd time on, the request is generated every
2n-th timer B2 underflow.
-When bits INV01 and INV00 are set to 11b (the ICTB2 counter
increments when the timer B2 underflow occurs at the falling edge
of the timer A1 reload control signal) and a setting value is n, the
timer B2 interrupt request is generated every 2n-th timer B2
underflow.
1 to 15
WO
Unimplemented.
Write 0. Read as undefined value.
−
NOTES:
1. Read-modify-write instructions cannot be used to set the ICTB2 register. Refer to Usage Notes for details.
2. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register while the TB2S bit is set to 0 (count stops). If the INV01
bit is set to 0, do not set the ICTB2 register when timer B2 underflows, regardless of the TB2S bit setting.
Figure 16.7
TB2SC Register, ICTB2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 185 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer B2 Register(1)
b15
b8 b7
b0
Symbol
TB2
Address
0355h - 0354h
Function
If a setting value is n, f1 is divided by n+1.
Timers A1, A2, and A4 start every time timer B2 underflows.
After Reset
Undefined
Setting Range
RW
0000h to FFFFh
RW
NOTE:
1. Read and write this register in 16-bit units.
Dead Time Timer(1, 2, 3)
b7
b0
Symbol
Address
After Reset
DTT
030Ch
Undefined
Function
Setting Range
RW
This one-shot timer is used to delay the timing for a turn-on signal
to be switched to its active level in order to prevent the upper and
lower arm short circuit.
If a setting value is n, the count source is counted n times after the
start trigger occurs, and then the timer stops.
01h to FFh
WO
NOTES:
1. Read-modify-write instructions cannot be used to set the DTT register. Refer to Usage Notes for details.
2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled). No dead time is
generated when the INV15 bit is set to 1 (dead time disabled).
3. The INV16 bit in the INVC1 register determines the start trigger of the DTT register. The INV12 bit determines the count source.
Figure 16.8
TB2 Register, DTT Register when Using Three-Phase Motor Control Timer Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 186 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Timer Ai, Ai1 Register(1, 2, 3, 4, 5) (i = 1, 2, 4)
b15
b8 b7
b0
Symbol
Address
After Reset
TA1, TA2, TA4
TA11, TA21, TA41
0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh
0303h - 0302h, 0305h - 0304h, 0307h - 0306h
Undefined
Undefined
Function
If a setting value is n, f1 is counted n times after a start trigger
occurs, and then the timer stops. Output signal level for each
phase changes when timers A1, A2, or A4 stop.
Setting Range
RW
0000h to FFFFh
WO
NOTES:
1. Write these registers in 16-bit units. Read-modify-write instructions cannot be used to set registers TAi and TAi1. Refer to
Usage Notes for details.
2. If the TAi or TAi1 register is set to 0000h, the counter does not start and the timer Ai interrupt is not generated.
3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), an output signal is switched to its active level with
delay simultaneously with the dead time timer underflow.
4. When the INV11 bit is set to 0 (Timers A11, A21, and A41 are not used (three-phase mode 0)), the contents of the TAi register
are transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to 1 (Timers A11, A21, and A41 are
used (three-phase mode 1)), the contents of the TAi1 register are transferred by the first timer Ai start trigger, and then contents
of the TAi register are transferred by the next timer Ai start trigger. Subsequently, the contents of registers TAi1 and TAi are
transferred alternately to the reload register by each timer Ai start trigger.
5. Do not set registers TAi and TAi1 in the timer B2 underflow timing.
Three-Phase Output Buffer Register i(1) (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
IDB0, IDB1
030Ah, 030Bh
XX11 1111b
Bit Symbol
Bit Name
Function
RW
DUi
Upper arm (U-phase)
output buffer i
Set output levels of the three-phase output shift
registers. The set value is reflected in each
turn-on signal as follows:
RW
DUBi
Lower arm (U-phase)
output buffer i
0: Active (ON)
1: Inactive (OFF)
RW
DVi
Upper arm (V-phase)
output buffer i
When read, the contents of the three-phase
output shift registers are returned.
RW
DVBi
Lower arm (V-phase)
output buffer i
RW
DWi
Upper arm (W-phase)
output buffer i
RW
DWBi
Lower arm (W-phase)
output buffer i
RW
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
−
NOTE:
1. When values are written to registers IDB0 and IDB1, these values are transferred to the three-phase output shift registers by a
transfer trigger. The value written in the IDB0 register becomes the initial output level of each phase when the transfer trigger occurs.
The value written in the IDB1 register becomes the next output signal level when the falling edge of the timer A1, A2 and A4 one-shot
pulses is detected.
Figure 16.9
TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 187 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
0340h
Bit Symbol
Figure 16.10
Table 16.2
After Reset
00h
Bit Name
Function
RW
TA0S
Timer A0 count start bit
0: Count stops
1: Count starts
RW
TA1S
Timer A1 count start bit
0: Count stops
1: Count starts
RW
TA2S
Timer A2 count start bit
0: Count stops
1: Count starts
RW
TA3S
Timer A3 count start bit
0: Count stops
1: Count starts
RW
TA4S
Timer A4 count start bit
0: Count stops
1: Count starts
RW
TB0S
Timer B0 count start bit
0: Count stops
1: Count starts
RW
TB1S
Timer B1 count start bit
0: Count stops
1: Count starts
RW
TB2S
Timer B2 count start bit
0: Count stops
1: Count starts
RW
TABSR Register when Using Three-Phase Motor Control Timer Function
Pin Settings when Using Three-Phase Control Timer Function(1)
Bit Setting
Port
Function
PSC Register
PSL1, PSL2,
Registers
PS1, PS2
Registers(2)
P7_2
V
PSC_2 = 1
PSL1_2 = 0
PS1_2 = 1
P7_3
V
−
PSL1_3 = 1
PS1_3 = 1
P7_4
W
−
PSL1_4 = 1
PS1_4 = 1
P7_5
W
−
PSL1_5 = 0
PS1_5 = 1
P8_0
U
−
PSL2_0 = 1
PS2_0 = 1
P8_1
U
−
PSL2_1 = 0
PS2_1 = 1
NOTES:
1. Set these registers after setting the INV02 bit in the INVC0 register to 1 (three-phase motor control timer
function used).
2. Set registers PS1 and PS2 after setting other registers.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 188 of 352
M32C/8A Group
16.1
16. Three-Phase Motor Control Timer Function
Triangular Wave Modulation Mode
In triangular wave modulation mode, one cycle of carrier waveform consists of two timer B2 underflow cycles.
A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. Two of
the timer Ai one-shot pulses are used to output one cycle of the PWM waveform. Table 16.3 lists specifications
and settings of triangular wave modulation mode.
Triangular wave modulation mode has two operation modes, three-phase mode 0 and three-phase mode 1.
TAi register is used in three-phase mode 0. Every time a timer B2 underflow interrupt occurs, the one-shot pulse
width is set in the TAi register.
Registers TAi and TAi1 are used in three-phase mode 1. Two different widths of the one-shot pulse can be set in
these registers. If a setting value of the ICTB2 register is n, a timer B2 underflow interrupt is generated every n-th
or every 2n-th timer B2 underflow to set values in registers TAi and TAi1.
Table 16.3
Specifications and Settings of Triangular Wave Modulation Mode
Item
INV06 bit
INV11 bit
Bits INV01 and
INV00
PWCON bit
ICTB2 register
Carrier wave cycle
Upper arm active
level output width
INV13 bit
Timer B2 interrupt
generation timing
Timer B2 reload
timing
Three-Phase Mode 0
0
0
00b or 01b
Three-Phase Mode 1
0
1
00b
10b
0
1
0 or 1
n
2 × (m + 1)
f1
2 × (m+1)
f1
1 × (m+1 - b +a )
k k
f1
−
Indicates the timer A1 reload control signal state.
Timer B2 underflow
Every nth timer B2
Every 2nth timer B2 underflow
underflow
Every odd-numbered Every even(2n × j - 1) timer B2
numbered (2n × j)
underflow
timer B2 underflow
Timer B2 underflow
• Timer B2 underflow (PWCON = 0)
• Timer B2 underflow at the rising edge of the timer A1 reload control
signal (PWCON = 1)
When a value is written to the IDBp register (p = 0, 1), the value is transferred only once by the
first transfer trigger.
1 ×(m+1 - a
2k-1+a2k)
f1
Transfer timing from
IDBp register to
three-phase output
shift register
Dead time timer start • At the falling edge of the one-shot pulse of timer A1, A2 and A4 (INV16 = 0)
timing
• At the rising edge of the three-phase output shift register (INV16 = 1)
−: Can be either 0 or 1.
m: Value of the TB2 register
a2k-1: Value set to the TAi register at odd-numbered time.
a2k: Value set to the TAi register at even-numbered time.
bk: Value set to the TAi1 register at k-th time.
ak: Value set to the TAi register at k-th time.
j: the number of interrupts
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
11b
Page 189 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Figure 16.11 shows an example of the triangular wave modulation operation (three-phase mode 0). Figures 16.12
and 16.13 show examples of the triangular wave modulation operation (three-phase mode 1).
Triangular Waveform as a Carrier Wave (Three-phase mode 0)
Carrier wave
Signal wave
TB2S bit in the
TABSR register
Timer B2
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the TB2IC register
Timer A4 start trigger signal (1)
TA4 register
a1
Reload register(1)
a1
a2
a3
a2
a1
a4
a3
a2
a5
a4
a3
a6
a5
a4
a7
a6
a5
a8
a7
a6
a9
a8
a7
a9
a8
Timer A4 one-shot pulse(1)
Upper arm (U-phase)
output signal(1)
Lower arm (U-phase)
output signal(1)
INV14 bit in
INVC1 register = 0
(Active Low)
INV14 bit in
INVC1 register = 1
(Active High)
DU0 = 1
Rewrite registers IDB0 and IDB1
DU0 = 1
DU1 = 0
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1
DUB0 = 0
DUB0 = 0
U-phase
U-phase
Dead time
U-phase
Dead time
U-phase
NOTE:
1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram.
The above applies under the following conditions:
- INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows)
INV02 bit = 1 (Three-phase control timer function used)
INV03 bit = 1 (Three-phase control timer output enabled)
INV06 bit = 0 (Triangular wave modulation mode)
- INVC1 register: INV10 bit = 0 (Timer B2 underflow)
INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0))
INV15 bit = 0 (Dead time enabled)
INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase))
- ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow)
The following shows examples to change PWM output levels.
- Default value of the timer: TA4 = a1 (The TA4 register is rewritten every time the timer B2 interrupt occurs.)
First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time TA4 = a5, fifth time TA4 = a6
- Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the sixth timer B2 interrupt.
Figure 16.11
Triangular Wave Modulation Operation (Three-Phase Mode 0)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
DU1 = 1
Page 190 of 352
DUB1 = 0
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV01 and INV00 = 10b)
Carrier wave
Signal wave
TB2S bit in the
TABSR register
Timer B2
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the TB2IC register
INV13 bit in the INVC1 register
Timer A4 start trigger signal (1)
TA4 register
a1
a2
a3
a4
a5
TA41 register
b1
b2
b3
b4
b5
Reload register(1)
b1
a1
b1
b2
a1
a2
b2
b3
a3
a2
b3
b4
a3
a4
b4
b5
a4
Timer A4 one-shot pulse (1)
Upper arm (U-phase)
output signal(1)
Lower arm (U-phase)
output signal(1)
INV14 bit in
INVC1 register = 0
(Active Low)
INV14 bit in
INVC1 register = 1
(Active High)
Rewrite registers IDB0 and IDB1
DU0 = 1
DU0 = 1
DU1 = 0
DU1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1
DUB0 = 0
DUB1 = 0
DUB0 = 0
U-phase
U-phase
U-phase
Dead time
Dead time
U-phase
NOTE:
1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram.
The above applies under the following conditions:
- INVC0 register: Bits INV01 and INV00 = 10b (ICTB2 counter is incremented by 1 at the rising edge of the timer A1 reload control signal)
INV02 bit = 1 (Three-phase control timer function used)
INV03 bit = 1 (Three-phase control timer output enabled)
INV06 bit = 0 (Triangular wave modulation mode)
- INVC1 register: INV10 bit = 0 (Timer B2 underflow)
INV11 bit = 1 (Timer A11, T21, A41 used (Three-phase mode 1))
INV15 bit = 0 (Dead time enabled)
INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase))
- ICTB2 register = 01h (First timer B2 interrupt occurs when timer B2 underflows for the first time, and the subsequent
interrupts occur every second timer B2 underflow.)
The following shows examples to change PWM output levels.
- Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.)
First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3
- Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.12
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 10b)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 191 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV0 and INV00 = 11b)
Carrier wave
Signal wave
TB2S bit in the
TABSR register
Timer B2
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the TB2IC register
INV13 bit in the INVC1 register
Timer A4 start trigger signal (1)
TA4 register
a1
a2
a3
a4
a5
TA41 register
b1
b2
b3
b4
b5
Reload register(1)
b1
a1
b1
b1
a1
b2
a2
b2
b2
b3
a2
a3
b3
b3
a3
b4
a4
b4
b4
b5
a4
Timer A4 one-shot pulse (1)
Upper arm (U-phase)
output signal(1)
Lower arm (U-phase)
output signal(1)
INV14 bit in
INVC1 register = 0
(Active Low)
Rewrite registers IDB0 and IDB1
DU0 = 1
DU0 = 1
DU1 = 0
DU1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB1 = 1
DUB0 = 0
DUB1 = 0
DUB0 = 0
U-phase
U-phase
Dead time
INV14 bit in
INVC1 register = 1
(Active High)
U-phase
Dead time
U-phase
NOTE:
1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram.
The above applies under the following conditions:
- INVC0 register: Bits INV01 and INV00 = 11b (ICTB2 counter is incremented by 1 at the falling edge of the timer A1 reload control signal)
INV02 bit = 1 (Three-phase control timer function used)
INV03 bit = 1 (Three-phase control timer output enabled)
INV06 bit = 0 (Triangular wave modulation mode)
- INVC1 register: INV10 bit = 0 (Timer B2 underflow)
INV11 bit = 1 (Timers A11, A21, A41 used (Three-phase mode 1))
INV15 bit = 0 (Dead time enabled)
INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase))
- ICTB2 register = 01h (Every second timer B2 underflow.)
(ICTB2 register = 02h, if INV01 bit = 0)
The following shows examples to change PWM output levels.
- Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.)
First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3
- Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.13
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 11b)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 192 of 352
M32C/8A Group
16.2
16. Three-Phase Motor Control Timer Function
Sawtooth Wave Modulation Mode
In sawtooth wave modulation mode, one cycle of carrier waveform consists of one timer B2 underflow cycle.
A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. One timer
Ai one-shot pulse is used to output one cycle of the PWM waveform. Table 16.4 lists specifications and settings of
sawtooth wave modulation mode.
Table 16.4
Specifications and Settings of Sawtooth Wave Modulation Mode
Item
INV06 bit
INV11 bit
Bits INV01 and INV00
PWCON bit
ICTB2 register
INV16 bit
Carrier wave cycle
Three-Phase Mode 0
1
0
00b or 01b
0
n
0
1 × (m + 1)
f1
Upper arm active level output
width
Timer B2 interrupt generation
timing
Timer B2 reload timing
Transfer timing from IDBp
register to three-phase output
shift register (p = 0, 1)
Dead time timer start timing
1 ×a
k
f1
Every n-th timer B2 underflow
Timer B2 underflow
Every time a transfer trigger occurs.
At the falling edge of the one-shot pulse of timer A1, A2 and A4
m: Value of the TB2 register
ak: Value set to the TAi register at k-th time.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 193 of 352
M32C/8A Group
16. Three-Phase Motor Control Timer Function
Figure 16.14 shows an example of the sawtooth wave modulation operation.
Sawtooth Waveform as a Carrier Wave
Carrier wave
Signal wave
TB2S bit in the
TABSR register
Timer B2
Set to 0 by an interrupt request acknowledgement or by program
IR bit in the TB2IC register
Timer A4 start trigger signal (1)
TA4 register
a1
a2
a1
a3
a2
a4
a3
a5
a4
a6
a5
a7
a6
a8
a7
Timer A4 one-shot pulse (1)
Upper arm (U-phase)
output signal(1)
Lower arm (U-phase)
output signal(1)
DU1 = 1
DU0 = 1 DU1 = 1
Rewrite registers IDB0 and IDB1
DU0 = 0
DUB1 = 1
DUB0 = 1 DUB1 = 1
DUB0 = 0
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
INV14 bit in
INVC1 register = 0
(Active Low)
INV14 bit in
INVC1 register = 1
(Active High)
U-phase
Dead time
U-phase
U-phase
Dead time
U-phase
NOTE:
1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram.
The above applies under the following conditions:
- INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows)
INV02 bit = 1 (Three-phase control timer function used)
INV03 bit = 1 (Three-phase control timer output enabled)
INV06 bit = 1 (Sawtooth wave modulation mode)
- INVC1 register: INV10 bit = 0 (Timer B2 underflow)
INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0))
INV15 bit = 0 (Dead time enabled)
INV16 bit = 0 (Falling edge of one-shot pulse of timers A1, A2, and A4)
- ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow)
- TB2SC register: PWCON bit = 0 (Timer B2 underflow)
The following shows examples to change PWM output levels.
- Default value of the timer: TA4 = a1 (The TA4 register is changed every time the timer B2 interrupt occurs.)
First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time = a5
- Default value of the registers IDB0 and IDB1: DU0 = 0, DUB0 = 1, DU1 = 1, and DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 1 at the fourth timer B2 interrupt.
Figure 16.14
Sawtooth Wave Modulation Operation
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 194 of 352
a8
M32C/8A Group
16.3
16. Three-Phase Motor Control Timer Function
Short Circuit Prevention Features
16.3.1
Prevention Against Upper/Lower Arm Short Circuit by Program Errors
This function prevents the upper and lower arm short circuit caused by setting the upper and lower output
buffers in registers IDB0 and IDB1 to active simultaneously by program errors and so on.
To use this function, set the INV04 bit in the INVC0 register to 1 (simultaneous turn-on signal output disabled).
If any pair of output buffers (U and U, V and V, or W and W) are simultaneously set to active, the INV05 bit
becomes 1 (detected), and the INV03 bit becomes 0 (three-phase motor control timer output disabled). Then,
the port outputs are forcibly cutoff and the pins are placed in the high-impedance states. When this prevention
function is performed, set the registers associated with the three-phase motor control timer function again.
16.3.2
Arm Short Circuit Prevention Using Dead Time Timer
The dead time timer prevents arm short circuit caused by turn-off delay of external upper and lower transistors.
To enable the dead time timer, set the INV15 bit in the INVC1 register to 0 (dead time enabled). The count
source for dead time timer (fDT) can be selected using the INV12 bit, and the dead time can be set using the
DTT register.
The dead time is obtained from the following formulas.
1
f1
2
f1
× n (INV12 = 0)
× n (INV12 = 1)
n: Value in the DTT register
Figure 16.15 shows an example of dead time timer operation.
U-phase output signal
(internal signal)
OFF
ON
OFF
U-phase output signal
(internal signal)
ON
OFF
ON
Dead timer
Dead time
Dead time timer
Figure 16.15
16.3.3
U-phase turn-on
signal output
OFF
ON
OFF
U-phase turn-on
signal output
ON
OFF
ON
Dead Time Timer Operation
Forced-Cutoff Function by the NMI Input
When an “L” signal is input to the NMI pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor
control timer output disabled), the port outputs are forcibly cutoff, and then the pins are placed in the highimpedance states. Also, the NMI interrupt occurs at the same time.
To enable the three-phase motor control timer function after the forced cutoff is performed, set the registers
associated with the three-phase motor control timer function again while an “H” signal is input to the NMI pin.
Forced-cutoff function by the NMI input can be used when the INV02 bit in the INVC0 register is set to 1
(three-phase motor control timer function used) and the INV03 bit is set to 1 (three-phase motor control timer
output enabled).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 195 of 352
M32C/8A Group
17. Serial Interfaces
17. Serial Interfaces
Serial interfaces consist of five channels (UART0 to UART4).
Each UARTi (i = 0 to 4) has an exclusive timer to generate the serial clock and operates independently of each other.
UARTi has the following modes.
• Clock synchronous mode
• Clock asynchronous mode
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (clock-divided synchronous function, GCI mode)
• Special mode 4 (SIM mode)
• Special mode 5 (bus conflict detect function, IE mode) (optional)(1)
NOTE:
1. Please contact a Renesas sales office for optional features.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 196 of 352
M32C/8A Group
17.1
17. Serial Interfaces
UART0 to UART4
Figure 17.1 shows a UART0 to UART4 block diagram. Figures 17.2 to 17.10 show the registers associated with
UART0 to UART4. Refer to the tables listing for register and pin settings in each mode.
RXDi
TXDi
CLK1 and CLK0
00
CKDIR
f1
01
0
f8
F2n(1)
10
UiBRG
register
1/(m+1)
1
CKPOL
CLKi input
CLKi
1/16
SMD2 to SMD0
100, 101, 110
1/16
100, 101, 110
1/2
0
1
Polarity
switching
Function Select
Register(2)
CLKi output
001
Receive
Transmit/
clock
receive
unit
Transmit
clock
Receive
control circuit
Transmit
control circuit
001
CKDIR
Polarity
switching
RTSi output
CTSi / RTSi
CTSi input
Function Select
(3)
CRD
Register
CRS
m = Setting value of the UiBRG register
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Select either Input/output port (CLKi input) or CLKi output in the Function Select Registers. (Refer to Programmable I/O Port.)
3. Select either Input/output port or RTSi output in the Function Select Registers. (Refer to Programmable I/O Port.)
0 IOPOL
RXDi
SP
1
STPS
0
1
001
101
PRYE 001
0
SP
PAR
1
SMD2 to SMD0
0
0
0
0
0
b8
100
101
110
0
0
UARTi receive shift register
100
b7
110
b6
b5
b4
b3
b2
b1
b0
D6
D5
D4
D3
D2
D1
D0
001
101
110
D8
D7
UiRB register
Logic inverse circuit + MSB/LSB conversion circuit
High-order bits of data bus
Low-order bits of data bus
Logic inverse circuit + MSB/LSB conversion circuit
D8
STPS
0
SP
SP
1
PRYE 001
0
PAR
1
100
101
110
D7
001
101
b8
b6
001
101
110
SMD2 to SMD0
i = 0 to 4
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: bits in the UiMR register
CLK1 and CLK0, CKPOL, CRD, and CRS: bits in the UiC0 register
UiERE: bit in the UiC1 register
Figure 17.1
UART0 to UART 4 Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 197 of 352
D5
D4
D3
D2
D1
D0
b5
b4
b3
b2
b1
b0
UiTB register
100
b7
110
D6
UARTi transmit shift register
Error signal
output circuit
UiERE
0
1
0
1
IOPOL
TXDi
M32C/8A Group
17. Serial Interfaces
UARTi transmit/receive mode register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0MR to U2MR
U3MR, U4MR
0368h, 02E8h, 0338h
0328h,02F8h
00h
00h
Bit Symbol
Bit Name
b2 b1 b0
SMD0
SMD1
Serial interface mode select bits
SMD2
Figure 17.2
0 0 0: Serial interface disabled
0 0 1: Clock synchronous mode
0 1 0: I2C mode
1 0 0: UART mode, 7-bit data length
1 0 1: UART mode, 8-bit data length
1 1 0: UART mode, 9-bit data length
Do not set to values other than the above
RW
RW
RW
RW
CKDIR
Clock select bit
0: Internal clock
1: External clock
RW
STPS
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
RW
PRY
Parity select bit
Enabled when PRYE=1
0: Odd parity
1: Even parity
RW
PRYE
Parity enable bit
0: Parity disabled
1: Parity enabled
RW
IOPOL
TXD, RXD input/output
polarity switch bit
0: Not inverted
1: Inverted
RW
U0MR to U4MR Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
Page 198 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Special Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
U0SMR to U2SMR
U3SMR, U4SMR
0367h, 02E7h, 0337h
0327h, 02F7h
00h
00h
Bit Symbol
Bit Name
Function
IICM
I2C mode select bit
0 : Other than I2C mode
1 : I2C mode
RW
ABC
Arbitration lost detect flag
control bit(1)
0: Updated per bit
1: Updated per byte
RW
BBS
Bus busy flag(1, 2)
0: Stop condition detected (bus is free)
1: Start condition detected (bus is busy)
RW
−
(b3)
Reserved bit
Set to 0
RW
ABSCS
Bus conflict detect
sampling clock select bit (3)
0: Rising edge of serial clock
1: Timer Aj underflow (j = 0, 3, 4) (4)
RW
ACSE
Auto clear function select
bit for transmit enable bit (3)
0: No auto clear function
1: Auto cleared when bus conflict occurs
RW
Transmit start condition
select bit(3)
0 : Not related to RXDi
1 : Synchronized with RXDi
RW
Clock division synchronous
bit(5,6)
0: External clock not divided
1: External clock divided by 2
RW
SSS
SCLKDIV
NOTES:
1. These bits are used in I 2C mode.
2. The BBS bit is set to 0 by writing a 0. Writing a 1 has no effect.
3. These bits are used in IE mode.
4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal,
UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal,
UART4: Timer A4 underflow signal.
5. The SCLKDIV bit is used in GCI mode.
6. Refer to the note for the SU1HIM bit in the UiSMR2 register.
Figure 17.3
U0SMR to U4SMR Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 199 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Special Mode Register 2 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR2 to U2SMR2
U3SMR2, U4SMR2
0366h, 02E6h, 0336h
0326h, 02F6h
00h
00h
Bit Symbol
Bit Name
Function
RW
IICM2
I2C mode select bit 2
0: ACK/NACK interrupt used
1: Transmit/receive interrupt used
RW
CSC
Clock synchronous bit(1)
0: Not clock synchronized
1: Clock synchronized
RW
SWC
SCL wait output bit(2)
0: No wait state/release wait states
1:SCLi pin is held "L" after receiving 8th bit.
RW
ALS
SDA output auto stop bit (1)
When arbitration lost is detected,
0: SDAi output not stopped
1: SDAi output stopped
RW
STC
UARTi auto initialization bit(2)
When start condition is detected,
0: UARTi not initialized
1: UARTi initialized
RW
SWC2
SCL wait output bit 2 (1)
0: Serial clock output from SCLi pin
1: SCLi pin is held "L"
RW
SDHI
SDA output stop bit(2)
0: Output data
1: Output stopped (Hi-impedance state)
RW
External clock synchronous
enable bit(3)
0: Not synchronized with external clock
1: Synchronized with external clock
RW
SU1HIM
NOTES:
1. These bits are used when the MCU is in master mode in I 2C mode.
2. These bits are used when the MCU is in slave mode in I 2C mode.
3. The external clock synchronous function can be selected with the combination of the SU1HIM bit and the SCLKDIV bit in the
UiSMR register. The SU1HIM bit is used in GCI mode.
Figure 17.4
SCLKDIV Bit in the
UiSMR register
SU1HIM Bit in the
UiSMR2 register
0
0
Not synchronized
0
1
Same frequency as external clock
1
0 or 1
U0SMR2 to U4SMR2 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 200 of 352
External Clock Synchronous Function Select
External clock divided by 2
M32C/8A Group
17. Serial Interfaces
UARTi Special Mode Register 3 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR3 to U2SMR3
U3SMR3, U4SMR3
0365h, 02E5h, 0335h
0325h, 02F5h
00h
00h
Bit Symbol
Bit Name
RW
Function
SS function enable bit (1)
0: SS function disabled
1: SS function enabled (2)
RW
CKPH
Clock phase set bit (1)
0: No Clock delay
1: Clock delay
RW
DINC
Serial input pin set bit (1)
0: Pins TXDi and RXDi selected (master mode)
1: Pins STXDi and SRXDi selected (slave mode)
RW
NODC
Clock output select bit
0: CLKi is CMOS output
1: CLKi is N-channel open drain output
RW
Mode error flag (1)
0: No mode error
1: Mode error occurred (3)
RW
SSE
ERR
SDAi output is delayed by the following cycles.
DL0
DL1
b7 b6 b5
SDAi digital delay set bits (4, 5)
DL2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: No delay
1: 1-to-2 cycles
0: 2-to-3 cycles
1: 3-to-4 cycles
0: 4-to-5 cycles
1: 5-to-6 cycles
0: 6-to-7 cycles
1: 7-to-8 cycles
of BRG
of BRG
of BRG
of BRG
of BRG
of BRG
of BRG
count
count
count
count
count
count
count
source
source
source
source
source
source
source
RW
RW
RW
NOTES:
1. These bits are used in special mode 2.
2. When the SS pin is set to 1, set the CRD bit in the UiC0 register to 1 ( CTS function disabled).
3. The ERR bit is set to 0 by writing a 0. Writing a 1 has no effect.
4. Digital delay is added to a SDAi output using bits DL2 to DL0 in I 2C mode. Set them to 000b (no delay) in other than I 2C mode.
5. When the external clock is selected, SDAi output is delayed by approximately 100 ns in addition.
Figure 17.5
U0SMR3 to U4SMR3 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 201 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Special Mode Register 4 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR4 to U2SMR4
U3SMR4, U4SMR4
0364h, 02E4h, 0334h
0324h, 02F4h
00h
00h
Bit Name
STAREQ
Start condition generate bit(1, 3)
0: Clear
1: Start
RW
Restart condition generate
bit(1, 3)
0: Clear
1: Start
RW
STPREQ
Stop condition generate bit(1, 3)
0: Clear
1: Start
RW
STSPSEL
SCL, SDA output select bit (1)
0: Serial input/output circuit selected
1: Start/stop condition generation circuit
selected (4)
RW
ACKD
ACK data bit(2)
0: ACK
1: NACK
RW
ACKC
ACK data output enable bit(2)
0: Serial data output
1: ACK data output
RW
SCLHI
SCL output stop bit(1)
When the bus is free,
0: SCLi output not stopped
1: SCLi output stopped
RW
SWC9
SCL wait output bit 3 (1)
0: No wait state/release wait state
1: SCLi pin is held "L" after receiving 9th bit
RW
RSTAREQ
Function
RW
Bit Symbol
NOTES:
1. These bits are used when the MCU is in master mode in I 2C mode.
2. These bits are used when the MCU is in slave mode in I 2C mode.
3. When each condition generation is completed, the corresponding bit becomes 0. When a condition generation is failed, the bit
remains as 1.
4. Set the STSPSEL bit to 1 (start/stop condition generation circuit selected) after setting the STAREQ bit, RSTAREQ bit, or
STPREQ bit to 1 (start).
Figure 17.6
U0SMR4 to U4SMR4 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 202 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Transmit/Receive Control Register 0 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0C0 to U2C0
U3C0, U4C0
036Ch, 02ECh, 033Ch
032Ch, 02FCh
0000 1000b
0000 1000b
Bit Symbol
Bit Name
Function
b1 b0
CLK0
UiBRG count source select
bits(1)
CLK1
0 0: f1 selected
0 1: f8 selected
1 0: f2n selected (2)
1 1: Do not set to this value
RW
RW
RW
CRS
CTS function select bit
Enabled when CRD = 0
0: CTS function selected
1: CTS function not selected
RW
TXEPT
Transmit shift register
empty flag
0: Data in the transmit shift register
(during transmit operation)
1: No data in the transmit shift register
(transmit operation is completed)
RO
CRD
CTS function disable bit
0: CTS function enabled
1: CTS function disabled
RW
NCH
Data output select bit 3)
0: TXDi/SDAi and SCLi are CMOS output ports
1: TXDi/SDAi and SCLi are N-channel open
drain output ports
RW
CKPOL
CLK polarity select bit
0: Transmit data output at the falling edge and
receive data input at the rising edge of the
serial clock
1: Transmit data output at the rising edge and
receive data input at the falling edge of the
serial clock
RW
UFORM
Bit order select bit (4)
0 : LSB first
1 : MSB first
RW
NOTES:
1. Set the UiBRG register after setting bits CLK1 and CLK0.
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
CST bit in the TCSPR register to 1 before setting bits CLK1 and CLK0 to 10b.
3. P7_0/TXD2, P7_1/SCL2 are N-channel open drain output ports. They cannot be selected as CMOS output ports.
4. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 101b
(UART mode, 8-bit data length). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I 2C mode), or to 0 when bits
SMD2 to SMD0 are set to 100b (UART mode, 7-bit data length) or 110b (UART mode, 9-bit data length).
Figure 17.7
U0C0 to U4C0 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 203 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Baud Rate Register(1, 2) (i = 0 to 4)
b0
b7
Symbol
U0BRG to U2BRG
U3BRG, U4BRG
Address
0369h, 02E9h, 0339h
0329h, 02F9h
After Reset
Undefined
Undefined
Function
Setting Range
RW
00h to FFh
WO
If the setting value is n,
the UiBRG register divides a count source by n+1
NOTES:
1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details.
2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
U0C1 to U2C1
U3C1, U4C1
036Dh, 02EDh, 033Dh
032Dh, 02FDh
0000 0010b
0000 0010b
Bit Symbol
Bit Name
Function
RW
TE
Transmit enable bit
0: Transmit operation disabled
1: Transmit operation enabled
RW
TI
UiTB register empty flag
0: Data in the UiTB register
1: No data in the UiTB register
RO
RE
Receive enable bit
0: Receive operation disabled
1: Receive operation enabled
RW
RI
Receive complete flag
0: No Data in the UiRB register
1: Data in the UiRB register
RO
UARTi transmit interrupt source
select bit
0: No data in the UiTB register (TI = 1)
1: Transmit operation is completed (TXEPT = 1)
RW
UiRRM
Continuous receive mode
enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enabled (3)
RW
UiLCH
Data logic select bit (1)
0: Not inverted
1: Inverted
RW
Special mode 3
Clock-divided synchronous
stop bit
0: Synchronization stopped
1: Synchronization started
Special mode 4
Error signal output enable bit (2)
0: Not output
1: Output
UilRS
SCLKSTPB
UiERE
RW
NOTES:
1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b
(UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are
set to 010b (I2C mode) or 110b (UART mode, 9-bit data length).
2. Set bits SMD2 to SMD0 before setting the UiERE bit.
3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
Figure 17.8
U0BRG to U4BRG Registers, U0C1 to U4C1 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 204 of 352
M32C/8A Group
17. Serial Interfaces
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
031Fh
Bit Symbol
Bit Name
After Reset
00h
Function
IFSR0
INT0 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR1
INT1 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR2
INT2 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR3
INT3 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR4
INT4 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR5
INT5 interrupt polarity
select bit(1)
0: One edge
1: Both edges
RW
IFSR6
UART0, UART3
interrupt source select bit
0: UART3 bus conflict, start condition detection,
stop condition detection
1: UART0 bus conflict, start condition detection,
stop condition detection
RW
IFSR7
UART1, UART4
interrupt source select bit
0: UART4 bus conflict, start condition detection,
stop condition detection
1: UART1 bus conflict, start condition detection,
stop condition detection
RW
NOTE:
1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the
corresponding INTilC register to 0 (falling edge).
Figure 17.9
IFSR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 205 of 352
M32C/8A Group
17. Serial Interfaces
UARTi Transmit Buffer Register (1) (i = 0 to 4)
b15
b8 b7
b0
Symbol
Address
After Reset
U0TB to U2TB
U3TB, U4TB
036Bh - 036Ah, 02EBh - 02EAh, 033Bh - 033Ah
032Bh - 032Ah, 02FBh - 02FAh
Undefined
Undefined
Bit Symbol
−
(b7-b0)
−
(b8)
−
(b15-b9)
Function
RW
Transmit data (D7 to D0)
WO
Transmit data (D8)
WO
Unimplemented.
Write 0. Read as undefined value.
−
NOTE:
1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.
UARTi Receive Buffer Register (i = 0 to 4)
b15
b8 b7
b0
Symbol
Address
After Reset
U0RB to U2RB
U3RB, U4RB
036Fh - 036Eh, 02EFh - 02EEh, 033Fh - 033Eh
032Fh - 032Eh, 02FFh - 02FEh
Undefined
Undefined
Bit Symbol
−
(b7-b0)
−
(b8)
−
(b10-b9)
Function
Bit Name
RW
Received data (D7 to D0)
RO
Received data (D8)
RO
Unimplemented.
Write 0. Read as undefined value.
−
ABT
Arbitration lost detect flag (1)
0: Not detected (won)
1: Detected (lost)
RW
OER
Overrun error flag(2)
0: No overrun error
1: Overrun error
RO
FER
Framing error flag(2, 3)
0: No framing error
1: Framing error
RO
PER
Parity error flag(2, 3)
0: No parity error
1: Parity error
RO
SUM
Error sum flag(2, 3)
0 No error occurred
1: Error occurred
RO
NOTES:
1. Only a 0 can be written to the ABT bit.
2. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to
0 (receive operation disabled), bits OER, FER, PER and SUM become 0.
When all of bits OER, FER and PER become 0, the SUM bit also becomes 0.
Bits FER and PER become 0 by reading the low-order byte in the UiRB register.
3. Bits FER, PER and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode)
or 010b (I2C mode). A read from these bits returns undefined value.
Figure 17.10
U0TB to U4TB Registers, U0RB to U4RB Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 206 of 352
M32C/8A Group
17.1.1
17. Serial Interfaces
Clock Synchronous Mode
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used
for transmit and receive control.
Table 17.1 lists specifications of clock synchronous mode. Table 17.2 lists pin settings. Figure 17.11 shows
register settings. Figure 17.12 shows an example of a transmit and receive operation when an internal clock is
selected. Figure 17.13 shows an example of a receive operation when an external clock is selected.
Table 17.1
Clock Synchronous Mode Specifications
Item
Specification
Data format
Data length: 8 bits long
Serial clock
Internal clock or external clock can be selected by the CKDIR bit in the UiMR register
(i = 0 to 4)
Baud rate
• When the CKDIR bit is set to 0 (internal clock):
fj / (2 (m + 1)
fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)
• When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin
Transmit/receive control
Selectable among the CTS function, RTS function, or CTS/RTS function disabled
Transmit and receive
start condition
Internal clock is selected:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• “L” signal is applied to the CTSi pin when the CTS function is used
External clock is selected(2):
• Set the TE bit to 1
• The TI bit is 0
• Set the RE bit to 1
• The RI bit in the UiC1 register is 0 when the RTS function is used
When above 4 conditions are met, RTSi pin outputs “L”
If transmit-only operation is performed, the RE bit setting is not required in both cases.
Interrupt request
generation timing
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when data transmit operation from the UARTi transmit shift register is completed
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
Overrun error(3)
Overrun error occurs when the 7th bit of the next data is received before
reading the UiRB register
Selectable function
• CLK polarity
Transmit data output timing and receive data input timing can be selected
• LSB first or MSB first
Data is transmitted and received from either bit 0 or bit 7
• Serial data logic inverse
Transmit and receive data are logically inverted
• Continuous receive mode
The TI bit becomes 0 by reading the UiRB register
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 207 of 352
M32C/8A Group
Table 17.2
17. Serial Interfaces
Pin Settings in Clock Synchronous Mode
Bit Setting
Port
P6_0
P6_1
P6_2
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
CTS0 input
PD6_0 = 0
−
−
PS0_0 = 0
RTS0 output
−
−
PSL0_0 = 0
PS0_0 = 1
CLK0 input
PD6_1 = 0
−
−
PS0_1 = 0
CLK0 output
−
−
PSL0_1 = 0
PS0_1 = 1
RXD0 input
PD6_2 = 0
−
−
PS0_2 = 0
−
−
PSL0_3 = 0
PS0_3 = 1
output(4)
P6_3
TXD0
P6_4
CTS1 input
PD6_4 = 0
−
−
PS0_4 = 0
RTS1 output
−
−
PSL0_4 = 0
PS0_4 = 1
CLK1 input
PD6_5 = 0
−
−
PS0_5 = 0
CLK1 output
−
−
PSL0_5 = 0
PS0_5 = 1
RXD1 input
PD6_6 = 0
−
−
PS0_6 = 0
−
−
PSL0_7 = 0
PS0_7 = 1
P6_5
P6_6
TXD1
output(4)
P7_0(3)
TXD2
output(4)
−
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
P7_1
RXD2 input
PD7_1 = 0
−
−
PS1_1 = 0
P7_2
CLK2 input
PD7_2 = 0
−
−
PS1_2 = 0
CLK2 output
−
PSC_2 = 0
PSL1_2 = 0
PS1_2 = 1
P7_3
CTS2 input
PD7_3 = 0
−
−
PS1_3 = 0
RTS2 output
−
PSC_3 = 0
PSL1_3 = 0
PS1_3 = 1
P9_0
CLK3 input
PD9_0 = 0
−
−
PS3_0 = 0
CLK3 output
−
−
PSL3_0 = 0
PS3_0 = 1
RXD3 input
PD9_1 = 0
−
−
PS3_1 = 0
−
−
PSL3_2 = 0
PS3_2 = 1
CTS3 input
PD9_3 = 0
−
PSL3_3 = 0
PS3_3 = 0
RTS3 output
−
−
−
PS3_3 = 1
CTS4 input
PD9_4 = 0
−
PSL3_4 = 0
PS3_4 = 0
RTS4 output
-
−
−
PS3_4 = 1
P9_5
CLK4 input
PD9_5 = 0
−
PSL3_5 = 0
PS3_5 = 0
CLK4 output
−
−
−
PS3_5 = 1
P9_6
TXD4 output(4) −
−
−
PS3_6 = 1
P9_7
RXD4 input
−
−
PS3_7 = 0
P6_7
P9_1
P9_2
P9_3
P9_4
TXD3
output(4)
PD9_7 = 0
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 is an N-channel open drain output port.
4. After UARTi (i = 0 to 4) operating mode is selected and the pin function is set in the Function Select Registers,
the TXDi pin outputs an “H” signal until a transmit operation starts (the TXDi pin is in a high-impedance state
when N-channel open drain output is selected).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 208 of 352
M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit
bits 7 to 4 = 0000b
Interrupt disabled
Clock synchronous mode
Clock select bit
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register= 00h
UiC0 register: bits CLK1 and CLK0
CRS bit
CRD bit
NCH bit
CKPOL bit
UFORM bit
UiBRG register count source select bits
CTS function select bit
CTS function disable bit
Data output select bit
CLK polarity select bit
Bit order select bit
<When an internal clock is used>
fj
2(m + 1)
UiBRG register = m
m = 00h to FFh
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit
UiLCH bit
Bit 7 = 0
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt source select bit
Continuous receive mode enable bit (2)
Data logic select bit
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
Transmit interrupt priority level select bit
Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0
IR bit= 0
Receive interrupt priority level select bit
Interrupt not requested
Baud rate =
fj: f1, f8, f2n (1)
Pin settings in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
Interrupt enabled
Transmit operation enabled
Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to the UiTB register.
Read the UiRB register when a receive operation is completed.
i = 0 to 4
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. The UiRRM bit can be set to 1 (continuous receive mode used), only when the CKDIR bit in the UiMR register is set to 1
(external clock) and RTS function is disabled.
Figure 17.11
Register Settings in Clock Synchronous Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 209 of 352
M32C/8A Group
17. Serial Interfaces
TC
Internal clock
TE bit in the
UiC1 register
1
TI bit in the UiC1
register
1
0
0
“H”
CTSi Input
“L”
Write data to the UiTB register
Transfer data from UiTB register
to UARTi transmit shift register
TCLK
Communication stops
because CTSi = "H"
“H”
CLKi output
Communication stops because
TE bit = 0
“L”
“H”
TXDi output
“L”
TXEP bit in the
UiC0 register
1
IR bit in the
SiTIC register
1
0
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5
Set to 0 by an interrupt request acknowledgement or by program
0
“H”
RXDi input
D0 D1 D2 D3 D4 D5 D6
“L”
RI bit in the
UiC1 register
1
IR bit in the SiRIC
register
1
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5
Transfer data from UARTi
receive shift register to UiRB
register
0
A read from the UiRB register
0
Set to 0 by an interrupt request acknowlegement or by program
TC = TCLK =
i = 0 to 4
2(m + 1)
fj
fj = f1, f8, f2n (1)
The above applies under the following conditions:
m = Setting value of the UiBRG register
- UiMR register: CKDIR bit = 0 (internal clock)
(00h to FFh)
- UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used)
CKPOL bit = 0 (transmit data output at the falling edge of the serial clock)
- UiC1 register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register)
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.12
Transmit and Receive Operations when Internal Clock is Selected
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 210 of 352
M32C/8A Group
17. Serial Interfaces
RE bit in the
UiC1 register
1
TE bit in the
UiC1 register
1
TI bit in the UiC1
register
1
0
0
0
“H”
RTSi output
Write dummy data to UiTB register
Transfer data from UiTB register
to UARTi transmit shift register
“L”
1
fEXT
Becomes "L" by reading UiRB register
“H”
CLKi input(1)
“L”
“H”
RXDi input
“L”
RI bit in the
UiC1 register
1
IR bit in the SiRIC
register
1
OER bit in the
UiRB register
1
D0 D1 D2 D3 D4 D5 D6
Transfer data from UARTi
receive shift register to UiRB
register
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6
A read from UiRB register
0
0
Set to 0 by an interrupt request acknowledgement or by program
0
i = 0 to 4
fEXT = external clock frequency
The above applies under the following conditions:
- UiMR register: CKDIR bit = 1 (external clock)
- UiC0 reigster: CRD bit = 1 (CTS function disabled)
CKPOL bit = 0 (receive data input at the rising edge of the serial clock)
NOTE:
1. Satisfy the following conditions, while the CLKi pin input is "H" before the data receive operation.
- UiC1 register: TE bit = 1 (transmit operation enabled)
RE bit = 1 (receive operation enabled)
- Write dummy data to the UiTB register
Figure 17.13
Receive Operations when External Clock is Selected
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 211 of 352
D7
M32C/8A Group
17. Serial Interfaces
17.1.1.1 CLK Polarity
As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial
clock.
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the
falling edge and receive data input at the rising edge of the serial clock )
CLKi
TXDi
RXDi
"H"
(note 1)
"L"
"H"
"L"
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
at the falling edge of the serial clock)
CLKi
TXDi
RXDi
"H"
(note 2)
"L"
"H"
"L"
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions:
- UFORM bit in the UiC0 register is set to 0 (LSB first)
- UiLCH bit in the UiC1 register is set to 0 (not inverted).
NOTES:
1. The CLKi pin output level is "H" when no transmit and receive operation is in progress.
2. The CLKi pin output level is "L" when no transmit and receive operation is in progress.
Figure 17.14
Serial Clock Polarity
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 212 of 352
M32C/8A Group
17. Serial Interfaces
17.1.1.2 LSB First or MSB First
As shown in figure 17.15, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
CLKi
TXDi
RXDi
"H"
"L"
"H"
"L"
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UFORM bit is set to 1 (MSB first)
CLKi
TXDi
RXDi
"H"
"L"
"H"
"L"
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
"H"
"L"
The above applies under the following conditions:
- CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge)
- UiLCH bit in the UiC1 register is set to 0 (not inverted).
Figure 17.15
Bit Order (8-Bit Data Length)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 213 of 352
M32C/8A Group
17. Serial Interfaces
17.1.1.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted
for transmit operation. A read from the UiRB register returns the inverted logic of receive data. Figure 17.16
shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
Serial clock
"H"
"L"
TXDi "H"
(not inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
RXDi "H"
(not inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit is set to 1 (inverted)
Serial clock
"H"
"L"
TXDi "H"
(inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
RXDi "H"
(inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions:
- CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge)
- UFORM bit in the UiC0 register is set to 0 (LSB first).
Figure 17.16
Serial Data Logic Inverse
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 214 of 352
M32C/8A Group
17. Serial Interfaces
17.1.1.4 Continuous Receive Mode
Continuous receive mode can be used when all of the following conditions are met.
• External clock is selected (the CKDIR bit in the UiMR register (i = 0 to 4) is set to 1)
• RTS function is disabled (RTSi pin is not selected in the Function Select Register)
When the UiRRM bit in the UiC1 register is set to 1 (continuous receive mode enabled), the TI bit in the UiC1
register becomes 0 (data in the UiTB register) by reading the UiRB register. Do not set dummy data to the
UiTB register if the UiRRM bit is set to 1.
17.1.1.5 CTS/RTS Function
• CTS Function
Transmit and receive operation is controlled by using the input signal to the CTSi pin (i = 0 to 4). To use
the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to
0 (CTS function enabled), and the CRS bit to 0 (CTS function selected).
With the CTS function used, the transmit and receive operation starts when all the following conditions are
met and an “L” signal is applied to the CTSi pin.
-The TE bit in the UiC1 register is set to 1 (transmit operation enabled)
-The TI bit in the UiC1 register is 0 (data in the UiTB register)
-The RE bit in the UiC1 register is set to 1 (receive operation enabled)
(If transmit-only operation is performed, the RE bit setting is not required)
When a high-level (“H”) signal is applied to the CTSi pin during transmitting and receiving, the transmit
and receive operation is disabled after the transmit and receive operation in progress is completed.
• RTS Function
The MCU can inform the external device that it is ready for a transmit and receive operation by using the
output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select
Register.
With the RTS function used, the RTSi pin outputs an “L” signal when all the following conditions are met,
and outputs an “H” when the serial clock is input to the CLKi pin.
-The RI bit in the UiC1 register is 0 (no data in the UiRB register)
-The TE bit is set to 1 (transmit operation enabled)
-The RE bit is set to 1 (receive operation enabled)
(If transmit-only operation is performed, the RE bit setting is not required)
-The TI bit is 0 (data in the UiTB register)
17.1.1.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in clock synchronous mode.
(1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0
(receive operation disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous mode).
(4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 215 of 352
M32C/8A Group
17.1.2
17. Serial Interfaces
Clock Asynchronous (UART) Mode
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.3 lists specifications of
UART mode. Table 17.4 lists pin settings. Figure 17.17 shows register settings. Figure 17.18 shows an
example of a transmit operation. Figure 17.19 shows an example of a receive operation.
Table 17.3
UART Mode Specifications
Item
Specification
Data format
Baud rate
• Data length: selectable among 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selectable among odd, even, or none
• Stop bit: selectable from 1 bit or 2 bits long
fj / (16 (m + 1))
fj = f1, f8, f2n(1), fEXT
m: setting value of the UiBRG register (00h to FFh)
fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is
set to 1 (external clock)
Transmit/receive control
Selectable among CTS function, RTS function or CTS/RTS function disabled
Transmit start condition
To start transmit operation, all of the following must be met:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
Receive start condition
To start receive operation, all of the following must be met:
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The RI bit is 1 (no data in UiRB register) when RTS function is used.
When the above two conditions are met, the RTSi pin output an “L” signal.
• The start bit is detected
Interrupt request generation
timing
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when the final stop bit is output from the UARTi transmit shift register
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
• Overrun error(2)
Overrun error occurs when the preceding bit of the final stop bit of the next data (the
first stop bit when selecting 2 stop bits) is received before reading the UiRB register
• Framing error
Framing error occurs when the number of the stop bits set by the STPS bit in
the UiMR register is not detected
• Parity error
Parity error occurs when parity is enabled and the received data does not have
the correct even or odd parity set by the PRY bit in the UiMR register.
• Error sum flag
Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs
Selectable function
• LSB first or MSB first
Data is transmitted or received from either bit 0 or bit 7
• Serial data logic inverse
Transmit and receive data are logically inverted. The start bit and stop bit are
not inverted
• TXD and RXD I/O polarity inverse
The level output from the TXD pin and the level applied to the RXD pin are
inverted. All the data including the start bit and stop bit are inverted.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 216 of 352
M32C/8A Group
Table 17.4
17. Serial Interfaces
Pin Settings in UART Mode
Bit Setting
Port
P6_0
P6_1
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
CTS0 input
PD6_0 = 0
−
−
PS0_0 = 0
RTS0 output
−
−
PSL0_0 = 0
PS0_0 = 1
CLK0 input
PD6_1 = 0
−
−
PS0_1 = 0
PD6_2 = 0
−
−
PS0_2 = 0
P6_2
RXD0 input
P6_3
TXD0 output(4) −
−
PSL0_3 = 0
PS0_3 = 1
P6_4
CTS1 input
PD6_4 = 0
−
−
PS0_4 = 0
RTS1 output
−
−
PSL0_4 = 0
PS0_4 = 1
P6_5
CLK1 input
PD6_5 = 0
−
−
PS0_5 = 0
P6_6
RXD1 input
P6_7
P7_0(3)
P7_1
PD6_6 = 0
−
−
PS0_6 = 0
TXD1
output(4)
−
−
PSL0_7 = 0
PS0_7 = 1
TXD2
output(4)
−
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
PD7_1 = 0
−
−
PS1_1 = 0
−
PS1_2 = 0
RXD2 input
P7_2
CLK2 input
PD7_2 = 0
−
P7_3
CTS2 input
PD7_3 = 0
−
−
PS1_3 = 0
RTS2 output
−
PSC_3 = 0
PSL1_3 = 0
PS1_3 = 1
P9_0
CLK3 input
PD9_0 = 0
−
−
PS3_0 = 0
P9_1
RXD3 input
PD9_1 = 0
−
−
PS3_1 = 0
−
−
PSL3_2 = 0
PS3_2 = 1
output(4)
P9_2
TXD3
P9_3
CTS3 input
PD9_3 = 0
−
PSL3_3 = 0
PS3_3 = 0
RTS3 output
−
−
−
PS3_3 = 1
CTS4 input
PD9_4 = 0
−
PSL3_4 = 0
PS3_4 = 0
RTS4 output
−
−
−
PS3_4 = 1
P9_5
CLK4 input
PD9_5 = 0
−
PSL3_5 = 0
PS3_5 = 0
P9_6
TXD4 output(4) −
−
−
PS3_6 = 1
P9_7
RXD4 input
−
−
PS3_7 = 0
P9_4
PD9_7 = 0
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 is an N-channel open drain output port.
4. After UARTi (i = 0 to 4) operating mode is selected and the pin function is set in the Function Select Registers,
the TXDi pin outputs an “H” signal until a transmit operation starts (the TXDi pin is in a high-impedance state
when N-channel open drain output is selected).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 217 of 352
M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0
CKDIR bit
STPS bit
PRY bit
PRYE bit
IOPOL bit
Interrupt disabled
UART mode(1) select bits
Clock select bit
Stop bit length select bit
Parity select bit
Parity enable bit
TXD, RXD I/O polarity switch bit
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0
CRS bit
CRD bit
NCH bit
CKPOL bit = 0
UFORM bit
UiBRG register = m
UiBRG register count source select bits
CTS function select bit
CTS function disable bit
Data output select bit
Bit order select bit (2)
m = 00h to FFh
Baud rate =
fj
16(m+1)
fj = f1, f8, f2n (3), fEXT
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit = 0
UiLCH bit
bit 7 = 0
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt request source select bit
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
Transmit interrupt priority level select bits
Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Receive interrupt priority level select bits
Interrupt not requested
Data logic select bit (4)
Pin settings in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
Interrupt enabled
Transmit operation enabled
Receive operation enabled
End itinial setting
Transmit operation starts by writing data to the UiTB register
Receive operation starts when the start bit is detected.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
fEXT: clock input to the CLKi pin when the external clock is selected
NOTES:
1. Set bits SMD2 to SMD0 to the following: 100b (7 bits long), 101b (8 bits long), 110b (9 bits long).
2. A bit order can be selected when 8-bit data length is selected. Set to 0 when 7-bit or 9-bit data length is selected.
3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
4. Whether data logic is inverted or not can be selected when 7-bit or 8-bit data length is selected. Set to 0 when 9-bit data
length is selected.
Figure 17.17
Register Settings in UART Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 218 of 352
M32C/8A Group
17. Serial Interfaces
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
TC
Internal transmit
clock
TE bit in the
UiC1 register
1
TI bit in the UiC1
register
1
0
Write data to UiTB register
0
Transfer data from UiTB register to UARTi transmit shift register
“H”
CTSi input
“L”
“H”
TXDi output
“L”
TXEPT bit in the
UiC0 register
1
IR bit in the
SiTIC register
1
Start bit
Transmission stops because TE = 0
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0
Parity bit
0
0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used)
- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed)
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
TC
Internal transmit
clock
TE bit in the
UiC1 register
1
TI bit in the UiC1
register
1
Write data to UiTB register
0
0
“H”
TXDi output
“L”
TXEPT bit in the
UiC0 register
1
IR bit in the
SiTIC register
1
Transfer data from UiTB register to UARTi transmit shift register
Start bit
Stop bits
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
0
0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits)
- UiC0 register: CRD bit = 1 (CTS function disabled)
- UiC1 register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register)
TC =
16(m + 1)
fj
fj: f1, f8, f2n (1), fEXT
fEXT: clock input to the CLKi pin when the external clock is selected
m: setting value of the UiBRG register (00h to FFh)
i = 0 to 4
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.18
Transmit Operation in UART Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 219 of 352
ST D0
M32C/8A Group
17. Serial Interfaces
Example of the receive operation timing (1 stop bit)
(note 1)
“H”
RXDi input
“L”
Start bit
Verify the level
(note 2)
D0
Stop bit
Input the
receive data
Clock divided by UiBRG
register
Internal receive clock
IR bit in the SiRIC register
RI bit in the UiC1 register
1
0
This bit becomes 1 when the data is transferred
from UARTi receive shift register to UiRB register
1
0
“H”
RTSi output
Set to 0 by an interrupt request
acknowledgement or by program
The output signal becomes "H"
when the receive operation starts
“L”
The output signal becomes "L"
when the RE bit in the UiC1 register
is set to 1
The RI bit becomes 0 and RTSi output
becomes "L" by reading the UiRB register
i = 0 to 4
The above applies under the following conditions:
- UiMR register: STPS bit = 0 (1 stop bit)
- UiC0 register: CRS bit = 1 (CTS function not used)
NOTES:
1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive
clock is generated after detecting the falling edge of the start bit, and then the receive operation starts.
2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled.
When the receive operatin is cancelled, the RTSi output becomes "L".
Figure 17.19
Receive Operation in UART Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 220 of 352
M32C/8A Group
17. Serial Interfaces
17.1.2.1 Baud Rate
In UART mode, the baud rate is the frequency of the clock divided by the setting value of the UiBRG register
(i = 0 to 4) and again divided by 16. Table 17.5 lists an example of baud rate setting.
Actual baud rate =
Table 17.5
Target
Baud Rate
(bps)
UiBRG register count source
16 × (UiBRG register setting value + 1)
Baud Rate
UiBRG
Count
Source
Peripheral Clock: 16MHz
UiBRG
Setting Value:
n
Actual Baud
Rate
(bps)
Peripheral Clock: 24MHz
UiBRG
Setting Value:
n
Peripheral Clock: 32MHz
Actual Baud
Rate
(bps)
UiBRG
Setting Value:
n
Actual Baud
Rate
(bps)
1200
f8
103(67h)
1202
155(9Bh)
1202
207(CFh)
1202
2400
f8
51(33h)
2404
77(4Dh)
2404
103(67h)
2404
4800
f8
25(19h)
4808
38(26h)
4808
51(33h)
4808
9600
f1
103(67h)
9615
155(9Bh)
9615
207(CFh)
9615
14400
f1
68(44h)
14493
103(67h)
14423
138(8Ah)
14388
19200
f1
51(33h)
19231
77(4Dh)
19231
103(67h)
19231
28800
f1
34(22h)
28571
51(33h)
28846
68(44h)
28986
31250
f1
31(1Fh)
31250
47(2Fh)
31250
63(3Fh)
31250
38400
f1
25(19h)
38462
38(26h)
38462
51(33h)
38462
51200
f1
19(13h)
50000
28(1Ch)
51724
38(26h)
51282
17.1.2.2 LSB First or MSB First
As shown in Figure 17.20, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order. This function
can be used when data length is 8 bits long.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
"H"
TXDi
"L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"H"
RXDi
"L"
(2) When the UFORM bit is set to 1 (MSB first)
TXDi
"H"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
"L"
RXDi
"H"
"L"
The above applies under the following conditions:
- UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock)
- UiC1 register: UiLCH bit = 0 (not inverted) and the UiLCH bit in the UiC1 register is set to 0 (not inverted).
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 17.20
Bit Order
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 221 of 352
M32C/8A Group
17. Serial Interfaces
17.1.2.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted
for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function
can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse
operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
TXDi
(not inverted)
"H"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D1
D2
D3
D4
D5
D6
D7
P
SP
"L"
(2) When the UiLCH bit is set to 1 (inverted)
TXDi
(inverted)
"H"
ST
D0
"L"
The above applies under the following conditions:
- UiC0 register: UFROM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
PRYE bit = 1 (parity enabled).
Figure 17.21
Serial Data Logic Inverse
17.1.2.4 TXD and RXD I/O Polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When
the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including
the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)
TXDi "H"
(not inverted) "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi "H"
(not inverted) "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL bit is set to 1 (inverted)
TXDi "H"
(inverted) "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi "H"
(inverted) "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
The above applies under the following conditions:
- UiC0 register: UFORM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
PRYE bit = 1 (parity enabled)
Figure 17.22
TXD and RXD I/O Polarity Inverse
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 222 of 352
ST: Start bit
P: Parity bit
SP: Stop bit
M32C/8A Group
17. Serial Interfaces
17.1.2.5 CTS/RTS Function
• CTS Function
Transmit operation is controlled by using the input signal to the CTSi pin . To use the CTS function, select
the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function
enabled), and the CRS bit to 0 (CTS function selected).
With the CTS function used, the transmit operation starts when all the following conditions are met and an
“L” signal is applied to the CTSi pin (i = 0 to 4).
-The TE bit in the UiC1 register is set to 1 (transmit operation enabled)
-The TI bit in the UiC1 register is 0 (data in the UiTB register)
When a high-level (“H”) signal is applied to the CTSi pin during transmitting, the transmit operation is
disabled after the transmit operation in progress is completed.
• RTS Function
The MCU can inform the external device that it is ready for a receive operation by using the output signal
from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register.
With the RTS function used, the RTSi pin outputs an “L” signal when all the following conditions are met,
and outputs an “H” when the start bit is detected.
-The RI bit in the UiC1 register is 0 (no data in the UiRB register)
-The RE bit is set to 1 (receive operation enabled)
17.1.2.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in UART mode.
(1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0
(receive operation disabled).
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, 7-bit data length), 101b (UART
mode, 8-bit data length), or 110b (UART mode, 9-bit data length).
(4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 223 of 352
M32C/8A Group
17.1.3
17. Serial Interfaces
Special Mode 1 (I2C Mode)
In I2C mode, the simplified I2C helps to communicate with external devices.
Table 17.6 lists specifications of I2C mode. Tables 17.7 and 17.8 list register settings. Tables 17.9 and 17.10 list
individual functions in I2C mode. Table 17.11 lists pin settings. Figure 17.23 shows a block diagram of I2C
mode. Figure 17.24 shows a transfer timing to the UiRB register (i = 0 to 4) and interrupt timing.
I2C Mode Specifications
Table 17.6
Item
Specification
Data format
• Data length: 8 bits long
Baud rate
• In master mode
When the CKDIR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):
fj / (2 (m + 1))
fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)
• In slave mode
When the CKDIR bit is set to 1 (external clock): input from the SCLi pin
Transmit start condition
To start transmit operation, all of the following must be met(2):
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
Receive start condition
To start receive operation, all of the following must be met(2):
• Set the TE bit to 1 (transmit operation enabled)
• The TI bit is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
Interrupt request generation
timing
• Start condition detection
• Stop condition detection
• ACK (Acknowledge) detection
• NACK (Not-Acknowledge) detection
Error detection
• Overrun error(3)
Overrun error occurs when the 8th bit of the next data is received before
reading the UiRB register
Selectable function
• Arbitration lost detect timing
Update timing of the ABT bit in the UiRB register (i = 0 to 4) can be selected.
Refer to 17.1.3.3 Arbitration
• SDAi digital delay
No digital delay or 2 to 8 cycle delay of the UiBRG count source can be
selected. Refer to 17.1.3.5 SDA Output
• Clock phase setting
Clock delay or no clock delay can be selected. Refer to 17.1.3.4 Serial Clock.
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, satisfy the conditions while an “H” signal is applied to the SCLi pin.
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 224 of 352
M32C/8A Group
17. Serial Interfaces
(note 1)
NCH
SDAi
ABT
Select SDA output
in Function Control
Register
DQ
T
ALS
SDHI
0
1
ACKD
UARTi transmit
shift register
Noise
filter
ACKC
0
1
STSPSEL
Delay circuit
DMA 0 to 3 request
Transmission
control circuit
IICM2 = 1
UARTi transmit interrupt request
NACK interrupt request
IICM = 1 and
IICM2 = 0
UARTi transmit
shift register
IICM = 0 or
IICM2 = 1
Reception
control circuit
DMA 0 to 3 request
UARTi receive interrupt request
ACK interrupt request
IICM = 1 and
IICM2 = 0
Start condition detection
SQ
Stop condition detection
Logic 0 write
signal to PDk_m
(note 1)
NCH
R
NACK
DQ
T
DQ
Logic 1 write
signal to PDk_m
T
SQ
Falling edge
detection
Start/stop condition detection
interrupt request
BBS
R
ACK
Start/stop condition
generation block
SCLi
Select SCL output in
Function Control
Register
Noise
filter
9th clock
UARTi
CLK
control
SWC2
SWC
R
Falling edge
of 9th bit
i = 0 to 4
IICM, BBS: bits in the UiSMR register
IICM2, SWC, ALS, SWC2, SDHI: bits in the UiSMR2 register
STSPSEL, ACKD, ACKC: bits in the UiSMR4 register
NCH: bit in the UiC0 register
ABT: UiRB register
PDk_m: bit in the Port Pk Direction Register corresponding to the SCLi pin
NOTE:
1. P7_0 and P7_1 do not have the dotted rectangular portion of the circuit.
Figure 17.23
I2C Mode Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
SQ
Page 225 of 352
STSPSEL IICM
0
0
1
1
M32C/8A Group
Table 17.7
17. Serial Interfaces
Register Settings in I2C Mode (1)
Register
UiMR
UiSMR
UiSMR2
UiSMR3
UiSMR4
Setting Value
Bit
Master
Slave
SMD2 to SMD0
Set to 010b
CKDIR
Set to 0
IOPOL
Set to 0
IICM
Set to 1
ABC
Select an arbitration lost detect timing Disabled
BBS
Bus busy flag
7 to 3
Set to 00000b
IICM2
See Table 17.9 and 17.10 Functions in I2C Mode
CSC
Set to 1 to enable clock
synchronization
SWC
Set to 1 to hold an “L” signal output from SCLi at the falling edge of the ninth
bit of the serial clock
ALS
Set to 1 to abort an SDAi output when Set to 0
detecting the arbitration lost
STC
Set to 0
SWC2
Set to 1 to forcibly make a signal output from SCL an “L”
SDHI
Set to 1 to disable SDA output
SU1HIM
Set to 0
SSE
Set to 0
CKPH
See Table 17.9 and 17.10 Functions in I2C Mode
DINC, NODC, ERR
Set to 0
DL2 to DL0
Set SDAi digital delay value
STAREQ
Set to 1 to generate the start
condition
RSTAREQ
Set to 1 to generate the restart
condition
STPREQ
Set to 1 to generate the stop
condition
STSPSEL
Set to 1 when using a condition
generation function
ACKD
Select ACK or NACK
ACKC
Set to 1 to output ACK data
SCLHI
Set to 1 to enable SCL output stop
when detecting the stop condition
Set to 0
SWC9
Set to 0
Set to 1 to hold an “L” signal output
from SCLi at the falling edge of the
ninth bit of the serial clock
i = 0 to 4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 226 of 352
Set to 1
Set to 0
Set to 1 to initialize UARTi by
detecting the start condition
Set to 0
M32C/8A Group
Table 17.8
17. Serial Interfaces
Register Settings in I2C Mode (2)
Register
UiC0
Setting Value
Bit
Master
Slave
CLK1, CLK0
Select the count source of the UiBRG Disabled
register
CRS
Disabled because the CRD bit is set to 1
TXEPT
Transmit shift register empty flag
CRD, NCH
Set to 1
CKPOL
Set to 0
UFORM
Set to 1
TE
Set to 1 to enable transmit operation
TI
UiTB register empty flag
RE
Set to 1 to enable receive operation
RI
Receive operation complete flag
UiLCH, UiERE
Set to 0
UiBRG
7 to 0
Set baud rate
IFSR
IFSR7, IFSR6
Select the UARTi interrupt source
UiTB
7 to 0
Set transmit data
UiRB
7 to 0
Receive data can be read
8
ACK or NACK is received
ABT
Arbitration lost detect flag
OER
Overrun error flag
UiC1
i = 0 to 4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 227 of 352
Disabled
Disabled
M32C/8A Group
17. Serial Interfaces
As shown in Table 17.9, I2C mode is entered when bits SMD2 to SMD0 in the UiMR register are set to 010b
(I2C mode) and the IICM bit in the UiSMR register to 1 (I2C mode). Because an SDAi transmit output passes
through a delay circuit, output signal from the SDAi pin changes after the SCLi pin level becomes low (“L”)
and the “L” output stabilizes.
Table 17.9
Functions in I2C Mode (1)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
Function
CKPH = 0
(no clock delay)
Interrupt source for
numbers 39 to 41(1)
(See Figure 17.24)
CKPH = 1
(clock delay)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 0
(no clock delay)
CKPH = 1
(clock delay)
Start condition or stop condition detection
(See Table 17.12 STSPSEL Bit Function)
Interrupt source for
No acknowledgement detection (NACKi) numbers 17, 19, 33, 35, at the rising edge of 9th bit of SCLi
37(1)
(See Figure 17.24)
UARTi transmit
operation - at the
rising edge of 9th bit
of SCLi
Acknowledgement detection (ACKi) Interrupt source for
numbers 18, 20, 34, 36, at the rising edge of 9th bit of SCLi
38(1)
(See Figure 17.24)
UARTi receive operation - at the falling edge
of 9th bit of SCLi
Data transfer timing
At rising edge of 9th bit of SCLi
from the UART receive
shift register to the UiRB
register
Falling edge of 9th bit Falling edge and
of SCLi
rising edge of 9th bit
of SCLi
UARTi transmit output
delay
Delay
Functions of P6_3,
P6_7, P7_0, P9_2,
P9_6
SDAi input and output
Functions of P6_2,
P6_6, P7_1, P9_1,
P9_7
SCLi input and output
Noise filter width
200 ns
i = 0 to 4
NOTE:
1. Use the following procedures to change an interrupt source.
(a) Disable an interrupt of the corresponding interrupt number.
(b) Change an interrupt source.
(c) Set the IR bit of a corresponding interrupt number to 0 (interrupt not requested).
(d) Set bits ILVL2 to ILVL0 of the corresponding interrupt number.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 228 of 352
UARTi transmit
operation - at the
next falling edge after
the 9th bit of SCLi
M32C/8A Group
Table 17.10
17. Serial Interfaces
Functions in I2C Mode (2)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
Function
CKPH = 0
(no clock delay)
IICM2 = 1
(UART transmit/receive interrupt)
CKPH = 1
(clock delay)
CKPH = 0
(no clock delay)
CKPH = 1
(clock delay)
Reading RXDi, SCLi pin Can be read regardless of the corresponding port direction bit
levels
Default value of TXDi,
SDAi output
Value set in the port register before entering I2C mode(1)
SCLi default and end
values
H
DMA source
(See Figure 17.24)
Acknowledgement detection (ACKi)
UARTi receive operation - at the falling edge
of 9th bit of SCLi
Storing receive data
1st to 8th bit of the receive data are stored
into bits 7 to 0 in the UiRB register
1st to 7th bits of the receive data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register
L
H
L
1st to 8th bits are
stored into bits 7 to 0
in the UiRB
register(2)
Reading receive data
The value in the UiRB register is read as it is
Bits 6 to 0 in the UiRB
register are read as
bits 7 to 1. Bit 8 in the
UiRB register is read
as bit 0(3)
i = 0 to 4
NOTES:
1. Set default value of the SDAi output while bits SMD2 to SMD0 in the UiMR register are set to 000b (serial
interface disabled).
2. Second data transfer to the UiRB register (at the rising edge of the ninth bit of SCLi).
3. First data transfer to the UiRB register (at the falling edge of the ninth bit of SCLi).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 229 of 352
M32C/8A Group
17. Serial Interfaces
(1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
D7
D6
D5
D4
D3
D2
D1
D0
9th bit
SCLi
SDAi
D8 (ACK,NACK)
ACK interrupt (DMA request) or
NACK interrupt
Transferred to the UiRB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
D7
D6
D5
D4
D3
D2
D1
D0
9th bit
SCLi
SDAi
D8 (ACK, NACK)
ACK interrupt (DMA request) or
NACK interrupt
Transferred to the UiRB register
b15
b9
b8
b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(3)When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
D7
D6
D5
D4
D3
D2
D1
D0
9th bit
SCLi
SDAi
D8 (ACK,NACK)
Receive interrupt
(DMA request)
Transmit interrupt
Transferred to the UiRB register
b15
b9
b8
b7
D0
−
b0
D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
(4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
D6
D5
D4
D3
D2
D1
D0
9th bit
SCLi
SDAi
D7
D8 (ACK, NACK)
Transmit interrupt
Receive interrupt
(DMA request)
Transferred to the UiRB register (first time)
b15
b9
b8
b7
D0
−
Transferred to the UiRB register
(second time)
b15
b9
D7 D6 D5 D4 D3 D2 D1
i = 0 to 4
The above applies when the CKDIR bit in UiMR register = 1 (external clock selected)
Transfer Timing to the UiRB Register and Interrupt Timing
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 230 of 352
b7
Contents of the UiRB register
Contents of the UiRB register
Figure 17.24
b8
D8 D7 D6 D5 D4 D3 D2
b0
b0
D1 D0
M32C/8A Group
Table 17.11
17. Serial Interfaces
Pin Settings in I2C Mode
Bit Setting
Port
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
SCL0 output
−
−
PSL0_2 = 0
PS0_2 = 1
SCL0 input
PD6_2 = 0
−
−
PS0_2 = 0
SDA0 output
−
−
PSL0_3 = 0
PS0_3 = 1
SDA0 input
PD6_3 = 0
−
−
PS0_3 = 0
SCL1 output
−
−
PSL0_6 = 0
PS0_6 = 1
SCL1 input
PD6_6 = 0
−
−
PS0_6 = 0
P6_7
SDA1 output
−
−
PSL0_7 = 0
PS0_7 = 1
SDA1 input
PD6_7 = 0
−
−
PS0_7 = 0
P7_0(3)
SDA2 output
−
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
SDA2 input
PD7_0 = 0
−
−
PS1_0 = 0
SCL2 output
−
PSC_1 = 0
PSL1_1 = 0
PS1_1 = 1
SCL2 input
PD7_1 = 0
−
−
PS1_1 = 0
SCL3 output
−
−
PSL3_1 = 0
PS3_1 = 1
SCL3 input
PD9_1 = 0
−
−
PS3_1 = 0
P9_2
SDA3 output
−
−
PSL3_2 = 0
PS3_2 = 1
SDA3 input
PD9_2 = 0
−
−
PS3_2 = 0
P9_6
SDA4 output
−
−
−
PS3_6 = 1
SDA4 input
PD9_6 = 0
−
SCL4 output
−
−
PSL3_7 = 0
PS3_7 = 1
SCL4 input
PD9_7 = 0
−
−
PS3_7 = 0
P6_2
P6_3
P6_6
P7_1(3)
P9_1
P9_7
PS3_6 = 0
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 and P7_1 are N-channel open drain output ports.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 231 of 352
M32C/8A Group
17. Serial Interfaces
17.1.3.1 Detecting Start Condition and Stop Condition
The MCU detects the start condition and stop condition. The start condition detection interrupt request is
generated when the SDAi (i = 0 to 4) pin level changes from high (“H”) to low (“L”) while the SCLi pin level is
held “H”. The stop condition detection interrupt request is generated when the SDAi pin level changes from “L”
to “H” while the SCLi pin level is held “H”.
The start condition detection interrupt shares the Interrupt Control Register and interrupt vector with the stop
condition detection interrupt. The BBS bit in the UiSMR register determines which interrupt is requested.
6 cycles < setup time(1)
6 cycles < hold time(1)
Setup time
Hold time
SCLi
SDAi
(start condition)
SDAi
(stop condition)
i=0 to 4
NOTE:
1. These are cycles of the main clock oscillation frequency f(XIN).
Figure 17.25
Start Condition or Stop Condition Detection
17.1.3.2 Start Condition or Stop Condition Output
The start condition is generated when the STAREQ bit in the UiSMR4 register (i = 0 to 4) is set to 1 (start).
The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to 1 (start).
The stop condition is generated when the STPREQ bit in the UiSMR4 is set to 1 (start).
The following is the procedure to output the start condition, restart condition, or stop condition.
(1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (start/stop condition generation circuit selected).
Table 17.12 and Figure 17.26 show functions of the STSPSEL bit.
Table 17.12
STSPSEL Bit Function
Function
STSPSEL = 0
STSPSEL = 1
Output from pins SCLi and
SDAi
Output the serial clock and data.
Output of the start condition or stop
Output of the start condition or stop
condition is controlled by the status of bits
condition is controlled by software utilizing STAREQ, RSTAREQ, and STPREQ.
port functions. (The start condition and
stop condition are not automatically
generated by hardware)
Timing to generate start
condition and stop condition
interrupt requests
When start condition and stop condition
are detected
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 232 of 352
When start condition and stop condition
generation are completed
M32C/8A Group
17. Serial Interfaces
(1) In slave mode,
the CKDIR bit is set to 1 (external clock) and the STSPSEL bit is set to 0 (no start condition and stop condition output)
SCLi
SDAi
Stop condition detection interrupt
Start condition detection interrupt
IR bit in the
BCNiIC register
1
0
Set to 0 by an interrupt request acknowledgement or by program
(2) In master mode,
the CKDIR bit is set to 0 (internal clock) and the STSPSEL bit is set to 1 (start condition and stop condition output)
0
Setting value of
STSPSEL bit
1
0
1
0
SCLi
SDAi
The STAREQ bit
is set to 1 (start)
IR bit in the
BCNiIC register
Start condition detection interrupt
The STAREQ bit is set to 1 (start)
Stop condition detection interrupt
1
0
Set to 0 by an interrupt request acknowledgement or by program
i = 0 to 4
Figure 17.26
STSPSEL Bit Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 233 of 352
M32C/8A Group
17. Serial Interfaces
17.1.3.3 Arbitration
The ABC bit in the UiSMR register (i = 0 to 4) determines an update timing of the ABT bit in the UiRB register.
At the rising edge of the clock input to the SCLi pin, the MCU determines whether a transmit data matches data
input to the SDAi pin.
When the ABC bit is set to 0 (update per bit), the ABT bit becomes 1 (detected - arbitration is lost) as soon as a
data discrepancy is detected. The ABT bit remains 0 (not detected - arbitration is won) if not detected. When the
ABC bit is set to 1 (update per byte), the ABT bit becomes 1 at the falling edge of the ninth cycle of the serial
clock if discrepancy is ever detected. When the ABT bit is updated per byte, set the ABT bit to 0 after an ACK
detection in the first byte data is completed. Then the next byte data transfer can be started.
When the ALS bit in the UiSMR2 register is set to 1 (SDAi output stopped) and the ABT bit becomes 1
(detected - arbitration is lost), the SDAi pin is placed in a high-impedance state simultaneously.
17.1.3.4 Serial Clock
The serial clock is used to transmit and receive data as is shown in Figure 17.24.
By setting the CSC bit in the UiSMR2 register to 1 (clock synchronized), an internally generated clock (internal
SCLi) is synchronized with the external clock applied to the SCLi pin. If the CSC bit is set to 1, the internal
SCLi becomes low (“L”) when the internal SCLi is held high (“H”) and the external clock applied to the SCLi
pin is at the falling edge. The contents of the UiBRG register are reloaded and a counting for “L” period is
started. When the external clock applied to SCLi pin is held “L” and then the internal SCLi changes “L” to “H”,
the UiBRG counter stops. The counting is resumed when the clock applied to SCLi pin becomes “H”. The
UARTi serial clock is equivalent to logical AND operation of the internal SCLi and the clock signal applied to
the SCLi pin.
The serial clock is synchronized between a half cycle before the falling edge of the first bit and the rising edge
of the ninth bit of the internal SCLi. Select the internal clock as the serial clock while the CSC bit is set to 1.
The SWC bit in the UiSMR2 register determines whether an output signal from the SCLi pin is held “L” at the
falling edge of the ninth cycle of the serial clock or not.
When the SCLHI bit in the UiSMR4 register is set to 1 (SCLi output stopped), a SCLi output stops as soon as
the stop condition is detected (the SCLi pin is in a high-impedance state).
When the SWC2 bit in the UiSMR2 register is set to 1 (SCLi pin is held “L”), the SCLi pin forcibly outputs an
“L” even in the middle of transmitting and receiving. The fixed “L” output from the SCLi pin is cancelled by
setting the SWC2 bit to 0 (serial clock), and then the serial clock inputs to or outputs from the SCLi pin.
When the CKPH bit in the UiSMR3 register is set to 1 (clock delay) and the SWC9 bit in the UiSMR4 register
is set to 1 (SCLi pin is held “L” after receiving 9th bit), an output signal from the SCLi pin is held “L” at the
next falling edge to the ninth bit of the clock. The fixed “L” output from the SCLi pin is cancelled by setting the
SWC9 bit to 0 (no wait state/release wait state).
17.1.3.5 SDA Output
Values set in bits 7 to 0 (D7 to D0) in the UiTB register are output in descending order from D7. The ninth bit
(D8) is ACK or NACK.
Set the default value of SDAi transmit output, while the IICM bit in the UiSMR register is set to 1 (I2C mode)
and bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled).
Bits DL2 to DL0 in the UiSMR3 register determine no delay or delay of 2 to 8 UiBRG register count source
cycles are added to an SDAi output.
When the SDHI bit in the UiSMR2 register is set to 1 (SDA output stopped), the SDAi pin is forcibly placed in
a high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi serial clock. The ABT bit
in the UiRB register may become 1 (detected).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 234 of 352
M32C/8A Group
17. Serial Interfaces
17.1.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored
into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the
UiRB register. The eighth bit (D0) is stored into bit 8 in the UiRB register.
If the IICM2 bit is set to 1 and the CKPH bit in the UiSMR3 register is set to 1 (clock delay), the same data as
that of when setting the IICM2 bit to 0 can be returned, by reading the UiRB register after the rising edge of the
ninth bit of the serial clock.
17.1.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register is set to 0 (start/stop condition not output) and the ACKC bit in
the UiSMR4 register is set to 1 (ACK data output), the SDAi pin outputs the setting value, ACK or NACK, of
the ACKD bit in the UiSMR4 register.
If the IICM2 bit is set to 0, the NACK interrupt request is generated when the SDAi pin is held high (“H”) at the
rising edge of the ninth bit of the serial clock. The ACK interrupt request is generated when the SDAi pin is
held low (“L”) at the rising edge of the ninth bit of the serial clock.
When ACK is selected to generate a DMA request source, the DMA transfer is activated by an ACK detection.
17.1.3.8 Transmit and Receive Operation Initialization
The following occurs when the STC bit in the UiSMR2 register is set to 1 (UARTi initialized) and the start
condition is detected:
• The UARTi transmit shift register is initialized and the contents of the UiTB register are transferred to the
UARTi transmit shift register. Then, the transmit operation is started at the next serial clock input to the
SCLi pin. UARTi output value remains the same as when the start condition was detected until the first bit
data is output.
• The UARTi receive shift register is initialized and the receive operation is started at the next serial clock
input to the SCLi pin.
• The SWC bit in the UiSMR2 register becomes 1 (SCLi pin is held “L” after receiving 8th bit). An output
from the SCLi pin becomes “L” at the falling edge of the ninth bit of the serial clock.
When UARTi transmit/receive operation is started with setting the STC bit to 1, the TI bit in the UiC1 register
remains unchanged. Also, select the external clock as the serial clock to start UARTi transmit/receive operation
with setting the STC bit to 1.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 235 of 352
M32C/8A Group
17.1.4
17. Serial Interfaces
Special Mode 2
Full-duplex clock synchronous serial communications are allowed in this mode. SS function is used for transmit
and receive control. The input signal to the SSi pin (i = 0 to 4) determines whether the transmit and receive
operation is enabled or disabled. When it is disabled, the output pin is placed in a high-impedance state. Table
17.13 lists specifications of special mode 2. Table 17.14 list pin settings. Figure 17.27 shows register settings.
Table 17.13
Special Mode 2 Specifications
Item
Specification
Data format
Baud rate
Data length: 8 bits long
• The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):
fj / (2 (m + 1))
fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)
• The CKDIR bit to 1 (external clock): input from the CLKi pin
Transmit/receive control
SS function
Output pin is placed in a high-impedance state to avoid data conflict between a
master and other masters, or a slave and other slaves.
Transmit and receive
start condition
Internal clock is selected (master mode):
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• “H” signal is applied to the SSi pin when the SS function is used
External clock is selected (slave mode)(2):
• Set the TE bit to 1
• The TI bit is 0
• Set the RE bit to 1
• “L” signal is applied to the SSi pin
If transmit-only operation is performed, the RE bit setting is not required in both cases.
Interrupt request
generation timing
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when data transmit operation from the UARTi transmit shift register is completed
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
• Overrun error(3)
Overrun error occurs when the 7th bit of the next data is received before
reading the UiRB register
• Mode error
Mode error occurs when an “L” signal is applied to the SSi pin in master mode
• CLK polarity
Transmit data output timing and receive data input timing can be selected
• LSB first or MSB first
Data is transmitted or received from either bit 0 or bit 7
• Serial data logic inverse
Transmit and receive data are logically inverted
• TXD and RXD I/O polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted.
• Clock phase
One of four combinations of serial clock polarity and phase can be selected
Selectable function
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 236 of 352
M32C/8A Group
Table 17.14
17. Serial Interfaces
Pin Settings in Special Mode 2
Bit Setting
Port
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1,
PSL3 Registers
PS0, PS1, PS3
Registers(1)(2)
−
−
PS0_0 = 0
CLK0 output (master) −
−
PSL0_1 = 0
PS0_1 = 1
CLK0 input (slave)
PD6_1 = 0
−
−
PS0_1 = 0
RXD0 input (master)
PD6_2 = 0
−
−
PS0_2 = 0
STXD0 output (slave) −
−
PSL0_2 = 1
PS0_2 = 1
TXD0 output (master) −
−
PSL0_3 = 0
PS0_3 = 1
SRXD0 input (slave)
PD6_3 = 0
−
−
PS0_3 = 0
P6_4
SS1 input
PD6_4 = 0
−
−
PS0_4 = 0
P6_5
CLK1 output (master) −
−
PSL0_5 = 0
PS0_5 = 1
CLK1 input (slave)
PD6_5 = 0
−
−
PS0_5 = 0
RXD1 input (master)
PD6_6 = 0
P6_0
SS0 input
P6_1
P6_2
P6_3
PD6_0 = 0
−
−
PS0_6 = 0
STXD1 output (slave) −
−
PSL0_6 = 1
PS0_6 = 1
TXD1 output (master) −
−
PSL0_7 = 0
PS0_7 = 1
SRXD1 input (slave)
−
−
PS0_7 = 0
TXD2 output (master) −
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
SRXD2 input (slave)
PD7_0 = 0
−
−
PS1_0 = 0
RXD2 input (master)
PD7_1 = 0
−
−
PS1_1 = 0
STXD2 output (slave) −
−
PSL1_1 = 1
PS1_1 = 1
P7_2
CLK2 output (master) −
PSC_2 = 0
PSL1_2 = 0
PS1_2 = 1
CLK2 input (slave)
PD7_2 = 0
−
−
PS1_2 = 0
P7_3
SS2 input
PD7_3 = 0
−
−
PS1_3 = 0
P9_0
CLK3 output (master) −
−
PSL3_0 = 0
PS3_0 = 1
CLK3 input (slave)
PD9_0 = 0
−
−
PS3_0 = 0
RXD3 input (master)
PD9_1 = 0
−
−
PS3_1 = 0
STXD3 output (slave) −
−
PSL3_1 = 1
PS3_1 = 1
TXD3 output (master) −
−
PSL3_2 = 0
PS3_2 = 1
SRXD3 input (slave)
PD9_2 = 0
−
−
PS3_2 = 0
P6_6
P6_7
P7_0(3)
P7_1(3)
P9_1
P9_2
PD6_7 = 0
P9_3
SS3 input
PD9_3 = 0
−
PSL3_3 = 0
PS3_3 = 0
P9_4
SS4 input
PD9_4 = 0
−
PSL3_4 = 0
PS3_4 = 0
P9_5
CLK4 output (master) −
−
−
PS3_5 = 1
CLK4 input (slave)
−
PSL3_5 = 0
PS3_5 = 0
TXD4 output (master) −
−
−
PS3_6 = 1
SRXD4 input (slave)
PD9_6 = 0
−
PSL3_6 = 0
PS3_6 = 0
RXD4 input (master)
PD9_7 = 0
−
−
PS3_7 = 0
−
PSL3_7 = 1
PS3_7 = 1
P9_6
P9_7
PD9_5 = 0
STXD4 output (slave) −
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 and P7_1 are N-channel open drain output ports.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 237 of 352
M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit
IOPOL bit = 0
Interrupt disabled
Clock synchronous mode
Clock select bit (1)
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register: SSE bit = 1
CKPH bit
DINC bit
NODC bit = 0
bits DL2 to DL0 = 000b
SS function enabled
Clock phase set bit (2)
Serial input pin set bit (1)
UiSMR4 register = 00h
UiC0 register: bits CLK1 to CLK0
CRD bit = 1
NCH bit
CKPOL bit
UFORM bit
UiBRG count source select bits
CTS function disabled
Data output select bit
CLK polarity select bit (2)
Bit order select bit
< When an internal clock is used >
fj
2(m + 1)
UiBRG register = m
m = 00h to FFh
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit = 0
UiLCH bit = 0
bit 7 = 0
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt souce select bit
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
Transmit interrupt priority level select bit
Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Receive interrupt priority level select bit
Interrupt not requested
Baud rate =
fj: f1, f8, f2n (3)
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
Interrupt enabled
Transmit operation enabled
Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to UiTB register.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
NOTES:
1. Set to 0 in master mode, and set to 1 in slave mode.
2. The clock phase is determined by the combination of the CKPH and CKPOL bits in the UiSMR3 register.
3. Bits CNT3 to CNT0 select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.27
Register Settings in Special Mode 2
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 238 of 352
M32C/8A Group
17. Serial Interfaces
17.1.4.1 Master Mode
Master mode is entered when the DINC bit in the UiSMR3 register (i = 0 to 4) is set to 1. The following pins
are used in master mode.
• TXDi: transmit data output
• RXDi: receive data input
• CLKi: serial clock output
To use the SS function, set the SSE bit in the UiSMR3 register to 1. A transmit and receive operation is
performed while an “H” is applied to the SSi pin. If an “L” is applied to the SSi pin, the ERR bit in the
UiSMR3 register becomes 1 (mode error occurred) and pins CLKi and TXDi are placed in high-impedance
states. Set the UiIRS bit in the UiC1 register to 1 (Transmit completion as interrupt source) to verify whether a
mode error has occurred or not by checking the EER bit in the transmission complete interrupt routine. To
resume serial communication after a mode error occurs, set the ERR bit to 0 (no mode error) while an “H”
signal is applied to the SSi pin. Pins TXDi and CLKi become in output mode.
17.1.4.2 Slave Mode
Slave mode is entered when the DINC bit in the UiSMR3 register is set to 0. The following pins are used in
slave mode.
• STXDi: transmit data output
• SRXDi: receive data input
• CLKi: serial clock input
To use the SS function, set the SSE bit in the UiSMR3 register to 1. When an “L” signal is applied to the SSi
input pin, the serial clock input is enabled, and a transmit and receive operation becomes available. When an
“H” signal is applied to the SSi pin, the serial clock input to the CLKi pin is ignored and the STXDi pin is
placed in a high-impedance state.
MCU
P1_3
MCU
P1_2
P9_3(SS3)
P9_0(CLK3)
P9_3(SS3)
P9_1(RXD3)
P9_0(CLK3)
P9_2(TXD3)
P9_1(STXD3)
(Master)
P9_2(SRXD3)
(Slave)
MCU
P9_3(SS3)
P9_0(CLK3)
P9_1(STXD3)
P9_2(SRXD3)
(Slave)
Figure 17.28
Serial Bus Communication Control with SSi Pin
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 239 of 352
M32C/8A Group
17. Serial Interfaces
17.1.4.3 Clock Phase Setting Function
The clock polarity and clock phase are selected from four combinations of the CKPH and CKPOL bits in the
UiSMR3 register (i = 0 to 4). The master must have the same serial clock polarity and phase as the slaves
involved in the communication. Figure 17.29 shows a transmit and receive operation timing.
(1) When the CKPH = 0 (no clock delay)
“H”
CLKi I/O (CKPOL = 0)
“L”
“H”
CLKi I/O (CKPOL = 1)
“L”
SSi input pin
In master mode
(internal clock)
(DINC = 0)
TXDi output
“H”
“L”
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
Receive data
input timing
SSi input pin
In slave mode
(external clock)
(DINC = 1)
“H”
“L”
“H”
STXDi output (1)
“L” Hi-Z
undefined
Hi-Z
Receive data
input timing
(2) When the CKPH = 1 (clock delay)
“H”
CLKi I/O (CKPOL = 0)
“L”
“H”
CLKi I/O (CKPOL = 1)
“L”
SSi input pin
In master mode
(internal clock)
(DINC = 0)
TXDi output
“H”
“L”
“H”
“L”
Receive data
input timing
SSi input pin
In slave mode
(external clock)
(DINC = 1)
i=0 to 4
“H”
“L”
“H”
STXDi
output (1)
“L”
Hi-Z
D0
Receive data
input timing
CKPH, DINC: bits in the UiSMR3 register
CKPOL: bit in the UiC0 register
NOTE:
1. P7_0 and P7_1 are N-channel open drain output ports. They must be pulled up externally to output data.
Figure 17.29
Transmit and Receive Operation Timing in Special Mode 2
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 240 of 352
D7
Hi-Z
M32C/8A Group
17.1.5
17. Serial Interfaces
Special Mode 3 (GCI Mode)
Full-duplex clock synchronous serial communications are allowed in this mode. When a trigger is input to the
CTSi (i = 0 to 4) pin, the internal clock which is synchronized with the continuous external clock is generated,
and a transmit and receive operation is started.
Table 17.15 lists specifications of GCI mode. Table 17.16 list pin settings. Figure 17.30 shows register settings.
Table 17.15
GCI Mode Specifications
Item
Specification
Data format
Data length: 8 bits long
Serial clock
Select the external clock
Set the CKDIR bit in the UiMR register (i = 0 to 4) to 1 (external clock).
When a trigger is input, the external clock or the clock divided by 2 becomes the
serial clock.
Transmit and receive start
condition
A transmit and receive operation starts when a trigger is input to the CTSi pin after all
the following are met:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 1 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• Set the SCLKSTPB bit in the UiC1 register is set to 0 (clock-divided
synchronization stopped)
The SCLKSTPB bit becomes 1 (clock-divided synchronization started) when a
trigger is input to the CTSi pin
Transmit and receive stop
condition
The SCLKSTPB bit in the UiC1 register is set to 0
Interrupt request generation
timing
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
• The UiIRS bit is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
• The UiIRS bit is set to 1 (transmit operation completed):
when data transmit operation from the UARTi transmit shift register is completed
Receive interrupt:
• When data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
Overrun error(1)
Overrun error occurs when the 7th bit of the next data is received before
reading the UiRB register
NOTE:
1. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 241 of 352
M32C/8A Group
Table 17.16
17. Serial Interfaces
Pin Settings in GCI Mode
Bit Setting
Port
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
P6_0
CTS0 input(3)
PD6_0 = 0
−
−
PS0_0 = 0
P6_1
CLK0 input
PD6_1 = 0
−
−
PS0_1 = 0
P6_2
RXD0 input
PD6_2 = 0
−
−
PS0_2 = 0
P6_3
TXD0 output
−
−
PSL0_3 = 0
PS0_3 = 1
P6_4
CTS1 input(3)
PD6_4 = 0
−
−
PS0_4 = 0
P6_5
CLK1 input
PD6_5 = 0
−
−
PS0_5 = 0
P6_6
RXD1 input
PD6_6 = 0
−
−
PS0_6 = 0
P6_7
TXD1 output
−
−
PSL0_7 = 0
PS0_7 = 1
P7_0(4)
TXD2 output
−
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
P7_1
RXD2 input
PD7_1 = 0
−
−
PS1_1 = 0
P7_2
CLK2 input
PD7_2 = 0
−
−
PS1_2 = 0
P7_3
CTS2 input(3)
PD7_3 = 0
−
−
PS1_3 = 0
P9_0
CLK3 input
PD9_0 = 0
−
−
PS3_0 = 0
P9_1
RXD3 input
PD9_1 = 0
−
−
PS3_1 = 0
P9_2
TXD3 output
−
−
PSL3_2 = 0
PS3_2 = 1
CTS3
input(3)
PD9_3 = 0
−
PSL3_3 = 0
PS3_3 = 0
P9_4
CTS4
input(3)
PD9_4 = 0
−
PSL3_4 = 0
PS3_4 = 0
P9_5
CLK4 input
PD9_5 = 0
−
PSL3_5 = 0
PS3_5 = 0
P9_6
TXD4 output
−
−
−
PS3_6 = 1
P9_7
RXD4 input
PD9_7 = 0
−
−
PS3_7 = 0
P9_3
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. CTS input is used as a trigger signal input.
4. P7_0 is an N-channel open drain output port.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 242 of 352
M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit = 1
IOPOL bit = 0
Interrupt disabled
Clock synchronous mode
Select external clock
UiSMR register: bits 6 to 0 = 0000000b
SCLKDIV bit
Clock division synchronous bit (1)
UiSMR2 register: bits 6 to 0 = 0000000b
SU1HIM bit
External clock synchronous enable bit (1)
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0 = 00b
CRD bit = 1
NCH bit
CKPOL bit = 0
UFORM bit = 0
CTS function disabled
Data output select bit
UiBRG register = 00h
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit = 0
UiLCH bit = 0
SCLKSTPB bit = 0
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt source select bit
Clock-divided synchronization stopped
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
Transmit interrupt priority level select bits
Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Receive interrupt priority level select bits
Interrupt not requested
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
Interrupt enabled
Transmit operation enabled
Receive operation enabled
End initial setting
Transmit/receive operation starts when a trigger is input to the
CTSi pin after writing data to the UiTB register.
Read the UiRB register when a receive operation is completed.
i = 0 to 4
NOTE:
1. The external clock synchronization function is determined by the combination of the SCLKDIV bit in the UiSMR register
and the SU1HIM bit in the UiSMR2 register. Refer to the table " Clock-Divided Synchronous Function Select" for details.
Figure 17.30
Register Settings in GCI Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 243 of 352
M32C/8A Group
17. Serial Interfaces
Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values
shown in Table 17.17, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a
transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock
cycle divided by two can be selected for the serial clock.
When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops
immediately.
Figure 17.31 shows an example of the clock-divided synchronous function.
Table 17.17
Clock-Divided Synchronous Function Select
SCLKDIV bit in the
UiSMR register
SU1HIM bit in the
UiSMR2 register
Clock-Divided Synchronous Function
0
0
Not synchronized
0
1
Same clock cycle as the external clock
1
0 or 1
External clock cycle divided by 2
External clock
from the CLKi pin
More than 1 clock
cycle is required
Trigger signal input
to the CTSi pin
1
2
3
4
5
6
7
8
Serial clock
The clock is stopped by the
SCLKSTPB bit in the UiC1 register
A
TXDi
1
2
3
4
5
6
7
8
Serial clock
B
TXDi
1
2
3
4
5
6
7
i = 0 to 4
A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1
B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1.
Figure 17.31
Clock-Divided Synchronous Function
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 244 of 352
8
M32C/8A Group
17.1.6
17. Serial Interfaces
Special Mode 4 (SIM Mode)
In SIM mode, the MCU can communicate with SIM interface devices using UART mode. Both direct and
inverse formats are available. The TXDi pin (i = 0 to 4) outputs a low-level (“L”) signal when a parity error is
detected.
Table 17.18 lists specifications of SIM mode. Table 17.19 list pin settings. Figure 17.32 lists register settings.
Figure 17.33 shows an example of SIM interface operation. Figure 17.34 shows an example of SIM interface
connection.
Table 17.18
SIM Mode Specifications
Item
Specification
Data format
• Data length 8-bit UART mode
• One stop bit
• Direct format:
Parity: even
Data logic: direct (not inverted)
Bit order: LSB first
• Inverse format:
Parity: odd
Data logic: inverse (inverted)
Bit order: MSB first
Set the CKDIR bit in the UiMR register is 0 (internal clock):
fj / (16 (m + 1))
fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)
Baud rate
Transmit/receive control
CTS/RTS function disabled
Transmit start condition
To start transmit operation, all of the following must be met:
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
Receive start condition
To start receive operation, all of the following must be met:
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The start bit is detected
Interrupt request generation
timing
Transmit interrupt:
• Set the UiIRS bit to 1 (transmit operation completed)
when the stop bit is output from the UARTi transmit shift register
Receive interrupt:
• when data is transferred from the UARTi receive shift register to the UiRB register
(receive operation completed)
Error detection
• Overrun error(2)
Overrun error occurs when the preceding bit of the stop bit of the next data is
received before reading the UiRB register
• Framing error
Framing error occurs when the number of the stop bits set using the STPS bit in
the UiMR register is not detected
• Parity error
Parity error occurs when parity is enabled and the received data does not have
the correct even or odd parity set with the PRY bit in the UiMR register.
• Error sum flag
Error sum flag is set to 1 when an overrun, framing, or parity error occurs
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
register remains unchanged as 0 (interrupt not requested).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 245 of 352
M32C/8A Group
Table 17.19
17. Serial Interfaces
Pin Settings in SIM Mode
Bit Setting
Port
Function
PSC Register
PD6, PD7, PD9
Registers(2)
PSL0, PSL1, PSL3
Registers
PS0, PS1, PS3
Registers(1)(2)
P6_2
RXD0 input
PD6_2 = 0
−
PS0_2 = 0
P6_3
TXD0 output
−
PSL0_3 = 0
PS0_3 = 1
P6_6
RXD1 input
PD6_6 = 0
−
PS0_6 = 0
P6_7
TXD1 output
−
PSL0_7 = 0
PS0_7 = 1
P7_0(3)
TXD2 output
−
PSC_0 = 0
PSL1_0 = 0
PS1_0 = 1
P7_1
RXD2 input
PD7_1 = 0
−
−
PS1_1 = 0
P9_1
RXD3 input
PD9_1 = 0
−
−
PS3_1 = 0
P9_2
TXD3 output
−
−
PSL3_2 = 0
PS3_2 = 1
P9_6
TXD4 output
−
−
−
PS3_6 = 1
P9_7
RXD4 input
PD9_7 = 0
−
−
PS3_7 = 0
NOTES:
1. Set registers PS0, PS1, and PS3 after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
3. P7_0 is an N-channel open drain output port.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 246 of 352
M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 101b
CKDIR bit = 0
STPS bit = 0
PRY bit
PRYE bit = 1
IOPOL bit = 0
Interrupt disabled
UART mode: 8-bit data length
Select internal clock
Select 1 stop bit
Parity select bit (1)
Parity enabled
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0
CRD bit = 1
NCH bit = 1
CKPOL bit = 0
UFORM bit
UiBRG register count source select bits
CTS function disabled
N-channel open drain output
UiBRG register = m
m = 00h to FFh
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit = 1
UiRRM bit = 0
UiLCH bit
UiERE bit = 1
Transmit operation disabled
Receive operation disabled
Transmit completion as transmit interrupt source
Data logic select bit (2)
Error signal output enabled
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
Transmit interrupt priority level select bits
Interrupt not requested
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Receive interrupt priority level select bits
Interrupt not requested
Bit order select bit (2)
Baud rate =
fj
16(m + 1)
fj = f1, f8, f2n (3)
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
Interrupt enabled
Transmit operation enabled
Receive operation enabled
End initial setting
Transmit operation starts by writing data to the UiTB register
Receive operation starts when the start bit is detected.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
NOTES:
1. Set to 1 in the direct format, and set to 0 in the inverse format.
2. Set to 0 in the direct format, and set to 1 in the inverse format.
3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
4. Determine whether an "L" is output from the TXDi pin by reading the port that shares a pin with the RXDi pin in the reception
complete interrupt routine. When an "L" is output, wait for one clock cycle to read the UiRB register.
Figure 17.32
Register Settings in SIM Mode
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 247 of 352
M32C/8A Group
17. Serial Interfaces
(1) Transmit operation
TC
Internal transmit
clock
1
TE bit in the
UiC1 register
(note 1)
0
Data is set in UiTB register
1
TI bit in the UiC1
register
0
“H”
TXDi output
“L”
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
Parity error signal
sent back from
receiving device
Data is transfer from UiTB register
to UARTi transmit shift register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Detect the level in interrupt routine
"L" level is sent back from the SIM card since parity error has occurred
Signal line level(2)
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TXEPT bit in the
UiC0 register
1
IR bit in the
SiTIC register
1
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
0
0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)
(2) Receive operation
TC
Internal receive
clock
1
RE bit in the
UiC1 register
0
Start bit
Transmit
waveform sent by
transmitting device
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
“H”
TXDi ouput
"L" level is sent back from the SIM card since parity error has occurred
“L”
Signal line level(3)
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RI bit in the
UiC1 register
1
IR bit in the SiRIC
register
1
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
0
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
Read from the UiRB register
0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
i = 0 to 4
TC =
16( m+ 1)
fj
fj: f1, f8, f2n (4)
NOTES:
1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing.
2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the
receiving device, is generated.
3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error
signal from the TXDi pin, is generated.
4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.33
SIM Interface Operation
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 248 of 352
M32C/8A Group
17. Serial Interfaces
MCU
SIM card
TXDi
RXDi
i = 0 to 4
NOTE:
1. Connect the TXDi and RXDi pins and pull up these pins.
Figure 17.34
SIM Interface Connection
17.1.6.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i = 0 to 4) is set to 1 (error signal output), the parity error signal
output is enabled. The parity error signal is output when a parity error is detected upon receiving data, and an
“L” signal is output from the TXDi pin in the timing shown in Figure 17.35. If the UiRB register is read while
a parity error signal is output, the PER bit in the UiRB register is set to 0 (parity error not occurred) and the
TXDi pin level becomes back to “H”.
To determine whether the parity error signal is output or not, read the port that shares a pin with the RXDi pin in
the transmission complete interrupt routine.
"H"
RXDi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"L"
"H"
Hi-Z
"L"
Receive
operation
complete flag
1
0
i = 0 to 4
The above applies under direct format conditions:
- UiMR register: PRY bit = 1 (odd parity)
- UiC0 register: UFORM bit = 0 (LSB first)
- UiC1 register: UiLCH bit = 0 (not inverted)
Figure 17.35
Parity Error Signal Output Timing
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 249 of 352
ST: Start bit
P: Even parity bit
SP: Stop bit
M32C/8A Group
17. Serial Interfaces
17.1.6.2 Formats
17.1.6.2.1 Direct Format
When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from
D0. When data is received, received data is stored into the UiRB register, starting from D0. A parity error is
determined with even parity.
Set the bits as follows to transmit or receive in the direct format.
• Set the PRYE bit in the UiMR register to 1 (parity enabled).
• Set the PRY bit in the UiMR register to 1 (even parity).
• Set the UFORM bit in the UiC0 register to 0 (LSB first).
• Set the UiLCH bit in the UiC1 register to 0 (not inverted).
17.1.6.2.2 Inverse Format
When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted
values is transmitted with odd parity, starting from D7. When data is received, received data is logically
inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity.
Set the bits as follows to transmit or receive in the inverse format.
• Set the PRYE bit to 1 (parity enabled).
• Set the PRY bit to 0 (odd parity).
• Set the UFORM bit to 1 (MSB first).
• Set the UiLCH bit to 1 (inverted).
(1) Direct format
P: Even parity
"H"
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
"L"
(2) Inverse format
P: Odd parity
TXDi
"H"
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
"L"
ST: Start bit
SP: Stop bit
i = 0 to 4
Figure 17.36
SIM Interface Formats
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 250 of 352
M32C/8A Group
18. A/D Converter
18. A/D Converter
M32C/8A Group has one 10-bit successive approximation A/D converter with a capacitance coupled amplifier.
The results of A/D conversion are stored into the AD0i registers (i = 0 to 7) corresponding to the selected pins. When
using DMAC operating mode, the conversion results are stored only into the AD00 register.
Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures
18.2 to 18.6 show registers associated with the A/D converter.
NOTE
This section is described in the 144-pin package as an example.
Pins AN15_0 to AN15_7 are not provided in the 100-pin package.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 251 of 352
M32C/8A Group
Table 18.1
18. A/D Converter
A/D Converter Specifications
Item
Specification
A/D conversion method
Successive approximation (with capacitance coupled amplifier)
Analog input voltage
0 V to AVCC (VCC1)
Operating clock φAD(1)
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
Resolution
Selectable from 8 bits or 10 bits
• One-shot mode
• Repeat mode
• Single sweep mode
• Repeat sweep mode 0
• Repeat sweep mode 1
• Multi-port single sweep mode
• Multi-port repeat sweep mode 0
Operating modes
Analog input pins(2)
A/D conversion start condition
Conversion rate per pin
144 pin package: 18 pins
8 pins each for AN (AN_0 to AN_7), AN15 (AN15_0 to AN15_7)
2 extended input pins (ANEX0 and ANEX1)
100 pin package: 10 pins
8 pins for AN (AN_0 to AN_7)
2 extended input pins (ANEX0 and ANEX1)
• Software trigger
The ADST bit in the AD0CON0 register is set to “1” (A/D conversion starts).
• External trigger (retrigger is enabled)
When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1.
• Hardware trigger (retrigger is enabled)
Timer B2 interrupt request of the three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
• Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
NOTES:
1. The φAD frequency must be16 MHz or lower when VCC1 = 4.2 to 5.5 V.
The φAD frequency must be10 MHz or lower when VCC1 = 3.0 to 5.5 V.
Without the sample and hold function, the φAD frequency must be 250 kHz or higher.
With the sample and hold function, the φAD frequency must be 1 MHz or higher.
2. AVCC = VCC1
AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) ≤ VCC1
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 252 of 352
M32C/8A Group
18. A/D Converter
0
Software trigger
TRG bit in
AD0CON0 register
1
ADST bit
0
ADTRG
Start trigger
Timer B2 interrupt request
1
(after ICTB2 register completes
TRG0 bit in
counting) of the three-phase
control timer function
AD0CON2 register
Bits OPA1 and OPA0
in AD0CON1 register
P9_6
ANEX1
P9_5
ANEX0
1X
X1
01
11
000
AN_0
000
001
AN_2
010
AN15_2
011
00
011
AN_4
AN15_3
100
101
AN_5
101
AN15_5
110
AN_6
Bits APS1 and APS0
in AD0CON2 register
110
111
AN15_6
111
Bits CH2 to CH0 in
AD0CON0 register
AN15_7
Bits CH2 to CH0 in
AD0CON0 register
AD00 register
AD01 register
AD02 register
Decoder
AD03 register
AD0CON0 register
AD04 register
Comparator
AD05 register
AD0CON1 register
AD06 register
AD07 register
AD0CON2 register
AD0CON3 register
Successive conversion register
Resistor ladder
CKS0 bit in
AD0CON0 register
1
AD0CON4 register
1/3
1/2
fAD
1
0
1/2
CKS2 bit in
AD0CON3 register
NOTES:
1. These pins are provided in the 144-pin package only.
2. AVCC = VCC1, AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) ≤ VCC1
Figure 18.1
P15(1, 2)
AN15_4
01
100
AN_7
AN15_1
010
00
AN_3
P10(2)
AN15_0
001
AN_1
A/D Converter Block Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 253 of 352
1/2
0
1
1
0
0
CKS1 bit in
AD0CON1 register
φAD
M32C/8A Group
18. A/D Converter
A/D0 Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
AD0CON0
0396h
00h
Bit Symbol
Bit Name
Function
b2 b1 b0
CH0
CH1
0 0 0: ANi_0
0 0 1: ANi_1
0 1 0: ANi_2
0 1 1: ANi_3
1 0 0: ANi_4
1 0 1: ANi_5
1 1 0: ANi_6
1 1 1: ANi_7 (i = none, 15)
Analog input pin
select bits(2, 3)
CH2
RW
RW
RW
RW
When the MSS bit in the AD0CON3 register = 0
b4 b3
0 0: One-shot mode
0 1: Repeat mode
1 0: Single sweep mode
1 1: Repeat sweep mode 0, repeat sweep mode 1
MD0
A/D operating mode
select bits 0 (2)
RW
When the MSS bit in the AD0CON3 register = 1
b4 b3
0 0:
Do not set to these values.
0 1:
1 0: Multi-port single sweep mode
1 1: Multi-port repeat sweep mode 0
MD1
RW
TRG
Trigger select bit
0: Software trigger
1: External trigger, hardware trigger (4)
RW
ADST
A/D conversion start bit
0: A/D conversion stops
1: A/D conversion starts (4)
RW
CKS0
Frequency select bit 0
(Note 5)
RW
NOTES:
1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Analog input pins must be configured again after an A/D operating mode is changed.
3. Bit CH2 to CH0 is enabled in one-shot mode and repeat mode.
4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after
the TRG bit is set to 1.
5. φAD frequency must be 16 MHz or below when VCC1 = 4.2 to 5.0V.
φAD frequency must be 10 MHz or below when VCC1 = 3.0 to 5.0V.
φAD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3
register.
CKS2 bit
in AD0CON3 register
CKS0 bit
in AD0CON0 register
CKS1 bit
in AD0CON1 register
φAD
0
fAD divided by 4
1
fAD divided by 3
0
fAD divided by 2
1
fAD
0
fAD divided by 8
1
fAD divided by 6
0
0
1
1
Figure 18.2
0
AD0CON0 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 254 of 352
M32C/8A Group
18. A/D Converter
A/D0 Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AD0CON1
Bit Symbol
After Reset
00h
Address
0397h
Bit Name
Function
RW
Single sweep mode and repeat sweep mode 0
b1 b0
0 0: ANi_0, ANi_1 (i = none, 15)
0 1: ANi_0 to ANi_3
1 0: ANi_0 to ANi_5
1 1: ANi_0 to ANi_7
Repeat sweep mode 1 (3)
SCAN0
A/D Sweep pin select bits (2)
b1 b0
0 0: ANi_0
0 1: ANi_0, ANi_1
1 0: ANi_0 to ANi_2
1 1: ANi_0 to ANi_3
Multi-port single sweep mode and multi-port
repeat sweep mode 0(4)
Set to 11b.
SCAN1
RW
RW
MD2
A/D operating mode
select bit 1(4)
0: Other than repeat sweep mode 1
1: Repeat sweep mode 1
RW
BITS
Resolution select bit
0: 8-bit mode
1: 10-bit mode
RW
CKS1
Frequency select bit 1
(Note 5)
RW
VCUT
VREF connection bit (8)
0: VREF not connected (7)
1: VREF connected
RW
b7 b6
RW
OPA0
Extended input pin function
select bits(4, 6)
OPA1
0 0: ANEX0 and ANEX1 are not used
0 1: Signal applied to ANEX0 is A/D converted
1 0: Signal applied to ANEX1 is A/D converted
1 1: External op-amp connection
RW
NOTES:
1. If the AD0CON1 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Bits SCAN1 and SCAN0 are enabled in single sweep mode, repeat sweep mode 0, 1, multi-port single sweep mode, and multiport repeat sweep mode 0.
3. These are prioritized pins used for A/D conversion when the MD2 bit is set to 1.
4. When the MSS bit in the AD0CON3 register is set to 1 (multi-port sweep mode used);
-set bits SCAN1 and SCAN0 to 11b
-set the MD2 bit to 0
-set bits OPA1 and OPA0 to 00b.
5. Refer to the note for the CKS0 bit in the AD0CON0 register.
6. Bits OPA1 and OPA0 can be set to 01b or 10b in one-shot mode and repeat mode. Set these bits to 00b or 11b in other
modes.
7. Do not set the VCUT bit to 0 during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A
converter.
8. When the VCUT bit is set to 1 from 0, wait for 1 μs or more to start the A/D conversion.
Figure 18.3
AD0CON1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 255 of 352
M32C/8A Group
18. A/D Converter
A/D0 Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0
AD0CON2
0394h
XX0X X000b
Bit Symbol
SMP
Bit Name
A/D conversion method
select bit
Function
0: Without sample and hold
1: With sample and hold
RW
RW
When the MSS bit in the AD0CON3 register = 0
b2 b1
APS0
Analog input port
select bits
APS1
0 0: AN_0 to AN_7, ANEX0, ANEX1
0 1: AN15_0 to AN15_7(2)
1 0:
Do not set to these values.
1 1:
When the MSS bit in the AD0CON3 register = 1
Set to 01b.
Unimplemented.
Write 0. Read as undefined value.
TRG0
External trigger source select bit
0: ADTRG selected
1: Timer B2 interrupt request of the three-phase
motor control timer function (after the ICTB2
register completes counting) selected
RW
−
(b7-b6)
Reserved bits
Set to 0.
Read as undefined value.
RW
AD0CON2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
−
(b4-b3)
−
NOTES:
1. If the AD0CON2 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. In the 100-pin package, do not set to 01b.
Figure 18.4
RW
Page 256 of 352
M32C/8A Group
18. A/D Converter
A/D0 Control Register 3(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
AD0CON3
Bit Symbol
Address
0395h
Bit Name
After Reset
XXXX X000b
Function
RW
DUS
DMAC operating mode
select bit
0: DMAC operating mode not used
1: DMAC operating mode used
RW
MSS
Multi-port sweep mode
select bit
0: Multi-port sweep mode not used
1: Multi-port sweep mode used (3)
RW
CKS2
Frequency select bit 2
(Note 4)
RW
b4 b3
RO
MSF0
Multi-port sweep status flags
MSF1
−
(b7-b5)
Reserved bits
(5)
0 0: AN_0 to AN_7
0 1: AN15_0 to AN15_7
1 0:
1 1: Do not set to these values.
Set to 0.
Read as undefined value.
RO
RW
NOTES:
1. If the AD0CON3 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. The AD0CON3 register may return an incorrect value if read during A/D conversion. It must be read or written after the A/D
conversion stops.
3. When the MSS bit is set to 1;
-set the DUS bit to 1 and configure DMAC.
-set bits MD1 and MD0 in the AD0CON0 register to 10b or 11b.
-set bits SCAN1 and SCAN0 in the AD0CON1 register to 11b, the MD2 bit to 0, bits OPA1 and OPA0 to 00b.
-set bits APS1 and APS0 in the AD0CON2 register to 01b.
-set bits MPS11 and MPS10 to 01b.
4. Refer to the note for the CKS0 bit in the AD0CON0 register.
5. Bits MSF1 and MSF0 are enabled when the MSS bit is set to 1. When the MSS bit is set to 0, a read from these bits returns an
undefined value.
Figure 18.5
AD0CON3 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 257 of 352
M32C/8A Group
18. A/D Converter
A/D0 Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0 0 0
AD0CON4
0392h
XXXX 00XXb
0 0
Bit Symbol
−
(b1-b0)
Bit Name
Reserved bits
MPS10
Multi-port sweep port
select bits(2)
MPS11
−
(b7-b4)
Function
RW
Set to 0.
Read as undefined value.
RW
b3 b2
RW
0 0: (Note 3)
0 1: AN_0 to AN_7, AN15_0 to AN15_7
1 0:
Do not set to these values.
1 1:
RW
Set to 0.
Read as undefined value.
Reserved bits
RW
NOTES:
1. If the AD0CON4 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Set bits MPS11 and MPS10 to 00b in the 100-pin package.
3. When the MSS bit in the AD0CON3 register is set to 0 (multi-port sweep mode not used), set bits MPS11 and MPS10 to 00b.
When the MSS bit is set to 1 (multi-port sweep mode used), set bits MPS11 and MPS10 to 01b.
A/D0 Register i(1, 2, 3, 4) (i = 0 to 7)
b8 b7
b15
b0
0 00 0 0 0
Symbol
Address
After Reset
AD00
AD01 to AD03
AD04 to AD06
AD07
0381h - 0380h
0383h - 0382h, 0385h - 0384h, 0387h - 0386h
0389h - 0388h, 038Bh - 038Ah, 038Dh - 038Ch
038Fh - 038Eh
00000000
00000000
00000000
00000000
Function
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
XXXXXXXXb
RW
8 low-order bits of A/D conversion result
RO
In 10-bit mode: 2 high-order bits of A/D conversion result
In 8-bit mode: Read as 0.
RO
Reserved bits. Read as 0.
RO
NOTES:
1. When the AD0i register is read by program in DMAC operating mode, the conversion result is incorrect.
2. If the next A/D conversion result is stored before reading the previous result in the AD0i register, the result will be incorrect.
3. Only AD00 register is enabled in DMAC operating mode. The contents of other registers are undefined.
4. When using both DMAC operating mode and 10-bit mode, select a 16-bit transfer for DMAC.
Figure 18.6
AD0CON4 Register, AD00 to AD07 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 258 of 352
M32C/8A Group
18. A/D Converter
If analog input shares the pin with other peripheral function inputs, a through current may flow to the peripheral
function inputs when an intermediate voltage is applied to the pin. To prevent through current, set the control bit for
the corresponding pin to 1, and other peripheral inputs are disconnected.
Table 18.2
Analog Input Pin Setting
Pin
Control Bit
Function
PSC Register
PSL3 Register
ANEX0
−
PSL3_5 = 1
P9_6
ANEX1
−
PSL3_6 = 1
P10_4
AN_4
P10_5
AN_5
P10_6
AN_6
P10_7
AN_7
P9_5
18.1
−
−
PSC_7 = 1
−
−
Mode Descriptions
The A/D converter has seven different modes. Table 18.3 lists settings for these modes.
Table 18.3
Mode Settings
AD0CON0 register
Mode
MD1 bit
MD0 bit
AD0CON1 register
MD2 bit
AD0CON3 register
MSS bit
DUS bit
One-shot mode
0
0
0
0
−
Repeat mode
0
1
0
0
−
Single sweep mode
1
0
0
0
−
Repeat sweep mode 0
1
1
0
0
−
Repeat sweep mode 1
Multi-port single sweep mode
1
1
1
0
1
0
0
1
−
1
Multi-port repeat sweep mode 0
1
1
0
1
1
−: Can be either 0 or 1.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 259 of 352
M32C/8A Group
18.1.1
18. A/D Converter
One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.4 lists
specifications of one-shot mode.
Table 18.4
One-Shot Mode Specifications
Item
Specification
Function
Analog voltage applied to a selected pin is converted once
Analog input pins
Select one pin from AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, or ANEX1
The following register settings determine which pin is used:
• Bits CH2 to CH0 in the AD0CON0 register
• Bits OPA1 and OPA0 in the AD0CON1 register
• Bits APS1 and APS0 in the AD0CON2 register
Start Condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
• A/D conversion is completed (the ADST bit becomes 0 when software trigger is
selected).
• Set the ADST bit to 0 by program (A/D conversion stops).
Interrupt request generation timing When the A/D conversion is completed
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
• DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0):
Read the AD0j register (j = 0 to 7) corresponding to a selected pin by program.
• DMAC operating mode is used (DUS bit = 1):
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. (Refer to 13. DMAC for DMAC settings)
Page 260 of 352
M32C/8A Group
18.1.2
18. A/D Converter
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code.
Table 18.5 lists specifications of repeat mode.
Table 18.5
Repeat Mode Specifications
Item
Specification
Function
Analog voltage applied to a selected pin is repeatedly converted
Analog input pins
Select one pin from AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, or ANEX1
The following register settings determine which pin is used:
• Bits CH2 to CH0 in the AD0CON0 register
• Bits OPA1 and OPA0 in the AD0CON1 register
• Bits APS1 and APS0 in the AD0CON2 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
Set the ADST bit register to 0 (A/D conversion stops)
Interrupt request generation timing • DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0):
Interrupt request is not generated.
• DMAC operating mode is used (DUS bit = 1):
Interrupt request is generated every time each A/D conversion is completed.
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
• DMAC operating mode is not used (DUS bit = 0):
Read the AD0j register (j = 0 to 7) corresponding to a selected pin by program.
• DMAC operating mode is used (DUS bit = 1):
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. (Refer to 13. DMAC for DMAC settings)
Page 261 of 352
M32C/8A Group
18.1.3
18. A/D Converter
Single Sweep Mode
In single sweep mode, analog voltage that is applied to multiple selected pins is converted to a digital code once
for each pin.
Table 18.6 lists specifications of single sweep mode.
Table 18.6
Single Sweep Mode Specifications
Item
Specification
Function
Analog voltage applied to selected pins is converted once for each pin
Analog input pins
Select one of the following.
• 2 pins (ANi_0 and ANi_1) (i = none, 15)
• 4 pins (ANi_0 to ANi_3)
• 6 pins (ANi_0 to ANi_5)
• 8 pins (ANi_0 to ANi_7)
The following register settings determine which pins are used:
• Bits SCAN1 and SCAN0 in the AD0CON1 register
• Bits APS1 and APS0 in the AD0CON2 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
• A sequence of A/D conversions is completed (the ADST bit becomes 0 when
software trigger is selected)
• Set the ADST bit to 0 by program (A/D conversion stops)
Interrupt request generation timing • DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0):
Interrupt request is generated after a sequence of A/D conversions is
completed.
• DMAC operating mode is used (DUS bit = 1):
Interrupt request is generated every time each A/D conversion is completed
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
• DMAC operating mode is not used (DUS bit = 0):
Read the AD0j register (j = 0 to 7) corresponding to a selected pin by program.
• DMAC operating mode is used (DUS bit = 1):
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. (Refer to 13. DMAC for DMAC settings)
Page 262 of 352
M32C/8A Group
18.1.4
18. A/D Converter
Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to multiple selected pins is repeatedly converted to a digital
code.
Table 18.7 lists specifications of repeat sweep mode 0.
Table 18.7
Repeat Sweep Mode 0 Specifications
Item
Specification
Function
Analog voltage applied to selected pins is repeatedly converted
Analog input pins
Select one of the following.
2 pins (ANi_0 and ANi_1) (i = none, 15)
4 pins (ANi_0 to ANi_3)
6 pins (ANi_0 to ANi_5)
8 pins (ANi_0 to ANi_7)
The following register settings determine which pins are used:
• Bits SCAN1 and SCAN0 in the AD0CON1 register
• Bits APS1 and APS0 in the AD0CON2 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
Set the ADST bit register to 0 (A/D conversion stops)
Interrupt request generation timing • DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0):
Interrupt request is not generated
• DMAC operating mode is used (DUS bit = 1):
Interrupt request is generated every time each A/D conversion is completed
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
• DMAC operating mode is not used (DUS bit = 0):
Read the AD0j register (j = 0 to 7) corresponding to a selected pin by program.
• DMAC operating mode is used (DUS bit = 1):
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. (Refer to 13. DMAC for DMAC settings)
Page 263 of 352
M32C/8A Group
18.1.5
18. A/D Converter
Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage applied to eight pins, prioritizing one to four pins, is repeatedly
converted to a digital code.
Table 18.8 lists specifications of repeat sweep mode 1.
Table 18.8
Repeat Sweep Mode 1 Specification
Item
Specification
Function
Analog voltage applied to 8 selected pins, prioritizing one to four pins, is
repeatedly converted.
Analog input pins
ANi_0 to ANi_7 (8 pins are selected from these pins) (i = none, 15)
Prioritized pins
Select one of the following.
• single pin (ANi_0)
• 2 pins (ANi_0 and ANi_1)
• 3 pins (ANi_0 to ANi_2)
• 4 pins (ANi_0 to ANi_3)
The following register settings determine which pins are used:
• Bits SCAN1 and SCAN0 in the AD0CON1 register
• Bits APS1 and APS0 in the AD0CON2 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
(retrigger of external trigger is invalid)
Stop condition
Set the ADST bit is set to 0 (A/D conversion stops)
Interrupt request generation timing • DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0):
Interrupt request is not generated.
• DMAC operating mode is used (DUS bit = 1):
Interrupt request is generated every time each A/D conversion is completed.
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
• DMAC operating mode is not used (DUS bit = 0):
Read the AD0j register (j = 0 to 7) corresponding to a selected pin by program.
• DMAC operating mode is used (DUS bit = 1):
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. (Refer to 13. DMAC for DMAC settings)
Page 264 of 352
M32C/8A Group
18. A/D Converter
When ANi_0 is prioritized (single pin)
Time
ANi_0
ANi_1
ANi_2
ANi_3
ANi_4
ANi_5
ANi_6
ANi_7
When ANi_0 and ANi_1 are prioritized (2 pins)
ANi_0
ANi_1
ANi_2
ANi_3
ANi_4
ANi_5
ANi_6
ANi_7
When ANi_0 to ANi_2 are prioritized (3 pins)
ANi_0
ANi_1
ANi_2
ANi_3
ANi_4
ANi_5
ANi_6
ANi_7
When ANi_0 to ANi_3 are prioritized (4 pins)
ANi_0
ANi_1
ANi_2
ANi_3
ANi_4
ANi_5
ANi_6
ANi_7
: A/D conversion
i = none, 15
Figure 18.7
Transition Diagram of Pins used in A/D Conversion in Repeat Sweep Mode 1
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 265 of 352
M32C/8A Group
18.1.6
18. A/D Converter
Multi-Port Single Sweep Mode
In multi-port single sweep mode, analog voltage applied to 16 selected pins is converted to a digital code once
for each pin. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode enabled).
Table 18.9 lists specifications of multi-port single sweep mode.
Table 18.9
Multi-Port Single Sweep Mode Specifications
Item
Specification
Function
Analog voltage applied to the 16 selected pins is repeatedly converted once for
each pin in the following order: AN_0 to AN_7 → AN15_0 to AN15_7
Analog input pins
• AN_0 → AN_1 → . . . → AN_7 → AN15_0 → AN15_1→ . . . → AN15_7
The following register settings determine which pins are used:
Bits MPS11 and MPS10 in the AD0CON4 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
• A sequence of A/D conversions is completed (the ADST bit becomes 0 when
software trigger is selected)
• Set the ADST bit to 0 by program (A/D conversion stops)
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed
(Set the DUS bit in the AD0CON3 register to 1)
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. Refer to 13. DMAC for DMAC settings. (Set the DUS bit in the
AD0CON3 register to 1)
Page 266 of 352
M32C/8A Group
18.1.7
18. A/D Converter
Multi-Port Repeat Sweep Mode 0
In multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly converted to
a digital code. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode enabled).
Table 18.10 lists specifications of multi-port repeat sweep mode 0.
Table 18.10
Multi-Port Repeat Sweep Mode 0 Specifications
Item
Specification
Function
Analog voltage applied to the 16 selected pins is repeatedly converted in the
following order: AN_0 to AN_7 → AN15_0 to AN15_7
Analog input pins
• AN_0 → AN_1 → . . . → AN_7 → AN15_0 → AN15_1→ . . . → AN15_7
The following register settings determine which pins are used:
Bits MPS11 and MPS10 in the AD0CON4 register
Start condition
Software trigger is selected. (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
• TRG0 bit = 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
Stop condition
Set the ADST bit is set to 0 (A/D conversion stops)
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed
(Set the DUS bit in the AD0CON3 register to 1)
Read of A/D conversion result
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit in the
AD0CON3 register to 1)
Page 267 of 352
M32C/8A Group
18.2
18. A/D Converter
Functions
18.2.1
Resolution
The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to 1 (10-bit mode),
the A/D conversion result is stored into bits 9 to 0 in the AD0i register (i = 0 to 7). When the BITS bit is set to 0
(8-bit mode), the A/D conversion result is stored into bits 7 to 0 in the AD0i register.
18.2.2
Sample and Hold
When the SMP bit in the AD0CON2 register is set to 1 (with sample and hold), the A/D conversion rate per pin
increases to 28 φAD cycles for 8-bit resolution and 33 φAD cycles for 10-bit resolution. The sample and hold
function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold
circuit is used or not.
18.2.3
Trigger Select Function
The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register determine a trigger to start
A/D conversion. Table 18.11 lists setting values for the trigger select function.
Table 18.11
Trigger Select Function Setting Values
Bit and Setting
Trigger
AD0CON0 Register
AD0CON2 Register
TRG = 0
−
TRG = 1(1)
TRG0 = 0
External trigger(2)
Falling edge of a signal applied to ADTRG
TRG0 = 1
Hardware trigger(2)
Timer B2 interrupt request of three-phase motor control timer
function (after the ICTB2 register completes counting)
Software trigger
A/D conversion starts when the ADST bit in the AD0CON0
register is set to 1
NOTES:
1. A/D conversion starts when the ADST bit is set to 1 (A/D conversion starts) and a trigger is generated.
2. A/D conversion starts over from the beginning, if an external trigger or a hardware trigger is inserted during
A/D conversion. (A/D conversion in progress is aborted.)
18.2.4
DMAC Operating Mode
DMAC operating mode is available in all operating modes. To select multi-port single sweep mode or multiport repeat sweep mode 0, DMAC operating mode must be used. When the DUS bit in the AD0CON3 register
is set to 1 (DMAC operating mode used), all A/D conversion results are stored into the AD00 register. DMAC
transfers the result from the AD00 register to a given memory space every time A/D conversion on a single pin
is completed. 8-bit DMA transfer must be selected for 8-bit resolution and 16-bit DMA transfer for 10-bit
resolution. Refer to 13. DMAC for DMAC instructions.
When using DMAC operating mode in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multiport single sweep mode, or multi-port repeat sweep mode 0, do not generate an external retrigger or hardware
retrigger.
18.2.5
Extended Analog Input Pins
In one-shot mode and repeat mode, the ANEX0 pin or ANEX1 pin can be used as the analog input pin. These
pins can be selected using bits OPA1 and OPA0 in the AD0CON1 register. The A/D conversion result for
ANEX0 input is stored into the AD00 register, and for ANEX1 input into the AD01 register. Both results are
stored into the AD00 register when the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode
used).
Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1) and the MSS bit
in the AD0CON3 register to 0 (multi-port sweep mode not used).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 268 of 352
M32C/8A Group
18.2.6
18. A/D Converter
External Operating Amplifier (Op-Amp) Connection Mode
In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using
extended analog input pins, ANEX0 and ANEX1.
When bits OPA1 and OPA0 are set to 11b (external op-amp connection), voltage applied to pins AN_0 to AN_7
are output from the ANEX0. Amplify this output signal by external op-amp and apply it to the ANEX1.
Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the
corresponding AD0i register (i = 0 to 7). The A/D conversion rate varies depending on the response
characteristics of the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly.
Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1).
Figure 18.8 shows a connection example of external op-amp connection mode.
Table 18.12
Extended Analog Input Pin Settings
AD0CON1 Register
OPA1 Bit
OPA0 Bit
0
0
ANEX0 Function
ANEX1 Function
Not used
Not used
0
1
P9_5 as an analog input
Not used
1
0
Not used
P9_6 as an analog input
1
1
Output to external op-amp
Input from external op-amp
Resistor ladder
AN_0
AN_1
AN_2
AN_3
Analog input
AN_4
Successive conversion register
AN_5
AN_6
AN_7
ANEX0
00b
ANEX1
External op-amp
Figure 18.8
18.2.7
Bits APS1 and APS0 in
the AD0CON2 register
Comparator
Connection Example in External Op-Amp Connection Mode
Power Consumption Reduce Function
When not using the A/D converter, the VCUT bit in the AD0CON1 register can disconnect the resistor ladder
of the A/D converter from the reference voltage input pin (VREF). As a result, power consumption can be
reduced by shutting off any current flow into the resistor ladder from the VREF pin.
When using the A/D converter, set the VCUT bit to 1 (VREF connected) prior to setting the ADST bit in the
AD0CON0 register to 1 (A/D conversion starts).
Do not set the VCUT bit to 0 (VREF not connected) during A/D conversion.
Even if the VCUT bit is set to 0, VREF remains connected to the D/A converter.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 269 of 352
M32C/8A Group
18.3
18. A/D Converter
Read from the AD0i Register (i = 0 to 7)
Use the following procedure to read the AD0i register by program.
• In one-shot mode and single sweep mode:
Ensure that the A/D conversion is completed before reading the corresponding AD0i register. The IR bit in the
AD0IC register becomes 1 when the A/D conversion is completed.
• In repeat mode, repeat sweep mode 0, and repeat sweep mode 1:
Read the AD0i register after setting the CPU clock as follows.
(1) Set the CM07 bit in the CM0 register to 0 (clock selected by the CM21 bit divided by the MCD
register).
(2) Set the MCD register to 12h (no division).
18.4
Output Impedance of Sensor Equivalent Circuit under A/D Conversion
To take full advantage of the A/D converter performance, Internal capacitor (C) charge shown in Figure 18.9
must be completed within the specified period (T) as sampling time. Output impedance of the sensor equivalent
circuit (R0) is determined by the following equation:
1
– ----------------------------t
⎧
C ( R0 + R ) ⎫
VC = VIN ⎨ 1 – e
⎬
⎩
⎭
X
⎛
VC = VIN – ---- VIN = VIN 1 – X
----⎞⎠
⎝
Y
Y
When t = T,
e
1
– ---------------------------- T
C ( R0 + R )
X
= ---Y
1
X
– ---------------------------- T = ln ---C ( R0 + R )
Y
T –R
R0 = – ------------X
C ln ---Y
where:
VC = Internal capacitor voltage
R = Internal resistance of the MCU
X = Accuracy (error) of the A/D converter
Y = Resolution (1024 in 10-bit mode, and 256 in 8-bit mode)
Figure 18.9 shows a connection example of analog input pin and external sensor equivalent circuit.
In the following example, the impedance R0 is obtained from the equation above when VC changes from 0 to
VIN-(1/1024)VIN within the time (T), if the difference between VIN and VC becomes 1LSB. (1/1024) means
that A/D accuracy drop, due to insufficient capacitor charge, is held to 1LSB at time of A/D conversion in the
10-bit mode. Actual error, however, is the value of absolute accuracy added to 1LSB.
When φAD = 10 MHz, T = 0.3 μs in A/D conversion with the sample and hold function. Output impedance
(R0) enough to complete charging the capacitor (C) within the time (T) is determined by the following
equation:
Using T = 0.3 μs, R = 2.0 kΩ, C = 7.5 pF, X = 1, Y = 1024,
–6
3
0.3 × 10
R0 = – ---------------------------------------------------– 2.0 × 10 ≅ 3.8 × 10 3 Ω
– 12
1
7.5 × 10
⋅ ln ------------1024
Thus, the allowable output impedance R0 of the sensor equivalent circuit, making the accuracy (error) 1LSB or
less, is approximately 3.8 kΩ maximum.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 270 of 352
M32C/8A Group
18. A/D Converter
Sensor equivalent
Circuit
R0
MCU
R (2.0 kΩ)
VIN
C (7.5 pF)
VC
Sampling time
Sample and hold is enabled :
Sample and hold is disabled :
Figure 18.9
Analog Input Pin and External Sensor Equivalent Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 271 of 352
3
φAD
2
φAD
M32C/8A Group
19. D/A Converter
19. D/A Converter
The D/A converter consists of two independent 8-bit R-2R ladder D/A converter circuits.
Digital code is converted to an analog voltage every time a value to be converted is written to the corresponding DAi
register (i = 0, 1).
The DAiE bit in the DACON register determines whether the D/A conversion result is output or not. When the DAiE
bit is set to 1 (input enabled), the corresponding port cannot be pulled up.
When the D/A converter is not used, set the DAi register to 00h and the DAiE bit to 0 (output disabled).
Output analog voltage (V) is obtained from the value n (n = decimal) set in the DAi register.
V=
VREF x n
256
(n = 0 to 255)
VREF: Reference voltage (VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0)
Table 19.1 lists specifications of the D/A converter. Figure 19.1 shows a block diagram of the D/A converter. Table
19.2 lists pin settings of DA0 and DA1. Figure 19.2 shows registers associated with the D/A converter. Figure 19.3
shows a D/A converter equivalent circuit.
Table 19.1
D/A Converter Specifications
Item
Specification
D/A conversion method
R-2R
Resolution
8 bits
Analog output pin
2 channels
Low-order bits of data bus
DA0E
0
DA0
DA0 Register
1
R-2R Resistor Ladder
DA1E
0
DA1
DA1 Register
1
R-2R Resistor Ladder
Figure 19.1
Table 19.2
Port
DA0E, DA1E: Bits in the DACON register
D/A Converter Block Diagram
Pin Settings
Function
Bit Setting
PD9 Register(2)
PSL3 Register
PS3 Register(1)(2)
P9_3
DA0 output
PD9_3=0
PSL3_3=1
PS3_3=0
P9_4
DA1 output
PD9_4=0
PSL3_4=1
PS3_4=0
NOTES:
1. Set the PS3 register after setting other registers.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 272 of 352
M32C/8A Group
19. D/A Converter
D/A Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
DACON
039Ch
XXXX XX00b
Bit Symbol
Bit Name
Function
RW
DA0E
D/A0 output enable bit
0: Output disabled
1: Output enabled
RW
DA1E
D/A1 output enable bit
0: Output disabled
1: Output enabled
RW
−
(b7-b2)
Unimplemented.
Write 0. Read as undefined value.
−
D/A Register i (i = 0,1)
b7
Symbol
DA0, DA1
b0
Address
0398h, 039Ah
After Reset
Undefined
Function
Output value of D/A conversion
Figure 19.2
Setting Range
RW
00h to FFh
RW
DACON Register, DA0 and DA1 Registers
DA0E
0
R
R
R
R
R
R
2R
R
r
DA0
1
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
Set in the DA0 register
0
1
AVSS
VREF(4)
NOTES:
1. The above applies when the DA0 register is set to 2Ah.
2. D/A1 has the same circuitry as the avove.
3. When the D/A converter is not used, set the DAiE bit (i = 0,1) in the DACON register to 0 (output disabled) and the DAi
register to 00h to stop current from flowing into the R-2R resistor to reduce unnecessary power consumption.
4. VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected).
Figure 19.3
D/A Converter Equivalent Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 273 of 352
M32C/8A Group
20. CRC Calculation
20. CRC Calculation
The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial of CRC CCITT (X16 + X12 + X5 + 1) generates CRC code.
The CRC code is a 16-bit code generated for a given length of the data block in bytes. The CRC code is stored in the
CRCD register every time one-byte data is transferred to the CRCIN register after a default value is written to the
CRCD register. CRC code generation for one-byte data is completed in two bus clock cycles.
Figure 20.1 shows a block diagram of the CRC circuit. Figure 20.2 shows CRC-associated registers. Figure 20.3
shows an example of the CRC calculation.
High-order bits of data bus
Low-order bits of data bus
8 low-order bits
8 high-order bits
CRCD register
CRC code generation circuit
X16 + X12 + X5 + 1
CRCIN register
Figure 20.1
CRC Calculation Block Diagram
CRC Data Register
b15
b8 b7
b0
Symbol
CRCD
Address
037Dh - 037Ch
Function
After default value is written to the CRCD register, the CRC code
can be read from the CRCD register by writing data to the CRCIN
register. Bit position of the default value is inverted. The inverted
value is read as the CRC code.
After Reset
Undefined
Setting Range
RW
0000h to FFFFh
RW
CRC Input Register
b7
b0
Symbol
Adddress
037Eh
CRCIN
Function
Data input.
Inverse bit position of data
Figure 20.2
CRCD Register, CRCIN Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 274 of 352
After Reset
Undefined
Setting Range
RW
00h to FFh
RW
M32C/8A Group
20. CRC Calculation
CRC Calculation and Setup Procedure to Generate CRC Code for 80C4h
CRC Calculation for M32C
CRC code: a remainder of division,
value of the CRCIN register with inversed bit position
Generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
Setting Steps
(1) Invert a bit position of 80C4h per byte by program
80h
01h, C4h
23h
b15
b0
CRCD register
(2) Set 0000h (default value)
b7
b0
(3) Set 01h
CRCIN register
Bit position of the CRC code for 80h (9188h)
is inverted to 1189h, which is stored into the
CRCD register in the 3rd cycle.
b15
b0
CRCD register
1189h
b7
b0
(4) Set 23h
CRCIN register
Bit position of the CRC code for 80C4h
(8250h) is inverted to 0A41h, which is stored
into the CRCD register in the 3rd cycle.
b15
b0
CRCD register
0A41h
Details of CRC Calculation
As shown in (3) above, bit position of 01h (00000001b) written to the CRCIN register is inverted to 10000000b.
Add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000h as the default value of the
CRCD register to perform the modulo-2 division.
1000 1000
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
Generator
polynomial
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
Data
Modulo-2 Arithmetic is
calculated on the law below
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
CRC code
0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can be
read from the CRCD register.
When going on to (4) above, 23h (00100011b) written in the CRCIN register is inverted to 11000100b.
Add 1100 0100 0000 0000 0000 0000b plus 16 digits, to 1001 0001 1000 1000b as a remainder of (3) left in the
CRCD register to perform the modulo-2 division.
0000 1010 0100 0001b (0A41h), the remainder with inverted bit position, can be read from CRCD register.
Figure 20.3
CRC Calculation
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 275 of 352
M32C/8A Group
21. X/Y Conversion
21. X/Y Conversion
The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and also inverts high-order bits and low-order bits of a
16-bit data. Figure 21.1 shows the XYC register.
The 16-bit XiR register (i = 0 to 15) and 16-bit YjR register (j = 0 to 15) are allocated to the same address. The XiR
register is a write-only register, while the YjR register is a read-only register. Access registers XiR and YjR from an
even address in 16-bit units. Performance cannot be guaranteed if registers XiR and YjR are accessed in 8-bit units.
X/Y Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XYC
Address
02E0h
Bit
Symbol
XXXX XX00b
Function
RW
XYC0
Read mode set bit
0: Data converted
1: Data not converted
RW
XYC1
Write mode set bit
0: Bit alignment not converted
1: Bit alignment converted
RW
−
(b7-b2)
Figure 21.1
Bit Name
After Reset
Unimplemented.
Write 0. Read as undefined value.
−
XYC Register
The XYC0 bit in the XYC register determines how to read the YjR register.
When setting the XYC0 bit to 0 (data converted) and reading the YjR register, all the bits j in registers X0R to X15R
can be read.
For example, bit 0 in the X0R register can be read when reading bit 0 in the Y0R register, bit 0 in the X1R register
when reading bit 1 in the Y0R register..., bit 0 in the X14R register when reading bit 14 in the Y0R register, and bit 0 in
the X15R register when reading bit 15 in the Y0R register.
Figure 21.2 shows a conversion table when the XYC0 bit is set to 0. Figure 21.3 shows an example of the X/Y
conversion.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 276 of 352
M32C/8A Group
21. X/Y Conversion
b0
Y1R register
Y0R register
Y3R register
Y2R register
Y5R register
Y4R register
Y8R register
Y7R register
Y6R register
Y10R register
Y9R register
Y12R register
Y11R register
Y15R register
Y14R register
Y13R register
Read address
X0R register
X1R register
X2R register
X3R register
Bits in YjR register
X4R register
X5R register
X6R register
X7R register
Write address
X8R register
X9R register
X10R register
X11R register
X12R register
X13R register
b15
X14R register
X15R register
b15
i = 0 to 15
j = 0 to 15
b0
Bits in XiR register
X0R register
Y0R register
X1R register
Y1R register
X2R register
Y2R register
X3R register
Y3R register
X4R register
Y4R register
X5R register
Y5R register
X6R register
Y6R register
X7R register
Y7R register
X8R register
Y8R register
X9R register
Y9R register
X10R register
Y10R register
X11R register
Y11R register
X12R register
Y12R register
X13R register
Y13R register
X14R register
Y14R register
X15R register
Y15R register
Figure 21.3
X/Y Conversion
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 277 of 352
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
Conversion Table when the XYC0 Bit is Set to 0
b14
b15
Figure 21.2
M32C/8A Group
21. X/Y Conversion
When setting the XYC0 bit in the XYC register to 1 (data not converted) and reading the YjR register, the value
written to the XiR register can be read. Figure 21.4 shows a conversion table when the XYC0 bit is set to 1.
Write address
Read address
X0R register,
Y0R register
X1R register,
Y1R register
X2R register,
Y2R register
X3R register,
Y3R register
X4R register,
Y4R register
X5R register,
Y5R register
X6R register,
Y6R register
X7R register,
Y7R register
X8R register,
Y8R register
X9R register,
Y9R register
X10R register, Y10R register
X11R register, Y11R register
X12R register, Y12R register
X13R register, Y13R register
X14R register, Y14R register
X15R register, Y15R register
b15
b0
Bits in XiR register
Bits in YjR register
Figure 21.4
i = 0 to 15
j = 0 to 15
Conversion Table when the XYC0 Bit is Set to 1
The XYC1 bit in the XYC register selects bit alignment written to the XiR register.
When the XYC1 bit is set to 0 (bit alignment not converted) and writing to the XiR register, bit alignment is written as
is. When the XYC1 bit is set to 1 (bit alignment converted) and writing to the XiR register, inverted bit alignment is
written.
Figure 21.5 shows a conversion when the XYC1 bit is set to 1.
b15
b0
Write data
b15
XiR register
(i = 0 to 15)
Figure 21.5
Conversion when the XYC1 Bit is Set to 1
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 278 of 352
b0
M32C/8A Group
22. Programmable I/O Ports
22. Programmable I/O Ports
75 programmable I/O ports, P6 to P15 (excluding P8_5), are available in the 144-pin package, and 39 programmable
I/O ports, P6 to P10 (excluding P8_5), are available in the 100-pin package. In microprocessor mode, P0 to P5 function
as bus control pins and cannot be used as I/O ports. P1_0 to P1_7, however, can be used as I/O ports when using with
8-bit external bus width only. The Port Pi Direction Registers determine individual port status, input or output. The
pull-up control registers determine whether the ports, divided into groups of four, are pulled up or not. P8_5 is an
input-only port and cannot be pulled up internally. The P8_5 bit in the P8 register indicates an NMI input level since
P8_5 shares its pin with NMI.
Figures 22.1 to 22.4 show programmable I/O port configurations.
Each pin functions as a programmable I/O port or I/O pin for internal peripheral functions, or bus control pin.
To use as an I/O pin for peripheral functions, refer to the description for individual peripheral functions. Refer to
8. Bus when used as a bus control pin.
Registers associated with the programmable I/O ports are as follows.
22.1
Port Pi Direction Register (PDi Register, i = 0 to 15)
Figure 22.5 shows the PDi register.
The PDi register configures a programmable I/O port as either input or output. Each bit in the PDi register
corresponds to one port.
In microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to
A22, A23, D0 to D15, CS0 to CS3, WRL / WR, WRH / BHE, RD, BCLK / ALE / CLKOUT, HLDA / ALE,
HOLD, ALE, and RDY. No bit controlling P8_5 is provided in the PDi register.
22.2
Port Pi Register (Pi Register, i = 0 to 15)
Figure 22.6 shows the Pi register.
The MCU inputs/outputs data from/to external devices by reading and writing to the Pi register. The Pi register
consists of a port latch to hold output data and a circuit to read the pin level. Each bit in the Pi register corresponds
to one port.
In microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written, nor read
the port level: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH / BHE, RD, BCLK / ALE / CLKOUT,
HLDA / ALE, HOLD, ALE, and RDY.
22.3
Function Select Register A (PSj Register, j = 0 to 3)
Figures 22.7 to 22.8 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if these functions share a single pin (excluding
DA0 and DA1).
When multiple peripheral function outputs are assigned to a single pin, set registers PSL0 to PSL3, and PSC to
select which function to use.
Tables 22.2 to 22.6 list peripheral function output control settings for each pin.
22.4
Function Select Register B (PSLk Register, k = 0 to 3)
Figures 22.9 to 22.10 show the PSLk register.
When multiple peripheral function outputs are assigned to a single pin, the PSLk register select which peripheral
function output to use.
Refer to 22.8 Analog Input and Other Peripheral Function Input for information on bits PSL3_3 to PSL3_6 in
the PSL3 register.
22.5
Function Select Register C (PSC Register)
Figure 22.11 shows the PSC register.
When multiple peripheral function outputs are assigned to a single pin, the PSC register selects which peripheral
function output to use.
Refer to 22.8 Analog Input and Other Peripheral Function Input for information on the PSC_7 bit in the PSC
register.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 279 of 352
M32C/8A Group
22.6
22. Programmable I/O Ports
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
Figures 22.12 to 22.15 show registers PUR0 to PUR4.
Registers PUR0 to PUR4 select whether the ports, divided into groups of four, are pulled up or not. Set the bit in
registers PUR0 to PUR4 to 1 (pull-up) and the bit in the PDi register to 0 (input mode) to pull-up the corresponding
port.
In microprocessor mode, set bits, corresponding to the bus control pins (P0 to P5), in registers PUR0 and PUR1 to
0 (no pull-up). P1 can be pulled up when they are used as input ports in microprocessor mode.
22.7
Port Control Register (PCR Register)
Figure 22.16 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. When the
PCR0 bit is set to 1, P channel in the CMOS port is turned off at all times and in result port P1 becomes N-channel
open drain output. This is, however, pseudo open drain. Therefore, the absolute maximum rating of the input
voltage is from -0.3 V to VCC2 + 0.3 V.
To use port P1 as data bus in microprocessor mode, set the PCR0 bit to 0 (CMOS output). When port P1 is used as
a port in microprocessor mode, set the output format using the PCR0 bit.
22.8
Analog Input and Other Peripheral Function Input
Bits PSL3_3 to PSL3_6 in the PSL3 register, and the PSC_7 bit in the PSC register separate peripheral function
inputs from analog input/output. If the analog I/O shares the pin with other peripheral function inputs, a through
current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin.
To use the analog I/O (DA0, DA1, ANEX0, ANEX1, or AN_4 to AN_7), set the corresponding bit to 1 (analog I/
O), and disconnect the peripheral function inputs to prevent an intermediate voltage from being applied to the
peripheral function inputs.
Set the corresponding bit to 0 (except analog I/O) when analog I/O is not used. All the peripheral function inputs
except the analog I/O are enabled when the corresponding bit is set to 0, and undefined when the bit is set to 1.
When the PSC_7 bit is set to 1, the IR bit in the KUPIC register remains unchanged as 0 even if KI0 to KI3 pin
input levels are changed.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 280 of 352
M32C/8A Group
22. Programmable I/O Ports
Programmable I/O ports
Pull-up select
PDi register
Port latch
Data bus
A
Peripheral
function input
B
Peripheral
function input
Option
Port
C
(A)
Hysteresis
(B)
Peripheral function
input
(C)
Peripheral function
input
−
−
−
−
−
−
−
−
P0_0 to P0_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_2
P5_5, P5_7
−
P8_3, P8_4
−
P8_6, P8_7
: Available
Figure 22.1
−: Not available
Programmable I/O Ports (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 281 of 352
−
−
M32C/8A Group
22. Programmable I/O Ports
Programmable I/O ports with the port control register
Pull-up select
PDi register
PCR0 bit
Port latch
Data bus
A
Peripheral
function input
B
PCR0 bit: bit in the PCR register
Option
Port
(A)
Hysteresis
(B)
Peripheral function
input
−
−
P1_0 to P1_4
P1_5 to P1_7
: Available
−: Not available
Programmable I/O ports with the function select register
INV03
Value written to INV03 bit
D
Write signal to INV03 bit
T
RESET
NMI
INV05
Q
R
INV02
Pull-up select
Registers PS1 and PS2
PDi register
Peripheral function output
Port latch
Data bus
Peripheral function input
Port P7_2 to P7_5, P8_0, P8_1
Figure 22.2
Programmable I/O Ports (2)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 282 of 352
M32C/8A Group
22. Programmable I/O Ports
Programmable I/O ports with the function select register
E
Pull-up select
Registers PS0 to PS3(1, 2)
PDi register
Peripheral function output
Port latch
Data bus
A
Peripheral
function input
B
Peripheral
function input
C
Analog signal
D
Port
(A)
Hysteresis
(B)
Peripheral
fucntion input
(C)
Peripheral
fucntion input
(D)
Analog I/F
P5_3(1)
−
−
−
−
P5_4, P5_6(2)
−
−
−
−
P6_0 to P6_7
−
−
−
P7_0, P7_1(3)
−
−
−
P7_6, P7_7
−
−
−
P9_0 to P9_2
−
−
P9_3 to P9_6
−
−
P9_7
−
−
P10_0 to P10_3
−
−
P11_0 to P11_3
−
−
−
−
P11_4, P12_0
−
−
−
−
P12_1 to P12_3
−
−
−
−
−
−
−
−
P13_5, P13_6
−
−
−
−
P13_7
−
−
−
−
P14_0 to P14_3
−
−
−
−
P14_4 to P14_6
−
−
−
−
P15_0
−
−
−
P15_1 to P15_3
−
−
−
P15_4
−
−
−
P15_5 to P15_7
−
−
−
Option
P8_2
−
P10_4 to P10_7
P12_4 to P12_7
P13_0 to P13_4
(note 4)
(E)
Circuit
−
−
−
−
−
−
: Available −: Not available
NOTES:
1. For P5_3, use the PM07 bit in the PM0 register, bits PM15 and PM14 in the PM1 register, and bits
CM01 and CM00 in the CM0 register to select CLKOUT or ALE output.
2. For P5_4 and P5_6, use bits PM15 and PM14 to select ALE output.
3. P7_0 and P7_1 are N-channel open drain output ports.
4. These ports are provided in the 144-pin package only.
Figure 22.3
Programmable I/O Ports (3)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 283 of 352
M32C/8A Group
22. Programmable I/O Ports
Input-only port (P8_5)
Data bus
NMI
Figure 22.4
Programmable I/O Ports (4)
Port Pi Direction Register (i = 0 to 15)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD0 to PD3
PD4 to PD7
PD8
PD9, PD10
PD11
PD12, PD13
PD14
PD15
Bit Symbol
Address
03E2h, 03E3h, 03E6h, 03E7h
03EAh, 03EBh, 03C2h, 03C3h
03C6h(4)
03C7h(1), 03CAh
03CBh(3, 4)
03CEh, 03CFh(3)
03D2h(3, 4)
03D3h(3)
Bit Name
After Reset
00h
00h
00X0 0000b
00h
XXX0 0000b
00h
X000 0000b
00h
Function
RW
PDi_0
Port Pi_0 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_1
Port Pi_1 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_2
Port Pi_2 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_3
Port Pi_3 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_4
Port Pi_4 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_5
Port Pi_5 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_6
Port Pi_6 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
PDi_7
Port Pi_7 direction bit
0: Input mode (functions as input port)
1: Output mode (functions as output port)
RW
NOTES:
1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt
or a DMA or DMACII transfer between these two instructions.
2. In microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to A22, A23,
D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, ALE, ALE, RDY.
3. Set registers PD11 to PD15 to FFh in the 100-pin package.
4. Nothing is implemented to the PD8_5 bit in the PD8 register, bits PD11_7 to PD11_5 in the PD11 register, and the P14_7 bit in
the PD14 register. Write a 0. A read from these bits returns undefined value.
Figure 22.5
PD0 to PD15 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 284 of 352
M32C/8A Group
22. Programmable I/O Ports
Port Pi Register (1, 2) (i = 0 to 15)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
P0 to P5
P6 to P10
P11 to P15
03E0h, 03E1h, 03E4h, 03E5h, 03E8h, 03E9h
03C0h, 03C1h(3), 03C4h(4), 03C5h, 03C8h
03C9h(5), 03CCh, 03CDh, 03D0h(5), 03D1h
Undefined
Undefined
Undefined
Bit Symbol
Bit Name
Pi_0
Port Pi_0 bit
Pi_1
Port Pi_1 bit
Function
Input mode
(The PDi_j bit (j = 0 to 7) in the PDi register = 0)
Read: Return the pin level.
Write: Write to the port latch.
RW
RW
RW
Output mode
(The PDi_j bit in the PDi register = 1)
Read: Return the port latch value.
Write: Write to the port latch and the port latch
value is output from the pin.
Pi_2
Port Pi_2 bit
Pi_3
Port Pi_3 bit
Pi_4
Port Pi_4 bit
RW
Pi_5
Port Pi_5 bit
RW
Pi_6
Port Pi_6 bit
RW
Pi_7
Port Pi_7 bit
RW
0: "L" level
1: "H" level
RW
RW
NOTES:
1. In microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to
D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, ALE, ALE, RDY.
2. Ports P11 to P15 are provided in the 144-pin package only.
3. P7_0 and P7_1 are N-channel open drain output ports. The pins are placed into high-impedance states when the corresponding
bits to P7_0 and P7_1 are set to 1.
4. The P8_5 bit is a read-only bit.
5. Nothing is implemented to bits P11_5 to P11_7 in the P11 register and the P14_7 bit in the P14 register. Write a 0. A read from
these bits returns undefined value.
Figure 22.6
P0 to P15 Registers
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 285 of 352
M32C/8A Group
22. Programmable I/O Ports
Function Select Register A0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PS0
03B0h
00h
Bit Symbol
Bit Name
Function
RW
PS0_0
Port P6_0
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_0 bit
RW
PS0_1
Port P6_1
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_1 bit
RW
PS0_2
Port P6_2
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_2 bit
RW
PS0_3
Port P6_3
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_3 bit
RW
PS0_4
Port P6_4
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_4 bit
RW
PS0_5
Port P6_5
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_5 bit
RW
PS0_6
Port P6_6
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_6 bit
RW
PS0_7
Port P6_7
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL0_7 bit
RW
Function Select Register A1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PS1
03B1h
00h
Bit Symbol
Figure 22.7
Bit Name
RW
PS1_0
Port P7_0
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_0 bit
RW
PS1_1
Port P7_1
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_1 bit
RW
PS1_2
Port P7_2
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_2 bit
RW
PS1_3
Port P7_3
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_3 bit
RW
PS1_4
Port P7_4
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_4 bit
RW
PS1_5
Port P7_5
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_5 bit
RW
PS1_6
Port P7_6
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL1_6 bit
RW
PS1_7
Port P7_7
output function select bit
0: I/O port/peripheral function input
1: Do not set to this value
RW
PS0 Register, PS1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
Page 286 of 352
M32C/8A Group
22. Programmable I/O Ports
Function Select Register A2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0
PS2
03B4h
00X0 0000b
0 0
Bit Symbol
Bit Name
Function
RW
PS2_0
Port P8_0
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL2_0 bit
RW
PS2_1
Port P8_1
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL2_1 bit
RW
−
(b4-b2)
Reserved bits
Set to 0
RW
−
(b5)
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
Reserved bits
−
Set to 0
RW
Function Select Register A3(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PS3
03B5h
00h
Bit Symbol
Bit Name
Function
RW
PS3_0
Port P9_0
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL3_0 bit
RW
PS3_1
Port P9_1
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL3_1 bit
RW
PS3_2
Port P9_2
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL3_2 bit
RW
PS3_3
Port P9_3
output function select bit
0: I/O port/peripheral function input
1: RTS3
RW
PS3_4
Port P9_4
output function select bit
0: I/O port/peripheral function input
1: RTS4
RW
PS3_5
Port P9_5
output function select bit
0: I/O port/peripheral function input
1: CLK4 output
RW
PS3_6
Port P9_6
output function select bit
0: I/O port/peripheral function input
1: TXD4/SDA4 output
RW
PS3_7
Port P9_7
output function select bit
0: I/O port/peripheral function input
1: Select by the PSL3_7 bit
RW
NOTE:
1. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt
or a DMA or DMACII transfer between these two instructions.
Figure 22.8
PS2 Register, PS3 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 287 of 352
M32C/8A Group
22. Programmable I/O Ports
Function Select Register B0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0
PSL0
03B2h
00h
0 0 0
0 0
Bit Symbol
Bit Name
Function
RW
PSL0_0
Port P6_0 peripheral function
output select bit
0: RTS0
1: Do not set to this value
RW
PSL0_1
Port P6_1 peripheral function
output select bit
0: CLK0 output
1: Do not set to this value
RW
PSL0_2
Port P6_2 peripheral function
output select bit
0: SCL0 output
1: STXD0
RW
PSL0_3
Port P6_3 peripheral function
output select bit
0: TXD0/SDA0 output
1: Do not set to this value
RW
PSL0_4
Port P6_4 peripheral function
output select bit
0: RTS1
1: Do not set to this value
RW
PSL0_5
Port P6_5 peripheral function
output select bit
0: CLK1 output
1: Do not set to this value
RW
PSL0_6
Port P6_6 peripheral function
output select bit
0: SCL1 output
1: STXD1
RW
PSL0_7
Port P6_7 peripheral function
output select bit
0: TXD1/SDA1 output
1: Do not set to this value
RW
Function Select Register B1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 1 0
PSL1
03B3h
00h
Bit Symbol
RW
Port P7_0 peripheral function
output select bit
0: Select by the PSC_0 bit
1: TA0OUT output
RW
PSL1_1
Port P7_1 peripheral function
output select bit
0: Select by the PSC_1 bit
1: STXD2
RW
PSL1_2
Port P7_2 peripheral function
output select bit
0: Select by the PSC_2 bit
1: TA1OUT output
RW
PSL1_3
Port P7_3 peripheral function
output select bit
0: Select by the PSC_3 bit
1: V
RW
PSL1_4
Port P7_4 peripheral function
output select bit
0: Select by the PSC_4 bit
1: W
RW
PSL1_5
Port P7_5 peripheral function
output select bit
0: W
1: Do not set to this value
RW
PSL1_6
Port P7_6 peripheral function
output select bit
0: Do not set to this value
1: TA3OUT output
RW
Reserved bit
Set to 0
RW
PSL0 Register, PSL1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Function
PSL1_0
−
(b7)
Figure 22.9
Bit Name
Page 288 of 352
M32C/8A Group
22. Programmable I/O Ports
Function Select Register B2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0
PSL2
03B6h
00X0 0000b
0 0 0
Bit Symbol
Bit Name
Function
RW
PSL2_0
Port P8_0 peripheral function
output select bit
0: TA4OUT output
1: U
RW
PSL2_1
Port P8_1 peripheral function
output select bit
0: U
1: Do not set to this value
RW
−
(b4-b2)
Reserved bits
Set to 0
RW
−
(b5)
−
(b7-b6)
Unimplemented.
Write 0. Read as undefined value.
Reserved bits
−
Set to 0
RW
Function Select Register B3
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
Address
After Reset
PSL3
03B7h
00h
Bit Symbol
Bit Name
Function
PSL3_0
Port P9_0 peripheral function
output select bit
0: CLK3 output
1: Do not set to this value
RW
PSL3_1
Port P9_1 peripheral function
output select bit
0: SCL3 output
1: STXD3
RW
PSL3_2
Port P9_2 peripheral function
output select bit
0: TXD3/SDA3 output
1: Do not set to this value
RW
PSL3_3
Port P9_3 peripheral function
output select bit (1)
0: Peripheral function input
1: DA0
RW
PSL3_4
Port P9_4 peripheral function
output select bit (1)
0: Peripheral function input
1: DA1
RW
PSL3_5
Port P9_5 peripheral function
output select bit (1)
0: Peripheral function input except ANEX0
1: ANEX0
RW
PSL3_6
Port P9_6 peripheral function
output select bit (1)
0: Peripheral function input except ANEX1
1: ANEX1
RW
PSL3_7
Port P9_7 peripheral function
output select bit
0: SCL4 output
1: STXD4
RW
NOTE:
1. If DA0, DA1, ANEX0, and ANEX1 are used with the PSL3_i bit (i = 3 to 6) setting to 0, power consumption may increase.
Figure 22.10
PSL2 Register, PSL3 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 289 of 352
M32C/8A Group
22. Programmable I/O Ports
Function Select Register C
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0
Symbol
Address
After Reset
PSC
03AFh
00X0 0000b
Bit Symbol
Bit Name
Function
PSC_0
Port P7_0 peripheral function
output select bit
0: TXD2/SDA2 output
1: Do not set to this value
RW
PSC_1
Port P7_1 peripheral function
output select bit
0: SCL2 output
1: Do not set to this value
RW
PSC_2
Port P7_2 peripheral function
output select bit
0: CLK2 output
1: V
RW
PSC_3
Port P7_3 peripheral function
output select bit
0: RTS2
1: Do not set to this value
RW
PSC_4
Port P7_4 peripheral function
output select bit
0: TA2OUT output
1: Do not set to this value
RW
−
(b6-b5)
Reserved bits
Set to 0
RW
PSC_7
Port P10_4 to P10_7 peripheral
function input select bit
0: P10_4 to P10_7 or KI0 to KI3
1: AN_4 to AN_7(1)
RW
NOTE:
1. Set bits ILVL2 to ILVL0 in the KUPIC register to 000b (interrupt disabled) to change the PSC_7 bit.
If AN_4 to AN_7 are used with the PSC_7 bit setting to 0, power consumption may increase.
Figure 22.11
PSC Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 290 of 352
M32C/8A Group
22. Programmable I/O Ports
Pull-Up Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PUR0
03F0h
00h
Bit Symbol
Bit Name
Function
RW
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
PU00
P0_0 to P0_3 pull-up
RW
PU01
P0_4 to P0_7 pull-up
RW
PU02
P1_0 to P1_3 pull-up
RW
PU03
P1_4 to P1_7 pull-up
RW
PU04
P2_0 to P2_3 pull-up
RW
PU05
P2_4 to P2_7 pull-up
RW
PU06
P3_0 to P3_3 pull-up
RW
PU07
P3_4 to P3_7 pull-up
RW
NOTE:
1. In microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as
I/O ports, it can be selected whether the ports are pulled up or not.
Pull-Up Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PUR1
03F1h
XXXX 0000b
Bit Symbol
Bit Name
Function
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
RW
PU10
P4_0 to P4_3 pull-up
PU11
P4_4 to P4_7 pull-up
RW
PU12
P5_0 to P5_3 pull-up
RW
PU13
P5_4 to P5_7 pull-up
RW
−
(b7-b4)
Unimplemented.
Write 0. Read as undefined value.
RW
−
NOTE:
1. In microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as
I/O ports, it can be selected whether the ports are pulled up or not.
Figure 22.12
PUR0 Register, PUR1 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 291 of 352
M32C/8A Group
22. Programmable I/O Ports
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PUR2
03DAh
00h
Bit Symbol
Bit Name
P6_0 to P6_3 pull-up
PU21
P6_4 to P6_7 pull-up
RW
PU22
P7_2 to P7_3 pull-up(1)
RW
PU23
P7_4 to P7_7 pull-up
RW
PU24
P8_0 to P8_3 pull-up
RW
PU25
P8_4 to P8_7 pull-up(2)
RW
PU26
P9_0 to P9_3 pull-up
RW
PU27
P9_4 to P9_7 pull-up
RW
PUR2 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
RW
PU20
NOTES:
1. P7_0 and P7_1 cannot be pulled up.
2. P8_5 cannot be pulled up internally.
Figure 22.13
Function
Page 292 of 352
RW
M32C/8A Group
22. Programmable I/O Ports
Pull-Up Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
<144-pin package>
Symbol
Address
After Reset
PUR3
03DBh
00h
Bit Symbol
Function
Bit Name
RW
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
PU30
P10_0 to P10_3 pull-up
PU31
P10_4 to P10_7 pull-up
RW
PU32
P11_0 to P11_3 pull-up
RW
PU33
P11_4 pull-up
RW
PU34
P12_0 to P12_3 pull-up
RW
PU35
P12_4 to P12_7 pull-up
RW
PU36
P13_0 to P13_3 pull-up
RW
PU37
P13_4 to P13_7 pull-up
RW
Pull-Up Control Register 3
<100-pin package>
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
0 0 0 0 0 0
PUR3
03DBh
00h
Bit Name
Bit Symbol
PU30
P10_0 to P10_3 pull-up
PU31
P10_4 to P10_7 pull-up
−
(b7-b2)
Figure 22.14
Reserved bits
PUR3 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 293 of 352
RW
Function
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
RW
RW
RW
Set to 0
RW
M32C/8A Group
22. Programmable I/O Ports
Pull-Up Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
PUR4
03DCh
XXXX 0000b
Bit
Symbol
Bit Name
P14_0 to P14_3 pull-up
PU41
P14_4 to P14_6 pull-up
RW
PU42
P15_0 to P15_3 pull-up
RW
PU43
P15_4 to P15_7 pull-up
RW
Unimplemented.
Write 0. Read as undefined value.
NOTE:
1. Set the PUR4 register to 00h in the 100-pin package.
PUR4 Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Pull-up setting for the corresponding ports
0: Not pulled up
1: Pulled up
RW
PU40
−
(b7-b4)
Figure 22.15
Function
Page 294 of 352
RW
−
M32C/8A Group
22. Programmable I/O Ports
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
After Reset
PCR
03FFh
XXXX X000b
Bit Symbol
Bit Name
Function
PCR0
Port P1 control bit(1)
0: CMOS output
1: N-channel open drain output(2)
RW
−
(b2-b1)
Reserved bits
Set to 0
RW
−
(b7-b3)
Unimplemented.
Write 0. Read as undefined value.
NOTES:
1. In microprocessor mode, set the PCR0 bit to 0 since port P1 is used as data bus . When using port P1 as an I/O port,
CMOS or N-channel open drain output can be selected.
2. This function is designed to make pseudo open drain by always turning off P channel in the CMOS port . Therefore, the
absolute maximum rating of the input voltage is from -0.3 V to VCC + 0.3 V.
Figure 22.16
PCR Register
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
RW
Page 295 of 352
−
M32C/8A Group
Table 22.1
22. Programmable I/O Ports
Unassigned Pin Handling in Microprocessor Mode
Pin Name
Handling
P1, P6 to P15
(excluding P8_5)(1)
Set pins to input mode and connect each pin to VSS via a resistor (pull-down);
or set pins to output mode and leave them open
BHE, ALE, HLDA,
XOUT(2), BCLK
Leave the pin open
HOLD, RDY
Connect the pin to VCC2 via a resistor (pull-up)
NMI(P8_5)
Connect the pin to VCC1 via a resistor (pull-up)
VREF
Connect the pin to VSS
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. When the external clock is applied to the XIN pin.
MCU
(Input mode)
...
...
P1, P6 to P15(1)
(except for P8_5)
(Input mode)
(Output mode)
Open
VCC1
NMI (P8_5)
BHE
HLDA
ALE
XOUT
BCLK
HOLD
RDY
Open
VCC2
VCC1
AVCC
AVSS
VREF
VSS
In microprocessor mode
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Figure 22.17
Unassigned Pin Handling
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 296 of 352
M32C/8A Group
Table 22.2
22. Programmable I/O Ports
Port P6 Peripheral Function Output Control
PS0 Register
PSL0 Register
Bit 0
0: P6_0/CTS0/SS0
1: Select by the PSL0_0 bit
0: RTS0
1: Do not set to this value
Bit 1
0: P6_1/CLK0 input
1: Select by the PSL0_1 bit
0: CLK0 output
1: Do not set to this value
Bit 2
0: P6_2/RXD0/SCL0 input
1: Select by the PSL0_2 bit
0: SCL0 output
1: STXD0
Bit 3
0: P6_3/SRXD0/SDA0 input
1: Select by the PSL0_3 bit
0: TXD0/SDA0 output
1: Do not set to this value
Bit 4
0: P6_4/CTS1/SS1
1: Select by the PSL0_4 bit
0: RTS1
1: Do not set to this value
Bit 5
0: P6_5/CKL1 input
1: Select by the PSL0_5 bit
0: CLK1 output
1: Do not set to this value
Bit 6
0: P6_6/RXD1/SCL1 input
1: Select by the PSL0_6 bit
0: SCL1 output
1: STXD1
Bit 7
0: P6_7/SRXD1/SDA1 input
1: Select by the PSL0_7 bit
0: TXD1/SDA1 output
1: Do not set to this value
Table 22.3
Port P7 Peripheral Function Output Control
PS1 Register
PSL1 Register
PSC Register
Bit 0
0: P7_0/TA0OUT input/
SRXD2/SDA2 input
1: Select by the
PSL1_0 bit
0: Select by the PSC_0 bit
1: TA0OUT output
0: TXD2/SDA2 output
1: Do not set to this value
Bit 1
0: P7_1/TA0IN/TB5IN/RXD2/
SCL2 input
1: Select by the
PSL1_1 bit
0: Select by the PSC_1 bit
1: STXD2
0: SCL2 output
1: Do not set to this value
Bit 2
0: P7_2/TA1OUT input/
CLK2 input
1: Select by the PSL1_2 bit
0: Select by the PSC_2 bit
1: TA1OUT output
0: CLK2 output
1: V
Bit 3
0: P7_3/TA1IN/CTS2/SS2
1: Select by the PSL1_3 bit
0: Select by the PSC_3 bit
1: V
0: RTS2
1: Do not set to this value
Bit 4
0: P7_4/TA2OUT input
1: Select by the PSL1_4 bit
0: Select by the PSC_4 bit
1: W
0: TA2OUT output
1: Do not set to this value
Bit 5
0: P7_5/TA2IN
1: Select by the PSL1_5 bit
0: W
1: Do not set to this value
Set to 0
Bit 6
0: P7_6/TA3OUT input
1: Select by the PSL1_6 bit
0: Do not set to this value
1: TA3OUT output
Set to 0
Bit 7
0: P7_7/TA3IN
1: Do not set to this value
Set to 0
−
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 297 of 352
M32C/8A Group
Table 22.4
22. Programmable I/O Ports
Port P8 Peripheral Function Output Control
PS2 Register
PSL2 Register
Bit 0
0: P8_0/TA4OUT input
1: Select by the PSL2_0 bit
0: TA4OUT output
1: U
Bit 1
0: P8_1/TA4IN
1: Select by the PSL2_1 bit
0: U
1: Do not set to this value
Bits 2 to 7 Set to 000000b
Table 22.5
Port P9 Peripheral Function Output Control
PS3 Register
PSL3 Register
Bit 0
0: P9_0/TB0IN/CLK3 input
1: Select by the PSL3_0 bit
0: CLK3 output
1: Do not set to this value
Bit 1
0: P9_1/TB1IN/RXD3/SCL3 input
1: Select by the PSL3_1 bit
0: SCL3 output
1: STXD3
Bit 2
0: P9_2/TB2IN/SRXD3/SDA3 input
1: Select by the PSL3_2 bit
0: TXD3/SDA3 output
1: Do not set to this value
Bit 3
0: P9_3/TB3IN/CTS3/SS3/DA0
1: RTS3
0: Peripheral function input
1: DA0
Bit 4
0: P9_4/TB4IN/CTS4/SS4/DA1
1: RTS4
0: Peripheral function input
1: DA1
Bit 5
0: P9_5/ANEX0/CLK4 input
1: CLK4 output
0: Peripheral function input except ANEX0
1: ANEX0
Bit 6
0: P9_6/SRXD4/ANEX1/SDA4 input
1: TXD4/SDA4 output
0: Peripheral function input except ANEX1
1: ANEX1
Bit 7
0: P9_7/RXD4 input/ADTRG/SCL4 input
1: Select by the PSL3_7 bit
0: SCL4 output
1: STXD4
Table 22.6
Port P10 Peripheral Function Input Control
PSC Register
Bit 7
0: P10_4 to P10_7 or KI0 to KI3
1: AN_4 to AN_7
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 298 of 352
M32C/8A Group
23. Electrical Characteristics
23. Electrical Characteristics
Table 23.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
Value
Unit
VCC1,
VCC2
Supply voltage
VCC1 = AVCC
-0.3 to 6.0
V
VCC2
Supply voltage
−
-0.3 to VCC1 + 0.1
V
AVCC
Analog supply voltage
VCC1 = AVCC
-0.3 to 6.0
V
VI
Input voltage
RESET, CNVSS, BYTE, P6_0 to P6_7,
P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1),
VREF, XIN
-0.3 to VCC1 + 0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
-0.3 to VCC2 + 0.3
P7_0, P7_1
VO
Output voltage
-0.3 to 6.0
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P14_0 to 14_6, P15_0 to P15_7(1),
XOUT
-0.3 to VCC1 + 0.3
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
-0.3 to VCC2 + 0.3
P7_0, P7_1
Pd
Power dissipation
Topr
Tstg
V
-0.3 to 6.0
-40°C≤Topr≤85°C
500
mW
Operating ambient temperature
-20 to 85/
-40 to 85(2)
°C
Storage temperature
-65 to 150
°C
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. Contact a Renesas sales office if temperature range of -40 to 85°C is required.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 299 of 352
M32C/8A Group
Table 23.2
23. Electrical Characteristics
Recommended Operating Conditions (1)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified)
Symbol
Parameter
VCC1,
VCC2
Supply voltage (VCC1 ≥ VCC2)
AVCC
Analog supply voltage
VSS
Standard
Min.
Typ.
Max.
3.0
5.0
5.5
Unit
V
VCC1
V
Supply voltage
0
V
AVSS
Analog supply voltage
0
V
VIH
0.8VCC2
Input high “H” P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7,
voltage
P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(2)
VCC2
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1),
0.8VCC1
P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6,
P15_0 to P15_7(2),
XIN, RESET, CNVSS, BYTE
VCC1
VIL
Input low “L”
voltage
P7_0, P7_1
0.8VCC1
6.0
P0_0 to P0_7, P1_0 to P1_7
(in microprocessor mode)
0.5VCC2
VCC2
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(2)
0
0.2VCC2
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1),
P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6,
P15_0 to P15_7(2),
XIN, RESET, CNVSS, BYTE
0
0.2VCC1
P0_0 to P0_7, P1_0 to P1_7
(in microprocessor mode)
0
0.16VCC2
NOTES:
1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply
when P8_7 is used as XCIN.
2. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 300 of 352
V
V
M32C/8A Group
Table 23.3
23. Electrical Characteristics
Recommended Operating Conditions (2)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified
Symbol
Parameter
Standard
Min.
Typ.
Max.
Unit
IOH(peak)
Peak output
high “H”
current(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
-10.0
mA
IOH(avg)
Average
output “H”
current(1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
-5.0
mA
IOL(peak)
Peak output
“L” current(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
10.0
mA
IOL(avg)
Average
output “L”
current(1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
5.0
mA
NOTES:
1. Average output current is the average value within 100 ms.
2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less.
A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less.
A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less.
A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less.
A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less.
A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less.
3. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 301 of 352
M32C/8A Group
Table 23.4
23. Electrical Characteristics
Recommended Operating Conditions (3)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified)
Symbol
f(CPU)
f(XIN)
Standard
Parameter
Min.
Typ.
Max.
Unit
CPU clock frequency
(same frequency as f(BCLK))
VCC1 = 4.2 to 5.5V
0
32
MHz
VCC1 = 3.0 to 5.5V
0
24
MHz
Main clock input frequency
VCC1 = 4.2 to 5.5V
0
32
MHz
VCC1 = 3.0 to 5.5V
0
24
MHz
32.768
50
kHz
1
2
MHz
f(XCIN)
Sub clock frequency
f(Ring)
On-chip oscillator frequency
0.5
f(VCO)
VCO clock frequency (PLL frequency synthesizer)
20
80
MHz
f(PLL)
PLL clock frequency
VCC1 = 4.2 to 5.5V
10
32
MHz
VCC1 = 3.0 to 5.5V
10
24
MHz
VCC1 = 5.0V
5
ms
VCC1 = 3.3V
10
ms
tsu(PLL)
Wait time to stabilize PLL frequency
synthesizer
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 302 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 23.5
Electrical Characteristics (1)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless
otherwise specified)
Symbol
VOH
Parameter
Output
high “H”
voltage
Condition
IOH = -5 mA
VCC2 - 2.0
VCC2
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 μA VCC2 - 0.3
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
VCC2
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 μA VCC1 - 0.3
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
VCC1
XCOUT
IOH = -1 mA
V
V
2.5
V
Low drive
capability
No load
applied
1.6
V
XOUT
IOL = 5 mA
2.0
V
IOL = 200 μA
0.45
V
IOL = 1 mA
2.0
V
High drive
capability
No load
applied
0
V
Low drive
capability
No load
applied
0
V
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, ADTRG,
CTS0 to CTS4, CLK0 to CLK4,
TA0OUT to TA4OUT, NMI, KI0 to KI3,
RXD0 to RXD4, SCL0 to SCL4,
SDA0 to SDA4
0.2
1.0
V
RESET
0.2
1.8
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
VCC1
V
No load
applied
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
XCOUT
3.0
Unit
High drive
capability
Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“L” voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
VT+ - VT- Hysteresis
Standard
Typ. Max.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
XOUT
VOL
Min.
Page 303 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 23.6
Electrical Characteristics (2)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless
otherwise specified)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
IIH
Input high
“H” current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 5 V
5.0
μA
IIL
Input low “L” P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 0V
-5.0
μA
167
kΩ
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
RfXIN
Feedback
resistance
XIN
1.5
MΩ
RfXCIN
Feedback
resistance
XCIN
10
MΩ
VRAM
RAM data
retention
voltage
In stop mode
VI = 0V
20
40
2.0
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Table 23.7
Electrical Characteristics (3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25°C)
Symbol Parameter
ICC
Power
supply
current
Condition
ROMless
version
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
f(CPU) = 32 MHz
f(CPU) = 16 MHz
f(CPU) = 8 MHz
f(CPU) = f(Ring)
In on-chip oscillator low-power consumption mode
f(CPU) = 32 kHz
In low-power consumption mode
f(CPU) = f(Ring)
After entering wait mode from on-chip oscillator
low-power consumption mode
Stop mode (while clock is stopped)
Stop mode (while clock is stopped) Topr = 85°C
Page 304 of 352
Standard
Unit
Min. Typ. Max.
28
45 mA
16
mA
10
mA
1
mA
25
μA
50
μA
0.8
5
50
μA
μA
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 23.8
A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85°C, f(CPU) =
32MHz unless otherwise specified)
Symbol
Parameter
Measurement Condition
−
Resolution
VREF = VCC1
INL
Integral nonlinearity error
VREF = VCC1
= VCC2 = 5 V
Min.
Standard
Typ. Max.
Unit
10
Bits
AN_0 to AN_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
±3
LSB
External op-amp
connection mode
±7
LSB
DNL
Differential nonlinearity
error
±1
LSB
−
Offset error
±3
LSB
−
Gain error
±3
LSB
40
kΩ
RLADDER Resistor ladder
VREF = VCC1
8
tCONV
10-bit conversion time(1)(2)
2.06
μs
tCONV
8-bit conversion time(1)(2)
1.75
μs
tSAMP
Sampling time(1)
0.188
μs
VREF
Reference voltage
2
VCC1
V
VIA
Analog input voltage
0
VREF
V
NOTES:
1. The value is obtained when φAD frequency is at 16 MHz. Keep φAD frequency at 16 MHz or less.
2. With using the sample and hold function
Table 23.9
Symbol
D/A Conversion Characteristics
(VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85°C,
f(CPU) = 32MHz unless otherwise specified)
Parameter
−
Resolution
−
Absolute accuracy
tsu
Setup time
RO
Output resistance
IVREF
Reference power supply
input current
Measurement Condition
Min.
4
(note 1)
Standard
Typ. Max.
10
Unit
8
Bits
1.0
%
3
μs
20
kΩ
1.5
mA
NOTE:
1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to
00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT
bit in the AD0CON1 register is set to 0 (VREF not connected)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 305 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 23.10
Voltage Detection Circuit Electrical Characteristics
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25°C unless otherwise specified)
Symbol
Standard
Parameter
Vdet4
Vdet4 detection voltage
Vdet3
Vdet3 detection voltage
Vdet3s
Hardware reset 2 hold voltage
Vdet3r
Hardware reset 2 release voltage
Min.
Typ.
Max.
3.3
3.8
4.4
3.0
VCC1 = 3.0 V to 5.5 V
Unit
V
V
2.0
3.1
V
V
NOTES:
1. Vdet4 > Vdet3
2. Vdet3r > Vdet3 is not guaranteed.
Table 23.11
Power Supply Timing Characteristics
Symbol
Parameter
Measurement Condition
td(P-R)
Wait time to stabilize internal supply voltage
when power-on
VCC1 = 3.0 to 5.5 V
td(S-R)
Wait time to release hardware reset 2
VCC1 = Vdet3r to 5.5 V
td(E-A)
Start-up time for Vdet3 and Vdet4 detection
circuit
VCC1 = 3.0 to 5.5 V
Standard
Min.
Typ.
6(1)
NOTE:
1. When VCC1= 5 V
td(P-R)
Wait time to stabilize internal
supply voltage when power-on
Recommended
operating voltage
VCC1
td(P-R)
CPU clock
td(S-R)
Wait time to release
hardware reset 2
Vdet3r
VCC1
td(S-R)
CPU clock
td(E-A)
Start-up time for Vdet3 and Vdet4
detection circuit
VC26, VC27
Vdet3 and Vdet4
detection circuit
Stop
Operating
td(E-A)
Figure 23.1
Power Supply Timing Diagram
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 306 of 352
Max.
Unit
2
ms
20
ms
20
μs
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.12
External Clock Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
31.25
ns
tw(H)
External clock input high (“H”) pulse width
13.75
ns
tw(L)
External clock input low (“L”) pulse width
13.75
ns
tr
External clock rise time
5
ns
tf
External clock fall time
5
ns
Table 23.13
Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high (“H”) pulse width
40
ns
tw(TAL)
TAiIN input low (“L”) pulse width
40
ns
i = 0 to 4
Table 23.14
Timer A Input (Gate Signal Input in Timer Mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Standard
Min.
Max.
400
Unit
ns
tw(TAH)
TAiIN input high (“H”) pulse width
200
ns
tw(TAL)
TAiIN input low (“L”) pulse width
200
ns
i = 0 to 4
Table 23.15
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Table 23.16
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 307 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.17
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT input cycle time
2000
ns
tw(UPH)
TAiOUT input high (“H”) pulse width
1000
ns
tw(UPL)
TAiOUT input low (“L”) pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
i = 0 to 4
Table 23.18
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Standard
Min.
Max.
Unit
800
ns
tsu(TAIN-TAOUT) TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN) TAiIN input setup time
200
ns
i = 0 to 4
Table 23.19
Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on both edges)
80
ns
i = 0 to 5
Table 23.20
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Table 23.21
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 308 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.22
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG input cycle time (required for trigger)
1000
ns
tw(ADL)
ADTRG input low (“L”) pulse width
125
ns
Table 23.23
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high (“H”) pulse width
100
ns
tw(CKL)
CLKi input low (“L”) pulse width
100
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
tsu(D-C)
RXDi input setup time
30
ns
th(C-D)
RXDi input hold time
90
ns
80
0
ns
ns
i=0 to 4
Table 23.24
External Interrupt INTi Input (Edge Sensitive)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi input high (“H”) pulse width
250
ns
tw(INL)
INTi input low (“L”) pulse width
250
ns
i=0 to 5
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 309 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.25
Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (RD standard)
(note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard)
(note 1)
ns
(note 1)
ns
(note 1)
ns
tac2(RD-DB)
tac2(AD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
tsu(DB-BCLK)
Data input setup time
26
ns
tsu(RDY-BCLK)
RDY input setup time
26
ns
30
ns
ns
tsu(HOLD-BCLK) HOLD input setup time
Data input hold time
0
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
th(RD-DB)
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
tac1(AD-DB) =
109 × n
f(BCLK)
tac2(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
tac2(AD-DB) =
109 × p
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
Page 310 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.26
Microprocessor Mode (when accessing external memory space)
Symbol
Measurement
Condition
Parameter
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
-3
ns
th(RD-AD)
Address output hold time (RD standard)(3)
0
ns
th(WR-AD)
Address output hold time (WR
standard)(3)
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
(note 1)
ns
ns
18
ns
-3
ns
0
ns
Chip-select signal output hold time (RD
standard)(3)
th(WR-CS)
Chip-select signal output hold time (WR
standard)(3)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
-5
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)(3)
(note 1)
ns
tw(WR)
WR output width
(note 2)
ns
th(RD-CS)
See Figure
23.2
(note 1)
ns
18
-5
ns
18
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR)
=
tw(WR)
=
109 × m
f(BCLK)
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 311 of 352
ns
ns
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.27
Microprocessor Mode (when accessing external memory space with multiplexed bus)
Symbol
Measurement
Condition
Parameter
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
-3
ns
th(RD-AD)
Address output hold time (RD standard)(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR
standard)(5)
(note 1)
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
ns
ns
18
ns
-3
ns
Chip-select signal output hold time (RD
standard)(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR
standard)(5)
(note 1)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
-5
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
-2
ns
td(AD-ALE)
ALE signal output delay time (address standard)
(note 3)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(note 4)
ns
tdz(RD-AD)
Address output float start time
th(RD-CS)
ns
18
See Figure
23.2
-5
ns
ns
18
18
8
ns
ns
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(RD-CS)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-DB) =
109
f(BCLK) × 2
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) =
109 × m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) =
109 × n
f(BCLK) × 2
- 10 [ns] (if external bus cycle is aφ + bφ, n = a)
5. tc [ns] is added when recovery cycle is inserted.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 312 of 352
M32C/8A Group
23. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
30 pF
Note 1
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Figure 23.2
P0 to P15 Measurement Circuit
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 313 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1=VCC2=5V
tc
XIN input
tr
tf
tw(H)
tw(L)
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/
decrement select input)
In event counter mode
th(TIN-UP)
TAiIN input (count on falling edge)
tsu(UP-TIN)
TAiIN input (count on rising edge)
In event counter mode with two-phase pulse
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
RXDi
tw(INL)
INTi input
tw(INH)
NMI input
2 CPU clock cycles
+ 300 ns or more
("L" width)
Figure 23.3
VCC1 = VCC2 = 5 V Timing Diagram (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 314 of 352
2 CPU clock cycles
+ 300 ns or more
th(C-D)
M32C/8A Group
23. Electrical Characteristics
VCC1=VCC2=5V
Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK)
th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK)
HOLD Input
th(BCLK-HOLD)
HLDA Output
td(BCLK-HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK-HLDA)
Hi-Z
Measurement Conditions
-VCC1 = VCC2 = 4.2 to 5.5 V
-Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V
-Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 23.4
VCC1 = VCC2 = 5 V Timing Diagram (2)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 315 of 352
M32C/8A Group
23. Electrical Characteristics
Microprocessor Mode (when accessing an external memory space)
VCC1=VCC2=5V
Read Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
-3ns.min
td(BCLK-CS)
18ns.max(1)
CSi
th(RD-CS)
0ns.min
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
-3ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-5ns.min
tac1(RD-DB)(2)
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a φ + bφ, n = a + b)
Write Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
-3ns.min
td(BCLK-CS)
18ns.max
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
18ns.max
th(BCLK-AD)
-3ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3)
tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
Measurement Conditions:
3. Varies with operation frequency:
- VCC1 = VCC2 = 4.2 to 5.5 V
td(DB-WR) = (tcyc x m - 20) ns.min
- Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V
(if external bus cycle aφ + bφ, m = b)
- Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V
th(WR-DB) = (tcyc / 2 - 10) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
109
tw(WR) = (tcyc / 2 x n - 15) ns.min
tcyc=
f(BCLK)
(if external bus cycle aφ + bφ, n = (b x 2) - 1)
Figure 23.5
VCC1 = VCC2 = 5 V Timing Diagram (3)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 316 of 352
M32C/8A Group
23. Electrical Characteristics
Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
VCC1=VCC2=5V
Read Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
tcyc
th(RD-CS)(1)
CSi
ADi /DBi
tsu(DB-BCLK) 26ns.min
th(ALE-AD)(1)
td(AD-ALE)(1)
Address
Data input
tdz(RD-AD)
8ns.max
td(BCLK-AD)
18ns.max
Address
th(RD-DB) 0ns.min
th(BCLK-AD)
-3ns.min
tac2(RD-DB)(1)
ADi
BHE
th(RD-AD)(1)
tac2(AD-DB)(1)
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-5ns.min
NOTES:
1. Varies with operation frequency:
t d(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
t h(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
t h(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
t ac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) - 1)
t ac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a φ + bφ, p = {(a + b - 1) x 2} + 1)
Write Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(BCLK-CS)
-3ns.min
th(WR-CS)(2)
CSi
td(AD-ALE)(2)
th(ALE-AD)(2)
Address
ADi /DBi
Data output
td(DB-WR)(2)
td(BCLK-AD)
18ns.max
Address
th(WR-DB)(2)
th(BCLK-AD)
-3ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
WR,WRL,WRH
th(BCLK-WR)
-5ns.min
th(WR-AD)(2)
NOTES:
1. Varies with operation frequency:
t d(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
t h(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
t h(WR-AD) = (tcyc / 2 - 10) ns.min, t h(WR-CS) = (tcyc / 2 - 10) ns.min
t h(WR-DB) = (tcyc / 2 - 10) ns.min
t d(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a φ + bφ, m = (b x 2) - 1)
Measurement Conditions:
109
- VCC1 = VCC2 = 4.2 to 5.5 V
tcyc=
- Input high and low voltage VIH = 2.5 V, VIL = 0.8 V
f(BCLK)
- Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Figure 23.6
VCC1 = VCC2 = 5 V Timing Diagram (4)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 317 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 23.28
Electrical Characteristics (1)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless otherwise
specified)
Symbol
VOH
Parameter
Output
high “H”
voltage
Condition
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
IOH = -1 mA
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
XOUT
XCOUT
VOL
IOH = -0.1 mA
VCC2
VCC1 - 0.6
VCC1
2.7
VCC1
V
V
2.5
V
Low drive
capability
No load
applied
1.6
V
IOL = 1 mA
0.5
V
IOL = 0.1 mA
0.5
V
High drive
capability
No load
applied
0
V
Low drive
capability
No load
applied
0
V
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, ADTRG,
CTS0 to CTS4, CLK0 to CLK4,
TA0OUT to TA4OUT, NMI, KI0 to KI3,
RXD0 to RXD4, SCL0 to SCL4,
SDA0 to SDA4
0.2
1.0
V
RESET
0.2
1.8
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
VCC2 - 0.6
Unit
No load
applied
XOUT
VT+ - VT- Hysteresis
Standard
Typ. Max.
High drive
capability
Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“L” voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
XCOUT
Min.
Page 318 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 23.29
Electrical Characteristics (2)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless
otherwise specified)
Symbol
Standard
Parameter
Condition
IIH
Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“H” current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 3 V
4.0
μA
IIL
Input low
“L” current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 0V
-4.0
μA
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
VI=0V
500
kΩ
RfXIN
Feedback
resistance
XIN
3.0
MΩ
RfXCIN
Feedback
resistance
XCIN
20.0
MΩ
VRAM
RAM data
retention
voltage
In stop mode
Min.
40
Typ.
70
Max.
2.0
Unit
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Table 23.30
Electrical Characteristics (3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25°C)
Symbol Parameter
ICC
Power
supply
current
Condition
ROMless
version
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
f(CPU) = 24 MHz
f(CPU) = 16 MHz
f(CPU) = 8 MHz
f(CPU) = f(Ring)
In on-chip oscillator low-power consumption mode
f(CPU) = 32 kHz
In low-power consumption mode
f(CPU) = f(Ring)
After entering wait mode from on-chip oscillator
low-power consumption mode
Stop mode (while clock is stopped)
Stop mode (while clock is stopped) Topr = 85°C
Page 319 of 352
Standard
Unit
Min. Typ. Max.
22
33 mA
15
mA
9
mA
1
mA
25
μA
45
μA
0.8
5
50
μA
μA
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 23.31
A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85°C,
f(CPU) = 24MHz unless otherwise specified)
Symbol
Parameter
Measurement Condition
Standard
Min.
Typ. Max.
Unit
−
Resolution
VREF = VCC1
10
Bits
INL
Integral nonlinearity error (8-bit)
VREF = VCC1 = VCC2 = 3.3 V
±2
LSB
DNL
Differential nonlinearity error (8-bit)
±1
LSB
−
Offset error (8-bit)
±2
LSB
−
Gain error (8-bit)
±2
LSB
40
kΩ
RLADDER Resistor ladder
VREF = VCC1
time(1)(2)
8
μs
tCONV
8-bit conversion
4.9
VREF
Reference voltage
3
VCC1
V
VIA
Analog input voltage
0
VREF
V
NOTES:
1. The value when φAD frequency is at 10 MHz. Keep φAD frequency at 10 MHz or less.
If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 μs.
2. S&H not available.
Table 23.32
Symbol
D/A Conversion Characteristics
(VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V at Topr = -20 to 85°C,
f(CPU) = 24MHz unless otherwise specified)
Parameter
−
Resolution
−
Absolute accuracy
tsu
Setup time
RO
Output resistance
IVREF
Reference power supply
input current
Measurement Condition
Standard
Min.
Typ. Max.
4
(note 1)
10
Unit
8
Bits
1.0
%
3
μs
20
kΩ
1.0
mA
NOTE:
1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set
to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT
bit in the AD0CON1 register is set to 0 (VREF not connected)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 320 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.33
External Clock Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
41
ns
tw(H)
External clock input high (“H”) pulse width
18
ns
tw(L)
External clock input low (“L”) pulse width
18
ns
tr
External clock rise time
5
ns
tf
External clock fall time
5
ns
Table 23.34
Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high (“H”) pulse width
40
ns
tw(TAL)
TAiIN input low (“L”) pulse width
40
ns
i = 0 to 4
Table 23.35
Timer A Input (Gate Signal Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high (“H”) pulse width
200
ns
tw(TAL)
TAiIN input low (“L”) pulse width
200
ns
i = 0 to 4
Table 23.36
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Table 23.37
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 321 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.38
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT input cycle time
2000
ns
tw(UPH)
TAiOUT input high (“H”) pulse width
1000
ns
tw(UPL)
TAiOUT input low (“L”) pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
i = 0 to 4
Table 23.39
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
2
μs
tsu(TAIN-TAOUT) TAiOUT input setup time
500
ns
tsu(TAOUT-TAIN) TAiIN input setup time
500
ns
tc(TA)
TAiIN input cycle time
i = 0 to 4
Table 23.40
Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on both edges)
80
ns
i = 0 to 5
Table 23.41
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Table 23.42
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 322 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.43
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG input cycle time (required for trigger)
1000
ns
tw(ADL)
ADTRG input low (“L”) pulse width
125
ns
Table 23.44
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high (“H”) pulse width
100
ns
tw(CKL)
CLKi input low (“L”) pulse width
100
ns
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi output hold time
0
80
ns
ns
tsu(D-C)
RXDi input setup time
30
ns
th(C-D)
RXDi input hold time
90
ns
i=0 to 4
Table 23.45
External Interrupt INTi Input (Edge Sensitive)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi input high (“H”) pulse width
250
ns
tw(INL)
INTi input low (“L”) pulse width
250
ns
i=0 to 5
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 323 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.46
Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (RD standard)
(note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard)
(note 1)
ns
(note 1)
ns
(note 1)
ns
tac2(RD-DB)
tac2(AD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
tsu(DB-BCLK)
Data input setup time
30
ns
tsu(RDY-BCLK)
RDY input setup time
40
ns
60
ns
ns
tsu(HOLD-BCLK) HOLD input setup time
Data input hold time
0
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
th(RD-DB)
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
tac1(AD-DB) =
109 × n
f(BCLK)
tac2(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
tac2(AD-DB) =
109 × p
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
Page 324 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.47
Microprocessor Mode (when accessing external memory space)
Symbol
Measurement
Condition
Parameter
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)(3)
0
ns
th(WR-AD)
Address output hold time (WR
standard)(3)
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
(note 1)
ns
ns
18
ns
0
ns
0
ns
Chip-select signal output hold time (RD
standard)(3)
th(WR-CS)
Chip-select signal output hold time (WR
standard)(3)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
0
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)(3)
(note 1)
ns
tw(WR)
WR output width
(note 2)
ns
th(RD-CS)
See Figure
23.2
(note 1)
ns
18
-3
ns
18
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) =
109
f(BCLK) × 2
- 20 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR)
=
tw(WR)
=
109 × m
f(BCLK)
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 325 of 352
ns
ns
M32C/8A Group
23. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 23.48
Microprocessor Mode (when accessing external memory space with multiplexed bus)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
0
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time
18
18
See Figure
23.2
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(DB-WR)
Data output delay time (WR standard)
standard)(5)
th(WR-DB)
Data output hold time (WR
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
td(AD-ALE)
-3
ns
ns
ns
ns
18
ns
0
ns
(note 2)
ns
(note 1)
ns
18
ns
-2
ns
ALE signal output delay time (address standard)
(note 3)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(note 4)
tdz(RD-AD)
Address output float start time
ns
8
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(RD-CS)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-DB) =
109
f(BCLK) × 2
- 20 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) =
109 × m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) =
109 × n
f(BCLK) × 2
- 10 [ns] (if external bus cycle is aφ + bφ, n = a)
5. tc [ns] is added when recovery cycle is inserted.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 326 of 352
M32C/8A Group
23. Electrical Characteristics
VCC1=VCC2=3.3V
tc
XIN input
tr
tf
tw(H)
tw(L)
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/
decrement select input)
In event counter mode
th(TIN-UP)
TAiIN input (count on falling edge)
tsu(UP-TIN)
TAiIN input (count on rising edge)
In event counter mode with two-phase pulse
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
RXDi
tw(INL)
INTi input
tw(INH)
NMI input
2 CPU clock cycles
+ 300 ns or more
("L" width)
Figure 23.7
2 CPU clock cycles
+ 300 ns or more
VCC1 = VCC2 = 3.3 V Timing Diagram (1)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 327 of 352
th(C-D)
M32C/8A Group
23. Electrical Characteristics
VCC1=VCC2=3.3V
Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK)
th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK)
HOLD Input
th(BCLK-HOLD)
HLDA Output
td(BCLK-HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK-HLDA)
Hi-Z
Measurement Conditions
-VCC1 = VCC2 = 3.0 to 3.6 V
-Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V
-Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 23.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 328 of 352
M32C/8A Group
23. Electrical Characteristics
Microprocessor Mode (when accessing an external memory space)
VCC1=VCC2=3.3V
Read Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
0ns.min
td(BCLK-CS)
18ns.max(1)
CSi
th(RD-CS)
0ns.min
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
0ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-3ns.min
tac1(RD-DB)(2)
tac1(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
30ns.min(1)
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a φ + bφ, n = a + b)
Write Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
0ns.min
td(BCLK-CS)
18ns.max
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
18ns.max
th(BCLK-AD)
0ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3)
tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
Measurement Conditions:
3. Varies with operation frequency:
- VCC1 = VCC2 = 3.0 to 3.6 V
td(DB-WR) = (tcyc x m - 20) ns.min
- Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V
(if external bus cycle aφ + bφ, m = b)
- Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
th(WR-DB) = (tcyc / 2 - 20) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
109
tw(WR) = (tcyc / 2 x n - 15) ns.min
tcyc=
f(BCLK)
(if external bus cycle aφ + bφ, n = (b x 2) - 1)
Figure 23.9
VCC1 = VCC2 = 3.3 V Timing Diagram (3)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 329 of 352
M32C/8A Group
23. Electrical Characteristics
Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
VCC1=VCC2=3.3V
Read Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
tcyc
th(RD-CS)(1)
CSi
ADi /DBi
tsu(DB-BCLK) 30ns.min
th(ALE-AD)(1)
td(AD-ALE)(1)
Address
Data input
tdz(RD-AD)
8ns.max
td(BCLK-AD)
18ns.max
Address
th(RD-DB) 0ns.min
th(BCLK-AD)
0ns.min
tac2(RD-DB)(1)
ADi
BHE
th(RD-AD)(1)
tac2(AD-DB)(1)
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-3ns.min
NOTES:
1. Varies with operation frequency:
t d(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
t h(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
t h(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
t ac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) - 1)
t ac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a φ + bφ, p = {(a + b - 1) x 2} + 1)
Write Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
tcyc
th(BCLK-CS)
0ns.min
th(WR-CS)(2)
CSi
td(AD-ALE)(2)
th(ALE-AD)(2)
Address
ADi /DBi
Data output
td(DB-WR)(2)
td(BCLK-AD)
18ns.max
Address
th(WR-DB)(2)
th(BCLK-AD)
0ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
WR,WRL,WRH
th(BCLK-WR)
0ns.min
th(WR-AD)(2)
NOTES:
1. Varies with operation frequency:
t d(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
t h(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
t h(WR-AD) = (tcyc / 2 - 10) ns.min, t h(WR-CS) = (tcyc / 2 - 10) ns.min
t h(WR-DB) = (tcyc / 2 - 20) ns.min
t d(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a φ + bφ, m = (b x 2) - 1)
Measurement Conditions:
109
- VCC1 = VCC2 = 3.0 to 3.6 V
tcyc=
- Input high and low voltage VIH = 1.5 V, VIL = 0.5 V
f(BCLK)
- Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
Figure 23.10
VCC1 = VCC2 = 3.3 V Timing Diagram (4)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 330 of 352
M32C/8A Group
24. Usage Notes
24. Usage Notes
24.1
Power Supply
24.1.1
Power-on
At power-on, supply voltage applied to the VCC1 must meet the SVCC standard.
(Technical update: TN-M16C-116-0311)
Table 24.1
Symbol
SVCC
Supply Voltage Power-up Slope
Standard
Unit
Min. Typ. Max.
Supply voltage power-up slope (supply voltage range: 0 V to 2.0 V) 0.05
V/ms
Parameter
Voltage
SVCC
Supply voltage power-up slope
(VCC1)
SVCC
2.0 V
0V
Figure 24.1
SVCC Timing
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 331 of 352
Time
M32C/8A Group
24.1.2
24. Usage Notes
Power Supply Ripple
Stabilize supply voltage to meet the power supply standard listed in Table 24.2.
Table 24.2
Power Supply Ripple
Symbol
Standard
Parameter
f(ripple)
Vp-p(ripple)
VCC(|ΔV/ΔT|)
Min.
Unit
(VCC1 = 5 V)
10
kHz
(VCC1 = 3.3 V)
100
Hz
Power supply ripple voltage
fluctuation range
(VCC1 = 5 V)
0.5
V
(VCC1 = 3.3 V)
0.2
V
Power supply ripple voltage
fluctuation rate
(VCC1 = 5 V)
1
V/ms
0.1
V/ms
Vp-p(ripple)
Power supply ripple voltage fluctuation
range
24.1.3
Max.
Power supply ripple tolerable
frequency (VCC1)
(VCC1 = 3.3 V)
f(ripple)
f(ripple)
Power supply ripple tolerable frequency
(VCC1)
Figure 24.2
Typ.
VCC1
Vp-p(ripple)
Power Supply Fluctuation Timing
Noise
Use thick and shortest possible wiring to connect a bypass capacitor (0.1 μF or more) between VCC and VSS.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 332 of 352
M32C/8A Group
24.2
24. Usage Notes
Special Function Registers (SFRs)
24.2.1
100 Pin-Package
Set addresses 03CBh, 03CEh, 03CFh, 03D2h, and 03D3h to FFh after reset when using the 100-pin package.
Address 03DCh must be set to 00h after reset.
24.2.2
Register Settings
Table 24.3 lists registers containing write-only bits. Read-modify-write instructions cannot be used to set these
registers. If these registers are set using a read-modify-write instruction, undefined values are read from the
write-only bits in the register and written back to these bits. Table 24.4 lists read-modify-write instructions.
When establishing new values by modifying previous ones, write the previous values into RAM as well as to
the register. Change the contents of the RAM and then transfer the new values to the register.
Table 24.3
Registers with Write-Only Bits
Register
Address
Register
Address
WDTS register
000Eh
U3TB register
032Bh to 032Ah
U1BRG register
02E9h
U2BRG register
0339h
U1TB register
02EBh to 02EAh
U2TB register
033Bh to 033Ah
U4BRG register
02F9h
UDF register
0344h
U4TB register
02FBh to 02FAh
TA0
register(1)
0347h to 0346h
TA11 register
0303h, 0302h
TA1 register(1)
0349h to 0348h
TA21 register
0305h, 0304h
TA2 register(1)
034Bh to 034Ah
TA41 register
0307h, 0306h
TA3 register(1)
034Dh to 034Ch
DTT register
030Ch
TA4 register(1)
034Fh to 034Eh
ICTB2 register
030Dh
U0BRG register
0369h
U3BRG register
0329h
U0TB register
036Bh to 036Ah
NOTE:
1. In one-shot timer mode and pulse width modulation mode only.
Table 24.4
Read-Modify-Write Instructions
Function
Mnemonic
Transfer
MOVDir
Bit manipulation
BCLR, BMCnd, BNOT, BSET, BTSTC, BTSTS
Shift
ROLC, RORC, ROT, SHA, SHANC, SHL, SHLNC
Arithmetic
ABS, ADC, ADCF, ADD, ADDX, DADC, DADD, DEC, DSBB, DSUB, EXTS, EXTZ, INC,
MUL, MULEX, MULU, NEG, SBB, SUB, SUBX
Logical
AND, NOT, OR, XOR
Jump
ADJNZ, SBJNZ
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 333 of 352
M32C/8A Group
24.3
24. Usage Notes
Clock Generation Circuits
24.3.1
Main Clock
• When the CPU operating frequency is required 24 MHz or more, make an oscillator connected to the main
clock circuit (XIN-XOUT), or an external clock applied to the XIN pin have 24 MHz or less frequency, and
then multiply the main clock with the PLL frequency synthesizer. By using this procedure, a better EMC
(Electromagnetic Compatibility) performance can be achieved than using a more than 24 MHz oscillator
(external clock).
• If the main clock is selected as the CPU clock while an external clock is applied to the XIN pin, do not stop
the external clock.
(Technical update: TN-M16C-109-0309)
• When an external clock is used for the CPU clock, do not set the CM05 bit in the CM0 register to 1
(stopped).
24.3.2
Sub Clock
24.3.2.1
To Oscillate Sub Clock
To oscillate the sub clock, set the CM07 bit in the CM0 register to 0 (clock other than the sub clock) and the
CM03 bit to 1 (XCIN-XOUT drive capability HIGH). Then, set the CM04 bit in the CM0 register to 1 (XCINXCOUT oscillation function). Once the sub clock becomes stabilized, set the CM03 bit to 0 (XCIN-XOUT
drive capability LOW).
After the above procedure, the sub clock can be used as the CPU clock, or the count source for timer A and
timer B.
(Technical update: TN-16C-119A/EA)
24.3.2.2
Oscillation Parameter Matching
If an oscillation circuit constant matching for the sub clock oscillation circuit has only been evaluated with the
drive capability HIGH, the constant matching for drive capability LOW must also be evaluated.
Contact your oscillator manufacturer for details on the oscillation circuit constant matching.
24.3.3
Clock Dividing Ratio
To change bits MCD4 to MCD0, set the PM12 bit in the PM1 register to 0 (no wait state).
24.3.4
Power Consumption Control
Stabilize the main clock, sub clock, or PLL clock prior to switching the clock source for the CPU clock to one
of these clocks.
24.3.4.1
Wait Mode
• When entering wait mode with setting the CM02 bit in the CM0 register to 1 (peripheral clocks stop in wait
mode), set bits MCD4 to MCD0 in the MCD register to be the 10-MHz or less CPU clock frequency after
dividing the main clock.
• When entering wait mode, the instructions following the WAIT instruction are stored into the instruction
queue, and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• To enter wait mode, execute the WAIT instruction while a high-level (“H”) signal is applied to the NMI
pin.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 334 of 352
M32C/8A Group
24.3.4.2
24. Usage Notes
Stop Mode
• The MCU cannot enter stop mode if a low-level (“L”) signal is applied to the NMI pin. Apply an “H” signal
to enter stop mode.
• To exit stop mode by reset, apply an “L” signal to RESET pin until a main clock oscillation stabilizes.
• If using the NMI interrupt to exit stop mode, use the following procedure to set the CM10 bit in the CM1
register to 1 (all clocks stopped).
(Technical update: TN-16C-127A/EA)
(1) Exit stop mode using the NMI interrupt.
(2) Generate a dummy interrupt.
(3) Set the CM10 bit to 1 (all clocks stopped).
e.g.,
int
bset
#63
CM1
; dummy interrupt
; all clocks stopped
/*dummy interrupt routine*/
dummy
reit
• When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction
queue, and the program stops. When stop mode is exited, the instruction lined in the queue is executed
before the exit interrupt routine is handled. Insert a jmp.b instruction as follows after the instruction to set
the CM10 bit is set to 1.
(Technical update: TN-16C-124A/EA)
fset I
bset 0, cm1
jmp.b LABEL_001
LABEL_001:
nop
nop
nop
nop
mov.b #0, prcr
.
.
.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
; I flag is set to 1
; all clocks stopped (stop mode)
; jmp.b instruction executed (no instruction between jmp.b and LABEL.)
; nop(1)
; nop(2)
; nop(3)
; nop(4)
; protection set
Page 335 of 352
M32C/8A Group
24.3.4.3
24. Usage Notes
Suggestions to Reduce Power Consumption
The followings are suggestions to reduce power consumption when programming or designing systems.
Ports:
• Through current may flow into floating input pins. Set unassigned pins to input mode and connect them to
VSS via a resistor (pull down), or set unassigned pins to output mode and leave them open.
A/D converter:
• When the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to 0 (VREF not
connected). When the A/D conversion is performed, set the VCUT bit to 1 (VREF connection) and wait
1 μs or longer to start the A/D conversion.
D/A converter:
• When the D/A conversion is not performed, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output
disabled) and the DAi register to 00h.
Peripheral function clock stop:
• When entering wait mode from main clock mode, on-chip oscillator mode, or on-chip oscillator low-power
consumption mode, power consumption can be reduced by setting the CM02 bit in the CM0 register to 1 to
stop peripheral function clock source (fPFC). However, fC32 does not stop by setting the CM02 bit to 1.
• In low-speed mode, do not set the CM02 bit to 1 (peripheral clock stops in wait mode) when entering wait
mode.
(Technical update: TN-M16C-69-0104)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 336 of 352
M32C/8A Group
24.4
24. Usage Notes
Protection
The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to
1 (write enable). Set a register protected by the PRC2 bit immediately after the PRC2 bit is set to 1. Do not
generate an interrupt or a DMA or DMACII transfer between these two instructions.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 337 of 352
M32C/8A Group
24.5
24. Usage Notes
Interrupts
24.5.1
ISP Setting
After reset, ISP is initialized to 000000h. The program crash may occur if an interrupt is acknowledged before
setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting ISP to
an even address allows interrupt sequences to be executed at a higher speed.
To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be
acknowledged after the first instruction has been executed after reset.
24.5.2
NMI Interrupt
• The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in
use.
• The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to
determine the pin level after the NMI interrupt occurs.
24.5.3
INT Interrupt
• Edge Sensitive
Each of “H” or “L” width of signals applied to pins INT0 to INT5 must be 250 ns or more regardless of the
CPU clock frequency.
• Level Sensitive
Each of “H” or “L” width of signals applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns or
more. For example, each of “H” or “L” width must be 234 ns or more if the CPU clock is 30 MHz.
• The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings of
pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is changed.
Figure 24.3 shows an example of the switching procedure for an INTi interrupt source (i = 0 to 5).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 338 of 352
M32C/8A Group
24. Usage Notes
< Procedure for Edge Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit
Select either one edge or both edge
INTiIC register: POL bit
LVS bit = 0
Select polarity (Set to 0 when both edges are selected)
Select edge sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
< Procedure for Level Sensitive >
Start
INTiIC register: bits ILVL2 to ILVL0 = 000b
Interrupt disabled
IFSR register: IFSRi bit = 0
Select one edge
INTiIC register: POL bit
LVS bit = 1
Select polarity
Select level sensitive
INTiIC register: IR bit = 0
Clear the interrupt request bit
INTiIC register: bits ILVL2 to ILVL0
Interrupt enabled
End
Figure 24.3
Switching Procedure for INTi (i = 0 to 5) Interrupt Source
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 339 of 352
i = 0 to 5
M32C/8A Group
24.5.4
24. Usage Notes
Changing Interrupt Control Register
To change the Interrupt Control Register while an interrupt request is disabled, use the following instructions.
Changing IR bit:
The IR bit may not be changed to 0 (interrupt not requested) by writing, depending on which instruction is used.
If this causes a problem, use MOV instruction to change the register. (Technical update: TN-M16C-85-0204)
Changing any bits other than IR bit:
If an interrupt request is generated while writing to the corresponding Interrupt Control Register with
instructions such as MOV, the IR bit may not become 1 (interrupt requested) and the interrupt is not
acknowledged. If this causes a problem, use the following instructions to write to the register:
AND, OR, BCLR, BSET
24.5.5
Changing RLVL Register
The DMAII bit in the RLVL register is undefined after reset. To use interrupt priority level 7 for an interrupt,
set it to 0 before setting the Interrupt Control Register.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 340 of 352
M32C/8A Group
24.6
24. Usage Notes
DMAC
• Set the DMAC-associated registers while bits MDi1 and MDi0 (i = 0 to 3) in the channel i are set to 00b (DMA
disabled). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat transfer) at the end of the setup
procedure, which enables the DMA request of the channel i to be acknowledged.
• Write a 1 (requested) to the DRQ bit when setting the DMiSL register.
In the M32C/80 Series, if a DMA request is generated but a receiving channel is not ready(1), a DMA transfer does
not occur and the DRQ bit becomes 0.
NOTE:
1. Bits MDi1 and MDi0 are set to 00b or the DCTi register is 0000h (transferred 0 time).
• To start a DMA transfer using a software trigger, set bits DSR and DRQ in the DMiSL register to 1
simultaneously.
e.g.,
OR.B #0A0h, DMiSL
; set bits DSR and DRQ to 1 simultaneously
• While the DCTi register in the channel i is set to 1, do not generate a DMA request in the channel i in the timing
that bits MDi1 and MDi0 in the DMDj register (j = 0, 1) corresponding to the channel i are set to 01b (single
transfer) or 11b (repeat transfer). (Technical update: TN-M16C-88-0209)
• Select a peripheral function used as a DMA request source after setting the DMA-associated registers. When the
INT interrupt is selected as a DMA request source, do not set the DCTi register to 1.
• Wait six CPU clock cycles or more by program to enable DMA after setting the DMiSL register(2).
NOTE:
2. To enable DMA means changing bits MDi1 and MDi0 in the DMDj register from 00b (DMA disabled)
to 01b (single transfer) or 11b (repeat transfer).
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 341 of 352
M32C/8A Group
24.7
24. Usage Notes
Timers
24.7.1
Timer A, Timer B
Timers are stopped after reset. Set the TAiS (i = 0 to 4) or TBjS (j = 0 to 5) bit in the TABSR or TBSR register
to 1 (count starts) after setting timer operating mode, count source, and counter value.
The following registers and bits must be changed while the TAiS or TBjS bit is set to 0 (count stops).
• Registers TAiMR and TBjMR
• UDF register
• Bits TAZIE, TA0TGL, and TA0TGH in the ONSF register
• TRGSR register
24.7.2
Timer A
24.7.2.1
Timer A (Timer Mode)
• The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
• The TAi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. A setting value can be read between when the TAi register is set while a counter stops
and when a counter is started.
24.7.2.2
Timer A (Event Counter Mode)
• The TAiS bit (i = 0 to 4) is set to 0 (count stops) after reset. Set the TAiS bit to 1 (count starts) after
selecting timer operating mode and setting the TAi register.
• The TAi register indicates a counter value while counting at any given time. However, FFFFh can be read
if the timer underflows or 0000h if the timer overflows, in the reload timing. A setting value can be read
between setting the TAi register while a counter stops and starting a counter.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 342 of 352
M32C/8A Group
24.7.2.3
24. Usage Notes
Timer A (One-Shot Timer Mode)
• The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
• The following occurs when the TAiS bit in the TABSR register is set to 0 (count stops) while counting.
• The counter stops counting and the contents of the reload register is reloaded.
• The TAiOUT pin outputs a low-level (“L”) signal.
• The IR bit in the TAiIC register becomes 1 (interrupt requested) after one CPU clock cycle.
• One-shot timer is operated by an internal count source. When an external trigger is selected, a maximum of
one count source clock delay occurs between the trigger input to the TAiIN pin and the one-shot timer
output.
• The IR bit becomes 1 when one of the following procedures are used to set timer operating mode.
• When selecting one-shot timer mode after reset.
• When switching from timer mode to one-shot timer mode.
• When switching from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
• When a retrigger occurs while counting, the contents of the reload register is reloaded after the counter
decrements by one, and continues counting.
To generate a retrigger while counting, wait 1 count source clock cycle or more after the last trigger.
• When an external trigger input is selected to start counting in timer A one-shot timer mode, do not provide
an external retrigger input for 300 ns before a timer A counter value reaches 0000h. One-shot timer may
stop counting.
(Technical update: TN-16C-125A/EA)
24.7.2.4
Timer A (Pulse Width Modulation Mode)
• The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
• The IR bit becomes 1 when one of the following procedures are used to select timer operating mode.
• When selecting PWM mode after reset.
• When switching from timer mode to PWM mode.
• When switching from event counter mode to PWM mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
• The following occurs when the TAiS bit is set to 0 (count stops) while PWM pulse is output.
• The counter stops.
• If the TAiOUT pin outputs a high-level (“H”) signal, the signal changes to “L” and the IR bit
becomes 1.
• If the TAiOUT pin outputs an “L” signal, its output signal and the IR bit remains unchanged.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 343 of 352
M32C/8A Group
24.7.3
24. Usage Notes
Timer B
24.7.3.1
Timer B (Timer Mode, Event Counter Mode)
• The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 0 (count stops) after reset. Set the TBiS
bit to 1 (count starts) after selecting timer operating mode and setting the TBi register.
Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR
register.
• The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. A setting value can be read between setting the TBi register while a counter stops and
starting a counter.
24.7.3.2
Timer B (Pulse Period/Pulse Width Measurement Mode)
• To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR
register after the MR3 bit becomes 1, while the TBiS bit is set to 1.
(Technical update: TN-M16C-75-0110)
• Use the IR bit in the TBiIC register to detect overflow. The MR3 bit is used only to determine an interrupt
request source within the interrupt routine.
• When the first valid edge is input after the count starts, an undefined value is transferred to the reload
register. At this time, the timer Bi interrupt request is not generated.
• The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and
causes a timer Bi interrupt request to be generated before a valid edge is input.
• The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after
the count starts. If the same value is written to bits MR1 and MR0, the IR bit is not changed.
• Pulse width is repeatedly measured in pulse width measurement mode. Determine by program whether the
measurement result is high (“H”) or low (“L”).
• If an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt
request is generated only once, which results in the valid edge not being recognized. Do not let an overflow
occur.
• In pulse width measurement mode, determine whether an interrupt source is a valid edge input or an
overflow by reading the port level in the TBi interrupt routine.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 344 of 352
M32C/8A Group
24.8
24. Usage Notes
Three-Phase Motor Control Timer Function
• Do not write to the TAi or the TAi1 register (i = 1, 2, 4) in the timing that timer B2 underflows. If there is a
possibility to write in this timing, read the value of the timer B2 register to verify that there is a sufficient time
until timer B2 underflows, and then write to the TAi or the TAi1 register immediately.
(Technical update: TN-M16C-86-0205)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 345 of 352
M32C/8A Group
24.9
24. Usage Notes
Serial Interfaces
24.9.1
Changing UiBRG Register (i = 0 to 4)
Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are
changed, the UiBRG register must be set again.
24.9.2
Clock Synchronous Mode
24.9.2.1
Transmit Operation
If an external clock is selected, the following conditions must be met while the external clock is held “H” when
the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive
data input at the rising edge of the serial clock), or while the external clock is held “L” when the CKPOL bit is
set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled).
• Set the RE bit in the UiC1 register to 1 (receive operation enabled).
• The TI bit in the UiC1 register is 0 (data in the UiTB register).
The RE bit setting is not required for a transmit-only operation.
24.9.2.2
Receive Operation
• In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTiassociated registers for a transmit operation as well, even if the MCU is used only for receive operation.
Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.
• If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the
UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the
OER bit in the UiRB register becomes 1 (overrun error occurred). In this case, the UiRB register becomes
undefined. If an overrun error occurs, the IR bit in the SiRIC register is not changed to 1.
• The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).
(1) The CKDIR bit in the UiMR register is set to 1 (external clock).
(2) The RTS function is not used.
To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode
disabled), and write dummy data to the UiTB register every time a receive operation is completed.
24.9.3
UART Mode
Set the UiERE bit in the UiC1 register after setting the UiMR register.
24.9.4
Special Mode 1 (I2C Mode)
To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the UiSMR4 register
to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit
(the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1.
(Technical update: TN-16C-130A/EA)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 346 of 352
M32C/8A Group
24. Usage Notes
24.10 A/D Converter
• Set the ADST bit to 1 (A/D conversion starts) after setting registers AD0CON0 (ADST bit excluded),
AD0CON1, AD0CON2, AD0CON3, and AD0CON4.
• When the VCUT bit in the AD0CON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for 1 μs or more to start A/D conversion.
Set the VCUT bit to 0 when A/D conversion is not used to reduce power consumption.
• To prevent latch-up and malfunction due to noise and also to minimize a conversion error, insert a capacitor
between the AVSS pin and each of the following pins: the AVCC pin, VREF pin, or analog input pin ANi_j
(i = none, 15; j = 0 to 7). Insert a capacitor between the VCC pin and the VSS pin as well. Figure 24.4 shows
an example of individual pin handling.
MCU
VCC1
VCC1
VCC1
AVCC
VSS
VREF
C4
C1
C2
AVSS
VCC2
C3
VCC2
C5
ANi
VSS
NOTES:
1.C1 ≥ 0.47 μF, C2 ≥ 0.47 μF, C3 ≥ 10000 pF, C4 ≥ 0.1 μF, C5 ≥ 0.1 μF (reference values)
2.Use thick and shortest possible wiring to connect capacitors.
Figure 24.4
Individual Pin Handling
• Set the port direction bit in the PDk register (k = 0 to 15), which corresponds to a pin used as an analog input
pin, to 0 (input mode). Also, set the port direction bit in the PDk register corresponding to the ADTRG pin, to
0 (input mode.)
• When the key input interrupt is used, do not select pins P10_4 to P10_7 (AN_4 to AN_7) as analog input pins.
• φAD frequency must be 16 MHz or lower when VCC1 = 4.2 V to 5.5 V, or 10 MHz or lower when
VCC1 = 3.0 V to 5.5 V. When the sample and hold is not activated, φAD frequency must be 250 kHz or
higher. When the sample and hold is activated, φAD frequency must be 1 MHz or higher.
• When A/D operating mode is changed, set bits CH2 to CH0 in the AD0CON0 register or bits SCAN1 and
SCAN0 in the AD0CON1 register again to select analog input pins.
• The voltage applied to AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, and ANEX1 must be VCC1 or below.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 347 of 352
M32C/8A Group
24. Usage Notes
• If an A/D conversion in progress is forcibly aborted by setting the ADST bit in the AD0CON0 register to 0
(A/D conversion stops), the A/D conversion result will be incorrect. The AD0i register which is not
performing A/D conversion may also be incorrect. If the ADST bit is set to 0 during A/D conversion, do not
use values obtained from any of AD0i registers.
• External triggers cannot be used in DMAC operating mode. Do not read the AD00 register using instructions.
• Do not perform A/D conversion in wait mode.
• To abort an A/D conversion in progress by setting the ADST bit in the AD0CON0 register to 0 in single sweep
mode, disable interrupts before setting the ADST bit to 0.
(Technical update: TN-16C-132A/EA)
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 348 of 352
M32C/8A Group
24. Usage Notes
24.11 Programmable I/O Ports
• Pins P7_2 to P7_5, P8_0, and P8_1 have the forced cutoff function of the three-phase PWM output. When
these ports are set in output mode (port output, timer output, three-phase PWM output, serial interface output),
they are affected by the three-phase motor control timer function and the NMI pin setting. Table 24.5 shows
the INVC0 register setting, NMI pin input level, and output pin states.
Table 24.5
INVC0 Register Setting, NMI Pin Level, and Output Pin Status
INV02 Bit
Setting Value of the INVC0 Register
INV03 Bit
NMI Pin
Input Level
Pin States of P7_2 to P7_5, P8_0, P8_1
(when set in output mode)
0
(three-phase motor control
timer function not used)
−
−
Output functions selected using registers
PS1, PSL1, PSC, PS2, and PSL2
0
(three-phase motor control
timer output disabled)
−
1
(three-phase motor control
timer function used)
1
(three-phase motor control
timer output enabled)(1)
High-impedance states
H
Output functions selected using registers
PS1, PSL1, PSC, PS2, and PSL2
L
High-impedance states
(forcibly
terminated)
−: Not affected by the bit setting nor the pin state
NOTE:
1. The INV03 bit becomes 0 after a low-level (“L”) signal is applied to the NMI pin.
• The availability of the pull-up resistors is undefined until the internal power voltage stabilizes even if the
RESET pin is held “L”.
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 349 of 352
M32C/8A Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
E
c
HE
c1
b1
*2
Reference
Symbol
Terminal cross section
Index mark
c
36
A
1
ZD
ZE
37
A2
144
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
A1
F
L
L1
*3
e
y
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
bp
e
x
y
ZD
ZE
L
L1
Detail F
x
Previous Code
100P6Q-A / FP-100U / FP-100UV
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
HE
Reference Dimension in Millimeters
Symbol
c
c1
*2
E
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 350 of 352
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
M32C/8A Group
Index
Index
[A]
[M]
AD00 to AD07 ................................................... 258
AD0CON0 ........................................................... 254
AD0CON1 ........................................................... 255
AD0CON2 ........................................................... 256
AD0CON3 ........................................................... 257
AD0CON4 ........................................................... 258
AIER ..................................................................... 115
MCD ........................................................................ 73
MOD ......................................................................136
[O]
ONSF ....................................................................153
[P]
[C]
CM0 ............................................................... 71, 118
CM1 ........................................................................ 72
CM2 ........................................................................ 74
CPSRF ................................................................... 77
CRCD ................................................................... 274
CRCIN .................................................................. 274
[D]
D4INT ..................................................................... 39
DA0 ....................................................................... 273
DA1 ....................................................................... 273
DACON ................................................................ 273
DCT0 to DCT3 .................................................. 125
DM0SL to DM3SL ............................................ 122
DMA0 to DMA3 ................................................. 124
DMD0 ................................................................... 126
DMD1 ................................................................... 127
DRA0 to DRA3 .................................................. 125
DRC0 to DRC3 ................................................. 125
DS ............................................................................ 49
DSA0 to DSA3 .................................................. 124
DTT ....................................................................... 186
P0 to P15 ............................................................285
PCR .......................................................................295
PD0 to PD15 ......................................................284
PLC0 ....................................................................... 75
PLC1 ....................................................................... 75
PM0 ......................................................................... 46
PM1 ......................................................................... 47
PM2 ......................................................................... 76
PRCR ..................................................................... 94
PS0 ........................................................................286
PS1 ........................................................................286
PS2 ........................................................................287
PS3 ........................................................................287
PSC .......................................................................290
PSL0 .....................................................................288
PSL1 .....................................................................288
PSL2 .....................................................................289
PSL3 .....................................................................289
PUR0 ....................................................................291
PUR1 ....................................................................291
PUR2 ....................................................................292
PUR3 ....................................................................293
PUR4 ....................................................................294
PWCR0 .................................................................. 66
PWCR1 .................................................................. 67
[E]
[R]
EWCR0 to EWCR3
........................................... 55
RLVL ........................................................... 105, 134
RMAD0 to RMAD7 ..........................................115
[I]
ICTB2 ................................................................... 185
IDB0 ...................................................................... 187
IDB1 ...................................................................... 187
IFSR ............................................................ 113, 205
Interrupt Control Register (1) ....................... 103
Interrupt Control Register (2) ....................... 104
INVC0 ................................................................... 180
INVC1 ................................................................... 181
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 351 of 352
[T]
TA0 to TA4 ..........................................................149
TA0MR to TA4MR ............... 145, 146, 147, 148
TA1, TA2, TA4, TA11, TA21, TA41 ............. 187
TA1MR, TA2MR, TA4MR ..............................183
TABSR ..............................................152, 171, 188
TB0 to TB5 .........................................................170
M32C/8A Group
Index
TB0MR to TB5MR ........................ 167, 168, 169
TB2 ........................................................................ 186
TB2MR ................................................................. 182
TB2SC ................................................................. 185
TBSR .................................................................... 171
TCSPR .......................................................... 77, 144
TRGSR ...................................................... 151, 184
[U]
U0BRG to U4BRG ........................................... 204
U0C0 to U4C0 ................................................... 203
U0C1 to U4C1 ................................................... 204
U0MR to U4MR ................................................ 198
U0RB to U4RB .................................................. 206
U0SMR to U4SMR .......................................... 199
U0SMR2 to U4SMR2 ..................................... 200
U0SMR3 to U4SMR3 ..................................... 201
U0SMR4 to U4SMR4 ..................................... 202
U0TB to U4TB ................................................... 206
UDF ....................................................................... 150
[V]
VCR1
VCR2
...................................................................... 38
...................................................................... 38
[W]
WDC .............................................................. 40, 119
WDTS ................................................................... 119
[X]
X0R to X15R ...................................................... 276
XYC ....................................................................... 276
[Y]
Y0R to Y15R ...................................................... 276
Rev.1.00 Jul 15, 2007
REJ09B0385-0100
Page 352 of 352
REVISION HISTORY
Rev.
Date
Rev.1.00
Jul 15, 2007
M32C/8A Group Hardware Manual
Description
Page
−
Summary
First Edition issued
C-1
M32C/8A Group Hardware Manual
Publication Data :
Rev.1.00
Jul 15, 2007
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan
M32C/8A Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan