AZEBS10 Evaluation Board for AZS10 Ultra-Low Phase Noise Buffers & Translator www.azmicrotek.com DESCRIPTION FEATURES The AZEBS10 evaluation board is a multi-layer PCB assembly containing the AZS10 ultra-low phase noise buffer & translator and supporting components. It provides an excellent platform for initial design verification and validation of performance and functionality. • The AZS10 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for signals up to 1GHz. For designs with low amplitude signals, refer to the AZS15. The AZS10 is a configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 2 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance. • • APPLICATIONS • BLOCK DIAGRAM Crystal or SAW based oscillators with LVPECL or LVDS outputs LVDS, PECL clock reference and drivers LVDS, PECL Signal Conversion • GND VDD 2.5V-3.3V Operation Ultra-Low Phase Noise Floor o LVPECL -167dBc/Hz o LVDS -165dBc/Hz Configurable o LVPECL or LVDS output o ÷1 or ÷2 o Enable active high or low 1GHz+ bandwidth • EN VDD / 2 Q PECL divider (÷2) D receiver BOARD CONFIGURATION • mux LVDS QN b0 LOGIC • b1 www.azmicrotek.com +1-480-962-5881 Request a Sample Board is initially populated with a standard factory configuration as noted in this datasheet Board comes standard with 2 (two) installed AZS10 parts o SON8 (1.5mm x 1.0mm) 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description for AZS10 Pin 1 2 3 4 5 6 7 8 Name EN Q QN GND D B0 B1 VDD I/O/P I O O P I I I P Description Enable Output Signal Output Signal Negative Supply Input Signal Configuration Bit Configuration Bit Positive Supply 1 Q 2 QN 3 GND 4 S <Date Code> EN Properties Configurable functionality Configurable (LVPECL, LVDS) Configurable (LVPECL, LVDS) 0V Tertiary Levels Tertiary Levels 2.375V - 3.6V 8 VDD 7 B1 6 B0 5 D Figure 1 – Pin Configuration for AZS10Q (included on board) ENGINEERING NOTES FUNCTIONALITY The AZS10 has 8 configurations which are determined by the static voltage levels of B0 and B1. Table 2 details the configurations. Table 2 - Possible IC Configuration Configuration Bits B0 Open Open Open Low Low Low High High High www.azmicrotek.com +1-480-962-5881 Request a Sample B1 Open Low High Open Low High Open Low High Functional Configuration Output Type LVPECL LVPECL LVPECL LVPECL LVDS LVDS LVDS LVDS Not Used Enable Polarity Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used Division ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used 2 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 PARTS LIST Table 3 lists the factory installed parts and jumpers. As shipped, the AZEBS10 supports single supply operation. Other parts on the board are not installed, allowing the customer to customize the board for their internal needs. Table 3 – Evaluation Board Parts List AZM Installed Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Reference # C1 C2, C3, C5 C7, C8, C9, C10 C4, C6 R1, R4 R2, R3 J1, J2, J3, J4, J5, J6 FB1 EN, BO, B1 (X1 & X2) VDD (X1 & X2) VDD GND X1, X2 N/A Description 22μF 16V 10% Tant Cap 0.01µF 50V 10% Cer Cap 0.01µF 50V 10% Cer Cap 1000pF 50V 10% Cer Cap 49.9Ω 1/10W 1% Res 100Ω 1/10W 1% Res SMA Female RT Angle Ferrite Chip 1500Ω 500mA 2x3 Header 0.100" 1x3 Header 0.100" Horizontal Banana Jack (RED) Horizontal Banana Jack (BLK) AZS10QG Shorting Jumper 0.100" Case 2917 SMD 0402 SMD 0603 SMD 0402 SMD 0603 SMD 0603 SMD PCB Thru Hole 0603 SMD PCB Thru Hole PCB Thru Hole PCB Thru Hole PCB Thru Hole 8SON 1.5 x 1.0 N/A Optional Item 1 Reference # C11, C12 Description 0.01µF 50V 10% Cer Cap Case 0603 SMD 2 R5 100Ω 1/10W 1% Res 0603 SMD Optional components are used to create a LVDS load if the measurement device requires it. See Figure 16 for details. www.azmicrotek.com +1-480-962-5881 Request a Sample 3 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 AZEBS10 OPERATION OVERVIEW The AZEBS10 evaluation board is designed to evaluate all the operation modes of the AZS10. To do so, two (2) instances of the AZS10 are mounted to the board, one to evaluate LVPECL operation and one to evaluate LVDS operation. This is because the output loading is different for each of the output standard logic levels (Figure 2). X1 is for LVPECL operation X2 is for LVDS operation DUT – Device Under Test DUT – X1 LVPECL Outputs LVPECL Path CMOS Input (LVPECL Path) VDD 2.375V - 3.6V JUMPERS VDD LVDS Outputs GND CMOS Input (LVDS Path) LVDS Path DUT – X2 Figure 2 - AZEBS10 Evaluation Board Overview To minimize crosstalk and interference between the two mounted AZS10 parts, the AZEBS10 is designed to power one AZS10 DUT at a time. This is accomplished through the use of jumpers on the board. www.azmicrotek.com +1-480-962-5881 Request a Sample 4 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 TO PREVENT PERMANENT DAMAGE TO THE BOARD AND THE DUT(S), THE JUMPERS MUST BE CONFIGURED IN THE PROPER ORIENTATION ALL SHUNTS MUST BE ORIENTED IN THE VERTICAL POSITION WITH ONLY ONE SHUNT PER JUMPER CORRECT Figure 3 – Correct shunt orientation and connections WRONG Figure 4 – Wrong shunt orientation – This will damage evaluation board OPERATING MODES As described in Table 2, the AZS10 can be configured to operate eight (8) different ways to give the designer a flexible and robust part for a wide array of designs. This is evaluated with the jumpers. There are 4 jumper connections on the AZEBS10 that need to be made in order to evaluate the AZS10. These are: 1. 2. 3. 4. VDD Jumper – Selects which DUT is powered EN Jumper – Configures enable logic level high or low for X1 or X2 B0 Jumper – Configures B0 logic level for X1 or X2 (high, low or open) B1 Jumper – Configures B1 logic level for X1 or X2 (high, low or open) www.azmicrotek.com +1-480-962-5881 Request a Sample 5 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 CONFIGURATION 1 Configuration Bits B0 Open B1 Open Functional Configuration Output Type LVPECL Enable Polarity Active High Division ÷1 Figure 5 - Configuration 1 Jumper Connections • • • • X1 DUT is powered to VDD X1 EN pin is connected to VDD X1 B0 pin is left open X1 B1 pin is left open CONFIGURATION 2 Configuration Bits B0 B1 Open Low Functional Configuration Output Type Enable Polarity LVPECL Active High Division ÷2 Figure 6 - Configuration 2 Jumper Connections • • • • X1 DUT is powered to VDD X1 EN pin is connected to VDD X1 B0 pin is left open X1 B1 pin is connected to GND www.azmicrotek.com +1-480-962-5881 Request a Sample 6 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 CONFIGURATION 3 Configuration Bits B0 Open B1 High Functional Configuration Output Type LVPECL Enable Polarity Active Low Division ÷1 Figure 7 - Configuration 3 Jumper Connections • • • • X1 DUT is powered to VDD X1 EN pin is connected to GND X1 B0 pin is left open X1 B1 pin is connected to VDD CONFIGURATION 4 Configuration Bits B0 B1 Low Open Functional Configuration Output Type Enable Polarity LVPECL Active Low Division ÷2 Figure 8 - Configuration 4 Jumper Connections • • • • X1 DUT is powered to VDD X1 EN pin is connected to GND X1 B0 pin is connected to GND X1 B1 pin is left open www.azmicrotek.com +1-480-962-5881 Request a Sample 7 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 CONFIGURATION 5 Configuration Bits B0 Low B1 Low Functional Configuration Output Type LVDS Enable Polarity Active High Division ÷1 Figure 9 - Configuration 5 Jumper Connections • • • • X2 DUT is powered to VDD X2 EN pin is connected to VDD X2 B0 pin is connected to GND X2 B1 pin is connected to GND CONFIGURATION 6 Configuration Bits B0 B1 Low High Functional Configuration Output Type Enable Polarity LVDS Active High Division ÷2 Figure 10 - Configuration 6 Jumper Connections • • • • X2 DUT is powered to VDD X2 EN pin is connected to VDD X2 B0 pin is connected to GND X2 B1 pin is connected to VDD www.azmicrotek.com +1-480-962-5881 Request a Sample 8 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 CONFIGURATION 7 Configuration Bits B0 High B1 Open Functional Configuration Output Type LVDS Enable Polarity Active Low Division ÷1 Figure 11 - Configuration 7 Jumper Connections • • • • X2 DUT is powered to VDD X2 EN pin is connected to GND X2 B0 pin is connected to VDD X2 B1 pin is left open CONFIGURATION 8 Configuration Bits B0 B1 High Low Functional Configuration Output Type Enable Polarity LVDS Active Low Division ÷2 Figure 12 - Configuration 8 Jumper Connections • • • • X2 DUT is powered to VDD X2 EN pin is connected to GND X2 B0 pin is connected to VDD X2 B1 pin is connected to GND www.azmicrotek.com +1-480-962-5881 Request a Sample 9 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 INPUT TERMINATIONS The AZS10 input terminal bias is VDD/2 fed by an internal 10kΩ resistor. For clock applications, the input signal is AC coupled into the D input to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. See Figure 17 for schematic details. Signal Source AZEBS10 AZS10 D 0.01µF Input signal 50Ω 10kΩ VDD/2 Figure 13 – Input Termination OUTPUT TERMINATIONS LVPECL Most RF and phase noise test sets use AC coupled inputs. Figure 14 shows the AZEBS10 interfacing to test equipment, meeting both DC and AC termination requirements. On-board 100Ω resistors form the DC load. See AZS10 Application Notes for alternative loading. The test equipment 50Ω input impedance provides the AC termination through C1 and C2. Refer to Figure 17 for more details. VDD Vbp M2 M1 Vbn AZEBS10 Q 0.01µF QN 0.01µF 100Ω M4 M3 D AZS10 100Ω M5 Measurement Device 50Ω 50Ω GND or VT Figure 14 - LVPECL Output Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 10 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 LVDS The following LVDS termination is compliant to the LVDS specification TIA/EIA-644A. By default, the AZEBS10 is configured to have the measurement device provide the correct LVDS loading (Figure 15). Alternatively, LVDS loading can be optionally mounted to the board with the addition of C11, C12 (and cutting the traces around them), and R5 defined in Table 3 and Figure 16. See Figure 17 for more details. VDD M2 M1 - + Measurement Device AZEBS10 350mV AZS10 100Ω Q QN Receiver R5 M4 M3 + - Figure 15 – Default LVDS Output Termination VDD M2 M1 - AZEBS10 + C11 Measurement Device 350mV AZS10 100Ω Q QN M4 M3 + Receiver R5 C12 - Figure 16 - Optional LVDS Output Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 11 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 SCHEMATICS Figure 17 - Evaluation Board Schematic www.azmicrotek.com +1-480-962-5881 Request a Sample 12 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 Figure 18 - Evaluation Board, Top View www.azmicrotek.com +1-480-962-5881 Request a Sample 13 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 Figure 19 - Evaluation Board, Bottom View www.azmicrotek.com +1-480-962-5881 Request a Sample 14 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZEBS10 Evaluation Board for AZS10 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 15 Apr 2014, Rev 1.0