AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers www.azmicrotek.com DESCRIPTION FEATURES The AZEBP53Q evaluation board is a multi-layer PCB assembly containing the AZP53 low phase noise buffer and supporting components. They provide an excellent platform for initial design verification and validation of phase noise. All signal paths are designed for 50Ω impedance matched operation. • • • • • The AZP53 is a sine wave/CMOS to LVPECL buffer/divider optimized for very low phase noise (-165dBc/Hz). It is particularly useful in converting crystal or SAW based oscillators into LVPECL outputs for up 800MHz of bandwidth. For greater bandwidth, refer to the AZP63. The AZP53 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Refer to Table 2 for the comparison of parts within the AZP5x and AZP63 family. APPLICATIONS • BLOCK DIAGRAM LVPECL outputs optimized for very low phase noise (-165dBc/Hz) Up to 800MHz bandwidth Selectable ÷1, ÷2 output Selectable Enable logic 3.0V to 3.6V operation Converting crystal or SAW based oscillators to LVPECL output BOARD CONFIGURATION • • www.azmicrotek.com +1-480-962-5881 Request a Sample Board is initially populated with a standard factory configuration as noted in this datasheet Board comes standard with an installed AZP53Q part o SON8 (1.5mm x 1.0mm) o Other packages available upon request 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description for AZP53Q Pin 1 2 3 4 5 6 7 8 Name Q Q EN GND D EN_SEL DIV_SEL VDD 1 Q 2 EN 3 GND 4 Function LVPECL Output LVPECL Output Enable Negative Supply Sine or CMOS Input Enable Select Divide Select Positive Supply D<Date Code> Q Type Output Output Input Power Input Input Input Power 8 VDD 7 DIV_ SEL 6 EN_ SEL 5 D Figure 1 – Pin Configuration for AZP53Q ENGINEERING NOTES FUNCTIONALITY The AZP53 is an instance of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. Table 3 lists the specific AZP53 functional operation. www.azmicrotek.com +1-480-962-5881 Request a Sample 2 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers Table 2 - AZP51-54 & AZP63 Family Part Number Divide Ratio EN Logic EN pullup/pull-down Bandwidth AZP51 AZP52 AZP53 AZP54 AZP63 ÷1 ÷2 Selectable ÷1 or ÷2 ÷1 Selectable ÷1 or ÷2 active HIGH active HIGH selectable active LOW selectable Pull-up Pull-up selectable Pull-down selectable > 800MHz > 800MHz > 800MHz > 800MHz ≥ 1GHz Table 3 - AZP53 Functional Operations, ÷1 mode Part Number EN_SEL High, NC1 AZP53 Low Inputs EN Low, NC1 High High, NC1 Low DIV_SEL Low, NC1 High 1 Not connected 2 Don't care 3 Tri-State www.azmicrotek.com +1-480-962-5881 Request a Sample D Low High Outputs Q Q Low High High Low X2 Low High Z3 Low High X2 Z3 High Low Z3 Z3 Divide Ratio ÷1 ÷2 3 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers EVALUATION BOARD Figure 2 - Evaluation Board Schematic www.azmicrotek.com +1-480-962-5881 Request a Sample 4 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers Figure 3 - Evaluation Board, Top View www.azmicrotek.com +1-480-962-5881 Request a Sample 5 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers Figure 4 - Evaluation Board, Bottom View www.azmicrotek.com +1-480-962-5881 Request a Sample 6 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers PARTS LIST Table 4 lists the factory installed parts and jumpers. As shipped, the AZEBP53Q supports single supply operation. Later sections illustrate how to configure the board for dual supply operation. Other parts on the board are not installed, allowing the customer to customize the board for their internal needs. Table 4 – Evaluation Parts List Factory Installed Reference Designator V+ Part Banana Jack Notes VDD Supply V- Banana Jack GND (single supply) JMP1 Wire jumper between the two terminals of JMP1 AZEBP53Q factory wired for single supply operation. SUP8 Wire jumper between SUP8, V+ pin and center pin of F8. VDD applied to DUT Pin 8 SUP4 Wire jumper between SUP4, Vpin and center pin of F4. GND/VSS applied to DUT Pin 4 C9, C11 C4, C8, C10, C12, L5, C1F, C2F, C5F 22μF, 16 V tantalum capacitor 3.5x2.8mm 0.01μF ceramic capacitor 0402 Surface Mount F1, F2, F5 Female SMA connector Amphenol 901-144-8RFX or equivalent DUT AZP53Q 1.5x1.0mm package (EBP53) R2-,R1- 200Ω Resistor 0402 Surface Mount R5- 50Ω Resistor 0402 Surface Mount Customer Installed (as required) Reference Designator R1+ to R8+, R3- to R4-, R6- to R8- Part Resistor Notes 0402 or 0603 Surface Mount C1-C3, C7 Capacitor 0402 or 0603 Surface Mount C3F, C4F, C6F – C8F, C1S – C8S Capacitor 0402 or 0603 Surface Mount L9, L10 Inductor or Ferrite Bead 1206 Surface Mount F3, F4, F6 – F8, S1 – S8 Female SMA connector Amphenol 901-144-8RFX or equivalent www.azmicrotek.com +1-480-962-5881 Request a Sample 7 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers AZEBP53Q CONNECTIONS AND OPERATING MODES DIVIDE MODE CONNECTIONS The DIV_SEL pin controls the divide by one (÷1) and divide by two (÷2) mode selection. Table 5 - Divide Mode Connections Divide Mode DIV_SEL (Pin 7) logic Jumper ÷1 (Factory Default) No Connect None ÷1 Low ÷2 High Jumper across the two pins of R7-. Jumper across the two pins of L7. Jumper across the two pins of R7+. Jumper across the two pins of L7. R7+, R7- L7 Figure 5 - Divide Mode Jumpers www.azmicrotek.com +1-480-962-5881 Request a Sample 8 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers ENABLE SELECT CONNECTIONS The EN_SEL pin controls the logic polarity of the enable (EN) pin. Table 6 - Enable Select Jumpers Enable (EN, Pin 3) Mode 1 Active Low (Factory Default) 1 Active Low Active High 2 EN_SEL (Pin 6) logic Jumper No Connect None High Low 1 Active Low: Outputs are enabled when EN Low or no connect, tri-state when EN high. 2 Active High: Outputs are enabled when EH High or no connect, tri-state when EN low. Jumper across the two pins of R6+. Jumper across the two pins of L6. Jumper across the two pins of R6-. Jumper across the two pins of L6. R6+, R6-, L6 Figure 6 - Enable Select Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 9 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers POWER SUPPLY CONNECTIONS The evaluation board supports two methods of power supply connection. One method uses a single +3.3 V supply connected between VDD and GND. The other method uses dual supplies, +2.0 V connected to VDD and -1.3 V connected to VSS (IC Ground). Dual supply operation (VDD=+2.0V, VSS=-1.3V) enables direct coupling to 50Ω test equipment loads. The AZEBP53Q is factory configured for a single +3.3 V Supply. Table 7 - Power Supply Jumpers Supply Type Single +3.3 V Supply (Factory Default) Dual Supply (+2.0, -1.3 V) Voltage Connect to PCB Pin Jumper VDD (+3.3 V) V+ Jumper between the center pin of F8 and the V+ pin of SUP8. Jumper across the two pins of JMP1 GND GND, V- VDD (+2.0 V) V+ GND GND VSS (-1.3 V) V- Jumper between the center pin of F4 and the V- pin of SUP4. Jumper between the center pin of F8 and the V+ pin of SUP8. Jumper between the center pin of F4 and the V- pin of SUP4. JMP1 F8, SUP8 F4, SUP4 Figure 7 – Power Supply Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 10 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers SINGLE SUPPLY LVPECL OUTPUT TERMINATION (FACTORY DEFAULT) Most RF and phase noise test sets use AC coupled inputs. Figure 10 shows evaluation board interfacing to test equipment, meeting both DC and AC termination requirements. On-board 200Ω resistors (R1-, R2-) form the required DC loads. The test equipment 50Ω input impedance provides the AC termination through C1F and C2F. The parallel combination of the on-board 200Ω and test equipment 50Ω resistors results in a net 40Ω AC load termination, which is close enough to 50Ω for almost all measurement purposes. OUTPUT STAGE +3.3 V, VDD (V+, PIN 8) M1 M2 VPREF D (Internal) M3 M4 M5 VNREF GND (PIN 4) 16 mA JUMPER ACROSS C1F L1, L2 0.01 μF CUT PCB JUMPERS ACROSS C1F, C2F Q (PIN 1) F1 Q (PIN 2) F2 L2 R2200Ω S1 L1 R1200Ω GND C2F 0.01 μF 50Ω 50Ω S2 CUT PCB TRACES TO S1, S2 NEAR CHIP PCB CIRCUITRY EXTERNAL CIRCUITRY OR TEST EQUIPMENT GND Figure 8 - Single Supply Output Schematic JUMPER CUT Figure 9 - Single Supply Output Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 11 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers DUAL SUPPLY LVPECL OUTPUT TERMINATION (OPTIONAL CONFIGURATION) The AZP53 design contains LVPECL compatible current drive output stages to maximize switching speed shown in Figure 8. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. The associated output voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs. Both outputs should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. OUTPUT STAGE +2.0 V, VDD (V+, PIN 8) M1 M2 VPREF D (Internal) PCB CIRCUITRY M3 Q (PIN 1) F1 Q (PIN 2) F2 S1 M4 M5 EXTERNAL CIRCUITRY 50Ω 50Ω S2 16 mA CUT PCB TRACES TO S1, S2 NEAR CHIP VNREF -1.3 V, VSS (V-, PIN 4) GND Figure 10 - Dual Supply Output Schematic CUT Figure 11 - Dual Supply LVPECL Output Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 12 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers SINGLE SUPPLY FOUR RESISTOR TERMINATION (OPTIONAL CONFIGURATION) The four resistor technique eliminates the need for two power supplies and provides a Thevenin equivalent 50Ω termination. However the external circuitry must be high impedance to maintain the 50Ω loading. R1+, R1-, R2+ and R2- are customer installed items OUTPUT STAGE +3.3 V, VDD (V+, PIN 8) M1 PCB CIRCUITRY M2 VPREF R2+ 82Ω Q (PIN 1) Q (PIN 2) D (Internal) M3 M4 16 mA M5 VNREF R1+ 82Ω JUMPER PCB ACROSS L1, L2 F1 EXTERNAL CIRCUITRY F2 L1 S1 L2 S2 R2130Ω R1130Ω CUT PCB TRACES TO S1, S2 NEAR CHIP GND (PIN 4) Figure 12 - Single Supply Four Resistor Schematic JUMPER CUT . Figure 13 - Single Supply Four Resistor Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 13 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers INPUT CONNECTION The AZP53 input terminal bias is VDD/2 fed by an internal 10kΩ resistor. For clock applications, the input signal should be AC coupled into the D or D ¯ input to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. The values of C5F, L5 and R5- depend on the specific application. C5F is typically 0.01μF, L5 (capacitor) is also typically 0.01μF and R5- is typically 50Ω. R5-, C5F, and L5 are factory default installed items. CUT PCB JUMPER ACROSS C5F D(D) DRIVE SIGNAL AZP53/AZP63 INPUT STAGE (inside IC) F5 C5F 0.01µF 10kΩ L5 0.01µF R550Ω VDD/2 CUT PCB TRACE TO S5 NEAR CHIP S5 Figure 14 - Input Connection Schematic CUT Figure 15 - Input Connection Wiring www.azmicrotek.com +1-480-962-5881 Request a Sample 14 May 2012, Rev 2.0 Arizona Microtek, Inc. AZEBP53Q Evaluation Board for AZP53 Low Phase Noise Buffers Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 15 May 2012, Rev 2.0