Headphone Amplifiers Digital Input Class-D Headphone Amplifier BU7839GVW No.10102EAT03 ●Description Most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized.BU7839GVW has Stereo Audio DAC and HP amp functions for digital audio playback. Pop sound in ramp-up period is reduced due to built-in start-up sound reduction circuit or transistor for mute. Also, Built-in digital volume which can control L-ch & R-ch separately. ●Features 1) With Stereo Audio DAC and HP amp functions 2) Most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized 3) Pop sound in ramp-up period is reduced due to built-in start-up sound reduction circuit or transistor for mute 4) Built-in digital volume which can control L-ch & R-ch separately Immediate switching and zero cross switching for reduction of clicking sound at the time of gain change Gain change methods of soft switching can be selected with registers 5) Sampling frequency compatible with 8kHz-48kHz 6) Compatible with master slave with built-in PLL 7) Built-in soft mute function 8) Compatible with full front and full back formats 9) Compatible with 16, 18 & 24bit formats 10) Compatible with fs=32kHz,44.1kHz,48kHz with de-emphasis function 11) 2wire CPU I/F (2 addresses selectable 33h, 36h) ●Functions Stereo Audio DAC + HPamp ・2wire CPU I/F ・Serial audio I//F ・Interpolator ・ΔΣModulator ・Level Shifter ・PLL www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/15 2010.05 - Rev.A BU7839GVW Technical Note ●Absolute maximum rating Parameter Symbol Ratings Unit Analog power supply voltage AVDD -0.3 ～ 4.5 V Digital power supply voltage DVDD -0.3 ～ 2.1 V DVDDIO -0.3 ～ 4.5 V Terminal applied voltage 1 VIN1 DVSS-0.3 ～ DVDDIO+0.3 V Terminal applied voltage 2 *1 VIN2 DVSS-0.3 ～ 4.5 V Digital IO power supply voltage Allowance loss Pd 520 *2 mW Storage temperature range Tstg -50 ～ 125 ℃ Operation temperature range Topr -30 ～ 85 ℃ * 1 SDA,SCL terminal * 2 When you use at above Ta = 25 degree, 52mW are reduced concerning 1degree When you mount 114.6mm x 76.2mm x 1.6mm Note:When you use under the conditions which exceed this value, there are times when the device is destroyed. In addition usual operation is not guaranteed. ●Recommended operating range Parameter Analog power supply voltage Digital IO power supply voltage Digital power supply voltage www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Symbol Limits Unit Min Typ Max AVDD 2.5 2.8 3.0 V DVDDIO DVDD - 3.0 V DVDD 1.35 1.50 1.65 V 2/15 2010.05 - Rev.A BU7839GVW Technical Note ●External size figure 1PIN MARK 4.0±0.1 4.0±0.1 7839 0.08 0.9 MAX. 0.08 LOTNo. S S A P=0.65x4 0.7±0.1 0.7±0.1 0.65 24-Φ0.33±0.05 AB B P=0.65x4 S 0.65 Φ0.08 (Unit : mm) Fig.1 External size figure www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/15 2010.05 - Rev.A BU7839GVW Technical Note ●Block diagram MUTE_R VDD_R MCLK Interpolator BCLK ΔΣ Modulator Level Shifter VSS_R LRCLK SDI OUT_R Audio I/F MUTE_L VDD_L DVDDIO Interpolator ΔΣ Modulator Level Shifter OUT_L VSS_L DVSSIO 256fs PLLVDD SCL SDA 2wire CPU I/F Power on/off control Register PLL PLLCAP DVSS NRST ADR TEST DVDD DVSS REFCLK 12MHz in Fig. 2 Block diagram ●Description of each block ●2wire CPU I/F Interface with CPU, 2-wire control Write/read possible Device address is 2-address selectable (33h,36h) with ADR terminal ●Register This LSI is controlled all by register Write/read by 2wire CPU I/F ●Audio I/F Compatible with three modes of full front, full back and IIS Sampling frequency compatible with 8kHz～48kHz ●Interpolator,ΔΣModulator Variable over sampling, Order-variable ΔΣ modulator Optimum value is selected internally and automatically ●Level Shifter Level conversion in 3V series of analogue output Built-in mute transistor for start-up sound reduction ●PLL REFCLK terminal is taken as reference clock and 256fs is created It becomes the default setting when 12MHz is inputted to REFCLK Please change each setting if any frequency other than 12MHz is inputted to REFCLK www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/15 2010.05 - Rev.A BU7839GVW Technical Note ●Terminal table No Terminal name A1 MCLK Audio I/F Master clock A D Rest middle/ rear Initial value In/Out in 256fs B3 BCLK Audio I/F Bit clock B D In/Out in 64fs A2 LRCLK Audio I/F LR clock B D In/Out in fs Audio I/F Serial data E D In - - D - - C2 C1 SDI Classifi Digital/ cation Analog Function DVDDIO Digital IO VDD In/Out B4 SCL 2wire CPU I/F serial clock C D In - A5 SDA 2wire CPU I/F serial data D D In/Out in B2 NRST Reset E D In - Note I/O power supply L: reset A3 ADR Device address select E D In - L:33h or H:36h C3 TEST test pin E D In - Please connect to the ground D1 DVDD Digital core VDD - D - - Digital power supply A4 DVSS Digital core VSS - D - - Digital ground ﾞ H D In B5 REFCLK reference clock Input 10M～20MHz D5 PLLVDD PLL VDD - A - - C5 PLLCAP PLL capacitor F A Out Hiz PLL power supply C4 DVSS PLL, Digital VSS - D - - PLL, Digital ground ﾞ D4 VDD_R Analog VDD - A - - Rch power supply E4 OUT_R Rch output G A Out Hiz E5 MUTE_R Rch mute I A Out Hiz - A - - Rch ground Analog VDD - A - - Lch power supply Lch output G A Out Hiz I A Out Hiz - A - - D3 VSS_R Analog VSS E1 VDD_L E2 OUT_L D2 E3 MUTE_L Lch mute VSS_L Analog VSS For starting sound decrease For starting sound decrease Lch ground ●Terminal equivalent circuit figure DVDDIO DVDDIO LVS LVS A LVS B C DVSSIO DVSSIO DVSSIO PLLVDD DVDDIO LVS E D DVSSIO LVS F DVSSIO PLLVSS VDD_R VDD_L VDD_R VDD_R VDD_L VDD_L DVDDIO H G VSS_R VSS_R VSS_L VSS_L www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. LVS I DVSSIO VSS_R VSS_R VSS_L VSS_L 5/15 2010.05 - Rev.A BU7839GVW Technical Note ●Application circuit chart MUTE_R VDD_R 2.8V MCLK DSP ΔΣ Modulator Interpolator BCLK 220uF OUT_R Level Shifter 100uH 0.1uF VSS_R 16Ω LRCLK Audio I/F SDI MUTE_L VDD_L 2.8V DVDD～2.8V DVDDIO ΔΣ Modulator Interpolator 220uF OUT_L Level Shifter VSS_L 100uH 0.1uF 16Ω 256fs PLLVDD SCL CPU SDA 2wire CPU I/F Power on/off control Register 2.8V 0.068uF PLL PLLCAP DVSS NRST L: reset DVDD TEST ADR DVSS Device address L: 33h H: 36h REFCLK 12MHz in 1.5V Recommended parts Coil : murata Manufacturing LQH32CN101K23 Schottky diode : ROHM RSX201L-30 Capacitor : Rohm TCTAL0G227M8R-D2 Fig.3 Application circuit chart ●Measurement circuit chart MUTE_R VDD_R 2.8V MCLK DSP ΔΣ Modulator Interpolator BCLK Level Shifter 220uF OUT_R 100uH 0.1uF VSS_R LRCLK SDI Audio I/F 20KHz LPF A-Weight Audio Analyzer 20KHz LPF A-Weight Audio Analyzer 16Ω MUTE_L VDD_L 2.8V DVDD～2.8V DVDDIO ΔΣ Modulator Interpolator Level Shifter 220uF OUT_L 100uH VSS_L 0.1uF 16Ω 256fs PLLVDD SCL CPU SDA 2wire CPU I/F Power on/off control Register 2.8V 0.068uF PLL PLLCAP DVSS NRST L: reset ADR Device address L: 33h H: 36h TEST DVDD DVSS REFCLK 12MHz in 1.5V Fig.4 Measurement circuit chart www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/15 2010.05 - Rev.A BU7839GVW Technical Note ●Electrical Characteristic Ta=25degree,DVDD=DVDDIO=1.5V,VDD_R=VDD_L=PLLVDD=2.8V,REFCLK=12MHz,fs=44.1kHz,f=1kHz,Load=16Ω, A-weight,20kHzLPF,Slave mode Limits Parameter Symbol Unit Condition MIN TYP MAX Static consumption current DVDD IDDst - - 10 µA At the time of standby Static consumption current VDD_R+VDD_L ICCst - - 10 µA At the time of standby Static consumption current PLLVDD IPLLst - - 10 µA At the time of standby Consumption current DVDD IDD - 0.6 2.0 mA At the time of 0.1mW output (in slave mode) Consumption current VDD_R+VDD_L ICC - 2.0 6.0 mA At the time of 0.1mW output Consumption current PLL IPLL - 0.8 2.5 mA Output amplitude error Vout -2 - 2 dB Errors with reference to standard values at the time of 0dBFS output are as follows Channel-to-channel gain error Gerr -1 - 1 dB Lch-Rch S/N SN 60 80 - dB 0dBFS, A-Weight THD -40 -60 - dB -3dBFS, A-Weight Channel-to-channel isolation Iso 65 80 - dB 0dBFS, 1kHz BPF PSRR Psrr - 0 - dB THD+N <S/N measuring method> Measure the level ratio of the respective integral values of the signals and noise within the band of 20kHzLPF +A-Weight. <THD+N measuring method> Measure the level ratio of the total harmonic component + (plus) noise and the basic wave frequency component within the band of 20kHzLPF +A-Weight. ●Output amplitude error Output amplitude is determined by the equivalent series resistance of external coil. Let Lr, VDD and Z respectively stand for the equivalent series resistance, the power supply voltage value of VDD_R,VDD_L and the load impedance, the standard value of output amplitude becomes the following equation: Standard value of output amplitude [Vpp] = VDD x 0.5 x Z / ( Lr + Z + 2 ) OUT_R OUT_L Level Shifter 220uF LrΩ 100uH 2Ω ZΩ (16Ω) 0.1uF Shown in the following table is the standard values of output amplitude if VDD=2.8V, Load impedance Z=16Ω, and Equivalent series resistance is 0.7Ω, 4Ω or 7Ω. Equivalent series resistance [Ω] Standard value of output amplitude [Vpp] Standard value of output amplitude [dBv] Output power [mW] 0.0 1.24 -7.13 12.10 0.7 1.20 -7.46 11.21 4.0 1.02 -8.87 8.10 7.0 0.90 -9.98 6.27 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/15 2010.05 - Rev.A BU7839GVW Technical Note ●DC characteristic Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V Standardized values Item Symbol MIN TYP MAX 0.7x Input ’H’ Level VIH DVDDIO 0.3x Input ’L’ Level VIL DVDDIO 0.8x Output ’H’ Level VOH DVDDIO 0.2x Output ’L’ Level 1 VOL1 DVDDIO Output ’L’ Level 2 0.2x VOL2 (SDA terminal) DVDDIO Table 10 DC characteristic ●2wire CPU I/F Part Unit Note V V V Io=-1mA V Io=1mA V Io=3mA Device address is "0110011"(33h) or "0110110"(36h), i.e. 33h when ADR terminal is L or 36h when ADR terminal is H. Please don’t switch the ADR terminal while 2wire CPU I/F is operating. The transmission rate is compatible with a maximum of 400kbps 2wire CPU I/F device address ADR W/R A7 A6 A5 A4 A3 A2 A1 0 0 1 1 0 0 1 1 0/1 1 0 1 1 0 1 1 0 0/1 ・Bit transmission The data of 1bit is transmitted while SCL is H. In case of bit transmission, the signal transition of SDA can not be implemented while SCL is H. If SDA changes while SCL is H, START condition or STOP condition is generated, it is interpreted as control signal. SDA SCL SDA stable state: Data is effective SDA change is Possible ・START condition/STOP condition Data transmission on bus is not implemented while SDA and SCL are H. At this time, if SCL remains to be H and SDA is transited from H to L, then the START condition (S) is attained and so the access is started, and if SCL remains to be H and SDA is transited from L to H, then the STOP condition (P) is attained and so the access is terminated, which is shown below. SDA SCL S P START Condition STOP Condition This device accepts the continuous START condition and the continuous STOP condition. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/15 2010.05 - Rev.A BU7839GVW Technical Note ・Acknowledge After START condition is generated, data is transmitted at 8 bits once. After 8 bit transmission, the transmitter opens SDA, and the receiver returns the acknowledge signal with SDA taken as L. SDA output by transmitter Non-acknowledge SDA output by receiver acknowledge SCL 1 S 2 8 9 Clock ulse for acknowledge STARTCONDITION ・Write protocol Write protocol is shown below. Register address is transmitted by 1 byte after device address and write command have been transmitted. Third byte writes the data, which is written in by second byte, into internal register, and for fourth byte and subsequent bytes, the register address is incremented automatically. But, the register address becomes 00h by the transmission of 1 byte after the register address has become the final address (6Ch). The address is incremented after the transmission is over. S 0 1 1 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A data Register address Device address Register address increment Register address increment R/W=0 (Write in) Transmitting set is on Master side Transmitting set is on Slave side P data A = Acknowledge A = Non-acknowledge S = START condition P = STOP condition Sr= Retransmission starting condition ・Readout protocol Readout starts from 1 byte after device address and R/W bit have been written in. For the address after the readout register is finally accessed and the subsequent addresses, the data of the addresses that have been incremented is read out. As the readout of 1 byte after the address has become the final address, 00h is read out. The address is incremented after the transmission is over. S 0 1 1 0 0 1 1 0 A D7 D6 D5 D4 D3 D2 D1 D0 A Device address data R/W=0 (Write in) P data Register address increment Transmitting set is on Master side Transmitting set is on Slave side www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. D7 D6 D5 D4 D3 D2 D1 D0 A 9/15 Register address increment A = Acknowledge A = Non-acknowledge S = START condition P = STOP condition Sr= Retransmission starting condition 2010.05 - Rev.A BU7839GVW Technical Note ・Compound readout protocol After internal address is specified, create the retransmission starting condition, change the data transmitting direction and implement the readout. Subsequently, the data of the address that has been incremented is read out. As the readout of 1 byte after the address has become the final address, 00h is read out. The address is incremented after the transmission is over. After retransmission starting condition, compound write is possible with R/W=0 (write in). S 0 1 1 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 0 Register address Device address R/W=0 (White in) 1 1 0 0 1 1 1 A Slave address R/W=1(Read out) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 Data Data A P Register address increment Register address increment A = Acknowledge A = Non-acknowledge S = START condition P = STOP condition Sr= Retransmission starting condition Transmitting set is on Master side Transmitting set is on Slave side ・Timing diagram (Repeated) START condition t SU;STA t BUF BIT 7 t LOW t BIT 6 1/f HIGH Acknowledge STOP condition SCLK SCL SDA t HD;STA t SU;DAT t t HD;DAT SU;STO Ta=25 degree,DVDD=DVDDIO=1.8V, VDD_R=VDD_L=PLLVDD=3.0V Item Symbol Standard mode High-speed mode Unit min max min max fSCLK 0 100 0 400 kHz tHD;STA 4.0 - 0.6 - μs "Ｌ" Level time of SCL tLOW 4.7 - 1.3 - μs "H" Level time of SCL tHIGH 4.0 - 0.6 - μs Setup time of repeated START condition tSU;STA 4.7 - 0.6 - μs Data hold time ※1 tHD;DAT 0.1 3.45 0.1 0.9 μs Data setup time tSU;DAT 250 - 100 - ns Setup time of STOP condition tSU;STO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs SCL clock frequency Hold time of START condition Bus opening time between STOP condition and START condition *1 The maximum tHD;DAT is not allowed to exceed the “L” level time （tLOW） of SCL signal www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/15 2010.05 - Rev.A BU7839GVW Technical Note ●Audio I/F part ■At slave mode. Ta=25degree ,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8 V Limit Parameter Symbol MIN TYP MAX Unit Condition Fmclk = 256fs or 384fs MCLK frequency *1 Fmclk 2.048 - 18.432 MHz MCLK Duty Cycle Dmclk 40 - 60 % BCLK frequency Fbclk 0.512 - 3.072 MHz BCLK Duty Cycle Dbclk 40 - 60 % LRCLK frequency Flrclk 8 - 48 kHz LRCLK Hold Time Thdlr 80 - - ns SDI Setup Time Tsusdi 80 - - ns SDI Hold Time Thdsdi 80 - - ns Fbclk = 64fs Flrclk = 1fs *1 It is not necessary to adjust the phase of MCLK and BCLK and LRCLK, but it is necessary to be something related to synchronization Flrclk LRCLK Thdlr Thdlr BCLK Fbclk SDI Tsusdi Thdsdi Fig.5 Audio I/F AC timing(at slave mode) ■At master mode Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V Limit Parameter Symbol MIN TYP MAX Unit Condition BCLK frequency Fbclk 0.512 - 3.072 MHz Fbclk = 64fs LRCLK frequency Flrclk 8 - 48 kHz Flrclk = 1fs SDI Setup Time Tsusdi 80 - - ns SDI Hold Time Thdsdi 80 - - ns Flrclk LRCLK BCLK Fbclk SDI Tsusdi Thdsdi Fig.6 Audio I/F AC timing(at master mode) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/15 2010.05 - Rev.A BU7839GVW Technical Note ●Audio I/F format ・At bit[1:0]=”00” (16bit length) ■Rear stuffing format Lch LRCLK 0 1 2 3 13 14 15 Rch 16 17 18 29 30 31 0 1 2 3 13 14 15 16 17 18 29 30 31 0 BCLK SDI Don't care Don't care 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 Don't care 0 ■Front stuffing format Lch LRCLK 0 1 2 3 13 14 15 Rch 16 17 18 29 30 31 0 1 2 3 13 14 15 16 17 18 29 30 31 0 BCLK SDI 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Don't care 15 ■IISformat Lch LRCLK 0 1 2 3 4 14 15 Rch 16 17 18 19 30 31 0 1 2 3 13 14 15 16 17 18 19 30 31 0 BCLK SDI Don't care 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Don't care ・At bit[1:0]=”01” (18bit length) ■Rear stuffing Format Lch LRCLK 0 1 2 3 11 12 13 Rch 14 15 16 29 30 31 0 1 2 3 11 12 13 14 15 16 29 30 31 0 BCLK SDI Don't care Don't care 17 16 15 2 1 0 Don't care Don't care 17 16 15 2 1 0 Don't care ■Front stuffing format Lch LRCLK 0 1 2 3 15 16 17 Rch 18 19 20 29 30 31 0 1 2 3 15 16 17 18 19 20 29 30 31 0 BCLK SDI 17 16 15 2 1 0 Don't care Don't care 17 16 15 2 1 0 Don't care Don't care 15 ■IIS Format LRCLK Lch 0 1 2 3 4 16 17 Rch 18 19 20 21 30 31 0 1 2 3 13 16 17 18 19 20 21 30 31 0 BCLK SDI Don't care 17 16 15 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2 1 0 Don't care Don't care 12/15 17 16 15 2 1 0 Don't care Don't care 2010.05 - Rev.A BU7839GVW Technical Note ・At bit[1:0]=”10” (20bit length) ■Rear stuffing format Lch LRCLK 0 1 2 3 10 11 12 Rch 13 14 15 29 30 31 0 1 2 3 13 14 15 16 17 18 29 30 31 0 BCLK SDI Don't care Don't care 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care ■Front stuffing format Lch LRCLK 0 1 2 3 17 18 19 Rch 20 21 22 29 30 31 0 1 2 3 17 18 19 20 21 22 29 30 31 0 BCLK SDI 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care Don't care 19 ■IIS format LRCLK Lch 0 1 2 3 4 18 19 Rch 20 21 22 23 30 31 0 1 2 3 13 18 19 20 21 22 23 30 31 0 BCLK SDI Don't care 19 18 17 2 1 0 Don't care Don't care 19 18 17 2 1 0 Don't care Don't care ・At bit[1:0]=”11” (24bit length) ■Rear stuffing format Lch LRCLK 0 1 2 3 4 5 6 7 Rch 8 9 10 29 30 31 0 1 2 3 4 5 6 7 8 9 10 29 30 31 0 BCLK SDI Don't care 23 24 2 1 0 Don't care 23 22 2 1 0 Don't care ■Front stuffing format Lch LRCLK 0 1 2 3 22 23 24 Rch 25 26 27 28 29 30 31 0 1 2 3 22 23 24 25 26 27 28 29 30 31 0 BCLK SDI 23 22 21 1 0 Don't care 23 22 21 1 0 Don't care 23 ■IIS format LRCLK Lch 0 1 2 3 4 23 24 Rch 25 26 27 28 29 30 31 0 1 2 3 13 23 24 25 26 27 28 29 30 31 0 BCLK SDI Don't care 23 22 21 1 0 Don't care 23 22 21 1 0 Don't care Fig.7 Audio I/F Format www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/15 2010.05 - Rev.A BU7839GVW Technical Note ●PLL Part Ta=25degree,DVDD=DVDDIO=1.5V, VDD_R=VDD_L=PLLVDD=2.8V, REFCLK=12MHz, fs=44.1kHz specification Item Symbol Unit Condition MIN TYP MAX Lock up time Tlock - - 15 msec BCLK Duty Cycle Dbclk 40 - 60 % PLLCAP 0.068µF REFCLK 1/N 12MHz PD n32 n44 n48 VCO div_vco fs=48k,44.1k,32k fs refclk_enb p_pll 1/M 1/2 m32 m44 m48 fs=24k,22.05k,16k slave 1 256fs/384fs mclk_enb 1/4 fs=12k,11.025k,8k MCLK 0 1/4 BCLK 64fs LRCLK 1/256 fs slave D-Class Logic Fig.8 Block diagram of PLL part www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/15 2010.05 - Rev.A BU7839GVW Technical Note ●Ordering part number B U 7 Part No. 8 3 9 Part No. G V W - Package GVW:SBGA024W040 E 2 Packaging and forming specification E2: Embossed tape and reel SBGA024W040 <Tape and Reel information> 4.0 ± 0.1 0.9MAX. 4.0 ± 0.1 0.08 E D C B A Embossed carrier tape (with dry pack) Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) S 0.7± 0.1 24- φ 0.33±0.05 φ 0.08 M S AB A P=0.65×4 0.65 B 0.65 0.08 S 0.7±0.1 Tape P=0.65×4 1PIN MARK 1pin 1 2 3 4 5 (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Reel 15/15 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.05 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A