7. Autoranging Rectifier Module (ARM) Design Guide & Applications Manual For Maxi, Mini, Micro Family DC-DC Converters and Configurable Power Supplies The Autoranging Rectifier Module (ARM) provides an effective solution for the AC front end of a power supply designed with Vicor DC-DC converters. This high-performance power system building block satisfies a broad spectrum of requirements and agency standards. The ARM contains all of the power switching and control circuitry necessary for autoranging rectification, inrush current limiting, and overvoltage protection. This module also provides converter enable and status functions for orderly power up / down control or sequencing. To complete the AC front-end configuration, the user needs only to add hold-up capacitors and a suitable input filter with transient protection. POWER-DOWN SEQUENCE (Figure 7–2) When input power is turned off or fails, the following sequence occurs as the bus voltage decays: 1.2 Bus OK is de-asserted when the bus voltage falls below 205 Vdc (typical). 2.2 The converters are disabled when the bus voltage falls below 200 Vdc. If power is reapplied after the converters are disabled, the entire power-up sequence is repeated. If a momentary power interruption occurs and power is re-established before the bus reaches the disable threshold, the power-up sequence is not repeated. FUNCTIONAL DESCRIPTION (Figure 7–1) +OUT Initial Conditions. The switch that bypasses the inrush limiting PTC (positive temperature coefficient) thermistor is open when power is applied, as is the switch that engages the strap for voltage doubling. In addition, the downstream DC-DC modules are disabled via the Enable (EN) line, and Bus OK (BOK) is high. PTC Thermistor Strap L Strap –OUT N POWER-UP SEQUENCE (Figure 7–2) EN Microcontroller 1.1 Upon application of input power, the output bus capacitors begin to charge. The thermistor limits the charge current, and the exponential time constant is determined by the hold-up capacitor value and the thermistor cold resistance. The slope (dv/dt) of the capacitor voltage approaches zero as the capacitors become charged to the peak of the AC line voltage. BOK Figure 7–1 — Functional block diagram Power Up 2.1 If the bus voltage is less than 200 V as the slope nears zero, the voltage doubler is activated, and the bus voltage climbs exponentially to twice the peak line voltage. If the bus voltage is greater than 200 V, the doubler is not activated. 90–132 V AC Line Output Bus (Vdc) 3.1 If the bus voltage is greater than 235 V as the slope approaches zero, the inrush limiting thermistor is bypassed. Below 235 V, the thermistor is not bypassed. 400 300 200 100 0 1.1 2.1 Strap PTC Thermistor Bypass Converter Enable Bus OK 4.1 The converters are enabled ~150 milliseconds after the thermistor bypass switch is closed. 5.1 Bus OK is asserted after an additional ~150 millisecond delay to allow the converter outputs to settle within specification. Power Down 3.1 ~150 ms ~150 ms 4.1 5.1 2.2 1.2 Figure 7–2 —Timing diagram: power up / down sequence Timing Diagram, Power Up/Down Sequence Maxi, Mini, Micro Design Guide Page 31 of 88 Rev 4.9 Apps. Eng. 800 927.9474 vicorpower.com 800 735.6200 7. Autoranging Rectifier Module (ARM) Design Guide & Applications Manual For Maxi, Mini, Micro Family DC-DC Converters and Configurable Power Supplies OFF-LINE POWER SUPPLY CONFIGURATION capacitors were being charged through an un-bypassed thermistor, preventing the bus voltage from reaching the thermistor bypass threshold, thus disabling the power supply. The Enable output (the drain of a N channel MOSFET) is internally pulled up to 15 V through a 150 kΩ resistor. The ARM maintains the DC output bus voltage between 200 and 375 Vdc over the entire universal input range, this being compatible with the Maxi, Mini, Micro 300 V input converters as well as VI-260 family and VI-J60 family DC-DC converters. The ARM automatically switches to the proper rectification mode (doubled or undoubled) depending on the input voltage, eliminating the possibility of damage due to improper line connection. The VI-ARM-x1 is rated at 500 W in the low range (90 –132 Vac input), and 750 W in the high range (180 – 264 Vac input). The VI-ARMB–x2 is rated for 750 W and 1,500 W for the low and high input ranges respectively. Either of these modules can serve as the AC front end for any number and combination of compatible converters as long as the maximum power rating is not exceeded. See VI-ARMB derating curves (Figures 1 and 2) on VI-ARM data sheet. A signal diode should be placed close to and in series with the PC or GATE IN pin of each converter to eliminate the possibility of control interference between converters. The Enable pin switches to the high state (15 V) with respect to the negative output power pin to turn on the converters after the power-up inrush is over. The Enable function also provides input overvoltage protection for the converters by turning off the converters if the DC bus voltage exceeds 400 Vdc. The thermistor bypass switch opens if this condition occurs, placing the thermistor in series with the input voltage, which reduces the bus voltage to a safe level while limiting input current in case the varistors conduct. The thermistor bypass switch also opens if a fault or overload reduces the bus voltage to less than 180 Vdc. Strap (ST) Pin. In addition to input and output power pin connections, it is necessary to connect the Strap pin to the junction of the series hold-up capacitors (C1, C2, Figure 7–3) for proper (autoranging) operation. Varistors across the capacitors provide input transient protection. The bleeder resistors (R1, R2, Figure 7–3) discharge the hold-up capacitors when power is switched off. CAUTION: There is no input to output isolation in the ARM, hence the –Out of the ARM and thus the –In of the downstream DC-DC converter(s) are at a high potential. If it is necessary to provide an external enable / disable function by controlling the DC-DC converter’s PC or GATE IN pin (referenced to the –In) of the converter an opto-isolator or isolated relay should be employed. Enable (EN) Pin. (Figure 7–4) The Enable pin must be connected to the PC or GATE IN pin of all converter modules to disable the converters during power up. Otherwise, the converters would attempt to start while the hold-up C3 R1 N N Filter Z1 L ST F3 +V VI-ARM L BOK EN C7* C8* –V F1 C1 +IN C10 V1 V2 PC (GATE IN) Vicor DC-DC Converter D3 PR –IN R2 PE Part Description C1,2 Holdup capacitors C3–6 C2 C4 Vicor Part Number R3 4700pF (Y2 type) 01000 R1,2 150 k, 0.5 W 00127-1503 V1,2 220 V MOV 30234-220 F1,2 Use reccommended fusing for specific DC-DC Converters D1,2 Diode 00670 C7,8* Film Cap., 0.61 µF 34610 C5 D1 F2 Z1 MOV (270 V) 30076 D3,D4 1N5817 26108 C10,C11 0.001 µF R3, R4** 250 Ω F3 ABC-10 A VI-ARM-_1 ABC-10 A VI-ARMB-_2 +IN R4 C11 PC (GATE IN) Vicor DC-DC Converter D2 D4 PR –IN Not used with VI-260/VI-J60 Sizing PCB traces: C6 All traces shown in bold carry significant current and should be sized accordingly. *Required if C1 & C2 are located more than 6 inches (15 cm) from output of VI-ARM. **Not used with VI-260/VI-J60 To additional modules Figure 7–3 — Typical ARM application Maxi, Mini, Micro Design Guide Page 32 of 88 Rev 4.9 Apps. Eng. 800 927.9474 vicorpower.com 800 735.6200 7. Autoranging Rectifier Module (ARM) Design Guide & Applications Manual For Maxi, Mini, Micro Family DC-DC Converters and Configurable Power Supplies Not used with VI-260/VI-J60 +IN +IN +5 Vdc N ST 15 Vdc PC (GATE IN) +V Vicor DC-DC Converter BOK Microcontroller EN BOK Microcontroller Vicor DC-DC Converter Secondary referenced EN PR –V L –IN PC +V 15 Vdc ST PR –V L N –IN To additional modules To additional modules Figure 7–4 — Enable (EN) function Figure 7–5 — Bus OK (BOK) isolated power status indicator R1 L2/N Z1 L1 C1 L1 L2 R2 N R4 CM R3 F1 GND C2 L3 C3 N L2/N ST C4 L C1 R1 CM CM F1 C6 ST C5 C2 L1 L1 C4 C3 L3 Z1 L4 L L2 R2 GND Part C1 C2, C3 C4 F1 L1, L2 L3 R1, R2 R3 R4 Z1 Description 1.0 µF 4700pF (Y2 type) 0.15µF 10 A Max 27 µH 2.2 mH 10 Ω 150 kΩ, 0.5 W 2.2 Ω MOV Part L1,L4 L2, L3 C1 C2,C3,C4,C5 C6 R1 R2 F1 Z1 Vicor Part Number 02573 03285 03269 05147 32012 32006 Description 1,000 µH 12 A / 6.5 MΩ 22 µH 0.68 µF (X type) 4700pF (Y2 type) 0.22 µF (X type) 390 kΩ 1/2 W 10 Ω 1/2 W 15 A Max MOV Vicor Part Number 31743 33206 02573 03285 04068 30076 30076 Figure 7–6a — Recommended filter design; Low power filter connection for VI-ARM-x1 Figure 7–6b — Recommended filter design; High power filter connection for VI-ARMB-x2 Bus OK (BOK) Pin. (Figure 7–5) The Bus OK pin is intended to provide early-warning power fail information and is also referenced to the negative output pin. specified duration, i.e., the converters must hold up or ride through such an event while maintaining undisturbed output voltage regulation. Similarly, many of these same systems require notification of an impending power failure to allow time to perform an orderly shutdown. CAUTION: There is no input-to-output isolation in the ARM. It is necessary to monitor Bus OK via an optocoupler if it is to be used on the secondary (output) side of the converters. A line-isolation transformer should be used when performing scope measurements. Scope probes should never be applied simultaneously to the input and output as this will damage the module. Filter. Two input filter recommendations are shown for low-power VI-ARM-x1 and high-power VI-ARMB-x2. (Figures 7–6a and 7–6b) Both filter configurations provide sufficient common-mode and differential-mode insertion loss in the frequency range between 100 kHz and 30 MHz to comply with the Class B conducted emissions limit. The energy stored on a capacitor, which has been charged to voltage V, is: 2 where: Page 33 of 88 (1) C = capacitance V = voltage across the capacitor Energy is given up by the capacitors as they are discharged by the converters. The energy expended (the power-time product) is: Hold-up Capacitors. Hold-up capacitor values should be determined according to output bus voltage ripple, power fail hold-up time, and ride-through time. (Figure 7–7) Many applications require the power supply to maintain output regulation during a momentary power failure of Maxi, Mini, Micro Design Guide ε = 1/2(CV ) ε = stored energy Rev 4.9 Apps. Eng. 800 927.9474 ε = P∆t = C(V 12 – V22) / 2 (2) where: P = operating power ∆t = discharge interval V1 = capacitor voltage at the beginning of ∆t V2 = capacitor voltage at the end of ∆t vicorpower.com 800 735.6200 7. Autoranging Rectifier Module (ARM) Design Guide & Applications Manual For Maxi, Mini, Micro Family DC-DC Converters and Configurable Power Supplies Hold-up Time Ripple (V p-p) π–θ Power Fail Warning θ 254 V 205 V 190 V Ride-Through Time Bus OK Power Fail Converter Shut down Figure 7–7 — General timing diagram of bus voltage following interruption of the AC mains 100 90 35 Ride –Through Time (ms) Power Fail Warning Time (ms) 40 30 25 1,100 µF 820 µF 1,300 µF 1,600 µF µF (VI-ARM-x1) * 680 2,200 µF (VI-ARMB-x2) 20 15 10 * 5 0 250 70 90 Vac 50 40 30 20 750 1000 0 250 1500 1250 500 Operating Power (W) * 1500 75 Ripple Rejection (dB) P-P Ripple Voltage (Vac) 1250 80 25 * 15 10 5 500 1,100 µF 820 µF 1,300 µF 1,600 µF 750 µF (VI-ARM-x1) * 680 2,200 µF (VI-ARMB-x2) 1000 1250 70 65 60 55 50 45 40 1500 2 5 15 Operating Power (W) Maxi, Mini, Micro Design Guide 30 50 Output Voltage Figure 7–10 — Ripple voltage vs. operating power and bus capacitance, series combination of C1, C2 (Figure 7–3) Page 34 of 88 1000 Figure 7–9 — Ride-through time vs. operating power 30 0 250 750 Operating Power (W) Figure 7–8 — Power fail warning time vs. operating power and total bus capacitance, series combination of C1, C2 (Figure 7–3) 20 115 Vac 60 10 * 500 Total capacitance 820 µF 80 Figure 7–11 — Converter ripple rejection vs. output voltage (Typical) Rev 4.9 Apps. Eng. 800 927.9474 vicorpower.com 800 735.6200 7. Autoranging Rectifier Module (ARM) Design Guide & Applications Manual For Maxi, Mini, Micro Family DC-DC Converters and Configurable Power Supplies Rearranging equation 2 to solve for the required capacitance: C = 2P∆t / (V12–V22) The approximate operating ripple current (rms) is given by: Irms = 2P / Vac (3) (6) where: P = operating power level The power fail warning time (∆t) is defined as the interval between (BOK) and converter shutdown (EN) as illustrated in Figure 7–7. The Bus OK and Enable thresholds are 205 V and 190 V, respectively. A simplified relationship between power fail warning time, operating power, and bus capacitance is obtained by inserting these constants: Calculated values of bus capacitance for various hold-up time, ride-through time, and ripple voltage requirements are given as a function of operating power level in Figures 7–8, 7–9, and 7–10, respectively. C = 2P∆t / (2052 – 1902) EXAMPLE C = 2P∆t / (5,925) In this example, the output required at the point of load is 12 Vdc at 320 W. Therefore, the output power from the ARM would be 375 W (assuming a converter efficiency of 85%). The desired hold-up time is at least 9 ms over an input range of 90 to 264 Vac. It should be noted that the series combination (C1, C2, Figure 7–3) requires each capacitor to be twice the calculated value, but the required voltage rating is reduced to 200 V. Allowable ripple voltage on the bus (or ripple current in the capacitors) may define the capacitance requirement. Consideration should also be given to converter ripple rejection and resulting output ripple voltage. For example, a converter whose output is 15 V and nominal input is 300 V will provide typically 56 dB ripple rejection, i.e., 10 V p-p of input ripple will produce 15 mV p-p of output ripple. (Figure 7–11) Equation 3 is again used to determine the required capacitance. In this case, V1 and V2 are the instantaneous values of bus voltage at the peaks and valleys (Figure 7–7) of the ripple, respectively. The capacitors must hold up the bus voltage for the time interval (∆t) between peaks of the rectified line as given by: ∆t = (π– θ) / 2πf (4) θ = rectifier conduction angle (Figure 7–7) The approximate conduction angle is given by: θ = Cos-1V2 / V1 (5) Another consideration in hold-up capacitor selection is their ripple current rating. The capacitors’ rating must be higher than the maximum operating ripple current. Maxi, Mini, Micro Design Guide Determining Required Capacitance for Power Fail Warning. Figure 7–8 is used to determine capacitance for a given power fail warning time and power level, and shows that the total bus capacitance must be at least 820 µF. Since two capacitors are configured in series, each capacitor must be at least 1,640 µF. NOTE: The warning time is not dependent on line voltage. A hold-up capacitor calculator is available on the Vicor website, at http://asp.vicorpower.com/calculators/calculators.as p?calc=4 Determining Ride-through Time. Figure 7–9 illustrates ride-through time as a function of line voltage and output power, and shows that at a nominal line of 115 Vac, ridethrough would be 68 ms. Ride-through time is a function of line voltage. Determining Ripple Voltage on the Hold-up Capacitors. Figure 7–10 is used to determine ripple voltage as a function of operating power and bus capacitance, and shows that the ripple voltage across the hold-up capacitors will be 12 Vac. where: f = line frequency Page 35 of 88 Vac = operating line voltage Determining the Ripple on the Output of the DC-DC Converter. Figure 7–11 is used to determine the ripple rejection of the DC-DC converter and indicates a ripple rejection of approximately 60 dB for a 12 V output. If the ripple on the bus voltage is 12 Vac and the ripple rejection of the converter is 60 dB, the output ripple of the converter due to ripple on its input (primarily 120 Hz) will be 12 mV p-p. Rev 4.9 Apps. Eng. 800 927.9474 vicorpower.com 800 735.6200