APPLICATION NOTE | AN:024 Accurate Point-of-Load Voltage Regulation Using Simple Adaptive Loop Feedback By Maurizio Salato Principal Engineer, VI Chip® Applications Engineering Contents Page Introduction 1 Adaptive Loop Regulation Concept 1 PRM-AL Block Diagram 2 Introduction Accurate point-of-load (POL) voltage control is essential for highly dynamic electronic loads. ‘Adaptive loop’ is a technique for efficient, feed-forward compensation of isolated power management systems based on PRM® Regulator and VTM® Voltage Transformer combinations. This application note describes the design methodology for optimal DC set point compensation of PRM and VTM combinations[a], including small arrays of two identical VTMs driven by one PRM. DC Set Point Calculation 4 Considerations 8 Adaptive Loop with Half-Chip VTMs 9 For your reference, an automated spreadsheet version of the following procedure is available at http://cdn.vicorpower.com/documents/calculators/dcaldesign.xls. Adaptive Loop Regulation Concept Adaptive loop is a model-based, positive-feedback compensation technique that can easily complement negative feedback, voltage mode regulation. Figure 1 shows the conceptual block diagram. Design Example with VI Chip Customer Boards 13 Conclusion 17 Isolation barrier PRM output voltage Voltage loop Input power line K LOAD Output power line Factorized bus VTM PRM PRM output current Figure 1 Adaptive loop regulation conceptual diagram Adaptive loop Voltage drop model VTM temperature While the local voltage feedback loop maintains regulation at the PRM output, the adaptive loop (AL) provides compensation for the voltage drops that occur from the PRM output to the actual load. As stated before, AL is based on a model that requires VTM temperature and factorized bus current as inputs. The resistive behavior of power lines (factorized bus and output line) as well as the VTM, enables accurate modeling of their voltage drops. [a] The calculations represented in this application note apply to 24 V, 36 V and 48 V input PRMs. Though the same methodology applies to 28 V input MIL-COTS PRMs, care should be taken to apply the correct values. For further assistance, please contact a Field Applications Engineer via your local Technical Support Center. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 1 Major benefits of this approach are: • No signals need to be transmitted across VTM’s isolation barrier • Simpler circuit, lower component count Regulation accuracy is affected by the accuracy of this model; this application note explains how to optimize the model for a given system, and how to estimate the obtained accuracy. Standard regulation techniques are based on direct observation and integral error compensation of POL voltage, and the steady state error (compared to the reference) is therefore forced to be zero. AL only asymptotically approaches the zero error state, therefore widening the total distribution of the POL voltage. PRM-AL Block Diagram Figure 2 shows the functional block diagram for a full-chip PRM-AL regulator (e.g. P045F048T32AL). The OS and SC pins provide for local voltage feedback loop setting, while the VC and CD pins provide for settings and connections of the downstream system model. Figure 2 PRM-AL functional block diagram +OUT +IN 5 µF M1 D1 M2 M3 5 µF R16 93.1 kΩ OS G1=0.961 + PC Soft start and reference 10 kΩ R18 Enable Type 2 compensation VREF 1.24 V G2=0.0386 Modulator Error amplifier + IL PR 100 µA SC C18 0.22 µF 100 kΩ + 9 V, 5 mA max Inst. curr. protection Average current protection ∫ CD Q62 14 V 10 ms - IAL = V-OUT / RCD VH VC start pulse generator VC RS -IN SG 10 mΩ Adaptive loop -OUT In summary: • Local voltage feedback loop: – VREF, through R18, provides a reference voltage source on the SC pin. This is routed to the non-inverting input of the error amplifier, through the gain stage G1. – The factorized bus (+OUT) voltage is fed back to the inverting input of the error amplifier through R16. – SC and OS provide for the connection of the external resistor dividers. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 2 • Adaptive loop circuit: – The voltage controlled current source has variable gain, controlled by the resistance connected between CD and signal ground (SG) pins. The current injected on the VC line by the variable gain transconductance amplifier is: — directly proportional to the voltage across the sense resistor RS — inversely proportional to the resistor connected between CD and SG according to the following relationship: I AL = Equation 1 V-OUT R I = S F RCD RCD where IF is the factorized bus (PRM® output) current and V-OUT is the voltage drop across RS. – The VC pin voltage is added to the reference pin voltage SC through the gain stage G2. A PRM and VTM® system is considered, as shown in the block diagram in Figure 3. The system PCB adds further voltage drops from the PRM output to the load: the factorized bus resistance, RF, and the output line resistance, RO, which are assumed to be constant and equally divided on the positive and negative trace / wire. In order to account for them, these resistances must be estimated or measured. RF /2 +OUT +IN 5 µF 5 µF R16 93.1 kΩ + Error amplifier VTM RO /2 IOUT ROS2 PRM Type 2 compensation +OUT +IN ROS1 OS Modulator IF G1=0.961 + G2=0.0386 R18 10 kΩ 1.24 V RSC SC PNL / VF ROUT 0.22 µF C18 Vref K RCD LOAD Figure 3 Factorized Power Architecture (FPATM) system with adaptive loop control block diagram CD IAL = IF * RS / RCD SG IAL VC -IN RS VC -OUT 10 mΩ RVC RF /2 -IN RPTC -OUT RO /2 IF + IAL It is important to correctly identify the total voltage drop parameters, which are RF, ROUT and RO in this specific case. Their compensation model must therefore be resistive, and temperature dependent. Such a model is easy to implement, thanks to: • The PTC resistor embedded in the VTM module, which will change its value according to the VTM temperature. • RVC resistor, which allows precise match of RPTC to VTM ROUT temperature characteristic. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 3 The parallel of RVC and RPTC resistors, in series with RF/2 and RS resistors constitutes the voltage drop model. The AL circuitry forces a scaled version of the PRM output current (IAL) in the VC line, which then merges with the factorized bus current IF on its return path (as shown in Figure 4). Figure 4 Voltage drop model for the considered system Scaled PRM output current Modeled voltage drop VTM temperature IAL = IF • RS / RCD VC RS 10 mΩ -OUT VC RVC RF /2 -IN R PTC IF IF + IAL The voltage obtained on the VC pin, with some scale factor, is the model of the total voltage drop in the system. DC Set Point Calculation The necessary inputs to the procedure are shown in Table 1. Table 1 Adaptive loop calculation procedure inputs Standard Full-Chip VTM Characteristics • ROUT_25: 25ºC output resistance • ROUT_100: 100ºC output resistance Power System Characteristics • VF_NOM: nominal factorized bus voltage at no load • IOUT: maximum system (VTM) output current • K: transformer ratio • RPTC_25: PTC resistance at 25ºC • RPTC_100: PTC resistance at 100ºC • RF: factorized bus (PRM to VTM) total resistance • PNL: no load power dissipation at nominal input voltage • RO: output bus (VTM to point of load) total resistance AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 4 Table 2 summarizes the data for standard full-chip VTM® transformers. It is important to note that the internal resistors in the PRM have 1% tolerance. Table 2 Standard full-chip VTM data required (typical) Output Resistance VTM Part Number Temperature Sensor ROUT_25 ROUT_100 Tolerance Temp. RPTC_25 Coeff.(TCR) [%/°C] [%] 0.39 5 [mΩ] [mΩ] [%] [Ω] V048F015T100 0.99 1.17 11 3000 V048F020T080 1.31 1.56 10 2000 V048F030T070 1.61 1.97 10 V048F040T050 2.76 3.29 8 V048F060T040 5.76 6.73 5 V048F080T030 7.54 8.76 8 V048F096T025 V048F120T025 9.84 10.85 11.97 13.39 10 6 V048F160T015 29.76 32.80 7 V048F240T012 48.11 57.17 4 V048F320T009 79.48 96.10 6 V048F480T006 177.44 215.63 5 Tolerance 1000 560 510 With reference to Figure 3: A.Calculate the maximum voltage drop (at 25ºC and 100ºC) due to VTM output resistance ROUT. Equation 2 ΔVROUT _ 25 = ROUT _ 25 ⋅ IOUT Equation 3 ΔVROUT _ 100 = ROUT _ 100 ⋅ I OUT B. Calculate the maximum current flowing on the factorized bus. I F = K ⋅ I OUT + Equation 4 PNL VF _ NOM Although the no load power (PNL) required by the VTM is input voltage dependent, the variation has only a minor influence on the AL compensation, and will therefore be neglected in the following steps. C.Calculate the total PRM output voltage increase that will compensate all the drops (factorized bus resistance, VTM output resistance and output bus resistance). Equation 5 ΔVF _ 25 = Equation 6 ΔVF _ 100 = AN:024 ΔVROUT _ 25 + RO I OUT K ΔVROUT _ 100 + RO I OUT vicorpower.com K + ( RF + RS ) ⋅ I F + ( RF + RS ) ⋅ I F Applications Engineering: 800 927.9474 Page 5 D.Calculate the total temperature coefficient of the power circuit and the RVC resistor needed to match it. The PTC resistor and the VTM® ROUT resistance are subject to the same temperature, but they have different rates of change, as shown in Figure 5. Figure 5 ROUT and RPTC vs. VTM internal temperature RPTC ROUT RPTC_100 ROUT_100 ROUT_25 RPTC_25 25 100 TVTM [ºC] In order for the model to precisely match the voltage drop over temperature, its slope must match the system slope. The RVC resistor in parallel to RPTC can be calculated in order to meet this condition. RVC ⋅ RPTC _ 100 ΔRTOT = ΔVF _ 100 ΔVF _ 25 = RVC + RPTC _ 100 RVC ⋅ RPTC _ 25 RVC + RPTC _ 25 Equation 7 RVC = (1 − ΔRTOT ) RPTC _ 25 ⋅ RPTC _ 100 ΔRTOT ⋅ RPTC _ 25 − RPTC _ 100 There is an important reason for choosing a parallel rather than a series resistor to match the system temperature coefficient. At start-up, the PRM issues a 14 V, 10 ms pulse on the VC line to synchronously start the VTM. A series resistor would cause significant amplitude change on this signal, avoided by the parallel arrangement. However, the designer should exercise judgment and avoid extreme cases, where the temperature dependency might be so low as to cause the RVC value to fall below 200 Ω (which would cause overload during the 14 V, 10 ms startup pulse). E. Calculate the maximum VC pin voltage for the given system at 25ºC (100ºC should provide the same value, given the temperature dependency has been taken care of through RVC, [7]): VC _ MAX _ 25 = I AL ⋅ RPTC _ 25 ⋅ RVC RPTC _ 25 + RVC ⎛R ⎞ + ( I F + I AL ) ⋅ ⎜ F + RS ⎟ = ⎝ 2 ⎠ Equation 8 = RS AN:024 IF ⋅ RPTC _ 25 ⋅ RVC RCD _ MIN RPTC _ 25 + RVC vicorpower.com + ( I F + RS IF ⎛R ⎞ ) ⋅ ⎜ F + RS ⎟ RCD _ MIN ⎝ 2 ⎠ Applications Engineering: 800 927.9474 Page 6 Minimum allowable RCD value for current products is 20 Ω. F. Calculate the needed (if any) VSC trim that allows enough AL dynamic range under the worst case: VC_MAX_25 and ΔVF_100 (this will allow enough design margin). The voltage on VC, through the gain stage G2, is summed to the reference voltage SC in order to compensate for the voltage drop ΔVF. Because the VC voltage dynamic range is set, VSC might be reduced in order to match the relative changes of factorized bus and adaptive loop compensation. ΔVF _ 100 Equation 9 VF _ NOM ≤ G2 ⋅ VC _ MAX _ 25 G1 ⋅ VSC VSC ≤ G2 ⋅ VC _ MAX _ 25 ΔV G1 F _ 100 VF _ NOM G1 and G2 gains are 0.961 and 0.0386 respectively. If VSC ≤ Vref = 1.24 V, the external resistor to be connected on SC will be easily calculated as following: RSC = R18 Equation 10 VSC Vref − VSC The absolute minimum value for VSC is 0.25 V, because of the characteristic of the internal error amplifier. The minimum resistance value for RSC is therefore 2550 Ω. G.Calculate the voltage feedback divider resistor needed to set the nominal output voltage. Equation 11 VF _ NOM = G1 ⋅ VSC R16 + ROS ROS ROS = G1 ⋅ R16 VSC VF _ NOM − G1 ⋅ VSC ROS defines the gain on the voltage feedback, which accommodates for the chosen reference voltage VSC. It is recommended to calculate its value using the VSC voltage obtained with a standardized value resistor as RSC. Moreover, if a standard value resistor is not available to match (within 0.2%) the calculated ROS value, it is strongly recommended to use a parallel configuration. H. Calculate the RCD resistor that allows AL to compensate for the drops (25ºC or 100ºC will give the same result, because of RVC). AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 7 First, substitute the VC line voltage at full IF current (room temperature): VC _ 25 = Equation 12 ⎞ ⎛R RS ⋅ I F RPTC _ 25 ⋅ RVC ⎛ RS ⋅ I F ⎞ ⋅ + ⎜⎜ + I F ⎟⎟ ⋅ ⎜ F + RS ⎟ RCD RPTC _ 25 + RVC ⎝ RCD ⎠ ⎠ ⎝ 2 into the expression for the related factorized bus increase: ΔVF _ 25 = G2 ⋅ VC _ 25 = G2 ⋅ R16 + ROS = ROS ⎞ ⎛R RS ⋅ I F RPTC _ 25 ⋅ RVC ⎛ RS ⋅ I F ⎞ R + ROS ⋅ + ⎜⎜ + I F ⎟⎟ ⋅ ⎜ F + RS ⎟ 16 RCD RPTC _ 25 + RVC ⎝ RCD ⎠ ROS ⎠ ⎝ 2 Then solve for RCD: G2 Equation 13 RCD = ⎛ R ⎞ ⋅R R16 + ROS R RS I F ⎜ PTC _ 25 VC + F + RS ⎟ ⎜R ⎟ 2 ROS ⎝ PTC _ 25 + RVC ⎠ ΔVF _ 25 − G2 R16 + ROS ⎛ RF ⎞ + RS ⎟ I F ⎜ ROS ⎝ 2 ⎠ Considerations In order to improve regulation accuracy, the following guidelines should be followed: - Discrepancy between the model and the system will directly affect regulation accuracy. System characterization is strongly recommended during the design phase, specifically factorized bus (RF) and output line (RO) resistances. - Statistical distribution of components values plays also a key role on accuracy distribution. To this end, ‘Monte Carlo’ (or similar) analysis and optimization is strongly encouraged. It should include all the components directly affecting regulation, i.e. setting resistors, model resistors and component characteristics. Any extra component designed in the system, i.e. filter inductors, connectors, etc., should also be included if affected by variability. - While the impact of RS and RF on VC voltage may be neglected in a few cases, it normally affects accuracy distribution. In order to evaluate it, both resistors should be included in the analysis. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 8 Adaptive Loop with Half-Chip VTMs The major difference between full- and half-chip VTMs is the absence of temperature feedback. While the full-chip VTMs implement a PTC resistor, the half-chip modules use a simple precision resistor, as shown in Figure 6. Figure 6 Adaptive loop regulation concept without temperature feedback Isolation barrier PRM output voltage Voltage loop Input power line LOAD Output power line Factorized bus K VTM PRM PRM output current Adaptive loop Voltage drop model VTM resistor ID The absence of temperature feedback slightly degrades the regulation accuracy; however, the half-chip units have tighter parameter distributions, which partially compensate for the reduced model accuracy. The control configuration in this case is shown in Figure 7. RF /2 +OUT +IN 5 µF 5 µF R16 93.1 kΩ Type 2 compensation Modulator + Error amplifier G1=0.961 + G 2=0.0386 R18 SC 10 kΩ 1.24 V +OUT +IN ROS2 HalfChip VTM RSC PNL / VF ROS1 OS PRM IF RO /2 IOUT ROUT 0.22 µF C18 Vref K LOAD Figure 7 Adaptive loop control with half-chip VTM RCD CD IAL = IF * RS / RCD SG IAL VC VC -IN RS -OUT 10 mΩ RVC RF /2 -IN -OUT RO /2 IF + IAL The voltage drop model also differs with the one for the full-chip version (Figure 3), resulting in the simpler one shown in Figure 8. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 9 Figure 8 Voltage drop model in systems with half-chip VTMs Scaled PRM output current Modeled voltage drop IAL = IF • RS / RCD VC RS VC -OUT 10 mΩ RVC RF /2 IF -IN IF + IAL Having explained the differences, it is now possible to revise the design procedure in this specific case. Table 3 shows the necessary inputs. Table 3 Adaptive loop calculation procedure inputs for half-chip VTMs Half-Chip VTM Characteristics Power System Characteristics • VF_NOM: nominal factorized bus voltage at no load • ROUT_25: 25ºC output resistance • ROUT_100: 100ºC output resistance • IOUT: maximum system (VTM) output current • K: transformer ratio • RVC: VTM VC pin internal resistance • RF: factorized bus (PRM to VTM) total resistance • PNL: no load power dissipation at nominal input voltage • RO: output bus (VTM to point of load) total resistance Table 4 summarizes the data for the half-chip VTMs. Table 4 Half-chip VTM data required (typical) Output Resistance VTM Part Number ID Resistor ROUT_25 ROUT_100 Tolerance RVC Tolerance [mΩ] [mΩ] [%] [Ω] [%] VIV0102THJ 2.72 3.22 8 1430 VIV0103THJ 3.03 3.78 11 9310 VIV0104THJ 6.86 8.07 8 8870 VIV0105THJ 13.80 16.24 7 4640 VIV0101THJ 44.32 57.65 6 2050 AN:024 vicorpower.com Applications Engineering: 800 927.9474 1.0 Page 10 For sake of clarity, only the steps that differ from the procedure already explained for the full-chip VTMs are reported. Step(s): A., B., C.: unchanged D.Calculate the total temperature coefficient of the power circuit at the estimated VTM® working temperature. The VTM ROUT resistance is temperature dependent, as shown in Figure 9. Figure 9 Half-chip VTM ROUT vs. module internal temperature ROUT ROUT_100 ROUT_25 25 TVTM [ºC] 100 In order for the model to match the system voltage drop better, the VTM operating temperature should be estimated. In cases where temperature is unknown, a conservative approach would be to assume the module will operate at half of its temperature range, for example 75ºC: ΔVF _ 75 = ΔVF _ 25 + Equation 14 ΔVF _ 100 − ΔVF _ 25 75 ⋅ 50 Linear interpolation used in [14] is acceptable in this case, as ROUT temperature dependency is linear. E. Calculate the maximum VC pin voltage for the given system. Equation 15 ⎛R ⎞ VC _ MAX = I AL ⋅ RVC + ( I F + I AL ) ⋅ ⎜ F + RS ⎟ = 2 ⎝ ⎠ = RS IF RCD _ MIN ⋅ RVC + ( I F + RS IF ⎛R ⎞ ) ⋅ ⎜ F + RS ⎟ RCD _ MIN ⎝ 2 ⎠ F., G.: unchanged AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 11 H. Calculate the RCD resistor that allows AL to compensate for the drops. First, substitute the VC line voltage at full IF current (ambient temperature): VC = Equation 16 ⎛R ⋅I ⎞ ⎛R RS ⋅ I F ⎞ ⋅ RVC + ⎜⎜ S F + I F ⎟⎟ ⋅ ⎜ F + RS ⎟ RCD ⎠ ⎝ RCD ⎠ ⎝ 2 into the expression for the related factorized bus increase: ΔVF _ 75 = G2 ⋅ VC = G2 ⋅ R16 + ROS = ROS ⎞ ⎛R ⎛ R ⋅I RS ⋅ I F ⎞ R + ROS ⋅ RVC + ⎜⎜ S F + I F ⎟⎟ ⋅ ⎜ F + RS ⎟ 16 RCD ⎠ ROS ⎠ ⎝ 2 ⎝ RCD Then solve for RCD: Equation 17 RCD AN:024 R16 + ROS R ⎞ ⎛ RS I F ⎜ RVC + F + RS ⎟ ROS 2 ⎠ ⎝ = R + ROS ⎛ RF ⎞ ΔVF _ 75 − G2 16 + RS ⎟ I F ⎜ ROS ⎝ 2 ⎠ G2 vicorpower.com Applications Engineering: 800 927.9474 Page 12 Design Example with VI Chip® Customer Boards System requirements: Input: 36-75 V Output: 5 V, 36 A, 180 W VI Chip selection: PRM®: P048F048T24AL (due to the wide range input voltage and the power level). VTM®: V048F060T040 (due to output voltage and current requirements). Corresponding customer boards are P048F048T24AL-CB and V048F060T040-CB respectively. They come with a connector which routes factorized bus and VC line, as explained in the User Guide UG:003. Figure 10 shows the two selected boards once connected. Figure 10 PRM and VTM customer boards First, collect the characteristics from the VTM’s data sheet and from Table 2: • • • • • • ROUT_25: 5.76 mΩ ROUT_100: 6.73 mΩ K: 1/8 RPTC_25: 1000 Ω RPTC_100: 1000·(1+0.0039·75) = 1293 Ω PNL: 2.7 W AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 13 Second, calculate or measure the power system characteristics: • VF_NOM: VOUT/K = 40 V • IOUT: 36 A • RF and RO: these values are strictly related to the board traces or cables used to route power. A convenient way to obtain these values is to identify the current paths of interest, as shown in Figure 11. Figure 11 Factorized bus current path (long-dash red) and output current path (short-dash blue) Then, a simple DC impedance measurement from terminal to terminal will provide RF and RO values. In this particular case: RF= 10 mΩ RO= 80 uΩ It is now possible to apply the proposed procedure. A.Calculate the maximum voltage drop (at 25ºC and 100ºC) due to VTM output resistance, ROUT. ΔVROUT _ 25 = ROUT _ 25 ⋅ I OUT = 0.00576 ⋅ 36 = 0.207 V ΔVROUT _ 100 = ROUT _ 100 ⋅ I OUT = 0.00673 ⋅ 36 = 0.242 V B. Calculate the maximum current flowing on the factorized bus. I F = K ⋅ I OUT + AN:024 PNL VF _ NOM vicorpower.com 1 2. 7 = ⋅ 36 + = 4.568 A 8 40 Applications Engineering: 800 927.9474 Page 14 C.Calculate the total PRM® output voltage increase that will compensate all the drops (factorized bus resistance, VTM® output resistance and output bus resistance). ΔVF _ 25 = ΔVF _ 100 = ΔVROUT _ 25 + RO I OUT K ΔVROUT _ 100 + RO I OUT K + ( RF + RS ) ⋅ I F = 0.207 + 80 μ ⋅ 36 + (10 m + 10 m) ⋅ 4.568 = 1.77 V 18 + ( RF + RS ) ⋅ I F = 0.242 + 80 μ ⋅ 36 + (10 m + 10 m) ⋅ 4.568 = 2.05 V 18 D.Calculate the total temperature coefficient of the power circuit and the RVC resistor needed to match it. ΔRTOT = RVC = (1 − ΔRTOT ) ΔVF _ 100 ΔVF _ 25 = 2.05 = 1.158 1.77 RPTC _ 25 ⋅ RPTC _ 100 ΔRTOT ⋅ RPTC _ 25 − RPTC _ 100 = (1 − 1.158) 1000 ⋅ 1293 = 1513 Ω 1.158 ⋅ 1000 − 1293 The RVC value is greater than 200 Ω, therefore valid. The nearest available 1% resistor value chosen for RVC is 1500 Ω. E. Calculate the maximum VC pin voltage for the given system at 25ºC. From the PRM-AL data sheet, RCD_MIN = 20 Ω: VC _ MAX _ 25 = RS IF ⋅ RPTC _ 25 ⋅ RVC RCD _ MIN RPTC _ 25 + RVC = 10 m + ( I F + RS IF ⎛R ⎞ ) ⋅ ⎜ F + RS ⎟ = RCD _ MIN ⎝ 2 ⎠ 4.568 1000 ⋅ 1500 4.568 ⎛ 10 m ⎞ ⋅ + (4.568 + 10 m + 10 m ⎟ = 1.44 V )⋅⎜ 20 1000 + 1500 20 ⎝ 2 ⎠ F. Calculate the needed (if any) VSC trim that allows enough AL dynamic range under the worst case: VC_MAX_25 and ΔVF_100. VSC ≤ G2 ⋅ VC _ MAX _ 25 0.0386 ⋅ 1.44 = = 1.12 V ΔVF _ 100 2.05 0.961 G1 40 VF _ NOM As VSC ≤ Vref = 1.24 V, RSC must be installed: RSC = R18 AN:024 VSC 1.12 = 10 k = 93.3 kΩ Vref − VSC 1.24 − 1.12 vicorpower.com Applications Engineering: 800 927.9474 Page 15 RSC is greater than 2550 Ω, therefore acceptable. The closest 1% tolerance value is chosen, RSC = 93.1 kΩ, which provides for an obtained VSC = 1.12 V G.Calculate the voltage feedback divider resistor needed to set the nominal output voltage. ROS = G1 ⋅ R16 VSC 1.12 = 0.961 ⋅ 93.1 k = 2574 Ω VF _ NOM − G1 ⋅ VSC 40 − 0.961 ⋅ 1.12 The closest standard value would be 2550 Ω, which is almost 1% off the target. In order to gain accuracy, the highest standard value is chosen, 2610 Ω, and a parallel resistor is used in order to closely match the required value: ROS1 = 2610 Ω and ROS2 = 187 kΩ H.Calculate RCD resistor that allows AL to compensate for the drops. G2 RCD = ⎛ RPTC _ 25 ⋅ RVC ⎞ R16 + ROS R RS I F ⎜ + F + RS ⎟ ⎜R ⎟ ROS 2 ⎝ PTC _ 25 + RVC ⎠ ΔVF _ 25 R + ROS ⎛ RF ⎞ − G2 16 + RS ⎟ I F ⎜ ROS ⎝ 2 ⎠ = 93.1 k + 2574 ⎞ ⎛ 1 k ⋅ 1.5 k 10 m 10 m ⋅ 4.568⎜ + + 10 m ⎟ 2574 2 ⎝ 1 k + 1. 5 k ⎠ = 23.5 Ω 93.1 k + 2574 ⎛ 10 m ⎞ 1.77 − 0.0386 + 10 m ⎟ ⋅ 4.568 ⎜ 2574 ⎝ 2 ⎠ 0.0386 = The nearest standard value is chosen, RCD = 23.7 Ω. The design is now complete, the calculated resistors: RSC = 93.1 kΩ, ROS1 = 2610 Ω, ROS2 = 187 kΩ, RVC = 1500 Ω and RCD = 23.7 Ω can be implemented in the two customer boards and regulation accuracy verified. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 16 Conclusion This procedure highlights the adaptive loop regulation concept and the design procedure to achieve good voltage regulation for a simple PRM®/VTM® combination. Monte Carlo analysis shows that 1% regulation accuracy over line, load and temperature can be statistically achieved 82% (or greater) of the time. Figure 12 shows accuracy distribution for the design example previously illustrated. 100% 80% 80% 60% 60% 40% 40% 20% 20% 0% -4% Cumulative distribution function 100% Probability distribution function Figure 12 Accuracy distribution over line, load and temperature for the design example 0% -3% -2% -1% 0% 1% 2% 3% 4% The same design concepts are directly applicable to arrays of V·I Chips if proper modeling applied. It is recommended to contact V·I Chip Application Engineering for any array involving 2 or more PRMs and 3 or more VTMs. The automated spreadsheet version of the procedure is available at http://cdn.vicorpower.com/documents/calculators/dcaldesign.xls. AN:024 vicorpower.com Applications Engineering: 800 927.9474 Page 17 Appendix A Changes applicable to MIL-COTS versions of VI Chips. MIL-COTS VTM®: parameters and modeling of MIL-COTS VTMs are identical to the commercial counterparts with the same K factor. The AL design procedure can be applied directly. MIL-COTS PRM®: parameters and modeling of MP028F036M12AL are identical to the commercial parts as with the only exception of R16 which changes to 69.8kΩ, as shown in the figure below. +OUT +IN 5 µF M1 D1 M2 M3 5 µF R16 69.8 kΩ OS G1=0.961 + PC Soft start and reference 10 kΩ R18 Enable Type 2 compensation VREF 1.24 V G2=0.0386 Modulator Error amplifier + IL PR 100 µA SC C18 0.22 µF 100 kΩ + 9 V, 5 mA max Inst. curr. protection Average current protection ∫ CD Q62 14 V 10 ms - IAL = V-OUT / RCD VH VC start pulse generator VC RS -IN SG 10 mΩ -OUT Adaptive loop The automated spreadsheet version of the procedure for MIL-COTS products is available at http://cdn.vicorpower.com/documents/calculators/mil_al_design_procedure.xls Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. 11/2013 vicorpower.com Applications Engineering: 800 927.9474 Rev 1.4 Page 18

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