PI2002
TM
Cool-ORing
Series
Active ORing Controller IC with Load Disconnect Feature
Description
Features
The PI2002 Cool-ORingTM solution is a high-speed
Active ORing controller IC with a load disconnect
feature designed for use with back-to-back Nchannel MOSFETs in redundant power system
architectures. The PI2002 Cool-ORing controller
enables an extremely low power loss solution with
fast dynamic response to fault conditions, critical for
high availability systems. The PI2002 controls backto-back MOSFETs providing true bi-directional
switch capabilities to protect against both power
source and load fault conditions.
•
•
The gate drive output turns the MOSFETs on in
normal steady state operation, while achieving highspeed turn-off during input power source fault
conditions, that cause reverse current flow, with
auto-reset once the fault clears. The PI2002 has the
added benefit of being able to protect against output
load fault conditions that may induce excessive
forward current and device over-temperature by
removing gate drive from the back-to-back
MOSFETs with an auto-retry programmable off-time.
The back-to-back MOSFETs drain-to-drain voltage is
monitored to detect normal forward, excessive
forward, light load and reverse current flow. The
PI2002 provides an active low fault flag output to the
system during fault condition.
A temperature
sensing function turns off the MOSFETs and
indicates a fault if the junction temperature exceeds
145°C.
•
•
•
•
•
•
•
Power Source & Load Fault Protection
Fast Dynamic Response, with 120ns reverse &
150ns forward over-current turn-off delay time
4A gate discharge current
Accurate back-to-back MOSFETs drain-to-drain
voltage sensing to indicate system level fault
conditions
Programmable under & over-voltage detection
Over temperature fault detection
Programmable over-current Gate off time
Programmable short circuit load detection
function
Active low fault flag output
Applications
•
•
•
•
•
N+1 Redundant Power Systems
Servers & High End Computing
Telecom Systems
Active ORing with Load Disconnect
High current Active ORing
Package Options
The PI2002 is offered in the following packages:
• 3mm x 3mm 10 Lead TDFN package
• 8 Lead SOIC
Typical Applications:
Figure 1b: PI2002 Low Side Disconnect Switch
Figure 1a: PI2002 High Side ORing with load disconnect
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PI2002
Rev1.1 Page 1 of 23
Pin Description
Pin
Name
Pin Number
10-Pin
DFN
SO-8
GND
1
1
GATE
2
2
VC
3
3
OCT
4
4
SCD
5
n/a
FT
6
5
SP
7
6
SN
8
7
UV
9
8
OV
10
n/a
Description
Ground: This pin is ground for the gate driver and control circuitry.
Gate Drive Output: This pin drives the gates of the external Back-to-Back Nchannel MOSFETs. Under normal operating conditions, the GATE pin pulls high to
10V (typ) with respect to the SN pin. The controller turns the gate off during all fault
conditions except the Low Forward Current condition.
Controller Input Supply: This pin is the supply pin for the control circuitry and gate
driver. Connect a 1μF capacitor between VC pin and the GND pin. Voltage on this
pin is limited to 15.5V by an internal shunt regulator. For high voltage auxiliary
supply applications connect a shunt resistor between VC and the auxiliary supply.
Over-Current Timer Input: Connecting a capacitor ( ≤ 20nF) sets the gate off time
once an over-current condition is detected. No capacitor on this pin will result in
minimum off time, 40µs. Pulling this input low will disable Gate drive.
Short Circuit Detect Input: This input pin is for setting the load voltage where a
short circuit level is defined and detected. To enable slow MOSFET turn-on mode,
connect SCD to VC. Connect to load point for minimum threshold (0.335V) or use
resistor divider to increase threshold. Grounding pin enables the fast MOSFET turn
on mode. This pin is not available in the SO-8 package and the controller is set for
low Gate source current, 300µA.
Fault State Output: This open collector output pulls low 40µs after a fault condition
occurs. Fault logic inputs are VC Under-Voltage, input Under-Voltage, input OverVoltage, Forward Over-Current, Reverse Current, Low Forward Current (or shorted
switches) and Over-Temperature. Leave this pin open if unused.
Positive Sense Input & Clamp: Connect SP pin to the input power source side of
the MOSFETs. The polarity and magnitude of the voltage difference between SP
and SN provides an indication of current flow through the MOSFETs.
Negative Sense Input & Clamp: Connect SN to the output load side of the
MOSFET. The polarity and magnitude of the voltage difference between SP and SN
provides an indication of current flow through the MOSFETs.
Input Under-Voltage Input: The UV pin is used detects when the input is less than
the Under-Voltage threshold resulting in a low Fault pin. The input voltage UV
threshold is programmable through an external resistor divider. During an UnderVoltage fault, the Gate is pulled low. Connect UV to VC to disable this function.
Input Over-Voltage Input: The OV pin detects when the input is greater than the
Over-Voltage threshold resulting in a low Fault pin. OV “AND” a Forward Current
condition turns the MOSFETs off. The input voltage OV threshold is programmable
through an external resistor divider. Connect OV to GND to disable this function.
This pin is not available in the SO-8 package and OV function is disabled.
Package Pin-Outs
10 Lead TDFN (3mm x 3mm)
Top view
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8 Lead SOIC (5mm x 6mm)
Top view
PI2002
Rev1.1 Page 2 of 23
Absolute Maximum Ratings
VC
-0.3V to 17.3V / 40mA
SP, SN, OV, OCT
-0.3V to 8.0V / 10mA
-0.3V to 17.3V / 10mA
UV, SCD, FT
GATE
-0.3V to 17.3V / 5A
GND
-0.3V / 5A peak
Storage Temperature
-65oC to 150oC
-40oC to Thermal shutdown
Operating Junction Temperature
250oC
Lead Temperature (Soldering, 20 sec)
ESD Rating
2kV HBM
Electrical Specifications
Unless otherwise specified: -40°C < TJ < 125°C, VC =12V, CVc = 1uF, COCT = 2nF, CGATE = 4nF
Parameter
Symbol
Min
VVC-GND
4.5
Typ
Max
Units
Conditions
13.2
V
3.7
4.2
mA
15.5
16
V
No VC Limiting Resistors
Normal Operating Conditions
No Faults
IVC=10mA
7.5
Ω
Delta IVC=10mA
4.5
V
VC Supply
Operating Supply Range(3)
Quiescent Current
IVC
Clamp Voltage
VVC-CLM
VC Clamp Shunt Resistance
15
RVC
VC Under-Voltage Rising Threshold
VVCUVR
VC Under-Voltage Falling Threshold
VVCUVF
VC Under-Voltage Hysteresis
4.3
4.0
4.15
V
VVCUVHS
150
mV
Under-Voltage Rising Threshold
VUVR
500
Under-Voltage Falling Threshold
VUVF
Under-Voltage Threshold Hysteresis
VUVHS
FAULT
Under-Voltage Bias Current
IUV
Over-Voltage Rising Threshold
VOVR
Over-Voltage Falling Threshold
VOVF
Over-Voltage Threshold Hysteresis
IOV
Fault Output Low Voltage
VFTL
Fault Output High Leakage Current
I FT-LC
Fault Delay Time
tFT-DEL
Over Temperature Fault (1)
Picor Corporation • picorpower.com
(1)
mV
25
mV
500
440
1
μA
540
mV
475
mV
25
mV
-1
200
20
mV
475
-1
VOV-HS
Over-Voltage Bias Current
Over Temperature Fault Hysteresis
440
540
40
1
μA
500
mV
IFT=2mA, VC>4.5V
10
μA
VFT=14V
60
μs
Includes output glitch filter
TFT
145
°C
TFT-HS
-10
°C
PI2002
Rev1.1 Page 3 of 23
Electrical Specifications
Unless otherwise specified: -40°C < TJ < 125°C, VC =12V, CVc = 1uF, COCT = 2nF, CGATE = 4nF
Parameter
Symbol
Min
Typ
Max
Units
Conditions
GATE DRIVER
VG = 1V, Normal Operating
Conditions, No Faults VSCD=0V
VG = 1V, Normal Operating
Conditions, No Faults VSCD=Vc
Gate Source Current
IG-SC
-1.5
mA
Gate Source Current
IG-SC
-0.30
mA
4.0
A
0.3
Ω
VG = 1.5V @ 25°C
0.2
V
TRVS-DLY + 50nsec
Pull Down Peak Current(1)
IG-PD
Gate Pull-down Resistance
(1)
RG-PD
AC Gate Pull-down Voltage
(1)
VG-PD
DC Gate Pull-down Voltage to GND
Gate Voltage @ VC UVLO
Gate Fault Condition Clear
(1)
Gate to SN Clamp Voltage
1.5
VG-PD
0.8
1.2
V
IG=100mA, in reverse fault
VG-UVLO
0.7
1
V
IG =10μA, 1.5<VC< VVCUVLO
VG-CL
45
VG-SN
9
10
Gate Voltage High
VG
VC0.5V
Gate Fall Time
tG-F
VC0.25V
10
%
11
V
IG = 100μA
V
VC- VSN < VG-CLMP
15
ns
90% to 10% of VG max.
5.5
V
VCM =SP & SN w/respect to GND
DIFFERENTIAL AMPLIFIER AND COMPARATORS
Common Mode Input Voltage
VCM
-0.1
VC to SN differential(1)
VVC-SP
3.5
Differential Operating Input Voltage
VSP-SN
-50
V
125
mV
SP-SN
SP Input Bias Current
ISP
3.5
μA
VCM =1.25V
SN Input Bias Current
ISN
-37
μA
VCM =1.25V
5.5
V
SP=0V (SN=0V)
SN (SP) Voltage
VSN(SP)
Reverse Comparator Off Threshold
VRVS-TH
-10
-6
-2
mV
VCM =3.3V
Reverse Comparator Hysteresis
VRVS-HS
2
3
5
mV
VCM =3.3V
120
150
ns
Reverse Fault to Gate Turn-off
Delay Time
Forward Comparator On Threshold
Forward Comparator Hysteresis
Forward Over-Current Comparator
Threshold
Forward Over-Current Comparator
Hysteresis
Forward Over-Current to Gate Turnoff Delay
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TRVS-DLY
VFWD-TH
2
5
9
mV
VCM =3.3V
VFWD-HS
-5
-3
-2
mV
VCM =3.3V
VFOC-TH
104
112
120
mV
VCM =3.3V
VFOC-HS
-8
-6
-4
mV
VCM =3.3V
150
180
ns
tFOC-DLY
PI2002
Rev1.1 Page 4 of 23
Electrical Specifications
Unless otherwise specified: -40°C < TJ < 125°C, VC =12V, CVc = 1uF, COCT = 2nF, CGATE = 4nF
OCT
OCT Source Current
IOCTSC
OCT Clamp Voltage
VOCT-CL
OCT Threshold Voltage High
VOCT-Hi
OCT Threshold Voltage Low
OCT OFF
-10
μA
VOCT = 1.25V
V
No Fault
1.75
V
SP=3.3V, SN=0V
VOCT-Lo
0.875
V
SP=3.3V, SN=0V
TOCT-OFF
350
µs
FOC fault condition
mV
IOCT = -100uA
mA
VOCT =2.25V SP-SN=125mV
1
μA
VSCD=0V
380
mV
VSP-SN=20mV, VG=1V
2.2
OCT Gate Drive Disable
VOCT-Lo
OCT Sink Current
IOCTSK
5
Iscd
-1
SCD Threshold Voltage High
VThSCDR
300
;SCD Threshold Voltage Low
VThSCDF
SCD Hysteresis
VThSCDR VThSCDF
3.2
4.2
500
10
SCD
SCD Bias Current
340
310
25
50
mV
75
mV
VSP-SN=20mV, VG=1V
Note 1: These parameters are not production tested but are guaranteed by design, characterization and
correlation with statistical process control.
Note 2: Current sourced by a pin is reported with a negative sign.
Note 3: Refer to the Auxiliary Power Supply section in the Application Information section for details on the VC
requirement to meet the MOSFET Vgs requirement.
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PI2002
Rev1.1 Page 5 of 23
Functional Description:
The PI2002 controller IC product is designed to drive
back-to-back N-channel MOSFETs in Active ORing
applications that also require a load disconnect
feature. The PI2002 used with external back-toback MOSFETs can function as an ideal ORing
diode in the high-side of a redundant power system
coupled with a load disconnect switch, significantly
reducing power dissipation and eliminating the need
for heatsinking.
The PI2002 provides the ability to block current in
both directions by driving two MOSFETs in a backto-back configuration as shown in Figure 1a. This
configuration offers the ability to protect the load and
the MOSFET, by pulling the gate low, during
Reverse Current, Forward Over-Current, UnderVoltage, Over-Voltage and Over-Temperature faults.
The fault flag is also issued during these fault
conditions.
Differential Amplifier:
The PI2002 integrates a high-speed low offset
voltage differential amplifier to sense the difference
between the Sense Positive (SP) pin voltage and
Sense Negative (SN) pin voltage with high accuracy.
The amplifier output is connected to three
comparators:
Reverse
comparator,
Forward
comparator, and Forward over-current comparator.
retry after a controlled off-time determined by the
capacitor value on the OCT input pins.
Over-Current Timer: OCT
OCT off-time is set by the OCT a capacitor as shown
in Figure 3.
The OCT block will control the off-time of the
MOSFETs after a FOC fault condition has occurred.
The equivalent block diagram is shown in Figure 2.
As the Set input at the OCT timer goes high, Out
will go low, pulling the GATE pin low. At the same
time a one shot of 40µs discharges the OCT
capacitor, then releases it charging the capacitor
again. Out and GATE pins stay low until the OCT
pin reaches the OCT high threshold (VOCT-Hi), then
Out goes high and the GATE pin sources current to
charge the MOSFET gates. As soon as the GATE
voltage reaches 45% of the GATE to SN clamp
voltage, or 45% of {VC-V(SN) -0.25V}, the Clamp
Detector asserts a low signal again at the NOR gate.
If FOC is still low then the GATE pin will be pulled
low and will start a new off-time cycle of the OverCurrent timer.
Reverse Current Comparator: RVS
The reverse current comparator provides the most
critical function in the controller, detecting negative
voltage caused by reverse current. When the SN
pin is 6mV higher than the SP pin, the reverse
comparator will enable the gate discharge circuit and
turn off the MOSFETs in typically 120ns.
The reverse comparator has typically 3mV of
hysteresis referenced to SP-SN.
Forward Current Comparator: FWD
The FWD comparator detects when a forward
current condition exists and SP is 5mV (typical)
positive with respect to SN. When SP-SN is less
than 5mV it will indicate a fault condition on the
FT pin during a light load while maintaining gate
drive to the MOSFETs. The PI2002 will initiate a
gate shutdown if the Forward “AND” the over-voltage
(OV) condition are true.
Forward Over-Current Comparator: FOC
The FOC comparator indicates an excessive forward
current condition when SP is 112mV higher than SN.
The PI2002 controller will initiate a fault condition
when the GATE output voltage is more than 45% of
the regulated gate to SN voltage and SP-SN is
higher than 112mV, the MOSFETs will turn off then
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Figure 2: OCT block and timing diagram
PI2002
Rev1.1 Page 6 of 23
when VC is lower than the VC Under-Voltage
Threshold.
UV:
The Under-Voltage (UV) input trip point can be
programmed through an external resistive divider to
monitor the input voltage. The UV comparator
initiates a gate low condition turning the MOSFETs
off and initiates a fault condition pulling the FT pin
low, when UV falls below the Under-Voltage Falling
Threshold.
Figure 3: OCT Off time vs. OCT capacitor value
Short Circuit Detect: SCD
This comparator block input (for 10L-TDFN package
only) can be connected to the load directly or
programmed to a higher voltage with a resistor
divider. The SCD function allows the user to define
the (Hard Short) voltage level expected if a non-ideal
short circuit occurs at the load. To prevent damage
of the MOSFETs under this condition (VSCD<335mV)
the gate charge current (IG-SC) is increased by a
factor of approximately 5 times resulting in fast
charging of the MOSFET gates.
This feature
enables the capability to distinguish between a
faulted load versus powering capacitive and low
resistive loads without entering the OCT mode. This
pin can be grounded to provide a fast gate charging
or pulled to VC for lower gate current to drive highly
capacitive loads with resulting slow gate charge
under the fault condition. If the resulting temperature
rise of the MOSFETs is thermally coupled to the
controller, invoking a thermal shutdown, the thermal
time constant of the system will determine the
average duty cycle further protecting the MOSFETs.
The SCD pin is not available in the SO-8 package
version and is internally preset for slow gate charge,
where the Gate source current is 300µA.
VC and Internal Voltage Regulator:
The PI2002 has a separate input (VC) that provides
power to the control circuitry and the gate driver. An
internal regulator clamps the VC voltage to 15.5V.
For high side applications, the VC input should be
high enough above the bus voltage to properly
enhance the external N-channel MOSFETs.
The internal regulator circuit has a comparator to
monitor VC voltage and initiates a FAULT condition
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OV:
The Overvoltage (OV) input trip point (for 10L-TDFN
package only) can be programmed through an
external resistive divider to monitor the input voltage.
The OV comparator initiates a fault condition and
pulls the FT pin low when OV rises above the
Overvoltage Rising Threshold. The PI2002 will turn
the Gate output off if the OV and the Forward
Current conditions are both true. The low resistance
redundant paths of an Active ORing system tend to
force all the input sources to the same voltage
making it difficult to identify the noncompliant
source. By ANDing OV with the Forward Current
Threshold the noncompliant source is identified and
disconnected from the system.
The OV pin is not available in the SO-8 package
version and is disabled.
Over-Temperature Detection:
The internal Over-Temperature block monitors the
junction temperature of the controller. The OverTemperature threshold is set to 145°C with -10°C of
hysteresis.
When the controller temperature
exceeds this threshold, the Over-Temperature circuit
pulls GATE pin low and initiates a fault condition and
pulls the FT pin low. By maintaining proper thermal
matching between the controller and the power
MOSFETs, this function can be used to protect the
MOSFETs from thermal runaway conditions.
Gate Driver:
The gate driver (GATE) output is configured to drive
external N-channel MOSFETs. In the high state, the
gate driver applies a current source that is
dependent on the SCD pin voltage. The controller
regulates the gate voltage to 10V above the SN pin
when the VC voltage is 10.5V higher than the SN
pin. Otherwise the gate voltage (VG) to VSN will be
{VG-SN = VC - VSN – 0.5V}. Note that VC is the
controller internal regulated voltage.
When a reverse current fault is initiated, the gate
driver pulls the GATE pin low and discharges the
FET gate with 4A peak capability.
PI2002
Rev1.1 Page 7 of 23
When the input source voltage is applied and before
the MOSFET is fully enhanced, a voltage greater
than the Forward Over-Current (FOC) Threshold
may be present across the MOSFET. To avoid an
erroneous FOC detection, a VGS detector blanks
the FOC and FWD comparators from initiating a
fault, until the GATE pin reaches 45% of VG-CLMP. If
VC is too low to establish the Gate Clamp condition
the reference for detection is 45% of {VC-V(SN) 0.25V}.
The GATE pin pulls low under the following fault
conditions:
•
•
•
•
•
•
Reverse Current
Forward Over-Current “AND” clamp detector is
cleared
Over Temperature
Input Under-Voltage
Input Over-Voltage “AND” nominal Forward
Current
VC pin Under-Voltage
Fault:
The fault circuit output is an open collector with 40μs
delay to prevent any false triggering. The FT pin
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will be pulled low when any of the following faults
occurs:
• Reverse Current
• Forward Over-Current “AND” clamp detector is
cleared
• Forward Low Current “AND” clamp detector is
cleared
• Over Temperature
• Input Under-Voltage
• Input Over-Voltage “AND” nominal Forward
Current
• VC pin Under-Voltage
The Forward Current fault condition occurs when the
MOSFETs gates are high but are not conducting a
significant level of forward current or may indicate
the MOSFETs are shorted either internally or
externally (VD1-D2 < 6mV).
The VGS detector prevents FOC or FWD from
initiating a fault when the MOSFET gate is low. The
gate to SN voltage has to reach sufficient voltage to
establish the Rds(on) condition before these faults
are detected.
PI2002
Rev1.1 Page 8 of 23
Figure 4: PI2002 Controller Internal Block Diagram (10 Lead TDFN package pin out shown)
Figure 5: Comparator hysteresis, values are for reference only, please refer to the electrical specifications
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PI2002
Rev1.1 Page 9 of 23
Figure 6: PI2002 State Diagram
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PI2002
Rev1.1 Page 10 of 23
Figure 7: Timing diagram for two PI2002 controllers in an Active ORing and Load Disconnect application
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PI2002
Rev1.1 Page 11 of 23
Typical Characteristics:
Figure 8: Controller bias current vs. temperature
Figure 10: Reverse condition gate turn-off delay time
vs. temperature.
Figure 12: Reverse comparator threshold vs.
temperature. VCM: Common Mode Voltage.
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Figure 9: VC UVLO threshold vs. temperature
Figure 11: Forward Over-Current condition gate turn-off
delay time vs. temperature.
Figure 13: FOC comparator threshold vs. temperature.
VCM: Common Mode Voltage.
PI2002
Rev1.1 Page 12 of 23
Typical Characteristics: Continued
Figure 14: Gate to SP clamp voltage vs. temperature.
Figure 15: Gate output source current vs. temperature
Figure 16: Gate output source current vs. temperature
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PI2002
Rev1.1 Page 13 of 23
Application Information:
The PI2002 is designed to replace ORing diodes and
load disconnect switches in high current redundant
power architectures. Replacing a traditional diode
with a PI2002 controller IC and two low on-state
resistance back-to-back N-channel MOSFETs will
result in significant power dissipation reduction as well
as board space reduction, efficiency improvement,
input power source and output load protection and
additional protection features. This section describes
in detail the procedure to follow when designing with
the PI2002 Active ORing controller and two back-toback N-Channel MOSFETs. Two design examples
are presented, one Active ORing with load disconnect
design example and one low side disconnect switch
example.
Fault Indication:
FT output pin is an open collector and should be
pulled up to the logic voltage or to the controller VC
via a resistor (10KΩ)
Over-Current Timer: OCT
Connect a capacitor, equal or less than 20nF, to set
off time after over-current shutdown (see Figure 3).
Short Circuit Detect: SCD
Connect SCD pin to VC to avoid inrush current into a
high capacitive load, or connect SCD to GND pin for
fast MOSFET turn on.
Note: The SCD pin is not available in the SO-8
package and the controller is set for low Gate
source current, 300µA.
Auxiliary Power Supply (Vaux):
Vaux is an independent power source required to
supply power to the PI2002 VC input. The Vaux
voltage should be higher than Vin (redundant power
source output voltage) by the required gate-to-source
voltage (Vgs) to fully enhance the MOSFET, plus 0.5V
maximum gate to VC headroom (VHDVC-G)
Vaux = Vin + Vgs + VHDVC-G
Where, VHDVC-G is defined as the 0.5V maximum drop
from VC in the Gate Voltage High (VG) specification in
the Gate Driver section of the Electrical Specification.
For example, if the bus voltage is 3.3V and the
MOSFET requires 4.5V of Vgs to fully enhance the
MOSFET, then Vaux should be at least 3.3V + 4.5V +
0.5V = 8.3V.
If Vaux is higher than 15V then a bias resistor (Rbias)
is required, and should be connected between the
PI2002 VC pin and Vaux. The resistor is selected
based on the input voltage range.
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Minimize the resistor value for low Vaux voltage levels
to avoid a voltage drop that may reduce the VC
voltage lower than required to drive the gate of the
MOSFET. Select the value of Rbias using the
following equations:
Rbias =
Vaux min − VC clamp
IC max
Rbias maximum power dissipation:
Pd Rbias =
(Vaux max − VC clamp ) 2
Rbias
Rbias maximum power dissipation is at maximum
input voltage and minimum clamp voltage (15V).
Where:
Vauxmin : Vaux minimum voltage
Vauxmax : Vaux maximum voltage
VC Clamp : Controller clamp voltage, 15.5V
IC max
: Controller maximum bias current (4.2mA)
N-Channel MOSFET Selection:
There are several factors that affect the MOSFET
selection including cost, on-state resistance (Rds(on)),
current rating, power dissipation, thermal conductivity,
drain-to-source breakdown voltage (BVdss), gate-tosource voltage rating (Vgs), and gate threshold
voltage (Vgs(TH)).
The first step is to select suitable MOSFETs based on
the BVdss requirement for the application. The BVdss
voltage rating should be higher than the applied Vin
voltage plus expected transient voltages.
Stray
parasitic inductance in the circuit can also contribute
to significant transient voltage conditions, particularly
during MOSFET turn-off after a reverse current fault
has been detected. In Active ORing applications when
one of the input power sources is shorted, a large
reverse current is sourced from the circuit output
through the MOSFET. Depending on the output
impedance of the system, the reverse current may
reach over 60A in some conditions before the
MOSFET is turned off. Such high current conditions
will store energy even in a small parasitic element.
For example, a 1nH parasitic inductance with 60A
reverse current will store 1.8µJ (½Li2). When the
MOSFET is turned off, the stored energy will be
released and will produce high negative voltage
ringing at the MOSFETs input. This event will create a
high voltage difference across the MOSFETs.
Note:
Since the two MOSFETs are connected in to back-toback configuration, the maximum breaking voltage is
BVdss of one MOSFET plus one diode forward
voltage.
PI2002
Rev1.1 Page 14 of 23
The MOSFET current rating and maximum power
dissipation are closely related. Generally the lower the
MOSFET Rds(on), the higher the current capability
and the lower the resultant power dissipation. This
leads to reduced thermal management overhead, but
will ultimately be higher cost compared to higher
Rds(on) parts. It is important to understand the
primary design goal objectives for the application in
order to effectively trade off the performance of one
MOSFET versus another.
Power dissipation in active ORing circuits is derived
from the total source current and the on-state
resistance of the selected MOSFET.
MOSFET power dissipation:
Pd MOSFET = Is 2 ∗ Rds(on)
Where :
Is
: Source Current
Rds(on) : MOSFET on-state resistance
Note:
In the calculation use Rds(on) at maximum MOSFET
temperature because Rds(on)
is temperature
dependent. Refer to the normalized Rds(on) curves in
the MOSFET manufacturers datasheet. Some
MOSFET Rds(on) values may increase by 50% at
125°C compared to values at 25°C.
should be adequate for protecting MOSFETs with
maximum Vgs ratings of ±12V or greater.
OV/UV resistor selection:
The UV and OV comparator inputs are used to
monitor the input voltage and will indicate a fault
condition when this voltage is out of range. The UV
and OV pins can be configured in two different ways,
either with a divider on each pin, or with a threeresistor divider to the same node, enabling the
elimination of one resistor. Under-Voltage is
monitored by the UV pin input and Over-Voltage is
monitored with the OV pin input.
Note: The OV pin is not available in the SO-8 package
and OV function is disabled.
The Fault pin ( FT ) will indicate a fault (active low)
when the UV pin is below the threshold or when the
OV pin is above the threshold. The UV and OV
thresholds are 0.50V typical with 25mV hysteresis and
their input current is less than ±1µA. It is important to
consider the maximum current that will flow in the
resistor divider and maximum error due to UV and OV
input current. Set the resistor current to 100µA or
higher to maintain 1% accuracy for UV and OV due to
the bias current.
The three-resistor voltage divider configuration for
both UV and OV to monitor the same voltage node is
shown in Figure 17:
Ra =
The Junction Temperature rise is a function of power
dissipation and thermal resistance.
V (OVTH )
I Ra
TriseMOSFET = RthJA ∗ PdMOSFET = RthJA ∗ Is 2 ∗ Rds(on) ,
Where:
RthJA : Junction-to-Ambient thermal resistance
Rds(on) and PI2002 sensing:
The PI2002 senses voltage across the ORing
MOSFETs via the SP and SN pins to determine the
status of the current through the MOSFETs. Refer
Figure 1a. When the MOSFETs are fully enhanced,
the total drop across the back to back MOSFETs (and
between SP and SN) is; VSD=Rds(on)*Is * 2.
The reverse current threshold is set for -6mV and
when the differential voltage between the SP & SN
pins is more negative than -6mV, i.e. SP-SN≤-6mV,
the PI2002 detects a reverse current fault condition
and pulls the MOSFET gate pin low to turn off the
MOSFET and prevent further reverse current. The
reverse current fault protection disconnects the power
source fault condition from the redundant bus and
allows the system to keep running.
The GATE pin output voltage is clamped to 11V
maximum with respect to the SN pin. The 11V clamp
Picor Corporation • picorpower.com
Figure 17: UV & OV three-resistor divider
configuration.
Ra =
V (OVTH )
I Ra
Set Ra value based on system allowable current
I Ra Ra =
V (OVTH )
I Ra
⎛ V (OV ) ⎞
Rb = Ra • ⎜⎜
− 1⎟⎟
⎝ V (UV )
⎠
⎛ V (UV ) ⎞
Rc = (Ra + Rb ) • ⎜⎜
− 1⎟⎟
⎝ VTH
⎠
Where:
V (UVTH ) : UV threshold voltage
V (OVTH ) : OV threshold voltage
V(UV)
PI2002
: UV voltage
Rev1.1 Page 15 of 23
I Ra
: Ra current.
Alternatively,
a
two-resistor
voltage
divider
configuration can be used and is shown in (Figure 18).
Figure 18: Two-resistor divider configuration
The UV resistor voltage divider can be obtained from
the following equations:
R1UV =
V (UVTH )
I RUV
Set R1UV value based on system allowable current
I RUV ≥ 100 μA
⎛ V (UV )
⎞
− 1⎟⎟
R 2UV = R1UV ⎜⎜
⎝ V (UVTH ) ⎠
Where:
Typical application Example 1:
High Side Active ORing:
Requirement:
Redundant Bus Voltage = 3.3V
Load Current = 15A (assume through each redundant
path)
Maximum Ambient Temperature = 75°C
Auxiliary Voltage = 12V (11V to 13V)
Solution:
1. A single PI2002 with two suitable external
MOSFETs for each redundant 3.3V power source
should be used, configured as shown in the circuit
schematic in Figure 19
2. Select a suitable N-Channel MOSFET: Most
industry standard MOSFETs have a Vgs rating of
+/-12V or higher. Select an N-Channel MOSFET
with a low Rds(on) which is capable of supporting
the full load current with some margin, so a
MOSFET capable of at least 18A in steady state
is reasonable. An exemplary MOSFET having
these characteristic is FDS6162N7 from Fairchild.
Set R1OV value based on system allowable current
From FDS6162N7 datasheet:
• N-Channel MOSFET
• VDS= 20V
• ID = 23A continuous drain current
• VGS(MAX)= ± 12V
• RθJA= 40°C/W
• RDS(on)=2.9mΩ typical at ID=23A, VGS≥4.5V,
TJ=25°C
I RUV ≥ 100 μA
Reverse current threshold is:
V (UVTH ) : UV threshold voltage
: R1UV current
I RUV
R1UV =
V (UVTH )
I RUV
⎛ V (OV )
⎞
− 1⎟⎟
R 2 OV = R1OV ⎜⎜
⎝ V (OVTH ) ⎠
Where:
I RVS =
Forward over-current threshold is:
V (OVTH ) : OV threshold voltage
I ROV
: R1OV current
V RVS −TH
− 6mV
= −1.03 A
=
2 * Rds(on) 2 * 2.9mΩ
I FOC =
V FOC −TH
114mV
=
= 19.66 A
2 * Rds(on) 2 * 2.9mΩ
Power dissipation final junction temperature for
each MOSFET:
Rds(on) is 3.5mΩ maximum at 25°C & 4.5Vgs and will
increase as the temperature increases. Add 25°C to
maximum ambient temperature to compensate for the
temperature rise due to power dissipation. At 100°C
(75°C + 25°C) Rds(on) will increase by 28%.
Rds(on) = 3.5mΩ ∗1.28 = 4.48mΩ maximum at 100°C
Trise= RthJA ∗ Is2 ∗ Rds(on)
Maximum Junction temperature
TJ max = TA + Trise
⎛ 40°C
⎞
TJ max = 75°C + ⎜
∗ (15A)2 ∗ 4.48mΩ⎟ = 115°C
⎝ W
⎠
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 16 of 23
Recalculate based on calculated Junction
temperature, 115°C.
⎛ V (OV ) ⎞
⎛ 3.6V
⎞
− 1⎟ = 498Ω
Rb = Ra⎜⎜
− 1⎟⎟ = 2.49kΩ⎜
⎝ 3.0V
⎠
⎝ V (UV )
⎠
At 115°C Rds(on) will increase by 32%.
Rds(on) = 3.5mΩ ∗1.32 = 4.62mΩ
or 499Ω 1%
⎞
⎛ V (UV )
Rc = (Ra + Rb )⎜⎜
− 1⎟⎟
⎝ V (UVTH ) ⎠
⎛ 3.0V
⎞
= (2.49kΩ + 499Ω )⎜
− 1⎟ = 14.95kΩ
⎝ 500mV
⎠
⎛ 40°C
⎞
TJ max = 75°C + ⎜
∗ (15A)2 ∗ 4.62mΩ⎟ = 116.5°C
⎝ W
⎠
3. Vaux: Make sure Vaux voltage is higher than Vin
(power source output) by the voltage required to
fully enhance the MOSFET. Minimum required
Vaux = Vin + Vgs + 0.5V = 3.3V + 4.5V + 0.5V =
8.3V. Since 8.3V is less than the 11V minimum
Aux supply voltage, there is sufficient voltage
available to drive the gate of the MOSFET.
or 15kΩ 1%
4. SP and SN pins: Connect the SP pin to the
MOSFET drain pin at the input and the SN pin to
the MOSFET drain pin at the load side.
5. OCT pin: Connect 18nF capacitor between OCT
pin and the GND pin to achieve the maximum off
time after forward over-current condition occurs.
6. SCD pin: Connect the SCD pin to the GND pin
for fast MOSFET enhancement.
7.
FT pin: Connect to the logic input and to the
logic power supply via a 10KΩ resistor.
8. Program UV and OV to monitor input voltage:
Program UV at 3.0V and OV at 3.6V
Use the three-resistor divider configuration:
I Ra = 200μA
Ra =
V (UVTH ) 500mV
=
= 2.5kΩ or 2.49kΩ 1%
I Ra
200μA
Figure 19: High side Active ORing function.
Figure 20: PI2002 performance in example 1, applied short at Vin1.
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 17 of 23
Typical application Example 2:
Low side disconnect switch
Requirement:
Bus Voltage = -48V (-36V to -60V, 100V for 100ms
transient)
Maximum operating load current = 5A
Load current shutdown set at = 6A
Maximum Ambient Temperature = 60°C
Solution:
1. A PI2002 with a suitable MOSFET for -48V
power source should be used and configured as
shown in Figure 22. The VC is biased from the
return line through a bias resistor.
2. Select a suitable N-Channel MOSFET: Select
the N-Channel MOSFET with voltage rating
higher than the input voltage, Vin, plus any
expected transient voltages, with a low Rds(on)
that is capable of supporting the full load current
with margin. For instance, a 100V rated
MOSFET with 10A current capability is suitable.
An
exemplary
MOSFET
having
these
characteristic is Si4486EY from Vishay Siliconix.
From Si4486EY datasheet:
•
N-Channel MOSFET
•
VDS= 100V
•
ID = 23A continuous drain current at 125°C
•
VGS(MAX) = ± 20V
•
RθJA= 50°C/W
•
RDS(on)=20mΩ typical at VGS=10V, TJ=25°C
At 111°C Rds(on) will increase by 71%.
Rds(on) = 25mΩ ∗1.71 = 4.75mΩ maximum at 111°C
⎛ 50°C
⎞
∗ (5.0 A)2 ∗ 42.75mΩ⎟ = 113°C
TJ max = 60°C + ⎜
W
⎝
⎠
Vaux: Connect each controller to the return path
with a separate bias resistor, Rbias.
To reduce Rbias power dissipation, VC clamp is
selected at 13V which is less than the actual PI2002
clamp voltage (15V typical). 13V is higher than
PI2002 maximum gate clamp voltage (11V).
Rbias =
IC max
Pd Rbias =
(Vaux max − VC clampMIN ) 2
Rbias
=
(60V − 15V ) 2
= 369mW
5.49 KΩ
3. Select sense resistor: Sense resistor is
selected based on load current shutdown.
Where
V FOC −TH 114mV
=
= 19mΩ
I Shutdown
6A
Select 20mΩ resistor
20mΩ Sense Resistor power dissipation at
maximum operating current
2
Pd RSense = I max * R Sense = (5 A) 2 20mΩ = 0.5W
As an exemplary selected 1206 20mΩ/1W/1%
sense resistor from Vishay-Dale:
Vth.reverse − 6mV
=
= −300mA
Rds(on)
20mΩ
Part Number: WSL1206R0200FEK
Power dissipation:
Maximum current turn off:
Rds(on) is 25mΩ maximum at 25°C & 10Vgs and
will increase as the temperature increases. Add
40°C to maximum ambient temperature to
compensate for the temperature rise due to power
dissipation. At 100°C (60°C + 40°C) Rds(on) will
increase by 63%.
Isd MAX =
V FOC −TH − MAX 121mV
=
= 6.05 A
R Sense
20mΩ
Minimum current turn off:
Isd MIN =
Rds(on) = 25mΩ ∗1.63 = 41mΩ maximum at 100°C
⎛ 50°C
⎞
∗ (5.0 A)2 ∗ 41mΩ⎟ = 111°C
TJ max = 60°C + ⎜
W
⎝
⎠
36V − 13V
= 5.48KΩ
4.2mA
Rbias maximum power dissipation is at maximum
input voltage and minimum clamp voltage
R Sense =
Maximum Junction temperature
=
or 5.49KΩ
Reverse current threshold is:
Is.reverse =
Vaux min − VC clamp
V FOC −TH − MIN 107mV
=
= 5.35 A
R Sense
20mΩ
4. SP and SN pins: Connect the SP pin to the
MOSFET source and controller GND pin, and
connect the SN pin to Vin- and the drain of the
MOSFET.
Recalculate based on calculated Junction
temperature, 111°C.
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 18 of 23
5. OCT pin: Connect 18nF capacitor between OCT
pin and the GND pin to achieve the maximum off
time after forward over-current condition occurs.
6. SCD pin: Connect the SCD pin to the VC pin
for slow MOSFET turn on to avoid over-current
shutdown due to inrush current.
7.
FT pin: Connect the FT pin to logic input and
to the logic power supply or to the VC pin via a
resistor.
UV and OV inputs: UV and OV are not used in this
example. Connect UV pin to VC pin and OV pin to
GND pin do not leave them unconnected.
Figure 22: PI2002 (10L-TDFN package) in low side
disconnect switch application
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 19 of 23
be very close from each other and their pins
should be connected with a short trace.
Layout Recommendation:
Use the following general guidelines when designing
printed circuit boards. An example of the typical
land pattern for a TDFN PI2002 and SO-8/PowerPak
MOSFET is shown in Figure 23:
•
It is best to connect the gate of the MOSFETs to
the GATE pin of the controller with a short and
wide trace.
•
The GND pin of the controller carries high peak
current and it should be returned to the ground
plane through a low impedance path.
•
Connections from the SP and SN pins to Vin
and Vout respectively very close to the
MOSFETs, SP to Q1 drain pin and SN to Q2
drain pin.
•
The VC bypass capacitor should be located as
close as possible to the VC and GND pins.
Place the PI2002 and VC bypass capacitor on
the same layer of the board. The VC pin and
CVC PCB trace should not contain any vias.
•
Connect all MOSFET Q1 Drain pins together
with a wide trace to reduce trace parasitics and
to accommodate the high current input.
Similarly, connect all MOSFET Q2 Drain pins
together with a wide trace to accommodate the
high current output. Q1 and Q2 Sources should
•
Connect the power source very close to the Q1
drain connection to reduce the effects of stray
parasitics. If a short trace is not possible,
connect C3 (typically 1µF) as shown in Figure
23.
Figure 23: PI2002 and MOSFET layout
recommendation
Figure 24: PI2002 Mounted on PI2002-EVAL1
Please visit www.picorpower.com for information on PI2002-EVAL1
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 20 of 23
Package Drawings: 8 Lead SOIC
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 21 of 23
Package Drawings: 10 Lead TDFN
Ordering Information
Part Number
PI2002-00-QEIG
PI2002-00-SOIG
Package
Transport Media
3mm x 3mm 10L TDFN
8L SOIC
Tape &Reel
Tape &Reel
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 22 of 23
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when
in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is
extended to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR
LIMITED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
within the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to
improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any
product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general
policy does not recommend the use of its components in life support applications wherein a failure or malfunction
may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life
support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC
modules and accessory components, fully configurable AC-DC and DC-DC power
supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor
for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a
failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale,
which are available upon request.
Specifications are subject to change without notice.
Vicor Corporation
25 Frontage Road
Andover, MA 01810
USA
Picor Corporation
51 Industrial Drive
North Smithfield, RI 02896
USA
Customer Service: [email protected]
Technical Support: [email protected]
Tel: 800-735-6200
Fax: 978-475-6715
Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 23 of 23