TECHNICAL NOTE High-performance Regulator IC Series for PCs FET Integrated Switching Regulators for DDR-SDRAM Cores BD95513MUV ●Description BD95513MUV is a switching regulator capable of supplying high current output (up to 3A) at low output voltages (0.7V~5.0V) over a broad range of input voltages (4.5V~28V). The regulator features an internal N-MOSFET power transistor for high 3 TM efficiency and low space consumption, while incorporating ROHM’s proprietary H Reg control mode technology, yielding the industry’s fastest transient response time against load changes. SLLM (Simple Light Load Mode) technology is also integrated to improve efficiency when powering lighter loads, as well as soft start, variable frequency, short-circuit protection with timer latch, over-voltage protection, and REF functions. This regulator is suited for PC applications. ●Features 1) Internal low ON-resistance power N-MOSFET 2) Internal 5V linear voltage regulator 3 TM 3) Integrated H Reg DC/DC converter controller 4) Selectable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and forced continuous mode 5) Built-in thermal shutdown, low input, current overload, output over- and under-voltage protection circuitry 6) Soft start function to minimize rush current during startup 7) Adjustable switching frequency (f = 200 kHz ~ 1000 kHz) 8) Built-in output discharge function 9) VQFN032-V5050 package size 10) Tracking function 11) Internal bootstrap diode ●Applications Mobile PCs, desktop PCs, LCD-TV, digital household electronics Sep. 2008 ●Absolute Maximum Ratings (Ta = 25 °C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 External VCC Voltage BOOT Voltage BOOT-SW Voltage Output Feedback Voltage SS/FS/MODE Voltage VREG Voltage EN/CTL Input Voltage PGOOD Voltage Output Current (Average) Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Junction Temperature Symbol VCC VDD VIN EXTVCC BOOT BOOT-SW FB SS/FS/MODE VREG EN/CTL PGOOD ISW Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax Value 7 *1 7 *1 30 *1 7 *1 35 7 *1 VCC VCC VCC 7 *1 7 *1 3 *1 0.38 *2 0.88 *3 *6 2.06 *4 *6 4.56 *5 *6 -10 ~ +100 -55 ~ +150 +150 Unit V V V V V V V V V V V A W W W W °C °C °C *1 Do not exceed Pd. *2 Ta ≧ 25 °C (IC only), power dissipated at 3.0 mW / °C. *3 Ta ≧ 25 °C (single-layer board, 20.2 mm2 copper heat dissipation pad), power dissipated at 7.0 mW / °C. *4 Ta ≧ 25 °C (4-layer board, 10.29 mm2 copper heat dissipation pad on top layer, 5505 mm2 pad on 2nd and 3rd layer), power dissipated at 16.5 mW / °C. *5 Ta ≧ 25 °C (4-layer board, all layers with 5505 mm2 copper heat dissipation pads), power dissipated at 36.5 mW / °C. *6 Values observed with chip backside soldered. When unsoldered, power dissipation is lower. ●Operating Conditions (Ta = 25 °C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 External VCC Voltage BOOT Voltage SW Voltage BOOT-SW Voltage MODE Input Voltage EN/CTL Input Voltage PGOOD Voltage Minimum On Time Symbol VCC VDD VIN EXTVCC BOOT SW BOOT-SW MODE EN/CTL PGOOD tonmin ★This product is not designed for use in a radioactive environment. 2/15 Min 4.5 4.5 4.5 4.5 4.5 -0.7 4.5 0 0 0 - Max 5.5 5.5 28 5.5 33 28 5.5 5.5 5.5 5.5 100 Unit V V V V V V V V V V ns ●Electrical Characteristics (Unless otherwise noted, Ta =25°C, AVIN =12V, VCC =VDD =VREG, EN/CTL=5V, MODE=0V, RFS =180kΩ) Min. Limit Typ. Max. IIN1 IIN2 IINstb ENlow ENhigh IEN CTLlow CTLhigh ICTL GND 2.3 GND 2.3 - 1200 150 0 12 1 1800 250 10 0.8 5.5 20 0.8 5.5 6 μA μA μA V V μA V V μA VREG Input Voltage VREG 4.90 5.00 5.10 V Maximum Current [5V Switch] IREG 100 - - mA 4.2 - 4.4 1.0 4.6 2.0 V Ω EXTVCC:Sweep up 4.1 100 4.1 100 4.3 160 4.3 160 4.5 220 4.5 220 V mV V mV VCC:Sweep up VCC:Sweep down VREG:Sweep up VREG:Sweep down 400 10.0 - 500 22.0 450 600 40.0 550 nsec μsec nsec - 120 120 200 200 mΩ mΩ 0.420 - 0.490 1 0.560 - V ms 0.812 0.840 0.868 V 1.4 - 2.2 - 3.0 100 μA mV 3 - - A 0.693 0.700 0.707 V Parameter [Whole Device] AVIN Bias Current 1 AVIN Bias Current 2 AVIN Standby Current EN Low Voltage EN High Voltage EN Bias Voltage CTL Low Voltage CTL High Voltage CTL Bias Current [5V Regulator] Symbol EVCC_UVLO Switch Resistance REVCC [Under-Voltage Lockout Protection] AVIN Threshold Voltage AVIN _ UVLO AVIN Hysteresis Voltage dAVIN _ UVLO VREG Threshold Voltage VREG_ UVLO VREG Hysteresis Voltage dVREG_ UVLO [H3REGTM Control Block] ON Time ton MAX ON Time tonmax MIN OFF Time toffmin [FET Block] High-side ON Resistance Ron_high Low-side ON Resistance Ron_low [SCP Block] SCP Startup Voltage VSCP Delay tSCP [Over-Voltage Protection Block] OVP Detect Voltage VOVP [Soft Start Block] Charge Current Iss Standby Voltage Vss_stb [Current Regulation Block] Maximum Output Current IOCP [Voltage Detection Block] Feedback Terminal Voltage 1 VFB1 EXTVCC Input Threshold Voltage Unit Condition EXTVCC=5V CTL=EN=0V VIN=6.0 to 25V IREG=0 to 100mA When VFB: 30% down When VFB: 20% up Ta =-10°C to 100°C Iout = 0A to 3A Feedback Terminal Voltage 2 VFB2 0.690 0.700 0.710 V Feedback Terminal Bias Current IFB -100 0 100 nA SLLM Condition VthSLLM VCC-0.5 - VCC V Forced Continuous Mode [Power Good Block] VFB Power Good Low Voltage VFB Power Good High Voltage VthCONT GND - 0.5 V SLLM Longest low-gate off time: ∞ Continuous mode VFB PL VFB PH 0.605 0.745 0.63 0.77 0.655 0.795 V V When VFB: 10% down When VFB: 10% up [MODE Block] 3/15 ●Reference Data 100 100 SLLM SLLM 40 60 Continuous Mode QLLM 0.1 Io [A] 1 10 0 0.01 2μsec/div SW (10V/div) 20 0 0.1 Io [A] 1 10 2μsec/div VOUT (50mV/div) SW (10V/div) IOUT (2A/div) 0.01 Fig.3 Io-Efficiency (VIN=19V,VOUT=2.5V) VOUT (50mV/div) Fig.6 Transient Response (VIN=19V, VOUT=2.5V) Fig.5 Transient Response (VIN=12V, VOUT=2.5V) 2μsec/div 2μsec/div 2μsec/div VOUT (50mV/div) VOUT (50mV/div) SW (10V/div) SW (10V/div) SW (10V/div) IOUT (2A/div) IOUT (2A/div) Fig.8 Transient Response (VIN=12V, VOUT=2.5V) Fig.7 Transient Response (VIN=7V, VOUT=2.5V) 2μsec/div IL HG LG Fig.10 SLLM Mode (IOUT=0A) Fig.9 Transient Response (VIN=19V, VOUT=2.5V) 2μsec/div 2μsec/div VOUT VOUT VOUT 2μsec/div IOUT (2A/div) VOUT (50mV/div) IOUT (2A/div) 1 SW (10V/div) IOUT (2A/div) Fig.4 Transient Response (VIN=7V, VOUT=2.5V) 0.1 Io [A] Fig.2 Io-Efficiency (VIN=12V,VOUT=2.5V) Fig.1 Io-Efficiency (VIN=7V,VOUT=2.5V) QLLM 40 20 0 Continuous Mode η [%] QLLM 20 VOUT (50mV/div) 80 60 Continuous Mode η [%] η [%] 60 0.01 SLLM 80 80 40 100 IL IL HG LG HG LG Fig.11 SLLM Mode (IOUT=0.4A) 4/15 Fig.12 1 SLLM Mode (IOUT=1A) 10 ●Reference Data 10μsec/div 10μsec/div VOUT 200μsec/div EN VOUT 2[V/div] SW PGOOD Fig.13 QLLM Mode (IOUT=0A) 2msec/div EN Fig.14 QLLM Mode (IOUT=1A) Fig.15 PGOOD Rising Waveform 200μsec/div VOUT 2[V/div] VIN HG/LG VOUT 2[V/div] SW IL 5[A/div] PGOOD VOUT Fig.17 SCP Timer Latch Waveform Fig.16 PGOOD Falling Waveform 400μsec/div VIN EN VREG 2[V/div] HG/LG VOUT 2[V/div] VOUT SW Fig.19 VIN change (19→5V) Fig.20 EN wake up 5/15 Fig.18 VIN change (5→19V) ●Block Diagram VREG VIN VCC 13 7 AVIN SS 16 VDD EN 10 VREG AVIN Reference Block 8 UVLO Soft Start SS VIN 1 VIN(4.5～28V) 2 3 CTL VREF×0.85 VSS×0.85 VOUT REF(0.7V) VREG BOOT 5 Delay 26 H3Reg Controller Block MODE EN Power Good PGOOD R SW MODE S FB 18 AVIN MODE Q 28 Driver Circuit 30 31 21 REF×1.2 UVLO ILIM SCP TSD VOUT 29 SS EXTVCC 14 OCP 27 17 6 ILIM SCP 4 FB 22 OVP 23 VREG VDD PGND 24 25 32 EN/UVLO MODE 15 11 VREG 9 FS MODE ●Pin Configuration 23 12 GND ●Pin Function Table PGND PGND PGND 24 20 N.C. 19 VOUT Thermal TSD Protection 5V Reg 22 VDD 21 N.C. VOUT 20 19 FB REF 18 17 16 SS PGND 25 SW 26 15 VREG SW 27 14 EXTVcc SW 28 13 VCC SW 29 12 GND SW 30 11 FS SW 31 10 EN PGND 32 9 MODE 1 2 3 4 VIN VIN VIN VIN 5 6 7 8 BOOT PGOOD AVIN CTL *Connect the underside (FIN) to the ground terminal PIN No. PIN Name 1-4 5 VIN BOOT 6 PGOOD 7 AVIN 8 CTL 9 MODE 10 EN 11 FS 12 13 14 15 16 17 18 19 20 21 22-25 26-31 32 GND VCC EXTVCC VREG SS REF FB VOUT N.C. VDD PGND SW PGND FIN Underside 6/15 PIN Function Battery voltage input (4.5 ~ 28 V) HG driver power supply Power good output (high when output ±10% of regulation) Battery voltage sense Linear regulator on/off (high = 5.0V, low = off) Control mode selection GND : Continuous Mode 3.0V : QLLM VCC : SLLM Enable output (high when VOUT ON) Switching frequency adjustment (RFS = 30 k ~ 100 kΩ) Sense ground Power supply input External power supply input IC reference voltage (5.0V / 200mA) Soft start condenser input Output reference voltage (0.7 V) Feedback input (0.7 V) Voltage discharge output Power supply input (5 V) Power ground Output to inductor Power ground Substrate connection ●Pin Descriptions ・VCC This pin supplies power to the IC’s internal circuitry, excluding the FET driver. The input supply voltage range is 4.5 to 5.5 V, with a maximum current draw of 900 µA. This pin should be bypassed with a capacitance of approximately 0.1 µF. ・EN Enables or disables the switching regulator. When the voltage on this pin reaches 2.3 V or higher, the internal switching regulator is turned on. At voltages less than 0.8 V, the regulator is turned off. ・VDD This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak current when switching on or off, this pin should be bypassed with a capacitance of approximately 1 µF. ・VREG Output pin from the 5 V linear regulator. This pin also supplies power to the internal driver and control circuitry. VREG standby function is controlled by the CTL pin. The output supplies 5V at 100 mA and should be bypassed to ground using a 10 µF capacitor with a rating of X5R or X7R. ・EXTVCC External power supply input for the linear regulator. When the voltage on the EXTVCC pin exceeds 4.4 V, the regulator uses it in conjunction with other power sources to supply VREG. Leave the EXTVCC pin floating when not in use. ・REF Reference voltage output pin. The reference voltage is set internally by the IC to 0.7 V, and the IC works to keep VREF approximately equal to VFB. Variations in voltage levels on this pin affect the output voltage, so the pin should be bypassed with a 100 pF ~ 0.1 µF ceramic capacitor. ・SS Soft start/stop pin. When EN is set high, the capacitor between the internal current source and SS-GND controls the startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7 V), the output voltage is held at the same voltage as the SS pin. ・AVIN The BD95513MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this line should be bypassed with either a power capacitor or RC filter. ・FS Frequency-adjusting resistance input pin. Attaching a resistance of 30 k ~ 100 kΩ adjusts the switching frequency from 200 kHz ~ 1 MHz. ・BOOT This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC. The maximum voltage on this pin should not exceed +30 V vs. GND or +7 V vs. SW. When operating the switching regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (VIN + VDD) ~ VDD. ・PGOOD Power good indicator. This open-drain output should be connected via a 100 kΩ pull-up resistor. ・MODE Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode; when high, SLLM mode. ・CTL Linear regulator control pin. When voltage is 2.3 V or higher, a logic HIGH is recognized and the internal regulator (VREG = 5 V) is switched on. At voltages of 0.8 V or lower, a logic LOW is recognized and the regulator is switched off. However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW. ・FB Output voltage feedback input. VFB is held at 0.7 V by the IC. ・SW Output from the switching regulator to the inductor. This output swings from VIN ~ GND. The trace from the output to the inductor should be as short and wide as possible. ・VOUT Voltage output discharge pin. When EN is off, this output is pulled low. ・VIN Power supply input. The IC can accept any input from 4.5 V to 28 V. This pin should be bypassed directly to ground by a power capacitor. ・PGND Power ground terminal. 7/15 ●Operation 3 The BD95513MUV is a switching regulator incorporating ROHM’s proprietary H Reg CONTROLLA control system. When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time interval. This improves the regulator’s transient response. When light-load mode is activated, the IC employs the Simple Light Load Mode (SLLM) controller, further improving system efficiency. 3 TM H Reg Control (Normal Operation) VFB When VFB falls below the reference voltage (0.7 V), the H3Reg CONTROLLA is activated; VREF tON HG VREF VIN × 1 [sec]・・・(1) f High gate output is determined by the above formula. LG (Rapid Changes in Load) VFB When VOUT drops due to a sudden change in load and the voltage remains below VREF after the preprogrammed tON time interval has elapsed, the system quickly restores VOUT by extending the tON time, thereby improving transient response. VREF Io tON+α HG LG Light Load Control (SLLM Mode) VFB SLLM mode is enabled by setting the MODE pin to logic high. When the low gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), the SLLM function is activated, disabling high gate output. If VFB falls below VREF again, the high gate is switched back on, lowering the switching frequency of the regulator and yielding higher efficiency when powering light loads. VREF HG LG 0A (QLLM Mode) QLLM mode is enabled by setting the MODE pin to HiZ or middle voltage. When the lower gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), QLLM mode is activated, disabling high gate output. If VFB falls below VREF within a programmed time interval (typ. 40 µs), the high gate is switched on, but if VFB does not fall below VREF, the lower gate is forced on, dropping VFB and switching the high gate back on. The minimum switching frequency is set to 25 kHz (T = 40 µS), which keeps the regulator’s frequency from entering the audible spectrum but yields less efficient results than SLLM mode. VFB VREF HG LG 0A 8/15 ●Timing Chart ・Soft Start Function The soft start function is enabled when the EN pin is set high. Current control circuitry takes effect at startup, yielding a EN moderate “ramping start” in output voltage. tSS Soft start timing and incoming current are given by equation (2) and (3) below: Soft start period: SS tSS = VREF×Css 2μA(typ) [sec] ・・・(2) VOUT Rush current: IIN(ON)= IIN Co×VOUT tss [A] ・・・(3) (Css: soft start capacitor; Co: output capacitor) ・Timer Latch-type Short Circuit Protection VREF×0.70 When output voltage falls to VREF x 0.70 or less, the output short circuit protection engages, turning the IC off after a set period of time to prevent internal damage. When EN is switched back on or when UVLO is cleared, output continues. The time period before shutting off is set internally at 1 ms. VOUT 1ms SCP EN/UVLO ・Output Over-Voltage Protection VOUT VREF×1.2 When output reaches or exceeds VREF x 1.2, the output over-voltage protection is engaged, turning the low-side FET completely on to reduce the output (low gate on, high gate off). When the output falls, it returns to standard mode. HG LG Switching 9/15 ●External Component Selection 1. Inductor (L) Selection The inductor’s value directly influences the output ripple current. As formula (4) indicates below, the greater the inductance or switching frequency, the lower the ripple current: (VIN-VOUT)×VOUT ΔIL= [A]・・・(4) L×VIN×f ΔIL VIN The proper output ripple current setting is about 30% of maximum output current. IL ΔIL=0.3×IOUTmax. [A]・・・(5) VOUT L L= Co (VIN-VOUT)×VOUT ΔIL×VIN×f [H]・・・(6) (ΔIL: output ripple current, f: switching frequency) Output ripple current ※ Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor’s rated current value. ※ To minimize possible inductor damage and maximize efficiency, choose an inductor with a low DCR and ACR resistance. 2. Output Capacitor Selection (CO) VIN When determining the proper output capacitor, be sure to factor in the equivalent series resistance (ESR) and equivalent series inductance (ESL) required to set the output ripple voltage at 20 mV or more. VOUT L ESR When selecting the limit of the inductor, be sure to allow enough margin for the output voltage. Output ripple voltage is determined by formula (7) below: ESL Co ΔVOUT=ΔIL×ESR+ESL×ΔIL / TON・・・(7) Output Capacitor (ΔIL: Ouput ripple current, ESR: equivalent series resistance, ESL: equivalent series inductance) Give special consideration to the conditions of formula (7) for output capacitance. must be established within the soft start timeframe. Co≦ tss×(Ilimit-IOUT) VOUT ・・・(8) Also, keep in mind that the output rise time tss: Soft start timeframe (see p. 10, equation (2)) Ilimit: Maximum output current Choosing a capacitance that is too large can cause startup malfunctions, or in some cases, may engage the short circuit protection. 3. Input Capacitor Selection (CIN) In order to prevent extreme over-current conditions, the input capacitor must have a low enough ESR to fully support a large ripple in the output. The formula for RMS ripple current (IRMS) is given by equation (9) below: VIN CIN VOUT L IRMS=IOUT× √VIN(VIN-VOUT) [A]・・・(9) VIN Co When VIN=2×VOUT, IRMS= IOUT 2 Input Capacitor A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency. 10/15 4. Frequency Adjustment The resistance connected to the FS terminal adjusts the on-time (tON) during normal operation as illustrated to the left. When tON, input voltage and VREF voltage are known, the switching frequency can be determined by the following formula: 600 From top: 500 VIN= 5V 7V 12V 19V Frequency [kHz] 400 VREF F= ・・・(10) VIN×tON 300 However, real-life considerations (such as external MOSFET gate capacitance and switching time) must be factored in as they affect the overall switching rise and fall time. This leads to an increase in tON, lowering the total frequency slightly. 200 100 0 0 50 100 150 200 250 Additionally, when output current lingers around 0A in continuous mode, this “dead time” also has an effect upon tON, further lowering the switching frequency. Confirm the switching frequency by measuring the current through the coil (at the point where current does not flow backwards) during normal operation. RFS[kΩ] The BD95513MUV operates by feeding the output voltage back through a resistive voltage divider. The output voltage is set by the following equation (see schematic below): Output Voltage = R1+R2 R2 × VREF (0.7V) + 1 2 ×ΔIL×ESR・・・(11) The switching frequency is also amplified by the same resistive voltage divider network: fsw = R1+R2 ×(frequency set by RFS) [Hz]・・・(12) R2 VIN REF(0.7V) H3RegTM CONTROLLA VIN R Q SLLM TM Output Voltage Driver S SLLM FB ESR Circuit R1 R2 11/15 ●Evaluation Board Circuit (Frequency=300kHz Continuous Mode/QLLM/SLLM Example Circuit) VIN 12V BD95513MUV 7 AVIN 13 VCC 10 EN EN VDD 21 8 CTL VIN 14 15 VDD REF C11 PGND PGND 1~4 VOUT L1 EXTVCC SW 1.8V/3A 26~31 VREG D1 VREG(5V) 5 R9 6 PGND C14 CTL 5V BOOT MODE C12 9 C10 C3 MODE 22~25,32 PGOOD 16 R6 SS/ TRACK PGND VOUT 12 GND PGND 19 FS C1 C5 C7 C6 11 REF(0.7V) FB 18 CE 20 R8 C4 17 C13 3V R7 VREG R1 R4 VREG GND ●Evaluation Board Parts List Part No U1 D1 C1 C3 C4 C5 C6 C7 C11 C12 C13 Value Company 1uF 1uF 10uF 1000pF 0.1uF 1uF 10uF 0.1uF 220pF ROHM ROHM KYOCERA KYOCERA KYOCERA MURATA KYOCERA KYOCERA KYOCERA KYOCERA MURATA Part name BD95513MUV RB051L-40 CM105B105K06A CM105B105K16A CM316B106K06A GRM39X7R102K50 CM105B104K06A CM105B105K16A CM316B106M16A CM05B104K25A GRM39C0G221J50 Part No R1 R4 R6 R7 R8 R9 L1 C14 C15 C16 12/15 Value Company Part name 10Ω 10Ω 68KΩ 31kΩ 20kΩ 100kΩ 1.8uH 470uF 1uF 1uF ROHM ROHM ROHM ROHM ROHM ROHM SUMIDA SANYO KYOCERA KYOCERA MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 CDEP104-1R8ML 2R5TPE470ML CM105B105K06A CM105B105K06A ●Operation Notes (1) Absolute maximum ratings Exceeding the absolute maximum ratings (such as supply voltage, temperature range, etc.) may result in damage to the device. In such cases, it may be impossible to identify problems such as open circuits or short circuits. If any operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power supply polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power supply lines The PCB layout pattern should be designed to provide the IC with low-impedance GND and supply lines. To minimize noise on the supply and GND lines, ground and power supply lines of analog and digital blocks should be separated. For all power lines supplying ICs, connect a bypass capacitor between the power supply and the GND terminal. If using electrolytic capacitors, keep in mind that their capacitance is reduced at lower temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use thermal design techniques that allow for a sufficient margin for power dissipation in actual operating conditions. (6) Inter-pin shorts and mounting errors Use caution when positioning he IC for mounting on PCBs. The IC may be damaged if there are any connection errors or if pins are shorted together. (7) Operation in strong electromagnetic fields Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to malfunction. (8) ASO When using the IC, set the output transistor so that it does not exceed either absolute maximum ratings or ASO. (9) Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit), which is designed to shut down the IC only to prevent thermal overloading. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC if this circuit is activated, or in environments in which activation of this circuitry can be assumed. BD95513MUV TSD ON Temp. [°C] (typ.) 175 Hysteresis Temp. [°C] (typ.) 15 (10) Testing on application boards When testing the IC with application boards, connecting capacitors directly to low-impedance terminals can subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should be turned off completely before connecting it to or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 13/15 (11) Regarding IC input pins This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistance Transistor (NPN) Pin A Pin B C B 端子 B E Pin A N P+ N P P+ N P+ B B N P N P Substrate Parasitic Element P+ N C E P Sub Parasitic Element GND Parasitic Elements GND GND Parasitic Elements GND Other Adjacent Elements Example of IC Structure (12) Ground wiring traces When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. ●Power Dissipation 5.5 ① Θj-a = 328.9 °C/W 5.0 ④4.56W ② Power Dissipation Pd [W] 4.5 2 IC mounted on 1-layer board (with 20.2 mm copper thermal pad) Θj-a = 142.0 °C/W 4.0 ③ 3.5 2 IC mounted on 4-layer board (with 20.2 mm pad on top layer, 2 5502 mm pad on layers 2,3) Θj-a = 60.7 °C/W 3.0 ④ 2.5 2.0 1.5 1.0 ②0.88W ①0.38W 0 20 2 IC mounted on 4-layer board (with 5505mm pad on all layers) Θj-a = 27.4 °C/W ③2.06W 0.5 0 IC Only 40 60 80 100 120 140 Ambient Temperature Ta [°C] VQFN032-V5050 14/15 ●Ordering Instructions B D Product name ・BD955X 9 5 5 3 1 M U Package Type ・MUV : VQFN032-V5050 V ― E 2 Taping type name E2= Embossed carrier tape VQFN032-V5050 <Packing Specifications> <Dimensions> Tape Embossed carrier tape (with dry-pack) Quantity 2500 pcs Feed Direction E2 Pin 1 is located on the upper-left corner when the reel is held on the left and fed out to the right 1234 1234 Pin 1 1234 Reel 1234 1234 1234 (Unit:mm) Feed direction ※ Please place orders in quantities of full reels. 15/15 Catalog No.08T449A '08.9 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev3.0