AN360 C R YS TA L S ELECTION G UIDE FOR Si533 X A N D Si5355/56 D EVICES 1. Introduction This application note provides general guidelines for the selection and use of crystals with the Si533x and Si5355/56 family of any-frequency, any-output clock generators and zero-delay buffers. Many of these devices can use a local crystal to create the input reference frequency for the device. Covered topics are crystal selection, frequency accuracy, and frequency optimization. The equivalent circuit of a crystal and its connection to the Si533x/55/56 device is shown in Figure 1. IN1/XA Si533x/55/56 Lm z C0 Rm COSC = 18 pF CPAR OSC + AGC C1 Rm ESR CPAR = Trace Capacitance IN2/XB Figure 1. Equivalent Crystal Circuit The Si533x/5x devices support a crystal connected between pins Pin IN1/XA and Pin IN2/XB. In Revision 0.3 of this application note, we recommended a crystal with a nominal load capacitance specification of 12 pF. Recent testing has shown that an 18 pF crystal is the better choice to produce the most accurate oscillation frequency. The data sheets for the Si533x/55/56 also specify 12 pF and will be updated to agree with this revision of this application note. Hence, in this revision, Tables 1–4 have been revised to specify crystals with 18 pF load capacitance. The maximum crystal ESR and C0 values are defined to guarantee oscillation and short startup times. Rev. 0.5 3/12 Copyright © 2012 by Silicon Laboratories AN360 AN360 Table 1. Crystal Specifications for IN1 and IN2 pins [XO_RATE Reg 28[1:0] = 0] Parameter Symbol Min Typ Max Unit fXTAL 8 — 11 MHz Load Capacitance (on-chip differential) CL 17 18 19 pF Crystal Output Capacitance cO — — 6 pF Equivalent Series Resistance rESR — — 300 Crystal Max Drive Level Spec dL — — 100 µW Crystal Frequency Table 2. Crystal Specifications for IN1 and IN2 pins [XO_RATE Reg 28[1:0] = 1] Parameter Symbol Min Typ Max Unit fXTAL 11 — 19 MHz Load Capacitance (on-chip differential) CL 17 18 19 pF Crystal Output Capacitance cO — — 5 pF Equivalent Series Resistance rESR — — 200 W Crystal Max Drive Level Spec dL — — 100 µW Crystal Frequency Table 3. Crystal Specifications for IN1/XA and IN2/XB pins [XO_RATE Reg 28[1:0] = 2] Parameter Symbol Min Typ Max Unit fXTAL 19 — 26 MHz Load Capacitance (on-chip differential) CL 17 18 19 pF Crystal Output Capacitance CO — — 4 pF Equivalent Series Resistance rESR — — 100 W Crystal Max Drive Level Spec dL — — 100 µW Crystal Frequency Table 4. Crystal Specifications for IN1/XA and IN2/XB pins [XO_RATE Reg 28[1:0] = 3] Parameter Symbol Min Typ Max Unit fXTAL 26 — 30 MHz Load Capacitance (on-chip differential) CL 17 18 19 pF Crystal Output Capacitance cO — — 4 pF Equivalent Series Resistance rESR — — 75 W Crystal Max Drive Level Spec dL — — 100 µW Crystal Frequency The X_RATE register must be set as indicated in each of the above tables. In addition, set Register 28[4] = 1 and register 28[2] = 1 to enable and select the oscillation circuit. When the ClockBuilder Desktop software is used, it will automatically take care of these register writes. 2 Rev. 0.5 AN360 2. Frequency Accuracy The frequency accuracy of the crystal oscillator primarily depends on the crystal, parameters, and temperature. The crystal has frequency parameters of: Initial accuracy, typically ±20, ±50, or ±100 ppm. Variation with temperature. The crystal data sheet should specify the ppm/°C variation. Variation with time (aging). A secondary effect upon the crystal frequency of oscillation is caused by the total load capacitance (CTL) being different from the required load capacitance (CL) of the crystal. The total load capacitance is the sum of the PCB layout capacitance and the capacitance between pins IN1/XA and IN2/XB of the Si533x/55/56 (COSC), which is nominally 18 pF. If the traces between the crystal and the Si533x/55/56 are less than .15", it is reasonable to ignore the trace effects. The actual oscillation frequency due to the load capacitance mismatch can be calculated as: FACT = FXTAL x (1–(C1 x (1/(C0+CL) – 1/(C0+CTL))/2)) where: FXTAL = Rated Frequency of the Crystal CL = Rated capacitance load for the Crystal COSC = Capacitance of Si533x/55/56 between pins IN1/XA and IN2/XB CPAR = Capacitance of traces between crystal and Si533x/55/56. Ignore if traces are < .15" each. CTL = Total load seen by the Crystal = COSC + CPAR C0 = Crystal shunt capacitance C1 = Crystal motional capacitance Because the nominal C1 and C0 are never specified in a crystal data sheet, they must be measured. A network analyzer and several crystal PCB layouts are needed to perform the measurement. From measurements, we have found that C0/260 ~=C1. Hence we can give a good estimate of the frequency error from the following equation: FACT = FXTAL x (1 – (C0/520) x (1/(C0+CL) – (1/(C0+CTL)))) Using the above equation with CTL = 18 pF (Si533x/55/56 oscillator capacitance) and for crystals with CL from 12 to 18 pF, the ppm vs. C0 is plotted in Figure 2. Figure 2. Crystal Oscillation Error Rev. 0.5 3 AN360 When the CL capacitance required by the crystal is different than the 18 pF load presented by the Si533x/55/56, the ClockBuilder Desktop software can adjust the Si533x/55/56 output frequencies to compensate for the error in the crystal oscillation frequency. Please download the latest ClockBuilder Desktop software from www.silabs.com/ClockBuilder. Another option is to use the programming equations in the “Si5338 Reference Manual: Configuring the Si5338 without ClockBuilder Desktop" (formerly AN411) to compensate for the expected change in the crystal oscillation frequency. Whether using ClockBuilder Desktop or the Si5338 Reference Manual, the process of compensating for a non-18 pF crystal CL is the same. Simply use the FACT frequency rather than the FXTAL frequency for the crystal oscillation frequency. Using FACT instead of FXTAL may cause the feedback MultiSynth divider value to be a fraction rather than an integer, which may cause the output jitter to increase slightly. If the feedback MultiSynth value is fractional with FXTAL, then it will most likely be fractional when using FACT, and the jitter will likely not change. Because of the difficulty in knowing nominal C1 and C0, it makes the most sense to use crystals with 18 pf CL. This ensures that the oscillation frequency will be as specified by the crystal spec. The latest revision of the Si5338 EVB uses Epson FA-238 crystals with 18 pF CL, and we have found them to be readily available. 2.1. Optimum Crystal Frequency The output phase noise is generally best when the output frequency is an integer ratio of the crystal frequency. In addition, the output phase noise improves as the crystal frequency is made higher. Hence one should try to use a crystal that produces an output/input frequency ratio that is an integer and that keeps the crystal frequency between 20 and 30 MHz. All of the output jitter measurements in the data sheets are based upon a 25 MHz crystal. 4 Rev. 0.5 AN360 3. Selection of Compatible Crystals The crystals shown in Table 5 have been tested for compatibility with the Si533x and Si5355/56 family of devices. This is only a subset of compatible crystals. Any crystal meeting the specifications highlighted in Tables 1–4 will function with these devices. Note that many of the crystals tested do not have a load capacitance of 18 pF. If using these crystals, the crystal oscillation frequency will be in error as previously described in this application note. Table 5. Selection of Compatible Crystals Vendor Device Load Cap (pF) C0 (pF) C1 (fF) Lm (mH) Rm () FA-238 25.0000MB 12 0.81 3.2 13 28 FA-238 25.0000MB 18 0.88 3.1 13 20.6 TSX-3225 10 1.2 3.9 10 20 CTS 405C35B25M00000 13 2.1 8.8 4.6 4.5 ECS ECS-250-8-36CKM 8 0.67 2.6 16 32 NDK NX5032GA-25MHZ 8 1.5 6.3 6.5 11 Abracon AB10-25MHZ-E20-T 10 0.67 2.3 18 43.5 Epson Rev. 0.5 5 AN360 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Added "3. Selection of Compatible Crystals" on page 5. Revision 0.3 to Revision 0.4 Changed the recommended crystal CL from 12 pF to 18 pF. Adjusted crystal parameter names for clarity. Added crystal oscillation equation that does not have C1. Added Figure 2, “Crystal Oscillation Error,” on page 3. Revision 0.4 to Revision 0.5 6 Replaced all references to AN411 to the Si5338 Reference Manual, which replaces AN411. Rev. 0.5 AN360 NOTES: Rev. 0.5 7 AN360 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. 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