SL28SRC01 PCI Express Gen 2 & Gen 3 Clock Generator Features • Low power PCI Express Gen 2 & Gen 3clock generator • SSON input for enabling spread spectrum clock • One100-MHz differential SRC clocks • Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Low power push-pull output buffers (no 50ohm to ground needed) • Input frequency of 14.318MHz • Integrated 33ohm series termination resistors • Low jitter (<50pS) • Industrial Temperature -40oC to 85oC • 3.3V power supply • 16-pin TSSOP package Pin Configuration Block Diagram DOC#: SP-AP-0015 (Rev. 0.2) 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 11 www.silabs.com SL28SRC01 Pin Definitions Pin No. 1 XIN Name Type I 14.318 MHz Crystal input. 2 VDD PWR 3.3V power supply 3 VDD PWR 3.3V power supply 4 VSS GND Ground 5 VDD PWR 3.3V power supply 6 VSS GND Ground 7 SRC1 O, DIF 100 MHz Differential serial reference clocks. 8 SRC1# O, DIF 100 MHz Differential serial reference clocks. 9 VSS GND Description Ground 10 VDD PWR 3.3V power supply 11 VDD PWR 3.3V power supply 12 VSS GND Ground 13 VDD PWR 3.3V power supply 14 SSON I 3.3V LVTTL input for enabling spread spectrum clock 0 = Disable, 1 = Enable (-0.5% SS) Extrenal 10K ohm pull-up or pull-down resistor required 15 VSS 16 XOUT GND O Ground 14.318 MHz Crystal output. Table 1. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The SL28SRC01 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the SL28SRC01 to operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. DOC#: SP-AP-0015 (Rev. 0.2) Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim Page 2 of 11 SL28SRC01 capacitors are calculated to provide equal capacitive loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2 . Load Capacitance (each side) C lo c k C h ip Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) C i2 C i1 P in 3 to 6 p F X2 X1 C s1 = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance C s2 T ra c e 2 .8 p F XTAL Ce1 CLe CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Ce2 Cs .............................................. Stray capacitance (terraced) T r im 33pF Ci ...........................................................Internal capacitance Figure 2. Crystal Loading Example (lead frame, bond wires, etc.) , Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit – 4.6 V –0.5 4.6 VDC –65 150 °C Functional 0 85 °C Temperature, Operating Ambient, Industrial Functional -40 85 °C VDD Core Supply Voltage VIN Input Voltage Relative to VSS TS Temperature, Storage Non-functional TA (commercial) Temperature, Operating Ambient, Commercial TA (industrial) TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 – V UL-94 Flammability Rating UL (Class) Max. Unit 3.135 3.465 V 2.0 VDD + 0.3 V V–0 DC Electrical Specifications Parameter Description VDD 3.3V Operating Voltage VIH 3.3V Input High Voltage Condition 3.3 ± 5% Min. VIL 3.3V Input Low Voltage VSS – 0.3 0.8 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage IOH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V IOZ High-impedance Output Current –10 10 A DOC#: SP-AP-0015 (Rev. 0.2) Page 3 of 11 SL28SRC01 DC Electrical Specifications Parameter Description CIN Input Pin Capacitance COUT Output Pin Capacitance LIN Pin Inductance VXIH Xin High Voltage VXIL Xin Low Voltage IDD3.3V Dynamic Supply Current DOC#: SP-AP-0015 (Rev. 0.2) Condition Min. Max. Unit 1.5 5 pF 6 pF 7 nH 0.7VDD VDD V 0 0.3VDD V – 40 mA – Page 4 of 11 SL28SRC01 AC Electrical Specifications Parameter Description Condition Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns Crystal TDC XIN Duty Cycle The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When XIN is driven from an external clock source TR/TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD TCCJ XIN Cycle to Cycle Jitter As an average over 1-s duration – 500 ps LACC Long-term Accuracy Measured at VDD/2 differential – 250 ppm TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % Clock Input TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIL Input Low Voltage XIN / CLKIN pin – 0.8 V VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 – 20 uA IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA SRC TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Measured at 0V differential at 1 clock 9.87406 10.1762 ns TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 50 ps RMSGEN1 Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 0 108 ps Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 0 3.0 ps Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 0 3.1 ps Output phase jitter impact – PCIe* Gen3 Includes PLL BW 2 - 4 MHz, CDR = 10MHz) 0 1.0 ps LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm T R / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV RMSGEN2 RMSGEN2 RMSGEN3 DOC#: SP-AP-0015 (Rev. 0.2) Page 5 of 11 SL28SRC01 AC Electrical Specifications Parameter Tjphasepll Description Condition Phase Jitter (PLL BW 8-16MHz, 5-16MHz ) Min. Max. Unit 3.1 pS – 1.8 ms 10.0 – ns RMS value ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time Test and Measurement Set-up For SRC Signals This diagram shows the test load configuration for the differential SRC outputs Figure 3. 0.7V Differential Load Configuration Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0015 (Rev. 0.2) Page 6 of 11 SL28SRC01 Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0015 (Rev. 0.2) Page 7 of 11 SL28SRC01 Ordering Information Part Number Package Type Product Flow Lead-free SL28SRC01BZI 16-pin TSSOP Industrial, -40 to 85C SL28SRC01BZIT 16-pin TSSOP–Tape and Reel Industrial, -40 to 85C SL 28 SRC01 B Z I T Packaging Designator for Tape and Reel Temperature Designator Package Designator Z : TSSOP Revision Number A = 1st Silicon Generic Part Number Designated Family Number Company Initials This device is Pb free and RoHS compliant DOC#: SP-AP-0015 (Rev. 0.2) Page 8 of 11 SL28SRC01 Package Diagrams 16-pin TSSOP DOC#: SP-AP-0015 (Rev. 0.2) Page 9 of 11 SL28SRC01 Document History Page Document Title: SL28SRC01 PCI Express Gen 2 & Gen 3 Clock Generator REV. ECR# Issue Date 1.0 1.1 AA 1454 Orig. of Change Description of Change 09/13/09 JMA New datasheet 11/06/09 JMA Updated Figure 4 04/25/10 JMA 1. Updated pin 6 definition on page 2 2. Updated revision to be ISO compliant 3. Updated package information 4. Added commercial temperature grade 5. Added clock in features DOC#: SP-AP-0015 (Rev. 0.2) Page 10 of 11 SL28SRC01 The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. DOC#: SP-AP-0015 (Rev. 0.2) Page 11 of 11