Si 5 34 REVISION D Q UAD F R E Q U E N C Y C RYSTAL O S C I L L A T O R (XO) (10 M H Z TO 1.4 G H Z ) Features Si5602 Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz Four selectable output frequencies ® 3rd generation DSPLL with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Ordering Information: Applications See page 7. SONET/SDH Networking SD/HD video Test and measurement Clock and data recovery FPGA/ASIC clock generation Pin Assignments: See page 6. Description (Top View) The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si534 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si534 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si534 IC-based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. FS[1] 7 NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ 8 FS[0] (LVDS/LVPECL/CML) FS[1] Functional Block Diagram 7 VDD FS[1] Fixed Frequency XO CLK– CLK+ Any-rate 10–1400 MHz DSPLL® Clock Synthesis OE Rev. 1.3 4/13 NC 1 6 VDD OE 2 5 NC GND 3 4 CLK 8 FS[0] FS[0] (CMOS) GND Copyright © 2013 by Silicon Laboratories Si534 Si5 34 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Supply Current Symbol Test Condition Min Typ Max Units VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Output enabled LVPECL CML LVDS CMOS — — — — 111 99 90 81 121 108 98 88 Tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 ºC IDD Output Enable (OE) and Frequency Select FS[1:0]2 Operating Temperature Range TA mA Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE and FS[1:0] pins include a 17 k pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol Test Condition Min Typ Max Units fO LVPECL/LVDS/CML 10 — 945 MHz CMOS 10 — 160 MHz Measured at +25 °C at time of shipping — ±1.5 — ppm –7 –20 –50 — — — +7 +20 +50 ppm Frequency drift over first year — — ±3 ppm Frequency drift over 20-year life — — ±10 ppm Temp stability = ±7 ppm — — ±20 ppm Temp stability = ±20 ppm — — ±31.5 ppm Temp stability = ±50 ppm — — ±61.5 ppm fi Temperature Stability1,3 Aging fa Total Stability Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Rev. 1.3 Si534 Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Powerup Symbol Time4 Test Condition Min Typ Max Units — — 10 ms — — 20 ms tOSC Settling Time After FS[1:0] Change tFRQ Both FS[1] and FS[0] changing simultaneously Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP VOH IOH = 32 mA 0.8 x VDD — VDD V VOL IOL = 32 mA — — 0.4 V tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL = 15 pF — 1 — ns 45 — 55 % LVPECL Output Option1 LVDS Output Option2 CML Output Option2 VO VOD CMOS Output Option3 Rise/Fall time (20/80%) Symmetry (duty cycle) SYM LVPECL: (diff) LVDS: CMOS: VDD – 1.3 V 1.25 V (diff) VDD/2 Notes: 1. 50 to VDD – 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF Rev. 1.3 3 Si5 34 Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)1 for FOUT > 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps 50 kHz to 80 MHz (OC-192) — 0.26 0.37 ps Phase Jitter (RMS)1 for FOUT of 125 to 500 MHz J 12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps — 0.34 0.42 ps Phase Jitter (RMS) for FOUT of 10 to 160 MHz CMOS Output Only J 12 kHz to 20 MHz (OC-48)2 — 0.62 — ps 50 kHz to 20 MHz2 — 0.61 — ps 50 kHz to 80 MHz (OC-192) 2 Notes: 1. Refer to AN256 for further information. 2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz, 2 MHz for 10 MHz < FOUT <50 MHz. Table 5. CLK± Output Period Jitter Parameter Period Jitter* Symbol Test Condition Min Typ Max Units JPER RMS — 2 — ps Peak-to-Peak — 14 — ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 6. CLK± Output Phase Noise (Typical) Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 4 120.00 MHz 156.25 MHz 622.08 MHz LVDS LVPECL LVPECL –112 –122 –132 –137 –144 –150 n/a –105 –122 –128 –135 –144 –147 n/a –97 –107 –116 –121 –134 –146 –148 Rev. 1.3 Units dBc/Hz Si534 Table 7. Environmental Compliance The Si534 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross & Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level J-STD_020, MSL1 Gold over Nickel Contact Pads Table 8. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Table 9. Absolute Maximum Ratings1 Parameter Symbol Rating Units TAMAX 85 ºC Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V Input Voltage (any input pin) VI –0.5 to VDD + 0.3 V Storage Temperature TS –55 to +125 ºC ESD 2000 V TPEAK 260 ºC tP 20–40 seconds Maximum Operating Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Rev. 1.3 5 Si5 34 2. Pin Descriptions (Top View) FS[1] FS[1] 7 7 NC 1 6 VDD NC 1 6 VDD OE 2 5 CLK– OE 2 5 NC GND 3 4 CLK+ GND 3 4 CLK 8 8 FS[0] FS[0] CMOS LVDS/LVPECL/CML Table 10. Pin Descriptions Pin Symbol LVDS/LVPECL/CML Function CMOS Function 1 NC No connection No connection 2 OE* 3 GND Electrical and Case Ground Electrical and Case Ground 4 CLK+ Oscillator Output Oscillator Output 5 CLK– Complementary Output No connection 6 VDD Power Supply Voltage Power Supply Voltage 7 FS[1]* Frequency Select MSB Frequency Select MSB 8 FS[0]* Frequency Select LSB Frequency Select LSB Output enable Output enable 0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated) 1 = clock output enabled 1 = clock output enabled *Note: FS[1:0] and OE include a 17 k pullup resistor to VDD. See Section 3. "Ordering Information" on page 7 for details on frequency value ordering. 6 Rev. 1.3 Si534 3. Ordering Information The Si534 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si534 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si534 is supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. 534 X X D XXXXXX G R R = Tape & Reel Blank = Trays 534 Quad XO Product Family Operating Temp Range (°C) G –40 to +85 °C 1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Note: CMOS available to 160 MHz. Device Revision Letter 6-digit Frequency Designator Code Four unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for the specified combination of frequencies. Codes > 000100 refer to quad XOs programmed with the lowest frequency value selected when FS[1:0] = 00, and the highest value when FS[1:0] = 11. Six digit codes < 000100 refer to quad XOs programmed with the highest frequency value selected when FS[1:0] = 00, and the lowest value when FS[1:0] = 11. 2nd Option Code Code Temperature Stability (ppm, max, ±) A 50 B 20 C 7 Total Stablility (ppm, max, ±) 61.5 31.5 20 Example Part Number: 534AB000108DGR is a 5 x 7 mm quad XO in a 8 pad package. Since the six digit code (000108) is > 000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply, LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±20 ppm. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention Rev. 1.3 7 Si5 34 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si534. Table 11 lists the values for the dimensions shown in the illustration. Figure 2. Si534 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension A b b1 c c1 D D1 e E E1 H L L1 p R aaa bbb ccc ddd eee Min 1.50 1.30 0.90 0.50 0.30 Nom 1.65 1.40 1.00 0.60 — 5.00 BSC 4.40 2.54 BSC 7.00 BSC 6.20 0.65 1.27 1.17 — 0.70 REF — — — — — 4.30 6.10 0.55 1.17 1.07 1.80 — — — — — Max 1.80 1.50 1.10 0.70 0.60 4.50 6.30 0.75 1.37 1.27 2.60 0.15 0.15 0.10 0.10 0.05 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 8 Rev. 1.3 Si534 5. Si534 Mark Specification Figure 3 illustrates the mark specification for the Si534. Table 12 lists the line information. Figure 3. Mark Specification Table 12. Si53x Top Mark Description Line Position 1 1–10 “SiLabs 534” 2 1–10 Si530, Si531: Option1 + Option2 + Freq(7) + Temp Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 Description Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Rev. 1.3 9 Si5 34 6. 8-Pin PCB Land Pattern Figure 4 illustrates the 8-pin PCB land pattern for the Si554. Table 13 lists the values for the dimensions shown in the illustration. Figure 4. Si534 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF D3 5.705 REF e 2.54 BSC E2 4.20 REF GD 0.84 GE 2.00 — — VD 8.20 REF VE 7.30 REF X1 1.70 TYP X2 1.545 TYP Y1 2.15 REF Y2 1.3 REF ZD — 6.78 ZE — 6.30 Note: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design follows IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 10 Rev. 1.3 Si534 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Updated Table 1, “Recommended Operating Conditions,” on page 2. Device maintains stable operation over –40 to +85 ºC operating temperature range. Supply current specifications updated for revision D. Updated Table 2, “CLK± Output Frequency Characteristics,” on page 2. Added specification for ±20 ppm lifetime stability (±7 ppm temperature stability) XO. Updated Table 3, “CLK± Output Levels and Symmetry,” on page 3. Updated LVDS differential peak-peak swing specifications. Updated Table 4, “CLK± Output Phase Jitter,” on page 4. Updated Table 5, “CLK± Output Period Jitter,” on page 4. Revised period jitter specifications. Updated Table 9, “Absolute Maximum Ratings1,” on page 5 to reflect the soldering temperature time at 260 ºC is 20–40 sec per JEDEC J-STD-020C. Updated 3. "Ordering Information" on page 7. Changed ordering instructions to revision D. Added 5. "Si534 Mark Specification" on page 9. Revision 1.1 to Revision 1.2 Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in the footnote referring to AN256 in Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Updated ESD HBM sensitivity rating in Table 9 on page 5. Updated Table 7 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Revised Figure 2 on page 8 to reflect current package outline diagram. Updated Figure 3 and Table 12 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Revision 1.2 to Revision 1.3 Added Table 8, “Thermal Characteristics,” on page 5. Rev. 1.3 11 Si5 34 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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