AN900 OPTIMIZED SOLUTION REQUIREMENTS FOR THE ITALIAN WMB U S 1. Introduction This application note shows an optimized hardware solution for the Italian WMBUS application. The main design target is to comply with the Italian WMBUS requirements as described below. Power control between +27 and –27 dBm output with 1 dB linear power steps Silicon Labs reference design: 4463CPSQ27E169S External FEM is interfaced with Si4463: SKY66100-11 Operating frequency band: 169 MHz The RF schematic is shown in Appendix A. 2. Si4463 Settings The external PA from Skyworks Solutions (SKY66100-11) is used in transmit mode between the output power of +27 and +20 dBm. In order to achieve the best TX power efficiency under +20 dBm of output power the SKY66100-11 external PA is proposed to work in TX bypass mode. Moreover, in the output power region of +20 and +5 dBm the proposed TX mode for the Si4463 chip is the switched-PA mode (i.e. Class-E/Square-Wave). This gives a reliable solution with linear 1 dB power steps and the best TX power efficiency. However, below +5 dBm output power the recommended PA mode for the Si4463 chip is the switched-current mode which can even ensure linear 1 dB steps in the output power level down to -27 dBm. Table 1 shows the recommended PA settings for the given output power level. The Si4463 PA settings include 3 different registers such as PA_mode, PA_pwr_lvl and PA_Bias_Clkduty. The SKY66100-11 external FEM mode is controlled by the RF GPIOs of Si4463. The minimum number of the applied slices of PA_pwr_lvl, PA_Bias_Clkduty is what gives reliable results in terms of chip-to-chip variation as well, so the property values in Table 1 can be applied in a look-up table for a given application too. Of course, in a custom design some differences might occur in the measured output power levels compared to the Silicon Labs 4463CPSQ27E169S reference design due to possible different RF layout and board stack-up (i.e. to get the same output power level slight variance can be between the optimized PA settings compared to the values in Table 1.). To avoid this, it is suggested to copy and follow the mentioned reference design layout and matching network element values as much as possible. Rev. 0.1 6/15 Copyright © 2015 by Silicon Laboratories AN900 AN900 Table 1. Chip Configuration for Output Power Levels Output Power [dBm] 2 Current Cons. [mA] Si4463 PA Settings SKY66100-11 PA_mode PA_pwr_lvl PA_Bias_Clkduty FEM_mode 27,1 341 0x09 0x11 0x11 transmit 26 287 0x09 0x0D 0x10 transmit 25 253 0x09 0x0D 0x0D transmit 24 226 0x09 0x0A 0x0F transmit 23,1 208 0x09 0x07 0x15 transmit 22 183 0x09 0x09 0x0E transmit 21 166 0x09 0x09 0x0D transmit 20,1 109 0x08 0x5F 0x00 bypass 19 97 0x08 0x3D 0x00 bypass 18,1 89 0x08 0x32 0x00 bypass 17,1 82 0x08 0x2B 0x00 bypass 16 75 0x08 0x25 0x00 bypass 15,1 70 0x08 0x21 0x00 bypass 14,1 64 0x08 0x1D 0x00 bypass 13 59 0x08 0x19 0x00 bypass 12 55 0x08 0x16 0x00 bypass 11,1 52 0x08 0x14 0x00 bypass 10,2 49 0x08 0x12 0x00 bypass 9,2 46 0x08 0x10 0x00 bypass 8,1 43 0x08 0x0E 0x00 bypass 7,2 35 0x08 0x14 0xC0 bypass 6 33 0x08 0x11 0xC0 bypass 5 38 0x09 0x25 0x25 bypass 4 36 0x09 0x23 0x23 bypass 3 34 0x09 0x21 0x21 bypass 2 33 0x09 0x1F 0x1F bypass Rev. 0.1 A N 900 Table 1. Chip Configuration for Output Power Levels (Continued) Output Power [dBm] Current Cons. [mA] Si4463 PA Settings SKY66100-11 PA_mode PA_pwr_lvl PA_Bias_Clkduty FEM_mode 0,9 32 0x09 0x1D 0x1D bypass 0 31 0x09 0x1C 0x1B bypass –0,9 30 0x09 0x1A 0x1A bypass –2 29 0x09 0x19 0x18 bypass –3 28 0x09 0x18 0x16 bypass –3,8 28 0x09 0x16 0x16 bypass –5 27 0x09 0x14 0x15 bypass –5,9 26 0x09 0x14 0x13 bypass –6,8 26 0x09 0x12 0x13 bypass –7,8 26 0x09 0x11 0x12 bypass –8,8 25 0x09 0x11 0x10 bypass –9,9 25 0x09 0x0F 0x10 bypass –10,9 24 0x09 0x0F 0x0E bypass –12,1 24 0x09 0x0E 0x0D bypass –13 24 0x09 0x0D 0x0D bypass –14,1 24 0x09 0x0C 0x0C bypass –15 23 0x09 0x0B 0x0C bypass –15,8 23 0x09 0x0B 0x0B bypass –17 23 0x09 0x09 0x0C bypass –18 23 0x09 0x08 0x0C bypass –18,8 23 0x09 0x08 0x0B bypass –20,1 23 0x09 0x07 0x0B bypass –21 23 0x09 0x07 0x0A bypass –22 23 0x09 0x07 0x09 bypass –23 22 0x09 0x07 0x08 bypass –24 22 0x09 0x07 0x07 bypass Rev. 0.1 3 AN900 Table 1. Chip Configuration for Output Power Levels (Continued) Output Power [dBm] 4 Current Cons. [mA] Si4463 PA Settings SKY66100-11 PA_mode PA_pwr_lvl PA_Bias_Clkduty FEM_mode –25 22 0x09 0x07 0x06 bypass –26,2 22 0x09 0x05 0x08 bypass –27,2 22 0x09 0x05 0x07 bypass Rev. 0.1 A N 900 3. WES0200 Measured Results Hardware: 4463CPSQ27E169S (WES0200-01 project as Silicon Labs reference design) Supply voltage for both Si4463 and SKY66100-11 is 3.3 V. Figure 1. Measured Output Power Plot Measured RX sensitivity is –104.7 dBm @ BER<0.1% with 100 kbps data rate and 50 kHz frequency deviation with 2-level GFSK modulation. Rev. 0.1 5 AN900 A P P E N D I X A: RF S C H E M A T I C 6 Rev. 0.1 A N 900 A P P E N D I X B: TO P - L A Y E R R F L A Y O U T Rev. 0.1 7 AN900 A P P E N D I X C: B A T C H F I L E #BatchName Si4463 #Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 #MOD_type: 0 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 #RF Freq.(MHz): 169 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 #API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0 # # RX IF frequency is -468750 Hz # WB filter 2 (BW = 51.53 kHz); NB-filter 2 (BW = 51.53 kHz) # # Modulation index: 4 RESET PATCH Si446x_C2_GENERAL.csg (C:\Program Files (x86)\Silabs\WDS3\Patch\Si446x_C2_GENERAL.csg) 'POWER_UP' 81 00 01 C9 C3 80 'GPIO_PIN_CFG' 03 00 03 03 00 00 00 'SET_PROPERTY' 'GLOBAL_XO_TUNE' 52 'SET_PROPERTY' 'FRR_CTL_A_MODE' 00 'SET_PROPERTY' 'FRR_CTL_B_MODE' 00 'SET_PROPERTY' 'FRR_CTL_C_MODE' 00 'SET_PROPERTY' 'FRR_CTL_D_MODE' 00 'SET_PROPERTY' 'INT_CTL_ENABLE' 00 'SET_PROPERTY' 'GLOBAL_CONFIG' 20 'SET_PROPERTY' 'GLOBAL_CLK_CFG' 00 SET_PROPERTY' 'PA_MODE' 09 SET_PROPERTY' 'PA_PWR_LVL' 11 SET_PROPERTY' 'PA_BIAS_CLKDUTY' 11 'SET_PROPERTY' 'MODEM_MOD_TYPE' 08 'SET_PROPERTY' 'MODEM_MAP_CONTROL' 00 'SET_PROPERTY' 'MODEM_DSM_CTRL' 07 'SET_PROPERTY' 'MODEM_CLKGEN_BAND' 0D 'SET_PROPERTY' 'SYNTH_PFDCP_CPFF' 2C 'SET_PROPERTY' 'SYNTH_PFDCP_CPINT' 0E 'SET_PROPERTY' 'SYNTH_VCO_KV' 0B 'SET_PROPERTY' 'SYNTH_LPFILT3' 04 'SET_PROPERTY' 'SYNTH_LPFILT2' 0C 'SET_PROPERTY' 'SYNTH_LPFILT1' 73 'SET_PROPERTY' 'SYNTH_LPFILT0' 03 8 Rev. 0.1 A N 900 'SET_PROPERTY' 'MODEM_DATA_RATE_2' 01 'SET_PROPERTY' 'MODEM_DATA_RATE_1' 86 'SET_PROPERTY' 'MODEM_DATA_RATE_0' A0 'SET_PROPERTY' 'MODEM_TX_NCO_MODE_3' 01 'SET_PROPERTY' 'MODEM_TX_NCO_MODE_2' C9 'SET_PROPERTY' 'MODEM_TX_NCO_MODE_1' C3 'SET_PROPERTY' 'MODEM_TX_NCO_MODE_0' 80 'SET_PROPERTY' 'MODEM_FREQ_DEV_2' 00 'SET_PROPERTY' 'MODEM_FREQ_DEV_1' 10 'SET_PROPERTY' 'MODEM_FREQ_DEV_0' 62 'SET_PROPERTY' 'MODEM_TX_RAMP_DELAY' 00 'SET_PROPERTY' 'PA_TC' 1D 'SET_PROPERTY' 'FREQ_CONTROL_INTE' 42 'SET_PROPERTY' 'FREQ_CONTROL_FRAC_2' 0C 'SET_PROPERTY' 'FREQ_CONTROL_FRAC_1' CC 'SET_PROPERTY' 'FREQ_CONTROL_FRAC_0' CC 'SET_PROPERTY' 'FREQ_CONTROL_CHANNEL_STEP_SIZE_1' CC 'SET_PROPERTY' 'FREQ_CONTROL_CHANNEL_STEP_SIZE_0' CD 'SET_PROPERTY' 'FREQ_CONTROL_W_SIZE' 20 'SET_PROPERTY' 'FREQ_CONTROL_VCOCNT_RX_ADJ' FA 'SET_PROPERTY' 'MODEM_MDM_CTRL' 00 'SET_PROPERTY' 'MODEM_IF_CONTROL' 08 'SET_PROPERTY' 'MODEM_IF_FREQ_2' 02 'SET_PROPERTY' 'MODEM_IF_FREQ_1' 80 'SET_PROPERTY' 'MODEM_IF_FREQ_0' 00 'SET_PROPERTY' 'MODEM_DECIMATION_CFG1' 30 'SET_PROPERTY' 'MODEM_DECIMATION_CFG0' 20 'SET_PROPERTY' 'MODEM_BCR_OSR_1' 00 'SET_PROPERTY' 'MODEM_BCR_OSR_0' BC 'SET_PROPERTY' 'MODEM_BCR_NCO_OFFSET_2' 02 'SET_PROPERTY' 'MODEM_BCR_NCO_OFFSET_1' BB 'SET_PROPERTY' 'MODEM_BCR_NCO_OFFSET_0' 0D 'SET_PROPERTY' 'MODEM_BCR_GAIN_1' 00 'SET_PROPERTY' 'MODEM_BCR_GAIN_0' AE 'SET_PROPERTY' 'MODEM_BCR_GEAR' 02 'SET_PROPERTY' 'MODEM_BCR_MISC0' 00 'SET_PROPERTY' 'MODEM_BCR_MISC1' 00 'SET_PROPERTY' 'MODEM_AFC_GEAR' 00 'SET_PROPERTY' 'MODEM_AFC_WAIT' 12 'SET_PROPERTY' 'MODEM_AFC_GAIN_1' 81 'SET_PROPERTY' 'MODEM_AFC_GAIN_0' 06 'SET_PROPERTY' 'MODEM_AFC_LIMITER_1' 03 'SET_PROPERTY' 'MODEM_AFC_LIMITER_0' 55 Rev. 0.1 9 AN900 'SET_PROPERTY' 'MODEM_AFC_MISC' A0 'SET_PROPERTY' 'MODEM_AGC_CONTROL' E0 'SET_PROPERTY' 'MODEM_AGC_WINDOW_SIZE' 11 'SET_PROPERTY' 'MODEM_AGC_RFPD_DECAY' 29 'SET_PROPERTY' 'MODEM_AGC_IFPD_DECAY' 29 'SET_PROPERTY' 'MODEM_FSK4_GAIN1' 80 'SET_PROPERTY' 'MODEM_FSK4_GAIN0' 1A 'SET_PROPERTY' 'MODEM_FSK4_TH1' FF 'SET_PROPERTY' 'MODEM_FSK4_TH0' FF 'SET_PROPERTY' 'MODEM_FSK4_MAP' 00 'SET_PROPERTY' 'MODEM_OOK_PDTC' 29 'SET_PROPERTY' 'MODEM_OOK_BLOPK' 0C 'SET_PROPERTY' 'MODEM_OOK_CNT1' A4 'SET_PROPERTY' 'MODEM_OOK_MISC' 23 'SET_PROPERTY' 'MODEM_RAW_SEARCH2' 84 'SET_PROPERTY' 'MODEM_RAW_CONTROL' 03 'SET_PROPERTY' 'MODEM_RAW_EYE_1' 02 'SET_PROPERTY' 'MODEM_RAW_EYE_0' AA 'SET_PROPERTY' 'MODEM_ANT_DIV_MODE' 02 'SET_PROPERTY' 'MODEM_ANT_DIV_CONTROL' 00 'SET_PROPERTY' 'MODEM_RSSI_JUMP_THRESH' 06 'SET_PROPERTY' 'MODEM_RSSI_CONTROL' 09 'SET_PROPERTY' 'MODEM_RSSI_CONTROL2' 1C 'SET_PROPERTY' 'MODEM_RSSI_COMP' 40 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE13_7_0' FF 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE12_7_0' C4 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE11_7_0' 30 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE10_7_0' 7F 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE9_7_0' F5 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE8_7_0' B5 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE7_7_0' B8 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE6_7_0' DE 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE5_7_0' 05 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE4_7_0' 17 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE3_7_0' 16 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE2_7_0' 0C 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE1_7_0' 03 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COE0_7_0' 00 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COEM0' 15 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COEM1' FF 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COEM2' 00 'SET_PROPERTY' 'MODEM_CHFLT_RX1_CHFLT_COEM3' 00 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE13_7_0' FF 10 Rev. 0.1 A N 900 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE12_7_0' C4 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE11_7_0' 30 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE10_7_0' 7F 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE9_7_0' F5 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE8_7_0' B5 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE7_7_0' B8 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE6_7_0' DE 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE5_7_0' 05 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE4_7_0' 17 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE3_7_0' 16 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE2_7_0' 0C 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE1_7_0' 03 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COE0_7_0' 00 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COEM0' 15 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COEM1' FF 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COEM2' 00 'SET_PROPERTY' 'MODEM_CHFLT_RX2_CHFLT_COEM3' 00 'SET_PROPERTY' 'MODEM_SPIKE_DET' 09 'SET_PROPERTY' 'MODEM_DSA_CTRL1' 40 'SET_PROPERTY' 'MODEM_DSA_CTRL2' 04 'SET_PROPERTY' 'MODEM_ONE_SHOT_AFC' 07 'SET_PROPERTY' 'MODEM_DSA_QUAL' 14 'SET_PROPERTY' 'MODEM_DSA_RSSI' 78 'SET_PROPERTY' 'MODEM_DECIMATION_CFG2' 00 'SET_PROPERTY' 'MODEM_IFPKD_THRESHOLDS' E8 'SET_PROPERTY' 'MODEM_RSSI_MUTE' 00 'SET_PROPERTY' 'MODEM_DSA_MISC' 20 'SET_PROPERTY' 'PREAMBLE_CONFIG' 21 'START_TX' 00 00 00 00 Rev. 0.1 11 AN900 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Rev. 0.1