AN887 Si534 X A N D P OWER S UPPLY N O I S E The Si534x is an industry-leading family of high-performance, ultra-low jitter Clock Generators and Jitter Attenuating Clocks. The Silicon Labs Si534x series can easily perform in systems with low to moderate power supply noise using simple power supply bypass capacitors. In systems with excessive power supply noise, output signal quality and/or jitter performance may be affected. This application note will illustrate the effects of excessive power supply noise, and offer some simple remedies for mitigation of the effects of excessively noisy power supplies. 1. Linear (LDO) vs. Switching Power Supplies One of the simplest methods of providing a regulated supply voltage is to use monolithic Low Drop-Out (LDO) linear voltage regulators on an unregulated DC source. LDOs take a higher source voltage and drop the voltage to the desired level by using linear pass elements (usually pass transistors) controlled by voltage regulation circuits. Linear or LDO regulators are good at providing clean and easy-to-design power sources, but Linear/LDO designs are not the most power efficient. Regulation is achieved by linearly dropping voltage across the LDO’s pass element. This voltage drop is dissipated as heat and reduces the overall efficiency of the power supply. In systems where power efficiency is a major concern, LDOs are not typically used. Switching power supplies are typically used in applications requiring power efficiency. Switching circuits operate by “chopping” or “switching” an unregulated DC voltage in a low-loss fashion into small packets of energy that are then “reassembled” in a way that translates the energy to a different DC voltage. The key to the switching power supply is that the voltage translation happens with high efficiency and minimal loss. Switching power supplies can achieve power efficiencies of 90% or better. Contrast this to typical Linear/LDO efficiencies of 60% or less. But the switcher’s power efficiency comes at the expense of circuit/component complexity and added power supply noise. For many digital systems this added power supply noise is not a concern. But for analog and/or mixed-signal systems, the added switching noise can have an unwanted effect on performance. Manufacturers of switching power supplies have tried to address the noise and component concerns by providing solutions with higher frequency switching in efforts to reduce component size and push switching noise to higher, and easier to filter, frequencies. Note: As of this writing, the Si534x family includes the Si5340, Si5341, Si5342, Si5344, Si5345, Si5346, and Si5347. Rev. 0.1 4/15 Copyright © 2015 by Silicon Laboratories AN887 AN887 2. Power Supply (PS) Noise Testing Methodology and Lab Setup To quantify the effects of Power Supply (PS) noise on a Si534x based system, a PS noise test methodology was developed to discover how a Si534x based system reacts to PS noise. This test is not to be confused with a traditional “Power Supply Rejection Ratio” or PSRR test. Traditional PSRR is a measure of PS-noise-voltage to output-noise-voltage expressed as a ratio. This is useful as a figure of merit for an amplifier, but not very useful for a clock generator. For a clock generator, such as the Si534x, what is desired is to know how PS noise affects characteristics of the output clock signal. Clock signal characteristics are most easily observed by measuring in the frequency/phase domain, which is customarily done by using a spectrum analyzer or phase noise analyzer. For this test methodology an Agilent E5052B Signal Source Analyzer was used, which provides both phase noise plots and integrated phase jitter measurements. While most real-world PS noise is composed of a variety of complex, wide-band waveforms, this test was done using a single frequency sine wave swept in amplitude and frequency. This swept single frequency methodology reveals the Si534x system’s frequency and amplitude response to PS noise. Once the target system’s PS noise response is known, PS noise mitigation can then be more effectively designed. The block diagram in Figure 1 shows the lab test setup used for PS noise testing. The Si5341-EVB was chosen as the system test platform for Si534x Power Supply (PS) testing since it both uses LDOs and can be easily modified to accept other power sources. Figure 1. Power Supply Noise Lab Testing Setup This lab setup was designed to allow adjustment of the amplitude and frequency of the sine wave “noise” component independently of the power supply DC voltage. This is accomplished by using a high current summing amplifier, adjustable power supplies, and signal generator as shown in Figure 1. The high current amplifier can supply currents in excess of those required by each of the three Si5341 VDD supplies. The typical source impedance of the high current amplifier in this test configuration is 0.04 to 0.05 Ω, providing a reasonable proxy for power supply output impedance. The Si5341 clock output signal used for this PS testing is a 300 MHz LVPECL differential clock. The 300 MHz differential clock goes through a Balun to translate the differential LVPECL into a single-ended input to the E5052B Signal Source Analyzer. The actual PS voltage on the 2 Rev. 0.1 AN887 EVB was monitored with an Oscilloscope. In this setup, each power supply can be isolated and tested individually while the remaining two supplies continue to use its on-board LDO. The external power is brought in to the EVB via one of the EVB’s on-board SMA clock output connectors that was re-purposed to serve as the power input for each of the three supplies. (Only a single clock output was needed for this test.) The Si5341 supply voltages tested are: 1. Analog supply at 3.3 V nominal (VDDA) 2. The 300 MHz LVPECL Clock output driver supply at 3.3 V nominal (VDDO) 3. Digital Core supply at 1.8 V nominal (VDD) For each test, the external DC supply voltage is set to provide the respective nominal DC supply voltage. The test amplitudes for the AC sine wave are nominally 10 mV, 25 mV, 50 mV and 100 mV pk-pk as measured on a test system board without any PS noise filtering (see Step 2 in Section “3. Basic Test Procedure” ). These noise drive levels are stored and used for nominal noise drive levels throughout all testing, even as PS filtering components may change in attempts to attenuate noise at each PS input of the Si5341 device. At each of those amplitude settings the frequencies swept are 0 Hz (DC), 100 KHz, 250 KHz, 500 KHz, 1 MHz, 2 MHz, 3 MHz, and 4 MHz. These frequencies were chosen to represent a reasonable range of switching power supply frequency components. 3. Basic Test Procedure 1. With the Si5341 EVB in the default LDO-only (as shipped) configuration, the output clock phase noise was measured and phase noise spectrum plot saved. This is the baseline performance level. 2. To calibrate the level of noise drive needed to result in the desired AC sine wave amplitude without bypass capacitors, each of the Si5341 EVB power rails were in turn stripped of all power supply bypass caps/ filtering components. The respective supply is then driven from the external source and Si5341 brought up to operational. The AC sine wave component is then added and drive level adjusted to result in the desired amplitude at each of the test frequencies. The amplifier drive levels are recorded at each step. The drive level is important since it represents the unfiltered level of PS noise as sourced from the PS while DC loaded by the active Si5341 device. 3. All as-shipped Si5341-EVB power supply bypass/filtering components are re-installed and EVB verified as fully operational based on phase noise data correlated from Step 1. 4. For each of the three power supplies: a. Drive respective supply from external source while the other two device supplies remain on-board LDO sourced. Initially measure phase noise and store phase noise plot data for DC baseline. b. For each sine wave frequency and amplitude drive setting (as recorded in Step 2), measure phase noise and fundamental spur level, store phase noise plot. c. Configure for next power supply. 3.1. Initial Test Data The data taken for each of the three power supplies is shown below in both tabular and graphical format. “NF” table entries indicate “None Found” or no spur was present. Rev. 0.1 3 AN887 4. Data for Analog VDDA—3.3 V Table 1. VDDA (Analog 3.3 V) Supply—EVB PS Filtering Clock: 300 MHz VDDA (Analog 3.3 V) Supply—EVB PS Filtering Clk Fmt: 3.3 V LVPECL 10 mV 25 mV 50 mV VDDA (V) Noise Profile Frequency PN –10 mV Fund. PN –25 mV Fund. PN –50 mV (KHz) (fs rms Spur (fs rms Spur (fs rms 12 k-20 M) (dBc) 12 k-20 M) (dBc) 12 k-20 M) 3.300 None 0 81.9 NF 81.9 NF 3.300 Sine 100 84.5 –92.2 90.3 3.300 Sine 250 83.9 –94.6 3.300 Sine 500 82.8 3.300 Sine 1000 3.300 Sine 3.300 3.300 Fund. Spur (dBc) PN –100 mV (fs rms 12 k-20 M) Fund. Spur (dBc) 81.9 NF 81.9 NF –86.1 111.2 –80.0 161.9 –74.6 87.3 –88.2 101.4 –82.0 137.2 –76.7 –98.8 84.4 –92.6 89.6 –86.5 105.2 –81.2 82.7 NF 83.0 –97.3 83.9 –93.9 85.7 –89.6 2000 82.2 NF 82.3 NF 82.3 –103.8 82.5 –101.7 Sine 3000 82.7 NF 82.0 NF 82.5 NF 82.2 NF Sine 4000 82.5 NF 82.6 NF 82.3 NF 82.1 NF *Note: “NF” means no spur. Figure 2. Total Phase Jitter—VDDA (3.3 V) 4 100 mV Rev. 0.1 AN887 5. Data for Output Driver VDDO—3.3 V Table 2. VDDO (Driver 3.3 V) Supply—EVB PS Filtering Carrier: 300 MHz VDDO (Driver 3.3 V) Supply—EVB PS Filtering Clk Fmt: 3.3 V LVPECL 10 mV 25 mV 50 mV VDDO (V) Noise Profile Frequency PN –10 mV Fund. PN –25 mV Fund. PN –50 mV (KHz) (fs rms Spur (fs rms Spur (fs rms 12 k-20 M) (dBc) 12 k-20 M) (dBc) 12 k-20 M) 3.300 None 0 82.7 NF 82.7 NF 3.300 Sine 100 82.8 NF 82.9 3.300 Sine 250 82.7 NF 3.300 Sine 500 82.8 3.300 Sine 1000 3.300 Sine 3.300 3.300 100 mV Fund. Spur (dBc) PN –100 mV (fs rms 12 k-20 M) Fund. Spur (dBc) 82.7 NF 82.7 NF NF 84.1 –95 84.6 –93 82.7 NF 83.5 –97 84.1 –94 NF 82.8 NF 83.0 NF 83.3 –98 82.7 NF 82.7 NF 82.9 NF 83.0 NF 2000 82.8 NF 82.8 NF 82.9 NF 82.8 NF Sine 3000 82.8 NF 82.8 NF 82.8 NF 82.8 NF Sine 4000 82.8 NF 82.8 NF 82.8 NF 83.0 NF *Note: “NF” means no spur. Figure 3. Total Phase Jitter—VDDO (3.3 V) Rev. 0.1 5 AN887 6. Data for Digital VDD—1.8 V Table 3. VDDD (Digital 1.8 V) Supply—EVB PS Filtering Carrier: 300 MHz VDDD (Digital 1.8 V) Supply — EVB PS Filtering Clk Fmt: 3.3 V LVPECL 10 mV 25 mV 50 mV VDDD (V) Noise Profile Frequency PN –10 mV Fund. PN –25 mV Fund. PN –50 mV (KHz) (fs rms Spur (fs rms Spur (fs rms 12 k-20 M) (dBc) 12 k-20 M) (dBc) 12 k-20 M) 1.800 None 0 82.5 NF 82.5 NF 1.800 Sine 100 82.7 NF 82.9 1.800 Sine 250 83.5 –98 1.800 Sine 500 82.9 1.800 Sine 1000 1.800 Sine 1.800 1.800 Fund. Spur (dBc) PN –100 mV (fs rms 12 k-20 M) Fund. Spur (dBc) 82.5 NF 82.5 NF NF 84.2 –94 85.6 –91 83.9 –95 86.9 –89 96.4 –84 NF 82.8 NF 83.4 –96 85.4 –92 82.8 NF 82.6 NF 82.7 NF 83.3 –98 2000 82.8 NF 82.8 NF 82.9 NF 82.9 NF Sine 3000 82.7 NF 82.5 NF 82.9 NF 83.0 NF Sine 4000 82.7 NF 82.8 NF 82.8 NF 82.7 NF *Note: “NF” means no spur. Figure 4. Total Phase Jitter—VDDD (1.8 V) 6 100 mV Rev. 0.1 AN887 7. Analysis of Initial Data PS noise levels below 50 mV appear to be well handled with the EVB’s existing PS bypass capacitor arrangement. The Output Driver (VDDO) PS bypass sufficiently handles the PS noise at all tested levels. The area of PS noise susceptibility appears to be mainly on the Analog (VDDA) supply, and to a lesser extent on the Digital (VDD) supply, for PS noise below 1 MHz and above 50 mV. The test results show that excessive PS noise can effect output clock jitter when using the simple bypass capacitor scheme used on Si5341 EVBs. Given this information, a solution for this level of potential excessive PS noise was devised. This solution is presented in the following section. 7.1. Solution for Excessive PS Noise Low frequency PS noise is best filtered by using larger value bypass capacitors designed to filter at lower frequencies. After some experimentation, adding a 33 µF tantalum capacitor to the Digital VDD (1.8 V) and a 220 µF tantalum capacitor to Analog VDDA (3.3 V) is a simple solution that effectively filters the excessive PS noise, as illustrated in following test data. Rev. 0.1 7 AN887 7.2. New Test Data with added Bypass Cap—Digital VDD (1.8 V) Table 4. VDDD (Digital 1.8 V) Supply—EVB PS Filtering + 33 µF Carrier: 300 MHz VDDD (Digital 1.8 V) Supply—EVB PS Filtering + 33 µF Clk Fmt: 3.3 V LVPECL 10 mV 25 mV 50 mV VDD (V) Noise Profile Frequency PN –10 mV Fund. PN –25 mV Fund. PN –50 mV (KHz) (fs rms Spur (fs rms Spur (fs rms 12 k-20 M) (dBc) 12 k-20 M) (dBc) 12 k-20 M) 1.800 None 0 82.8 NF 82.8 NF 1.800 Sine 100 82.9 NF 82.9 1.800 Sine 250 83.0 NF 1.800 Sine 500 83.0 1.800 Sine 1000 1.800 Sine 1.800 1.800 100 mV Fund. Spur (dBc) PN –100 mV (fs rms 12 k-20 M) Fund. Spur (dBc) 82.8 NF 82.8 NF NF 82.9 NF 84.0 –94 83.0 NF 82.9 NF 83.7 –96 NF 83.0 NF 83.0 NF 83.3 –99 82.9 NF 82.9 NF 83.0 NF 83.0 NF 2000 82.8 NF 82.8 NF 83.0 NF 83.0 NF Sine 3000 82.8 NF 82.8 NF 83.0 NF 83.0 NF Sine 4000 82.8 NF 82.8 NF 82.8 NF 82.8 NF *Note: “NF” means no spur. Figure 5. Total Phase Jitter—VDDD (1.8 V) with Added 33 µF 8 Rev. 0.1 AN887 7.3. New Test Data with added Bypass Cap—Analog VDDA (3.3 V) Table 5. VDDA (Analog 3.3 V) Supply—EVB PS Filtering + 220 µF Carrier: 300 MHz VDDA (Analog 3.3 V) Supply—EVB PS Filtering + 220 µF Clk Fmt: 3.3 V LVPECL 10 mV 25 mV VDD (V) Noise Profile Frequency PN –10 mV Fund. PN –25 mV (KHz) (fs rms Spur (fs rms 12 k-20 M) (dBc) 12 k-20 M) 3.300 Sine 0 82.7 NF 3.300 0 100 82.9 3.300 0 250 3.300 0 3.300 50 mV 100 mV Fund. Spur (dBc) PN –50 mV (fs rms 12 k-20 M) Fund. Spur (dBc) PN –100 mV (fs rms 12 k-20 M) Fund. Spur (dBc) 82.7 NF 82.7 NF 82.7 NF NF 84.1 –93.3 86.6 –89.0 94.4 –83.9 82.8 NF 83.6 –96.8 84.4 –92.8 87.8 –87.6 500 82.8 NF 83.1 –100.6 83.4 –97.0 84.6 –91.9 0 1000 82.8 NF 82.8 NF 83.3 –97.6 83.8 –95.4 3.300 0 2000 82.8 NF 82.8 NF 82.9 NF 83.0 –101.6 3.300 0 3000 82.7 NF 82.7 NF 82.7 NF 82.8 NF 3.300 0 4000 82.7 NF 82.7 NF 82.7 NF 82.8 NF *Note: “NF” means no spur. Figure 6. Total Phase Jitter—VDDA (3.3 V) with Added 220 µF Rev. 0.1 9 AN887 7.4. Analysis of Solution Data Addition of the larger bypass capacitors effectively suppresses the lower frequency PS noise when compared to the initial test data. Notice the dramatic reduction in output clock phase jitter after addition of the extra bypassing. This is a simple but effective solution for mitigating the effects of power supplies with excessive lower frequency (below 1 MHz) PS noise. 8. Conclusion If power supply efficiency isn’t a concern, the use of Linear or LDO regulators for powering the Si534x devices is suggested as it will give best power supply performance margins. If switching power supplies are required, attention should be paid to minimizing the power supply noise inherent to switching power supply designs. Each design should be evaluated for power supply noise effects during prototype stage. If power supply noise is excessive, use this application note as a guide to power supply filtering improvements. As shown by the data contained in this application note, a few simple component additions can essentially eliminate performance degradation in excessively noisy power supply environments. One popular technique used by many designers is to add locations for additional power supply filtering components, such as larger value bypass capacitors, in your PCB layout that can be added/removed later (with simple BOM change) without requiring a new PCB layout. 10 Rev. 0.1 AN887 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. 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