Data Sheet Rev. 1.62 / August 2014 ZSSC3122 cLite™ Low-Voltage Capacitive Sensor Signal Conditioner Mobile Sensing ICs Smart and Mobile ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Brief Description Benefits The ZSSC3122 is a CMOS integrated circuit for accurate capacitance-to-digital conversion and sensor-specific correction of capacitive sensor signals. Digital compensation of sensor offset, sensitivity, and temperature drift is accomplished via an internal digital signal processor running a correction algorithm with calibration coefficients stored in a non-volatile EEPROM. The ZSSC3122 is configurable for capacitive sensors with capacitances up to 10pF and a sensitivity of 125aF/LSB. It is compatible with both single capacitive sensors (both terminals must be accessible) and differential capacitive sensors. Measured and corrected sensor values can be 2 * output as I C™ , SPI, PDM, or alarms. 2 The I C™ interface can be used for a simple PCcontrolled calibration procedure to program a set of calibration coefficients into an on-chip EEPROM. The calibrated ZSSC3122 and a specific sensor are mated digitally: fast, precise, and without the cost overhead of trimming by external devices or laser. Maximum target input capacitance: 10pF Sampling rates as fast as 0.7ms at 8-bit resolution; 1.6ms at 10-bit; 5.0ms at 12-bit; 18.5ms at14-bit st Digital compensation of sensor: piece-wise 1 nd and 2 order sensor compensation or up to rd 3 order single-region sensor compensation st nd Digital compensation of 1 and 2 order temperature gain and offset drift Internal temperature compensation reference (no external components) Programmable capacitance span and offset Layout customized for die-die bonding with sensor for low-cost, high-density chip-on-board assembly † Accuracy as high as ±0.25% FSO@ -20 to 125°C, 3V, 5V, Vsupply ±10% Interfaces I²C™ or SPI interface—easy connection to a microcontroller PDM outputs (Filtered Analog Ratiometric) for both capacitance and temperature Up to two alarms that can act as full push-pull or open-drain switches Physical Characteristics Features Minimized calibration costs: no laser trimming, one-pass calibration using a digital interface Excellent for low-power battery applications Supply voltage: 1.8 to 5.5V Typical current consumption 650μA down to 60μA depending on configuration Typical Sleep Mode current: ≤ 1μA at 85°C Operation temperature: –20°C to +125°C Die or TSSOP14 package Available Support ZSSC3122 SSC Evaluation Kit available: SSC Evaluation Board, samples, software, documentation. Support for industrial mass calibration available. Quick circuit customization option for large production volumes. Application: Digital Output, Alarms VSUPPLY VDD cLite™ Vcore ZSSC3122 (+1.8V to 5.5V) 0.1µF 0.1µF Ready VSS GND SDA/MISO SCL/SCLK C0 SS Alarm_High CC * † Alarm_Low I2C™ is a registered trademark of NXP. See data sheet section 1.3 for restrictions. For more information, contact ZMDI via [email protected]. © 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.62 — August 28, 2014. All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner VDD (1.8V to 5.5V) ZSSC3122 Temp Sensor Vcore Ref Cap Offset Cap EEPROM 0.1µF Block Diagram CLK/Reset Ready SCL/SCLK SDA/MISO PDM 0.1µF Sensor C/A C0 C0 CC C1 C1 D MUX Analog Core 0.1µF 0.1µF PDM_C Output Communication Digital Core SUPPLY (+1.8V to 5.5V) VSUPPLY PDM_T C0 0.1µF Cap. Analog Output 0.1µF cLite™ Vcore ZSSC3122 Ready GND Temp Analog Output VSS SDA/MISO C0 SCL/SCLK SS CC LED CC VDD (+1.8V to 5.5V) VSS GND Alarm_High Application: Differential Capacitance Input V ZSSC3122 SS ROM Application: Analog Output Vcore Low Alarm High Alarm VSS cLite™ Alarm_Low/PDM_T DSP CDC (Optional) VDD Ready/PDM_C I2C / SPI Alarm_High C1 Alarm_High Alarm_Low Ordering Codes Sales Code Description Package ZSSC3122AA1BN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on un-sawn wafer, 370µm ZSSC3122AI1BN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on un-sawn wafer, 370µm ZSSC3122AI3BN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on un-sawn wafer, 725µm ZSSC3122AA3BN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on un-sawn wafer, 725µm ZSSC3122AA1CN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on frame, 370µm ZSSC3122AI1CN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on frame, 370µm ZSSC3122AA2*N ZSSC3122 TSSOP14 — Temperature range: -20°C to +125°C – Lead-free package Tube: substitute “T” for * in code Reel: substitute “R” for * in code ZSSC3122AI2*N ZSSC3122 TSSOP14 — Temperature range: -20°C to +85°C – Lead-free package Tube: substitute “T” for * in code Reel: substitute “R” for * in code ZSSC3122KIT ZSSC3122 SSC Evaluation Kit: Communication Board, SSC Board, Sensor Replacement Kit Board, USB Cable, 5 IC Samples (software can be downloaded from www.zmdi.com/zssc3122) Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.306 Fax +49.351.8822.337 USA Phone 1.855.275.9634 Phone +1.408.883.6310 Fax +1.408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.62 — August 28, 2014 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Contents 1 IC Characteristics .......................................................................................................................... 8 1.1 1.2 Absolute Maximum Ratings ..................................................................................................... 8 Operating Conditions............................................................................................................... 8 1.3 Electrical Parameters .............................................................................................................. 9 1.4 Current Consumption Graphs ................................................................................................ 12 1.4.1 1.4.2 1.5 1.6 2 Output Pad Drive Strength .................................................................................................... 13 Temperature Sensor Nonlinearity .......................................................................................... 14 Circuit Description ....................................................................................................................... 14 2.1 2.2 Signal Flow and Block Diagram ............................................................................................. 14 Analog Front End .................................................................................................................. 15 2.2.1 Capacitance-to-Digital Converter ..................................................................................... 15 2.2.2 Temperature Measurement ............................................................................................. 20 2.3 3 Update Mode Current Consumption ................................................................................ 12 Sleep Mode Current Consumption ................................................................................... 12 Digital Core ........................................................................................................................... 21 Normal Operation Mode .............................................................................................................. 21 3.1 Power-On Sequence ............................................................................................................. 23 3.2 Measurement Cycle .............................................................................................................. 23 3.3 Measurement Modes ............................................................................................................. 24 3.3.1 Update Mode ................................................................................................................... 25 3.3.2 Sleep Mode ..................................................................................................................... 27 3.4 Status and Diagnostics .......................................................................................................... 29 3.4.1 3.4.2 3.5 3.6 EEPROM Error Detection and Correction ........................................................................ 30 Alarm Diagnostics............................................................................................................ 31 Output Modes........................................................................................................................ 31 I2C™ and SPI ........................................................................................................................ 31 3.6.1 3.6.2 I2C™ Features and Timing .............................................................................................. 32 SPI Features and Timing ................................................................................................. 33 3.6.3 I2C™ and SPI Commands ............................................................................................... 34 3.6.4 Data Fetch (DF) ............................................................................................................... 34 Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 4 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.6.5 Measurement Request (MR)............................................................................................ 36 3.6.6 Ready Pin ........................................................................................................................ 37 3.7 3.8 4 5 6 7 PDM (Pulse Density Modulation) ........................................................................................... 37 Alarm Output ......................................................................................................................... 39 3.8.1 Alarm Registers ............................................................................................................... 39 3.8.2 Alarm Operation .............................................................................................................. 39 3.8.3 Alarm Output Configuration ............................................................................................. 41 3.8.4 Alarm Polarity .................................................................................................................. 41 Command Mode .......................................................................................................................... 42 4.1 4.2 Command Format ................................................................................................................. 42 Command Encodings ............................................................................................................ 42 4.3 Command Response and Data Fetch.................................................................................... 43 EEPROM .................................................................................................................................... 46 5.1.1 ZMDI Configuration Register (ZMDI_Config, EEPROM Word 02HEX) ............................... 48 5.1.2 Capacitance Analog Front End Configuration (C_Config, EEPROM Word 06HEX) ............ 49 5.1.3 Temperature Analog Front End Configuration (T_Config, EEPROM Word 11HEX) ............ 50 5.1.4 Customer Configuration Register (Cust_Config, EEPROM Word 1CHEX) ......................... 51 Calibration and Signal Conditioning Math .................................................................................... 52 6.1 6.2 Capacitance Signal Conditioning ........................................................................................... 52 Temperature Signal Compensation ....................................................................................... 54 6.3 Limits on Coefficient Ranges ................................................................................................. 54 Application Circuit Examples ....................................................................................................... 55 7.1 Digital Output with Optional Alarms ....................................................................................... 55 7.2 Analog Output with Optional Alarms ...................................................................................... 56 7.3 Bang-Bang Control System..................................................................................................... 57 7.4 Differential Input Capacitance ............................................................................................... 58 7.5 External Reference Capacitor................................................................................................ 59 8 ESD/Latch-Up-Protection ............................................................................................................ 59 9 Pin Configuration and Package ................................................................................................... 60 10 Test ............................................................................................................................................. 62 11 Reliability ..................................................................................................................................... 62 12 Customization ............................................................................................................................. 62 Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 13 Part Ordering Codes ................................................................................................................... 62 14 Related Documents ..................................................................................................................... 63 15 Glossary ...................................................................................................................................... 63 16 Document Revision History ......................................................................................................... 64 List of Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Figure 1.7 Figure 2.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 4.1 Figure 4.2 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 9.1 Data Sheet August 28, 2015 Best Case Settings (Typical Part) ..................................................................................................... 12 Worst Case Settings (Typical Part) .................................................................................................. 12 Typical Current Consumption during Sleep Mode (No Measurements) ........................................... 12 Output High Drive Strength Graph ................................................................................................... 13 Output Low Drive Strength Graph .................................................................................................... 13 First Order Fit (Typical Part) ............................................................................................................. 14 Second Order Fit (Typical Part) ........................................................................................................ 14 ZSSC3122 Block Diagram ................................................................................................................ 15 General Operation ............................................................................................................................ 22 Power-On Sequence with Fast Startup Bit Set in EEPROM ............................................................ 23 Measurement Cycle Timing ............................................................................................................. 24 Measurement Sequence in Update Mode ........................................................................................ 25 2 I C™ and SPI Data Fetching in Update Mode ................................................................................. 27 2 Measurement Sequence in Sleep Mode (Only I C™, SPI, or Alarms) ............................................. 28 2 I C™ and SPI Data Fetching in Sleep Mode .................................................................................... 29 2 I C™ Timing Diagram ...................................................................................................................... 32 SPI Timing Diagram .......................................................................................................................... 33 2 I C™ Measurement Packet Reads ................................................................................................... 35 SPI Output Packet with Positive Edge Sampling.............................................................................. 36 2 I C MR............................................................................................................................................... 36 SPI MR .............................................................................................................................................. 37 Example of Alarm Function............................................................................................................... 40 Alarm Output Flow Chart .................................................................................................................. 40 2 I C™ Command Format ................................................................................................................... 42 Command Mode Data Fetch ............................................................................................................. 45 Digital Output with Optional Alarms Example ................................................................................... 55 Analog Output with Optional Alarms Example .................................................................................. 56 Bang-Bang Control System Example ............................................................................................... 57 Differential Input Capacitance Example ........................................................................................... 58 Ext. Reference Input Capacitance Example ..................................................................................... 59 ZSSC3122 Pin-Out Diagram ............................................................................................................ 60 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 6 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner List of Tables Table 2.1 Table 3.1 Table 3.2 Table 3.3 Table 3.4 Table 3.5 Table 3.6 Table 3.7 Table 3.8 Table 3.9 Table 3.10 Table 3.11 Table 3.12 Table 4.1 Table 4.2 Table 4.3 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 6.1 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 9.1 Table 9.2 Data Sheet August 28, 2015 Selection Settings for CREF, and COFF (Capacitance ranges are nominal values) ............................ 19 CDC Resolution and Conversion Times ........................................................................................... 24 Update Rate Settings ....................................................................................................................... 25 Time Periods between Capacitance Measurements and Temperature Measurements for Different Resolution and Update Rates ........................................................................................................... 26 Status Table ...................................................................................................................................... 30 Diagnostic Detection ......................................................................................................................... 30 Normal Operation Diagnostic Table ................................................................................................. 30 Output Modes ................................................................................................................................... 31 Pin Assignment for Output Selections .............................................................................................. 31 2 I C™ Parameters .............................................................................................................................. 32 SPI Parameters................................................................................................................................. 33 2 I C™ and SPI Command Types ....................................................................................................... 34 Low Pass Filter Example for R = 10k............................................................................................. 38 Command List and Encodings .......................................................................................................... 43 Response Bits ................................................................................................................................... 44 Command Diagnostic Bits ................................................................................................................ 44 EEPROM Word Assignments ........................................................................................................... 46 ZMDI_Config Bit Assignments .......................................................................................................... 48 C_Config Bit Assignments ................................................................................................................ 49 T_Config Bit Assignments ................................................................................................................ 50 Cust_Config Bit Assignments ........................................................................................................... 51 Limits on Coefficient Ranges ............................................................................................................ 54 Example 1: Configuration Settings ................................................................................................... 55 Example 2: Configuration Settings ................................................................................................... 56 Example 3: Configuration Settings ................................................................................................... 57 Example 4: Configuration Settings ................................................................................................... 58 Example 5: Configuration Settings ................................................................................................... 59 Storage and Soldering Conditions .................................................................................................... 60 ZSSC3122 Pin Assignments for TSSOP-14 ..................................................................................... 60 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 7 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 1 IC Characteristics 1.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN Analog Supply Voltage VDD Voltages at Analog I/O – In Pin MAX UNITS -0.3 6.0 V VINA -0.3 VDD+0.3 V Voltages at Analog I/O – Out Pin VOUTA -0.3 VDD+0.3 V Storage Temperature Range TSTOR -55 150 °C SYMBOL MIN VSUPPLY 1.8 5.5 V TAMB -20 125 C IOUT 1.5 20 mA CVSUPPLY 100 External Capacitance between Vcore and Gnd—Sleep Mode CVCORE_SM 10 110 nF External Capacitance between Vcore and Gnd—Update Mode CVCORE_UM 90 330 nF Input Capacitance Span (Full Scale Values) C0 2 10 pF External Reference Capacitance C1 2 10 pF External Isolating Capacitance ) (CC pin to sensor common node) 3 CCC 1.2 TYP Operating Conditions See important footnotes at the end of the following table. PARAMETER Supply Voltage to Gnd ) Ambient Temperature Range 1 Output Pads/Pins Drive Strength 2 ) External Capacitance between VDD pin and Gnd 2 I C™ Pull-Up Resistor 3 ) SDA/MISO Load Capacitance 1 2 3 RPU TYP 220 MAX 470 16 1 2.2 CSDA UNITS nF pF k 200 pF Caution: If buying die, select the proper package to ensure that the maximum junction temperature is not exceeded. See section 1.5 for full details on output pad drive strengths. An external isolating capacitor allows a non-galvanic connection to special differential or external reference sensor types. Ccc could also be used to lower the overall capacitance level to a value that is supported by the ZSSC3122 because it limits the maximum capacitance seen by the ZSSC3122 input to CC even if C0 and C1 have higher values. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 8 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 1.3 Electrical Parameters See important footnotes at the end of the following table. PARAMETER SYMBOL CONDITIONS MIN TYP MAX Best case settings: 8-bit, 125ms Power Down 60 100 Worst case settings: 14-bit, 0ms Power Down 750 1100 UNITS SUPPLY CURRENT * Update Mode Current (varies with 1 part configuration) Extra Current with PDM enabled * Sleep Mode Current 1 IDD μA IPDM μA 150 ISLEEP -20 to 85°C 0.6 1 μA -20 to 125°C 1 3 μA 1.6 1.7 1.75 V 2.4 2.55 2.7 V 14 Bits Voltage Levels Power-On-Reset Level VPOR Active Regulated Voltage VREG Note: Regulated voltage can be measured on the Vcore pin. CAPACITANCE-TO-DIGITAL CONVERTER (CDC) RESCDC Resolution Excitation Frequency of External Capacitances C0 and C1 (for a system frequency fSYS) Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) * 8 fEXC fSYS/2 kHz INLCDC 10% to 90% input, 14-bit 0.2 % DNLCDC 10% to 90% input, 14-bit 0.9 LSB EEPROM Number of Erase/Write Cycles nWRI_EEP @85C 100k Data Retention tWRI_EEP @100C 10 Year TEMPERATURE CONVERSION Resolution in °C * RESTEMP ,3 Nonlinearity First Order Fit * ,4 Nonlinearity Second Order Fit * Data Sheet August 28, 2015 -20 to 125°C, 8-bit mode 0.64 0.96 1.6 -20 to 125°C, 14-bit mode 0.01 0.015 0.025 °C INLCDC -20 to 125°C ±0.5 ±1 °C INLCDC -20 to 125°C ±0.2 ±0.4 °C © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 9 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner PARAMETER SYMBOL PSRTEMP Voltage Dependency * CONDITIONS MIN TYP MAX VSUPPLY > VREG+0.25V 0.03 0.1 1.8V ≤ VSUPPLY ≤ VREG + 0.25V 1.25 2.25 UNITS °C/V PDM Output Output Range * VPDM_Range PDM Frequency fPDM Filter Settling Time * Ripple * 10 ,5 ,5 PDM Additional Error (Including * Ratiometricity Error) 90 fSYS/8 %VSUPPLY kHz tSETT 0% to 90% LPFilter 10k/400nF 9.2 ms VRIPP 0% to 90% LPFilter 10k/400nF 1.0 mV/V EPDM -20 to 125C 0.1 0.5 % 0 0.2 VSUPPLY DIGITAL I/O Voltage Output Level Low VOL Voltage Output Level High VOH Voltage Input Level Low VIL Voltage Input Level High VIH Communication Pin Input Capacitance * CIN 0.8 0 0.8 VSUPPLY 1 0.2 1 VSUPPLY VSUPPLY 10 pF ±10 % 2.25 MHz ±10 % TOTAL SYSTEM Capacitive Tolerance Between Parts * Ctol All capacitive values in the specification are subject to this variation Trimmed System Frequency fSYS All timing in this specification is subject to this variation. Frequency Variation Over Voltage and Temperature fvar All timing in this specification is subject to this variation. tSTA Fastest and slowest settings 4.25 55 ms tRESP_UP Fastest and slowest settings 0.70 165 ms tRESP_SL Fastest and slowest settings 1.25 45 ms , 6, 7 Start-Up-Time * Power-on (POR) to data ready Update Rate (Update Mode) * , 6, 7 Response Time (Sleep Mode) * Data Sheet August 28, 2015 , 6, 7 1.76 1.85 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 10 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner PARAMETER Parasitic to Gnd Tolerance Including package parasitics , (Pins C0, CC, and C1) * Peak-to-Peak Noise @ output (100 measurements in 14 bit) * SYMBOL CONDITIONS MAX UNITS 10 pF 5 20 LSB 3V10%, 3.3V10%, 5V10% ±0.25 ±0.75 2.5V10% ±0.50 ±1.25 NOUT MIN TYP Accuracy , 8, 9,10 Error, -20 to 125°C * AEout 2.0V10% %FSO ±2.5 * Parameter not tested during production but guaranteed by design. 1 See section 1.4 for full details for current consumption in each mode. 2 Parameter measured using internal test capacitors (0pF to 7pF in Mult 1). 3 Assumes optimal calibration points of 0°C and 100°C; see section 1.6 for more details. 4 Assumes optimal calibration points of -20°C, 40°C and 100°C; see section 1.6 for more details. 5 See section 3.7 for more details. 6 See section 3 for more details. 7 Timing values are for a nominal oscillator, for worst case, ±10% total frequency variation, multiply by 0.9 (min time) or 1.1 (max time). 8 Accuracy specification includes a 2-point temperature calibration for correcting the internal TC. 9 Accuracy specification assumes maximum parasitics of 10pF to ground. 10 Accuracy specification does not include PDM errors, see the PDM Output electrical parameters for additional errors when using PDM. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 11 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 1.4 Current Consumption Graphs Part current consumption depends on a number of different factors including voltage, temperature, capacitive input, resolution, and power down time. The best way to calculate the ZSSC3122’s power consumption is to measure the current consumption with the actual setup. If measurement is not possible, then the graphs in this section can provide a starting point for estimating the current consumption. 1.4.1 Update Mode Current Consumption Figure 1.1 Best Case Settings (Typical Part) * Parameter not within required temperature specifications (-40°C) 1.4.2 Figure 1.2 Worst Case Settings (Typical Part) * Parameter not within required temperature specifications (-40°C) Sleep Mode Current Consumption Figure 1.3 Typical Current Consumption during Sleep Mode (No Measurements) * Parameter not within required temperature specifications (-40°C) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 12 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 1.5 Output Pad Drive Strength Output High Drive Strength Graph 20mA Max. Allowed , Figure 1.4 20 Output High Drive Strength (mA) Cold / Best Case Typical Hot / Worst Case 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 4.3 4.8 5.3 Vsupply (V) Output Low Drive Strength Graph 20mA Max. Allowed , Figure 1.5 20 Output Low Drive Strength (mA) Cold / Best Case Typical Hot / Worst Case 0 1.8 2.3 2.8 3.3 3.8 Vsupply (V) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 13 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 1.6 Temperature Sensor Nonlinearity Temperature sensor nonlinearity can vary depending on the type of calibration and the selected calibration points. It is highly recommended that a temperature calibration is done with calibration points at least 20°C apart from each other. Figure 1.6 and Figure 1.7 show the resulting nonlinearity error for the full temperature range (-20°C to 125°C) using the optimal calibration points, 0°C and 100°C for a first-order fit and -20°C, 40°C, and 100°C for a second-order fit. Figure 1.6 First Order Fit (Typical Part) Figure 1.7 Second Order Fit (Typical Part) Temperature Error 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.0 -50 -0.1 0 50 100 150 2.5V 3V 5V Error (°C) Error (°C) Temperature Error 0.1 0.0 -50 -0.1 0 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 50 100 150 -0.5 Temperature (°C) Temperature (°C) 2 Circuit Description 2.1 Signal Flow and Block Diagram As seen in Figure 2.1, the ZSSC3122 comprises three main blocks: the analog core, digital core, and output communication. The capacitive input is first sampled by the analog core using a charge-balancing CDC and is adjusted for the appropriate capacitance range using the CDC_Offset, and CDC_Reference. The digital core corrects the digital sample with an on-chip digital signal processor (DSP), which uses coefficients stored in EEPROM for precise conditioning. An internal temperature sensor can be used to compensate for temperature effects of the capacitive input. A temperature value can also be calibrated and output as a 14-bit reading. 2 The corrected capacitance value can be read using four different output types, I C™, SPI, PDM, and alarms. They can all be directly interfaced with a microcontroller, and optional filtering of the PDM output can provide a ratiometric analog output. The alarm pins can also be used to control a variety of analog circuitry. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 14 of 65 2.5V 3V 5V ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 2.1 ZSSC3122 Block Diagram ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner VDD (1.8V to 5.5V) Vcore Temp Sensor Ref Cap Offset Cap 0.1µF EEPROM CLK/Reset Ready PDM 0.1µF Sensor C/A C0 C0 CC C1 C1 (Optional) D 2.2.1 Low Alarm High Alarm MUX SDA/MISO Ready/PDM_C Alarm_Low/PDM_T DSP CDC VSS 2.2 I2C / SPI SCL/SCLK SS Alarm_High ROM Analog Core Digital Core Output Communication Analog Front End Capacitance-to-Digital Converter st A 1 order charge-balancing capacitance-to-digital converter (CDC) is used to convert the input capacitance to the digital domain. The CDC uses a chopper-stabilized design to decrease any drift over temperature. The CDC interfaces to the sensor capacitor through the input multiplexer that controls whether the measurement is a capacitance or a temperature measurement. The input multiplexer also allows for two sensor capacitance configurations: a single sensor capacitance or a ratio based differential capacitive sensor, two-sensor, capacitor configuration, where the reference capacitor is part of the sensor. As part of a switched-capacitor network the reference capacitor C1 is driven by a square wave voltage of the frequency fEXC (refer to section 1.3). The sensor capacitance C 0 is not exposed to DC voltages in order to prevent aging effects of some sensor types. The configuration of the CDC is controlled by programming settings in EEPROM word C_Config. (See Table 5.3 for settings.) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 15 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.2.1.1. Single Ended In the case of a single-sensor capacitor, the CDC output is proportional to the ratio of the sensor capacitor to an internal reference capacitor (CREF). This internal reference capacitor value can be adjusted using the 3-bit trim CDC_Reference (bit settings in Table 5.3). To optimize the measured end-resolution further, another internal capacitor (COFF) allows the subtraction of a defined offset capacitance using the 3-bit trim CDC_Offset (bit setting in Table 5.3). Equations (1) to (2) describe the CDC output for a single sensor capacitance measurement. Select the values of CDC_Offset and CDC_Reference by using the tables in section 2.2.1.4. Z SENSOR (C0 COFF ) CREF (1) Z CDC 2 RES Z SENSOR (2) C OFF 1.44 CDC _ Offset 1 pF (3) C REF 1.44 CDC _ Reference 1 pF (4) With And Where: Symbol Description ZSENSOR Measured sensor ratio, must be in the range [0 to 1] C0 Input sensor capacitance COFF Zero shift of CDC CREF Reference capacitance ZCDC Digital raw converted capacitance value RES Programmable CDC resolution of 8, 10, 12, or 14 bits (bit setting in Table 5.3) CDC_Offset CDC offset trim setting (selection see section 2.2.1.4 and bit setting see Table 5.3) CDC_Reference CDC reference setting (selection see section 2.2.1.4 and bit setting see Table 5.3) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 16 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.2.1.2. Single Ended with External Reference Some sensors include an external reference capacitor as part of the sensor construction. If the external reference capacitance (C1) is constant or increases with increasing input sensor capacitance (C0), then use CDC output equations (5) to (7). In this case the CDC_Reference should be set to zero (bit setting in Table 5.3). (C0 COFF ) C1 (5) Z CDC 2 RES Z SENSOR (6) COFF 1.44 CDC _ Offset 1 pF (7) Z SENSOR Where Symbol Description ZSENSOR Measured sensor ratio, must be in the range [0 to 1] C0 Input sensor capacitance COFF Zero shift of CDC C1 External reference capacitance ZCDC Digital raw converted capacitance value RES Programmable CDC resolution of 8, 10, 12, or 14 bits (bit setting in Table 5.3) CDC_Offset CDC offset trim setting (selection see section 2.2.1.4 and bit setting see Table 5.3) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 17 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.2.1.3. Differential A differential capacitive sensor includes two capacitors C0 and C1 that are captured as a ratio. The differential sensor is built so that the sensor input capacitance C 0 increases while the external reference capacitance C1 decreases over the input signal range, but the total sum always remains constant. Equations describe the CDC output for a differential sensor capacitance measurement. The CDC_Reference and CDC_Offset capacitor trim bits need to be set to zero, and the Differential bit needs to be set to one. (See Table 5.3 for bit numbers and settings). The sum of C0 and C1 must not be bigger than the maximum input range of 10pF, except when CC is used as a decoupling capacitor. In differential mode special sensor types can allow a non-galvanic connection with an external isolating capacitor CCC between the sensor and the CC pin to avoid wear caused by mechanical moving parts. Z SENSOR C0 C0 C1 (8) ZCDC 2RES Z SENSOR (9) Where Symbol Description ZSENSOR Measured sensor ratio, must be in the range [0 to 1] C0 Input sensor capacitance (moves in the opposite direction of C1) C1 External reference capacitance (moves in the opposite direction of C0) ZCDC Digital raw converted capacitance value RES Programmable CDC resolution of 8, 10, 12, or 14 bits (bit setting in Table 5.3) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 18 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.2.1.4. Capacitive Range Selection For singled ended sensors use Table 2.1 as guidance to select appropriate values for the CDC (COFF) and (CREF) for a particular capacitance input range. The CDC_Offset and CDC_Reference bits are found in EEPROM word C_Config. (See Table 5.3 for bit numbers). Using Table 2.1, the CDC input range can be adjusted to optimize the coverage of the sensor signal and offset values to give the maximum sensor span that can be processed without losing resolution. Choose a range by fitting the input sensor span within the narrowest range in the table, but note that these tables are only approximate, so the range should be experimentally chosen with the actual setup. Also note that since internal capacitance values can vary over process (see spec parameter Ctol in section 1.3), the minimum and maximum sensor span should be at least ±10% within the min and max of the chosen range respectively. Note: A CREF setting of 0 (marked with * in the following tables) is only supported with an external reference capacitor (C1) for single-ended sensors. C1 capacitance values should be within the defined range. Table 2.1 3-bit set 0 1 2 3 4 5 6 7 CDC_Offset ‡ Selection Settings for CREF, and COFF (Capacitance ranges are nominal values ) 0* 1 CDC_Reference 3 4 2 5 0.0 C1 0.0 1.4 0.0 2.9 0.0 4.3 0.0 5.8 0.0 1.4 C1 1.4 2.9 1.4 4.3 1.4 5.8 1.4 7.2 2.9 C1 2.9 4.3 2.9 5.8 2.9 7.2 2.9 8.6 4.3 C1 4.3 5.8 4.3 7.2 4.3 8.6 4.3 5.8 C1 5.8 7.2 5.8 8.6 5.8 10.1 5.8 7.2 C1 7.2 8.6 7.2 10.1 7.2 11.5 8.6 C1 8.6 10.1 8.6 11.5 8.6 13.0 10.1 C1 10.1 11.5 10.1 13.0 10.1 14.4 6 7 7.2 0.0 8.6 0.0 10.1 1.4 8.6 1.4 10.1 1.4 11.5 2.9 10.1 2.9 11.5 2.9 13.0 10.1 4.3 11.5 4.3 13.0 4.3 14.4 11.5 5.8 13.0 5.8 14.4 5.8 15.8 PROHIBITED not recommended ‡ Production-related tolerances can change the nominal capacitance values by 10%. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 19 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.2.2 Temperature Measurement The temperature signal comes from an internal PTAT (proportional to absolute temperature) circuit that is a measure of the die temperature. The PTAT (VPTAT) voltage is used in the CDC to charge an internal capacitor (CT), while the bandgap voltage (VBG) is used to charge the offset and the reference trimmable capacitors. The CDC temperature output (ZTEMP) is defined by equations (10) to (13): Z TEMP 2 RES (VPTAT / VBG ) CT CTOFF CTREF (10) With CT 1.44 Temp _ Trim 1 pF (11) With CTOFF 1.44 CDC _ Offset 1 pF (12) CTREF 1.44 CDC _ Reference 1 pF (13) And Where Symbol Description ZTEMP Measured internal temperature RES Programmable CDC resolution of 8, 10, 12, or 14 bits (bit setting in Table 5.4) VPTAT Internal PTAT voltage VBG Internal bandgap voltage CT Temperature measurement capacitor CTOFF Temperature CDC zero shift CTREF Temperature reference capacitance Temp_Trim Temperature trim setting (bit setting in Table 5.4) CDC_Offset CDC offset trim setting (bit setting in Table 5.4) CDC_Reference CDC reference setting (bit setting in Table 5.4) Note: The factory settings for Temp_Trim, CDC_Offset, and CDC_Reference are optimized for the full temperature range of -20°C to 125°C guaranteeing a minimum effective resolution of 13 bits when 14 bits of resolution is selected. Unless a different temperature range is needed, it is strongly recommended that these settings not be changed. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 20 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2.3 Digital Core The digital core provides control logic for the analog front-end, performs input signal conditioning, and handles external communication. A digital signal processor (DSP) is used for conditioning and correcting the converted sensor and temperature inputs. The DSP can correct for up to a two-region piece-wise non-linear sensor input, and up to a second order non-linear temperature input. Alternatively a third-order correction of the sensor input for one region and up to a second-order non-linear temperature input can be selected. Refer to section 6 for details on the signal conditioning and correction math. The analog front-end configuration and correction coefficients for both the capacitive sensor and the temperature sensor are stored in an on-chip EEPROM (see section 5). 2 Four different types of outputs are available: I C™, SPI, PDM, and the Alarms. These output modes are used in combination with the two measurement modes: Update Mode and Sleep Mode. For a full description of normal operation in each mode, refer to section 3. The ZSSC3122 has an internal 1.85 MHz temperature-compensated oscillator that provides the time base for all operations. When VDD exceeds the POR level, the reset signal de-asserts and the clock generator starts. See section 3.1 for the subsequent power-up sequence. The exact clock frequency influences the measurement cycle time (see the frequency variation spec in section 1.3). To minimize the oscillator error as the VDD voltage changes, an on-chip regulator supplies the oscillator block. 3 Normal Operation Mode Figure 3.1 gives a general overview of ZSSC3122 operation. Details of operation, including the power-up sequence, measurement modes, output modes, diagnostics, and commands, are given in the subsequent sections. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 21 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 3.1 General Operation Yes Start_CM Command = Start_CM? Power-On Reset No, after Command Window expires (3ms / 10ms) Normal Operation Mode Start_NOM Perform initial measurement. UPDATE MODE SLEEP MODE (I2C™, SPI, PDM, or Alarms) (I2C™, SPI, or Alarms) Update Digital Output Register, PDMs, & Alarms Update Digital Output Register & Alarms Command = I2C DF or SPI DF? Update Period Over Update Rate Period Over or Command Received? Yes Fetch Data Data Sheet August 28, 2015 No Execute Command No Fetch Data Power Down (Wait for command.) No Command Received Command = I2C MR or SPI MR? Yes Perform Measurement Command Received. Command = Start_NOM? Yes Command Received (I2C/SPI only) Command = I2C DF or SPI DF? Yes Power Down (Wait for command) Command Received Power Down Command Mode (No measurement cycle. Full command set is available.) No MR Measurement Request DF Data Fetch Perform Measurement © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 22 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.1 Power-On Sequence Figure 3.2 shows the power-on sequence of the ZSSC3122. On system power-on reset (POR), the ZSSC3122 2 wakes as an I C™ device regardless of the output protocol programmed in EEPROM. After power-on reset, the ZSSC3122 enters the command window. It then waits for a Start_CM command for 3ms if the Fast_Startup EEPROM bit is set or 10ms otherwise (see Table 5.5). If the ZSSC3122 receives the Start_CM command during the command window, it enters and remains in Command Mode. Command Mode is primarily used in the calibration environment. See section 4 for details on Command Mode. If during the power-on sequence, the command window expires without receiving a Start_CM or if the part receives a Start_NOM command in Command Mode, the device will immediately assume its programmed output mode and will perform one complete measurement cycle. Timing for the initial measurement is described in section 3.2. At the end of the capacitance DSP calculation, the first data is written to the output register. Beyond this point, conversions are performed according to the programmed measurement mode settings (see section 3.3). Figure 3.2 Power-On Sequence with Fast Startup Bit Set in EEPROM POR Measurement Cycle Command Window Temperature Conversion (Temp Conv) Temp DSP Calculation (Temp Calc) Capacitance Conversion (Cap Conv) Cap DSP Calculation (Cap Calc) 3ms Power applied to device. Command window starts after a short power-on-reset window. When the Fast Startup bit is not set in EEPROM, the command window is 10ms. 1st corrected signal measurement written to output register (I2C™, SPI, PDMs, Alarms) Note: See section 3.2 for timing of the measurement cycle. Timing values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). 3.2 Measurement Cycle Figure 3.3 shows a typical measurement cycle. At the start of a measurement, there is a small wakeup period and then an internal temperature conversion/temperature DSP calculation is performed followed by a capacitance conversion/capacitance DSP calculation. The length of these conversions depends on the setting of the Resolution bits (see Table 3.1). The resolution can be found in EEPROM words C_Config and T_Config (see Table 5.3 and Table 5.4 for bit numbers). Each conversion cycle is followed by a DSP calculation, which uses the programmed calibration coefficients to calculate corrected temperature and capacitance measurements. In Update Mode, a temperature conversion is not performed every measurement cycle because it is considered a slower moving quantity. In this case, the measurement cycle timing is the same as Figure 3.3 without the temperature conversion/ temperature DSP calculation (see section 3.3.1 for more information). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 23 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 3.3 Measurement Cycle Timing § Legend: Timing for 8-bit resolution Timing for 10-bit resolution 0.30ms Timing for 12-bit resolution 1.15ms Timing for 14-bit resolution WAKEUP 4.5ms 18.0ms 0.25ms Temperature Conversion (Temp Conv) Temperature DSP Calculation (Temp Calc) 0.30ms Capacitance Conversion (Cap Conv) Capacitance DSP Calculation (Cap Calc) 0.30ms Corrected signal measurement 2 written to output register (I C™, SPI, PDM, or Alarms) 1.15ms 0.10ms 4.50ms 18.0ms Table 3.1 3.3 CDC Resolution and Conversion Times EEPROM Encoding CDC Resolution (Bits) Temperature Conversion Time (ms) § Capacitance Conversion Time (ms) § 00BIN 8 0.30 0.30 01BIN 10 1.15 1.15 10BIN 12 4.50 4.50 11BIN 14 18.0 18.0 Measurement Modes The ZSSC3122 can be programmed to operate in either Sleep Mode or Update Mode. The measurement mode is selected with the Measurement_Mode bit in the ZMDI_Config EEPROM word (see Table 5.2). In Update Mode, measurements are taken at a fixed, selectable rate (see section 3.3.1). In Sleep Mode, the part waits for commands from the master before taking measurements (see section 3.3.2). Figure 3.1 shows the differences in operation between the two measurement modes. § All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 24 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.3.1 Update Mode In Update Mode, the digital core will perform conversions at an update rate selected with the Update_Rate bits in the ZMDI_Config EEPROM word (see Table 5.2). Table 3.2 shows the power-down periods between conversions for the four Update_Rate settings. The benefit of slower update rates is power savings. Update Mode is compat2 ible with all the different output modes; I C™, SPI, PDMs, and the Alarms. As shown in Figure 3.4, at the completion of a measurement cycle, the digital output register, PDMs, and/or Alarms will be updated before powering down. When the power-down period expires, the ZSSC3122 will wake up and perform another measurement cycle. If the part is programmed for the fastest update rate, there is no power down period, and measurements happen continuously. Update Rate Settings Update_Rate Power Down Period (ms) 00BIN 0 01BIN 5 10BIN 25 11BIN 125 Figure 3.4 ** Measurement Sequence in Update Mode Power down period depends on selected update rate Cap Calc Power Down Cap Conv Write new corrected signal measurement to output register (I2C™, SPI, PDMs, Alarms) Cap Calc Power Down Write new corrected signal measurement to output register (I2C™, SPI, PDMs, Alarms) WAKEUP Cap Conv WAKEUP ZSSC3122 Core Activity Temp Conv Temp Calc Cap Conv Temperature is measured after every sixth capacitive measurement Cap Calc Power Down WAKEUP Table 3.2 Write new corrected signal measurement to output register (I2C™, SPI, PDMs, Alarms) Note: See section 3.2 for measurement cycle timing. To calculate the total time between capacitive measurements in Update Mode, add the measurement cycle timing from section 3.2 and the power down timing from Table 3.2. Typical settings might be a capacitance measurement with a resolution of 12-bits. In this example, the time between measurements = (4.5ms+ 0.1ms+ 0.3ms) + (power down period). Table 3.3 shows the time between measurements for the different update rate settings and bit resolutions. ** All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 25 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Temperature measurements are performed every six capacitive measurements. The actual frequency of temperature conversions varies with the update rate and AFE configuration settings. As shown in Figure 3.4 when a temperature measurement is performed, a capacitance measurement occurs immediately after, so the total measurement cycle time is increased by the length of the temperature conversion/temperature DSP calculation. To calculate the total time between temperature measurements in Update Mode, multiply the time between capacitive measurements as calculated in the above text by six (there are six capacitive measurements to every temperature measurement) and then add the temperature conversion time/temperature DSP calculation time from Table 3.1 For example a temperature measurement with a resolution of 12-bits has a conversion time/DSP calculation time of 4.5ms +0.25ms (from Table 3.1). Continuing with the above example (12-bit capacitive measurement), the time between temperature measurements is (capacitance update time * 6) + 4.75ms. Table 3.3 Time Periods between Capacitance Measurements and Temperature Measurements for Different Resolution and Update Rates Total Time between Capacitance Measurements (ms) Total Time between Temperature Measurements (ms) CDC Resolution (Bits) Update Rate 00BIN Update Rate 01BIN Update Rate 10BIN Update Rate 11BIN Update Rate 00BIN Update Rate 01BIN Update Rate 10BIN Update Rate 11BIN 8 0.70 5.70 25.70 125.70 4.75 34.75 154.75 754.75 10 1.55 6.55 26.55 126.55 10.70 40.70 160.70 760.70 12 4.90 9.90 29.90 129.90 34.15 64.15 184.15 784.15 14 18.40 23.40 43.40 143.40 128.65 158.65 278.65 878.65 3.3.1.1. Data Fetch in Update Mode 2 In Update Mode, I C™ and SPI are used to fetch data from the digital output register using a Data Fetch (DF) command (see section 3.6.3). Detecting when data is ready to be fetched can be handled either by polling or by monitoring the Ready pin (see section 3.6.6 for details on the Ready pin). The status bits of a DF tell whether or not the data is valid or stale (see section 3.4 regarding the status bits). As shown in Figure 3.5 after a measurement cycle is complete, valid data can be fetched. If the next data fetch is performed too early, the data will be the same as the previous fetch with stale status bits. As shown in Figure 3.5, a rise on the Ready pin can also be used to tell when valid data is ready to be fetched. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 26 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2 I C™ and SPI Data Fetching in Update Mode Power down period depends on selected update rate Cap Calc Power Down Cap Conv Cap Calc Write new corrected signal measurement to output register (I2C™ or SPI) I2C™/SPI Data Fetch Power Down WAKEUP Cap Conv WAKEUP ZSSC3122 Core Activity Temp Conv Temp Calc Cap Conv Write new corrected signal measurement to output register (I2C™ or SPI) I2C™/SPI Data Fetch I2C™/SPI Data Fetch Cap Calc Power Down WAKEUP Figure 3.5 Write new corrected signal measurement to output register (I2C™ or SPI) I2C™/SPI Data Fetch I2C™/SPI Data Fetch Serial Interface Activity Valid read occurs Stale values Valid read occurs Stale values Valid read occurs Ready Pin Note: See section 3.2 for timing of measurements. 3.3.2 Sleep Mode In Sleep Mode, the digital core will only perform conversions when the ZSSC3122 receives a Measurement Request command (MR); otherwise, the ZSSC3122 is always powered down. Measurement Request commands 2 can only be sent using I C™ or SPI, so PDM is not available. The Alarms can be used in Sleep Mode but only in 2 combination with I C™ or SPI. More details about MR commands in Sleep Mode operation can be found in section 3.3.2.1. Note: Sleep Mode power consumption is significantly lower than Update Mode power consumption (see section 1.3 for exact values). Figure 3.6 shows the measurement and communication sequence for Sleep Mode. The master sends an MR command to wake the ZSSC3122 from power down. After the ZSSC3122 wakes up, a measurement cycle is performed consisting of both a temperature and a capacitance conversion followed by the DSP correction calculations. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 27 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner At the end of a measurement cycle, the digital output register and Alarms will be updated before powering down. 2 An I C™ or SPI data fetch (DF) is performed during the power-down period to fetch the data from the output 2 register. In I C™ the user can send another MR to start a new measurement cycle without fetching the previous data, but in SPI, a DF must be done before another MR can be sent. After the data has been fetched, the ZSSC3122 remains powered down until the master sends an MR command. The timing for measurements can be found in section 3.2. Figure 3.6 2 Measurement Sequence in Sleep Mode (Only I C™, SPI, or Alarms) WAKEUP ZSSC3122 Core Activity Power Down Temp Conv Temp Calc Cap Conv Cap Calc Power Down Write new corrected signal measurement to output register (I2C™, SPI, Alarms) Command wakes ZSSC3122 Serial Interface Activity MR DF Valid read occurs Note: See section 3.2 for timing of measurements. 3.3.2.1. Data Fetch in Sleep Mode 2 In Sleep Mode, I C™ and SPI are used to request a measurement with a MR command and to fetch data from the digital output register using a Data Fetch (DF) command (see section 3.6.3). As shown in Figure 3.7, after a measurement cycle is complete, valid data can be fetched. The preferred method of detecting valid data is to wait for a rise on the Ready pin (see section 3.6.6 for details on the Ready pin). If the Ready pin is not available, the user must wait for the measurements to complete before performing the DF (see section 3.2 for measurement timing). The status bits of the DF can be used to tell whether the data is valid or stale (see section 3.4 regarding the status bits), but polling for the result must not be done before the time required for conversion has elapsed. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 28 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 3.7 2 I C™ and SPI Data Fetching in Sleep Mode WAKEUP ZSSC3122 Core Activity Power Down Temp Conv Temp Calc Cap Conv Cap Calc Power Down Write new corrected signal measurement to output register (I2C™ or SPI) Serial Interface Activity Command wakes ZSSC3122 MR DF Valid read occurs Ready Pin Note: See section 3.2 for timing of measurements. 3.4 Status and Diagnostics 2 Status bits (the two MSBs of the fetched high data byte, see Table 3.4) are provided in I C™ and SPI but not in PDM. The status bits are used to indicate the current state of the fetched data. Diagnostic detection is available in 2 2 I C™, SPI and PDM. In I C™ and SPI diagnostics are reported as a saturated high capacitance and temperature output (see Table 3.5). In PDM, diagnostics are reported as a railed high output level for both PDM_C (capacitive PDM) and PDM_T (temperature PDM). If a diagnostic value is reported then one or more of the errors shown in Table 3.6 occurred in normal operation. Configuration EEPROM diagnostics are detected at initial power-up of the ZSSC3122 or a wakeup in Sleep Mode and are permanent diagnostics. All other diagnostics are detected during a measurement cycle and reported in 2 the subsequent data fetch for I C™ or SPI or output register update for PDM. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 29 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Table 3.4 Status Table 2 Status Bits (I C™ or SPI) PDM Output 00BIN Clipped normal output 01BIN Not applicable Stale data: Data that has already been fetched since the last measurement cycle. Note: If a data fetch is performed before or during the first measurement after power-on reset, then Stale will be returned, but this data is actually invalid since the first measurement has not been completed. 10BIN Not applicable Command Mode: The ZSSC3122 is in Command Mode. 11BIN Not used Table 3.5 Valid data: Data that has not been fetched since the last measurement cycle. Not used Diagnostic Detection 2 I C™ or SPI Output Saturated output 3FFFHEX Table 3.6 Definition PDM Output High output (railed) level Definition A diagnostic has occurred in normal operation (see Table 3.6). Normal Operation Diagnostic Table Diagnostic Type Definition Configuration Error Permanent An EEPROM or RAM Parity Error occurred in the initial loading of the configuration registers. RAM Parity Error Transient A RAM Parity Error occurred during a microcontroller instruction in the last measurement cycle. EEPROM Error Transient A DED EEPROM error occurred in the last measurement cycle (see section 3.4.1). Math Warning Transient An internal math overflow has occurred in the last measurement cycle and the output might be invalid. 3.4.1 EEPROM Error Detection and Correction The contents of the EEPROM are protected via error checking and correction (ECC). Each of the 32 16-bit words contains 6 parity bits enabling single-bit error correction and double-bit error detection (SEC and DED) per word. In Command Mode both SEC and DED errors are reported in the response byte (see section 4.3). If the fetched EEPROM data has a DED error then the fetched data will be incorrect; however, if a SEC error was reported then the fetched data has been corrected, and it is the user’s choice to write the data back to attempt to correct the error. During Normal Operation Mode, a diagnostic will be flagged on any DED error, but an SEC error will be automatically corrected and not flagged as a diagnostic. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 30 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.4.2 Alarm Diagnostics The alarm outputs do not report diagnostics. If diagnostics are needed with alarm outputs, then either digital or PDM outputs must also be used. 3.5 Output Modes The ZSSC3122 has four different output modes as shown in Table 3.7. See the corresponding reference sections for specifics on each mode. Table 3.7 Output Modes Output Mode Reference Sections 2 IC Section 3.6 Read only SPI PDM Section 3.7 Alarms Section 3.8 As illustrated in the pin configuration in section 9, the output communication modes share pins. The Output_Selection bits in EEPROM word ZMDI_Config (see section 5.1.1) select which of these outputs will be enabled. Table 3.8 shows the pin configuration for the different output selections. Table 3.8 Pin Assignment for Output Selections Output Selection 2 I C™ (001BIN) SPI (011BIN) PDM_C (100BIN) PDM_C+T (110BIN) Pin 08 Alarm_ Low Alarm_Low Alarm_Low PDM_T Pin 09 Alarm_High Alarm_High Alarm_High Alarm_High Pin 10 Ready Ready PDM_C PDM_C Pin 12 SDA MISO SDA SDA Pin 13 SCL SCLK SCL SCL Pin 14 No input SS No input No Input 3.6 I2C™ and SPI 2 2 Two wire I C™ and three-wire read-only SPI are available for fetching data from the ZSSC3122. I C™ is used to 2 send calibration commands to ZSSC3122. To choose I C™ or SPI, set the corresponding Output_Selection Bits in EEPROM word ZMDI_Config. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 31 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner I2C™ Features and Timing 3.6.1 †† 2 The ZSSC3122 uses an I C-compatible communication protocol with support for 100kHz and 400kHz bit rates. 2 The ZSSC3122 I C™ slave address (00HEX to 7FHEX) is selected by the Device_ID bits in the Cust_Config EEPROM word (see Table 5.5 for bit assignments). The device will respond only to this address if the communication lock is set by programming 011BIN in the Comm_lock bits in the ZMDI_Config EEPROM word (see 2 Table 5.2 for bit assignments); otherwise, the device will respond to all I C™ addresses. The factory setting for 2 2 the I C™ slave address is 28HEX with Comm_lock set. See Figure 3.8 for the I C™ timing diagram and Table 3.9 for definitions of the parameters shown in the diagram. Figure 3.8 2 I C™ Timing Diagram SDA tSUDAT tLOW tBUS tHDSTA SCL tHDSTA Table 3.9 tHDDAT tHIGH tSUSTO 2 I C™ Parameters PARAMETER SYMBOL MIN fSCL 20 tHDSTA 0.1 s tLOW 0.6 s tHIGH 0.6 s Start condition setup time relative to SCL edge tSUSTA 0.1 s Data hold time on SDA relative to SCL edge tHDDAT 0 Data setup time on SDA relative to SCL edge tSUDAT 0.1 s Stop condition setup time on SCL tSUSTO 0.1 s tBUS 1 s SCL clock frequency 1 ) Start condition hold time relative to SCL edge Minimum SCL clock low width 2 ) Minimum SCL clock high width 2 ) Bus free time between stop condition and start condition 1 2 †† tSUSTA TYP MAX UNITS 400 kHz s 0.5 The minimum frequency of 20kHz applies to calibration/test only (required to meet Command Window timing). There is no minimum for NOM. Combined low and high widths must equal or exceed minimum SCL period. For details, refer to http://www.standardics.nxp.com/literature/books/i2c/pdf/i2c.bus.specification.pdf or other websites for this specification. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 32 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.6.2 SPI Features and Timing SPI is available only as half duplex (read-only from the ZSSC3122). SPI speeds of up to 800kHz can be supported. The SPI interface can be programmed to allow the master to sample MISO on the falling-edge or rising-edge of SCL via the SPI_Phase bit in EEPROM word Cust_Config (see Table 5.5 for bit assignments). See Figure 3.9 for the SPI timing diagram and Table 3.10 for definitions of the parameters shown in the timing diagram. Figure 3.9 SPI Timing Diagram tHDSS tHIGH SCLK tSUSS tLOW HiZ MISO HiZ tCLKD tCLKD SS tBUS Table 3.10 SPI Parameters PARAMETER SYMBOL MIN fSCL 50 tHDSS 2.5 s tLOW 0.6 s Minimum SCLK clock high width 1 tHIGH 0.6 s Clock edge to data transition tCLKD 0 Rise of SS relative to last clock edge tSUSS 0.1 s Bus free time between rise and fall of SS tBUS 2 s SCLK clock frequency SS drop to first clock edge ) Minimum SCLK clock low width 1 ) 1 TYP MAX UNITS 800 kHz 0.5 s Combined low and high widths must equal or exceed minimum SCLK period. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 33 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.6.3 I2C™ and SPI Commands As detailed in Table 3.11, there are three types of commands which allow the user to interface with the 2 ZSSC3122 in the I C™ or SPI modes. 2 Table 3.11 I C™ and SPI Command Types Type Data Fetch (DF) Measurement Request (MR) Calibration Commands 3.6.4 Description Used to fetch data in any digital mode Used to start measurements in Sleep Mode Used in Command Mode during the calibration process Communication Supported Reference Sections 2 Section 3.6.4 2 Section 3.6.5 I C™ and SPI I C™ and SPI 2 I C™ Only Section 4.2 Data Fetch (DF) The Data Fetch (DF) command is used to fetch data in any digital output mode. With the start of communication 2 (for I C™ after reading the slave address; for SPI at the falling edge of SS) the entire output packet will be loaded in a serial output register. The register will be updated after the communication is finished. The output is always scaled to 14 bits independent of the programmed resolution. The ordering of the bits is big-endian. 2 3.6.4.1. I C™ Data Fetch 2 th An I C™ Data Fetch command starts with the 7-bit slave address and the 8 bit = 1 (READ). The ZSSC3122 as the slave sends an acknowledge (ACK) indicating success. The number of data bytes returned by the ZSSC3122 is determined by when the master sends the NACK and stop condition. Figure 3.10 shows examples of fetching two and three bytes respectively. The full 14 bits of capacitive data are fetched in the first two bytes. The MSBs of the first byte are the status bits. If temperature data is needed, additional temperature bytes can be fetched. In Figure 3.10, the three-byte data fetch returns 1 byte of temperature data (8-bit accuracy) after the capacitive data. A fourth byte can be fetched where the six MSBs of the fetched byte are the six LSBs of a 14-bit temperature measurement. The last two bits of the fourth byte are undetermined and should be masked off in the application. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 34 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 2 Figure 3.10 I C™ Measurement Packet Reads I 2 C DF – 2 Bytes: Slave returns only capacitance data to master in 2 bytes S 6 5 4 3 2 1 0 R A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 N S Device Slave Address [6:0] Cap. Data [13:8] Wait for Slave ACK Cap. Data [7:0] Master ACK Master ACK Master NACK S 6 5 4 3 2 1 0 R A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 N S Device Slave Address [6:0] Cap. Data [13:8] Cap. Data [7:0] Temp. Data [13:6] I C DF – 3 Bytes: Slave returns 2 capacitance data bytes & temperature high byte (T[13:6]) to master 2 S Start Condition 2 S Stop Condition Slave Address Bit (Example: Bit 2) A Acknowledge (ACK) N Not Acknowledge (NACK) 2 Command or Data Bit (Example: Bit 2) R Read/Write (Read = 1) Status Bit 3.6.4.2. SPI Data Fetch By default the SPI interface will have data change after the falling edge of SCLK. The master should sample MISO on the rising (opposite) edge of SCLK. This is configurable via the SPI_Phase bit in EEPROM word Cust_Config (see Table 5.5 for bit assignments). The SPI protocol can handle high and low polarity of the clock line without configuration change. As seen in Figure 3.11 the entire output packet is 4 bytes (32 bits). The high capacitive data byte comes first, followed by the low byte. Then 14 bits of corrected temperature (T[13:0]) are sent: first the T[13:6] byte and then the {T[5:0],xx} byte. The last 2 bits of the final byte are undetermined and should be masked off in the application. nd If the user only requires the corrected capacitance value, the read can be terminated after the 2 byte. If the corrd rected temperature is also required but only at an 8-bit resolution, the read can be terminated after the 3 byte is read. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 35 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 3.11 SPI Output Packet with Positive Edge Sampling … SCLK MISO HiZ S1 S0 C13 C12 … … C7 C6 … … C0 T13 T12 … T1 x T0 HiZ SS Packet = [ {S(1:0),C(13:8)}, {C(7:0)}, {T(13:6)},{T(5:0),xx}] Where S(1:0) = Status bits of packet (normal, command, busy, diagnostic) C(13:8) = Upper 6 bits of 14-bit capacitance data. C(7:0) = Lower 8 bits of 14-bit capacitance data. T(13:6) = Corrected temperature data (if application does not require corrected temperature, terminate read early) T(5:0),xx =. Remaining bits of corrected temperature data for full 14-bit resolution HiZ = High impedance 3.6.5 Measurement Request (MR) A measurement request (MR) is a Sleep-Mode-only command sent by the master to wake up the ZSSC3122 and 2 start a new measurement cycle in both I C™ and SPI modes. See section 3.3.2 for more information on Sleep Mode. 2 3.6.5.1. I C™ Measurement Request 2 The I C MR is used to wake up the device in Sleep Mode and start a complete measurement cycle starting with a temperature measurement, followed by a capacitance measurement, followed by the DSP calculations, and then the results are written to the digital output register. As shown in Figure 3.12, the communication contains only the slave address and the WRITE bit (0) sent by the master. After the ZSSC3122 responds with the slave ACK, the master creates a stop condition. 2 Note: The I C MR function can also be accomplished by sending “don’t care” data after the address instead of immediately sending a stop bit. 2 Figure 3.12 I C MR 2 I C MR– Measurement Request: Slave starts a measurement cycle S 6 5 4 3 2 1 0 W A S Device Slave Address [6:0] S Start Condition Data Sheet August 28, 2015 S Stop Condition Wait for Slave ACK A Acknowledge (ACK) 2 Slave Address Bit (Example: Bit 2) W Read/Write bit (Example: Write = 0) © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 36 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.6.5.2. SPI Measurement Request The SPI MR is used to wake up the device in Sleep Mode and start a complete measurement cycle starting with a temperature measurement/temperature DSP calculation, followed by a capacitance measurement / capacitance DSP calculations, and then the results are written to the digital output register. As shown in Figure 3.13, executing an SPI MR command is a read of 8 bits, ignoring the data that is returned. Note: The SPI MR function can also be accomplished by performing a full SPI Data Fetch (see section 3.6.4.2) and ignoring the invalid data that will be returned. Figure 3.13 SPI MR SS SCLK MISO 3.6.6 x x Ignore Data Ready Pin 2 A rise on the Ready pin indicates that new data is ready to be fetched from either the I C™ or SPI interface. The Ready pin stays high until a Data Fetch (DF) command is sent (see section 3.6.3); it stays high even if additional measurements are performed before the DF. In Sleep Mode, sending a Measurement Request (MR) command resets the Ready pin. The Ready pin’s output driver type is selectable as either full push-pull or open drain via the Ready_Open_Drain bit in EEPROM word Cust_Config (see Table 5.5 for bit assignments and settings). Point-to-point communication most likely uses the full push-pull driver. If an application requires interfacing to multiple parts, then the open drain option can allow for just one wire and one pull-up resistor to connect all the parts in a bus format. 3.7 PDM (Pulse Density Modulation) PDM outputs for both corrected capacitance and temperature are available. PDM_C (capacitance PDM) appears on the READY/PDM_C pin, and PDM_T (temperature PDM) appears on the ALARM_LOW/PDM_T pin if enabled using the Output_Selection bits (see Table 5.2). The typical PDM frequency is 231.25kHz (i.e., the oscillator frequency 1.85MHz minimum/maximum corners of the oscillator frequency divided by 8). Both PDM signals are 14-bit values. In PDM Mode, the ZSSC3122 must be programmed to Update Mode (see section 3.3.1). Every time a conversion cycle has finished, the PDM will begin outputting the new value. An analog output value is created by low-pass filtering the output; a simple first-order RC filter will work in this application. Select the time constant of the filter based on the requirements for settling time and/or peak-to-peak ripple. Important: The resistor of the RC filter must be ≥10k. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 37 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Table 3.12 shows some filter examples using a 10k resistor. Table 3.12 Low Pass Filter Example for R = 10k PDM_C Filter Capacitance (nF) VPP Ripple (mV/V) 0 to 90% Settling Time (ms) Desired Analog Output Resolution 100 4.3 2.3 8 400 1.0 9.2 10 1600 0.3 36.8 12 6400 0.1 147.2 14 For a different (higher) resistor, the normalized ripple VPP[mV/V] can be calculated as VPPm V / V 4324 ( Rk CnF) (14) or the settling time tSETT for a 0% to 90% settling can be calculated as tSETT ms 0.0023 Rk CnF (15) ZSSC3122 provides high and low clipping limits for the PDM output. EEPROM words PDM_Clip_High and PDM_Clip_Low (EEPROM registers 16HEX and 17HEX; see Table 5.1) are the 14-bit high and low clipping limit registers respectively. The 14-bit values map directly to the output of the IC and can be calculated as 214 * clip _ level _ % PDM _ Clip ROUND( ) 100 (16) These registers apply to both PDM_C and PDM_T. Since diagnostics are reported in the PDM pin (see section 3.4), clipping limits allow diagnostics to be differentiated from the normal output. For detection of the diagnostic signal, a PDM_Clip_High limit of 97.5% (3E66HEX) or lower is recommended. Important: The default values for the high and low clipping limits (00HEX) are not compatible with PDM output, so the clipping limits must be changed if the PDM output is used. Otherwise, the PDM output will not work as expected. If the PDM output is not used, it is important to retain the default values of 00 HEX for the clipping limits. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 38 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.8 Alarm Output The alarm output can be used to monitor whether a corrected capacitance reading has exceeded or fallen below pre-programmed values. The alarm can be used to drive an open-drain load connected to VDD, as demonstrated in section 7.2, or it can function as a full push-pull driver. If a high voltage application is required, external devices can be controlled with the Alarm pins, as demonstrated in section 7.3. The two alarm outputs can be used at the same time, and these alarms can be used in combination with any of 2 the other three modes; I C™, SPI, or PDM. Note: When both PMD_C and PDM_T are selected only Alarm_High is available (see section 3.5). The alarm outputs are updated when a conversion cycle is completed. The alarm outputs can be used in both 2 Update Mode and Sleep Mode, but if Sleep Mode is used, I C™ or SPI must also be used to control the measurements (see section 3.3). 3.8.1 Alarm Registers Four registers are associated with the alarm functions: Alarm_High_On, Alarm_High_Off, Alarm_Low_On, and Alarm_Low_Off (see Table 5.1 for EEPROM addresses). Each of these four registers is a 14-bit value that determines where the alarms turn on or off. The two high alarm registers form the output with hysteresis for the Alarm_High pin, and the two low alarm registers form the output with hysteresis for the Alarm_Low pin. Each of the two alarm pins can be configured independently using Alarm_Low_Cfg and Alarm_High_Cfg located in EEPROM word Cust_Config (see Table 5.5 for bit assignments). Note: If two high alarms or two low alarms are needed, see section 3.8.4. 3.8.2 Alarm Operation As shown in Figure 3.14, the Alarm_High_On register determines where the high alarm trip point is and the Alarm_High_Off register determines where the high alarm turns off if the high alarm has been activated. The high alarm hysteresis value is equal to Alarm_High_On – Alarm_High_Off. The same is true for the low alarm where Alarm_Low_On is the low alarm trip point with Alarm_Low_Off determining the alarm shut off point. The low alarm hysteresis value is equal to Alarm_Low_Off – Alarm_Low_On. Figure 3.15 shows output operation flowcharts for both the Alarm_High and Alarm_Low pins. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 39 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 3.14 Example of Alarm Function High Alarm Pin On Alarm_High_On High Alarm Pin Off Corrected Capacitance Hysteresis Alarm_High_Off Low Alarm Pin Off Alarm_Low_Off Hysteresis Alarm_Low_On Low Alarm Pin On Time Figure 3.15 Alarm Output Flow Chart HIGH ALARM PIN No Measurement > Alarm_High_On? Alarm = Off Yes Alarm = On Measurement ≤ Alarm_High_Off? No Yes LOW ALARM PIN Alarm = Off No Measurement < Alarm_Low_On? Yes Alarm = On Measurement ≥ Alarm_Low_Off? No Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. Yes 40 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 3.8.3 Alarm Output Configuration The user can select the output driver configuration for each alarm using the Output Configuration bit in the Alarm_High_Cfg and Alarm_Low_Cfg registers in EEPROM word Cust_Config (see Table 5.5 for bit assignments). For applications, such as interfacing with a microcontroller or controlling an external device (as seen in section 7.3), select the full push-pull driver for the alarm output type. For an application that directly drives a load connected to VDD, as demonstrated in section 7.2, the typical selection is the open-drain output type. An advantage of making an alarm output open drain is that in a system with multiple devices, the alarm outputs of each ZSSC3122 can be connected together with a single pull-up resistance so that one can detect an alarm on any device with a single wire. 3.8.4 Alarm Polarity For both alarm pins, the polarity of the alarm output is selected using the Alarm Polarity bit in the Alarm_High_Cfg and Alarm_Low_Cfg registers in EEPROM word Cust_Config (see Table 5.5 for bit assignments). As shown in the example in section 7.3, the alarms can be used to drive a high voltage humidity control system. Since the humidifier or dehumidifier relays must be on when the alarms are on, the alarm polarity bits are set to 0 (active high). In the example given in section 7.2, an alarm is used to turn on an LED in an open drain configuration. In order for the LED to be on when the alarm is on, the output must be low, so the alarm polarity bit is set to 1 (active low). Another feature of the polarity bits is the ability to create two high alarms or two low alarms. For example, with applications requiring two high alarms, flip the polarity bit of the Alarm_Low pin, and it will act as a high alarm. However, in this case, the effect of the alarm low registers is also changed: the Alarm_Low_On register would act like the Alarm_High_Off register and the Alarm_Low_Off register would act like the Alarm_High_On register. The same can be done to achieve two low alarms: the Alarm_High pin would have the polarity bit flipped, and the two Alarm_High registers would have opposite meanings. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 41 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 4 Command Mode Command Mode is primarily used for calibrating the ZSSC3122. Command Mode is entered by sending a Start_CM during the command window (see section 3.1 for more details on how to enter Command Mode). In Command Mode, a set of commands are available to the user to calibrate the part (see Table 4.1). 4.1 Command Format 2 Command Mode commands are only supported for the I C™ protocol. As shown in Figure 4.1, commands are 4byte packets with the first byte being a 7-bit slave address followed by 0 for write. The second byte is the command byte and the last two bytes form a 16-bit data field. Figure 4.1 2 I C™ Command Format I2C WRITE, Command Byte, and 2 Command Data Bytes S 6 5 4 3 2 1 0 W A 7 6 5 4 3 2 1 0 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A S Device Slave Address Command Byte Wait for Slave ACK 4.2 S Start Condition S Stop Condition 2 Slave Address Bit (Example: Bit 2) Command Data [15:8] Wait for Slave ACK Command Data [7:0] Wait for Slave ACK Wait for Slave ACK A Acknowledge (ACK) W Read/Write Bit (Example: Write = 0) 2 Command or Data Bit (Example: Bit 2) Command Encodings Table 4.1 describes all the commands that are offered in Command Mode. Note: Only the commands listed in Table 4.1 are valid. Other encodings might cause unpredictable results. If data is not needed for the command, zeros must be supplied as data to complete the 4-byte packet. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 42 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Table 4.1 Command List and Encodings Command Byte 8 Command Bits (Hex) 00HEX to 1FHEX 40HEX to 5FHEX Third and Fourth Bytes 16 Data Bits(Hex) Description EEPROM Read of addresses 00HEX to 1FHEX 0000HEX After this command has been sent and executed, a data fetch must be performed (see section 3.6.4). YYYYHEX Write to EEPROM addresses 00HEX to 1FHEX (Y = data) The 2 bytes of data sent will be written to the address specified in the 6 LSBs of the command byte. Start_NOM 80HEX Response Time 0000HEX Ends Command Mode and transitions to Normal Operation Mode. 100μs 12ms Length of initial conversions depends on temperature and capacitance resolution settings (see section 3). Start_CM A0HEX 0000HEX 0000HEX 100μs Start Command Mode: used to enter the command interpreting mode. Start_CM is only valid during the power-on command window (see section 3.1). Get Revision B0HEX ‡‡ 100μs Get the revision of the part. After this command has been sent and executed, a data fetch must be performed (see section 3.6.4). 4.3 Command Response and Data Fetch 2 After a command has been sent and the execution time defined in Table 4.1 has expired, an I C™ Data Fetch (DF) can be performed to fetch the response. As shown in Figure 4.2, after the slave address has been sent, the first byte fetched is the response byte. The upper two status bits will always be 10BIN to represent Command Mode (see section 3.4). The lower two bits are the response bits. ‡‡ All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 43 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Table 4.3 describes the different responses that can be fetched. To determine if a command has finished executing, poll the part until a Busy response is no longer received. The middle four bits of the response byte are command diagnostic bits where each bit represents a different diagnostic (see Table 4.3). For more information on EEPROM errors see section 3.4.1. Note: Regardless of what the response bits are, one or more of the diagnostic bits may be set indicating an error occurred during the execution of the command. Note: Only one command can be executed at a time. After a command is sent another command must not be sent until the execution time of the first command defined in Table 4.1 has expired. For all commands except EEPROM Read and Get Revision, the data fetch should be terminated after the response byte is read. If the command was a Get Revision, then the user will fetch a one byte Revision as shown in Figure 4.2, example 2. The revision is coded with the upper nibble being the letter corresponding to a full layer change and the lower nibble being the metal change number, for example A0. If the command was an EEPROM Read, then the user will fetch two more bytes as shown in Figure 4.2, example 3. If a Corrected EEPROM Error diagnostic was flagged after an EEPROM read, the user has the option to write this data back to attempt to fix the error. Instead of polling to determine if a command has finished executing, the user can use the Ready pin. In this case, wait for the Ready pin to rise, which indicates that the command has executed. Then a data fetch can be performed to get the response and data (see Figure 4.2). See section 3.6.6 for more information on the Ready pin. Table 4.2 Response Bits Encoding Name 00BIN Busy 01BIN Positive Acknowledge The command executed successfully. 10BIN Negative Acknowledge The command was not recognized or an EEPROM write was attempted while the EEPROM was locked. Table 4.3 Description The command is busy executing. Command Diagnostic Bits Bit Position Name Description 2 Corrected EEPROM Error A corrected EEPROM error occurred in execution of the last command. 3 Uncorrectable EEPROM Error 4 RAM Parity Error 5 Configuration Error Data Sheet August 28, 2015 An uncorrectable EEPROM error occurred in execution of the last command. A RAM parity error occurred during a microcontroller instruction in the execution of the last command. An EEPROM or RAM parity error occurred in the initial loading of the configuration registers. © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 44 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Figure 4.2 Command Mode Data Fetch (1) I 2 C DF – Command Status Response – 1 Byte S 6 5 4 3 2 1 0 R A 7 6 5 4 3 2 1 0 N S Device Slave Address [6:0] Status Diagnostics [7:6] [5:2] Wait for Slave ACK Response [1:0] Master ACK Master NACK S 6 5 4 3 2 1 0 R A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 N S Device Slave Address [6:0] Status Diagnostics Response [1:0] [5:2] [7:6] cLite™ Revision Data Byte [7:0] (2) I 2 C Get Revision DF – Command Status Response and cLite™ Revision – 2 Bytes Wait for Slave ACK Master ACK Master ACK Master NACK S 6 5 4 3 2 1 0 R A 7 6 5 4 3 2 1 0 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 N S Device Slave Address [6:0] Status [7:6] Diagnostics Response [1:0] [5:2] EEPROM Data High Byte [15:8] EEPROM Data Low Byte [7:0] (3) I 2 C EEPROM DF – Command Status Response and EEPROM Data Fetch – 3 Bytes S Start Condition S 2 Slave Address Bit (Example: Bit 2) Data Sheet August 28, 2015 Stop Condition A 2 Acknowledge (ACK) Command or Data Bit (Example: Bit 2) N Not Acknowledge (NACK) R Read/Write Bit (Example: Read = 1) Status Bits (In Command Mode Always 10) © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 45 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 5 EEPROM The EEPROM array contains the calibration coefficients for gain and offset, etc., and the configuration bits for the analog front end, output modes, measurement modes, etc. The ZSSC3122 EEPROM is arranged as 32 16-bit words (see Table 5.1). The EEPROM is divided into two sections. Words 0HEX to 15HEX can only be written to if the EEPROM is unlocked. After the EEPROM is locked these locations can no longer be written to. The EEPROM lock bits are in the ZMDI_Config register (see Table 5.2 for the bit assignment). Words 16HEX to 1FHEX (highlighted blue in Table 5.1) are always unlocked and available to write to at all times. See section 4 for instructions on read2 ing and writing to the EEPROM in Command Mode via the I C™ interface. When programming the EEPROM, an internal charge pump voltage is used; therefore a high voltage supply is not needed. Note: If the EEPROM was accidentally locked, it can be unlocked with the following instructions (see section 4 for how to send commands). 1. Enter Command Mode with a Start_CM command. 2. Send an A2HEX for the command byte and 0000HEX for the command data. 3. Send an F0HEX for the command byte and 0021HEX for the command data. 4. Clear the EEPROM_Lock bits in the ZMDI_Config register with an EEPROM Write command. 5. Reset the part. There are four Customer_ID words available for customer use, two in the locked region and two in the unlocked region. They can be used as a customer serial number for module traceability. (see Table 5.1 for Customer_ID EEPROM addresses.) The integrity of the contents of the EEPROM array is ensured via ECC (see section 3.4.1). Table 5.1 provides a summary of the EEPROM contents. The configuration register bits are explained in detail in the following subsections. Table 5.1 EEPROM Word Assignments EEPROM Word Bit Range IC Default Name 00HEX 15:0 XXXXHEX Cust_ID0 Customer ID byte 0: For use by customer (default value is the upper 16 bits of the lot number) 01HEX 15:0 (LLLLLLLLBIN Cust_ID1 Customer ID byte 1: For use by customer (default value is the lower 8 bits of the lot number and an 8 bit wafer number) XXXXHEX 0000ssssBIN) §§ Description and Notes 02HEX 15:0 0B00HEX ZMDI_Config ZMDI Configuration Register (See section 5.1.1) 03HEX 15:0 0006HEX Not Available Do Not Change; must leave at factory settings 04HEX 15:0 00FTHEX Not Available Do Not Change; must leave at factory settings 05HEX 15:0 0000HEX Not Available Do Not Change; must leave at factory settings 06HEX 15:0 0C06HEX C_Config §§ AFE Capacitance Configuration Register: See Table 5.3. The T in the default setting for EEPROM word 04H represents the custom trim value determined by final test. Do not change this setting. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 46 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner EEPROM Word Bit Range IC Default Name 07HEX 15:0 0000HEX SOT_tco 08HEX 15:0 0000HEX Tco 09HEX 15:0 0000HEX SOT_tcg 0AHEX 15:0 0000HEX Tcg 0BHEX 15:0 0000HEX Offset Offset correction for capacitance 0CHEX 15:0 2000HEX Gain_1 Gain correction for capacitance (region 1) 0DHEX 15:0 0000HEX SOT_1 2 0EHEX 15:0 2000HEX Gain_2 Gain correction for capacitance (region 2) 0FHEX 15:0 0000HEX SOT_2 Or TOT_1 10HEX 15:0 7FFFHEX Raw_Break 11HEX 15:0 8D92HEX T_Config AFE Temperature Configuration Register (See Table 5.4) 12HEX 15:0 0000HEX Offset_T Offset correction for temperature 13HEX 15:0 2000HEX Gain_T Gain correction for temperature 14HEX 15:0 0000HEX SOT_T 2 15HEX 15:0 0000HEX TREF 16HEX 13:0 0000HEX PDM_Clip_High PDM high clipping limit (keep at zero unless PDM is enabled; must change default if PDM is used) 17HEX 13:0 0000HEX PDM_Clip_Low PDM low clipping limit (keep at zero unless PDM is enabled; may be changed if PDM is used) 18HEX 13:0 3FFFHEX Alarm_High_On High alarm on trip point 19HEX 13:0 3FFFHEX Alarm_High_Off High alarm off trip point 1AHEX 13:0 0000HEX Alarm_Low_On Low alarm on trip point 1BHEX 13:0 0000HEX Alarm_Low_Off Low alarm off trip point 1CHEX 15:0 0028HEX Cust_Config Customer Configuration Register (See section 5.1.4.) 1DHEX 15:0 0000HEX Not Available Do Not Change; must leave at factory settings 1EHEX 15:0 XXXXHEX Cust_ID2 Customer ID byte 2: For use by customer (default value is the 8 bit x and 8 bit y coordinates on the wafer) 1FHEX 15:0 0000HEX Cust_ID3 Customer ID byte 3: For use by customer Description and Notes nd 2 order temperature offset correction for capacitance Temperature offset correction for capacitance nd Data Sheet August 28, 2015 2 order temperature gain correction for capacitance Temperature gain correction for capacitance nd order correction for capacitance (region 1) nd 2 order correction for capacitance (region 2) rd alternatively 3 order correction (only one region) Break point dividing region 1 from region 2 nd order correction for temperature Raw temperature reading reference point © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 47 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 5.1.1 ZMDI Configuration Register (ZMDI_Config, EEPROM Word 02HEX) This register is loaded at power-on reset and upon exiting Command Mode using a Start_NOM command. Table 5.2 Bit Range *** ZMDI_Config Bit Assignments IC Default Name 0 0BIN Measurement_Mode 2:1 00BIN Power_Down_Period 3 0BIN Scale_Sot_Tc 4 0BIN Gain4x_C Description and Notes 0 = Update Mode 1 = Sleep Mode *** Power Down Period: 00BIN = 0ms 01BIN = 5ms 10BIN = 25ms 11BIN = 125ms Scales the SOT TC Terms: 0 = Scale x 1 1 = Scale x 2 Multiply Gain_1 and Gain_2 by 0 = multiply by 1 1 = multiply by 4 7:5 000BIN EEPROM_lock 011BIN = locked All other = unlocked When EEPROM is locked, the internal charge pump is disabled and the EEPROM can no longer be programmed. Note: If the EEPROM was accidentally locked, see section 5 for instructions for unlocking it. 10:8 011BIN Comm_lock 011BIN = locked All other = unlocked 2 When communication is locked, I C™ communication will only respond to its programmed address. Otherwise if communication is unlocked, 2 I C™ will respond to any address. 13:11 001BIN Output_Selection 2 001BIN = I C 011BIN = SPI 100BIN = PDM Capacitance (+ 2 alarms) 110BIN = PDM Capacitance + Temperature (+ 1 alarm) All other configurations are not allowed See Table 3.8 for more details. All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 48 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Bit Range IC Default Name 14 0BIN Third_order 0 = Piece-wise linear calibration with breakpoint 1 = Third-order calibration 15 0BIN Not Available Do Not Change – must leave at factory settings 5.1.2 Description and Notes Capacitance Analog Front End Configuration (C_Config, EEPROM Word 06HEX) This register is loaded immediately before a capacitance measurement is taken, so a power cycle is not needed for changes to take effect. Table 5.3 C_Config Bit Assignments Bit Range IC Default Name 2:0 110BIN CDC_Reference 5:3 000BIN CDC_Offset CDC offset capacitor selection (see Table 2.1) 9:6 0000BIN Not Available Do Not Change – must leave at factory settings 11:10 11BIN Resolution 13:12 00BIN Not Available 14 0BIN Differential Description and Notes CDC reference capacitor selection (see Table 2.1) CDC resolution and sample rate: 00BIN = 8 bits at 0.7 ms rate 01BIN = 10 bits at 1.6 ms rate 10BIN = 12 bits at 5.0 ms rate 11BIN = 14 bits at 18.5 ms rate ††† Do Not Change – must leave at factory settings Differential input capacitance selection: 0 = Single-ended 1 = Differential 15 ††† 0BIN Not Available Do Not Change – must leave at factory settings All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). See section 3.2 for additional timing factors. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 49 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 5.1.3 Temperature Analog Front End Configuration (T_Config, EEPROM Word 11HEX) This register is loaded immediately before a capacitance measurement is taken, so a power cycle is not needed for changes to take effect. Table 5.4 Bit Range 2:0 T_Config Bit Assignments IC Default 010BIN Name CDC_Reference Description and Notes CDC reference capacitor selection. The factory settings are set for a full span temperature range from -20°C to +125°C. Note: Do not change this setting from the factory setting unless a different temperature range is needed. 5:3 010BIN CDC_Offset CDC offset capacitor selection. The factory settings are set for a full span temperature range from -20°C to +125°C. Note: Do not change this setting from the factory setting unless a different temperature range is needed. 8:6 110BIN Temp_Trim Trim setting used for the temperature measurement. The factory settings are set for a full span temperature range from -20°C to +125°C. Note: Do not change this setting from the factory setting unless a different temperature range is needed. 9 0BIN Not Available 11:10 11BIN Resolution Do Not Change – must leave at factory settings Temperature resolution and sample rate: ‡‡‡ 00BIN = 8 bits at 0.7 ms rate 01BIN = 10 bits at 1.6 ms rate 10BIN = 12 bits at 5.0 ms rate 11BIN = 14 bits at 18.5 ms rate 15:12 ‡‡‡ 1000BIN Not Available Do Not Change – must leave at factory settings All time values shown are typical; for the worst case values, multiply by 1.1 (nominal frequency ±10%). Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 50 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 5.1.4 Customer Configuration Register (Cust_Config, EEPROM Word 1CHEX) This register is loaded at power-on reset and upon exiting Command Mode after receiving a Start_NOM command. Table 5.5 Cust_Config Bit Assignments Bit Range IC Default Name 6:0 0101000BIN Device_ID 8:7 00BIN Alarm_Low_Cfg 10:9 00BIN Alarm_High_Cfg Description and Notes 2 I C™ slave address Configure the Alarm_Low output pin: Bits Description 7 Alarm Polarity: 0 = Active High 1 = Active Low 8 Output Configuration: 0 = Full push-pull 1 = Open drain Configure the Alarm_High output pin: Bits Description 9 Alarm Polarity: 0 = Active High 1 = Active Low 10 Output Configuration: 0 = Full push-pull 1 = Open drain 11 0BIN SPI_Phase 12 0BIN Ready_Open_Drain 13 0BIN Fast_Startup Sets the Command Window length: 0 = 10 ms Command Window 1 = 3 ms Command Window 15:14 00BIN Not Available Do Not Change – must leave at factory settings Data Sheet August 28, 2015 The edge of SCLK that the master samples MISO on: 0 = positive edge 1 = negative edge Ready pin is 0 = Full push-pull 1 = Open drain © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 51 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 6 Calibration and Signal Conditioning Math ZMDI can provide software and hardware with samples to perform the calibration. For a complete description and detailed examples, see the ZSSC3122/ZSSC3123_SSC_Modular_Evaluation_Kit_Description_RevX_xy.pdf. For more details on the following equations, refer to ZSSC3122 Technical Note—Detailed Equations for ZSSC3122 Rev C Silicon Math (available on request). Note For best results the calibration should be done with all settings set to the final application including supply voltage, measurement mode, update rate, output mode, resolution, and AFE settings in the final packaging. 6.1 Capacitance Signal Conditioning The ZSSC3122 supports up to a two-region piece-wise, non-linear sensor input or a third-order correction selectable. The general form of the capacitance signal conditioning equation is provided below. Note: The following equations are only meant to show the general form and capabilities of the ZSSC3122 sensor signal conditioning. Two-region piece-wise, non-linear sensor input RawTC Raw_ C OFFSET T ( Tco T SOT _ tco ) 1 T ( Tcg T SOT _ tcg ) (17) Raw1 MIN( RawTC, Raw_ Break ) (18) Raw2 MAX( 0 , RawTC Raw_ Break ) (19) Out SOT _ 1* ( Gain _ 1* Raw1 ) 2 Gain _ 1* Raw1 (20) SOT _ 2 * ( Gain _ 2 * Raw2 ) 2 Gain _ 2 * Raw2 Or alternatively Non-linear sensor input up to third-order correction Raw1 Raw _ C OFFSET T (Tco T SOT _ tco ) 1 T (Tcg T SOT _ tcg ) Out TOT _ 1* (Gain _ 1* Raw1 )3 SOT _ 1* (Gain _1* Raw1 )2 Gain _ 1* Raw1 Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. (21) (22) 52 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Where: Symbol Description Raw_C Raw sensor reading. RawTC Temperature corrected raw value. Raw1 Raw value to be used for region 1 correction. Raw2 Raw value used for region 2 correction. Raw_Break Raw value at which the transition from region 1 to region 2 occurs. Offset Offset correction for sensor applied at 50% full scale input. Gain_1 Gain correction for sensor applied to region 1. SOT_1 Second-order correction for sensor region 1. Gain_2 Gain correction for sensor applied to region 2 – not used if only 1 region is used. SOT_2 alternatively TOT_1 Second-order correction for sensor region 2 – not used if only 1 region is used. Used as third-order term TOT_1 for third-order correction. Tco Correction for offset drift due to temperature. Tcg Correction for sensitivity (gain) change due to temperature. SOT_tco Second-order correction for offset drift due to temperature. SOT_tcg Second-order correction for sensitivity change due to temperature. TREF Raw temperature reading used as a reference temperature for the removal of all TC components. T Difference between current raw temperature and the reference temperature. OUT Corrected capacitance output value. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 53 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 6.2 Temperature Signal Compensation Temperature is measured internally. Temperature correction contains both linear gain and offset terms as well as a second-order term to correct for any nonlinearity. Note: The following equation is only meant to show the general form and capabilities of the internal ZSSC3122 temperature signal conditioning. T SOT _ T * ( Raw _ T ) 2 Gain _ T * Raw _ T Offset _ T (23) Where: Symbol Range Description Raw_T [0,16383] Raw temperature reading Gain_T [-32768,32767] Gain correction for internal temperature Offset_T [-32768,32767] Offset correction for internal temperature SOT_T [-32768,32767] Second-order correction for internal temperature T [-32768,32767] Corrected temperature output value 6.3 Limits on Coefficient Ranges There are range limits on some of the calibration coefficients that will be enforced by the calibration routine provided by ZMDI. These limits ensure the integrity of the internal calculations and would only limit the most extreme cases of sensor correction. Note: For Alarm-only applications, it is critical that the coefficient verification feature of the calibration routine is used since diagnostics are not reported for the Alarms (see section 3.4 for more details) Table 6.1 shows the limits for correction for the grade of temperature dependency and 2 dependency Table 6.1 Correction TCO 6060 PPM/K SOT_TCO 74 PPM/K TCG 12120 PPM/K Data Sheet August 28, 2015 nonlinearity of this Limits on Coefficient Ranges Coefficient SOT_TCG nd Condition 2 147 PPM/K 2 Based on raw temperature values Based on raw temperature values © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 54 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 7 Application Circuit Examples The ZSSC3122 provides functionality for many different configurations. The following examples correspond to the example circuits shown at the beginning of the specification; however, there are many other possibilities. Combinations of these examples and many other options can give the user maximum design flexibility. Settings for the configuration registers are given with each example. See Table 5.1 for register addresses. In the examples below bits 3 and 4 of the ZMDI_Config register are marked with an X because they are calculated during calibration and are coefficient dependent (see section 6). 7.1 Digital Output with Optional Alarms In this example, a single-ended input capacitance is con2 verted to the digital domain, corrected, and output via I C™. The configuration settings are shown in Table 7.1 below. The ZSSC3122 operates in Sleep Mode, in which measurement commands are used during normal operation. In this 2 example, the I C™ address is 28HEX and the Comm_lock is set. VSUPPLY (+1.8V to 5.5V) 0.1µF 0.1µF ZSSC3122 SDA/MISO VSS GND SCL/SCLK SS C0 Alarm_High The AFE configuration registers select 14-bit resolution for capacitance with a capacitance range from 2.9pF to 7.2pF. The internal temperature is set to 14-bit resolution. Alarm_Low CC Figure 7.1 Digital Output with Optional Alarms Example Example 1: Configuration Settings Configuration Register ZMDI_Config (Table 5.2) Cust_Config (Table 5.5) C_Config (Table 5.3) T_Config (Table 5.4) * cLite™ Vcore Ready In this application, both Alarm_High and Alarm_Low are used for digital communication. As shown in Table 7.1 below, both alarms are configured as active high and full push-pull drivers for digital communication. Table 7.1 VDD 15 0 0 0 1 † † † † 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 0 0 X X 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 † † † † 0 1 0 0 1 1 0* 1* 0* 0* 1* 0* 0 † 0 0 0 † † † 0 0 0 1 1 1 1 0 0 † 0 1* 0 1* 0 0* The factory settings are set for a full span temperature range from -20°C to +125°C. Do not change this setting unless a different temperature range is needed. † Reserved setting – do not change factory settings. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 55 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 7.2 Analog Output with Optional Alarms In this example, a single-ended input capacitance is converted, corrected and then both capacitance and temperature are output via PDM, which are then low-pass filtered for analog outputs. One of the optional alarms controls an LED. The configuration settings are shown below in Table 7.2. In the ZMDI_Config register, the output selection bits are set to 10 to select PDM. Example low-pass filter values are given in section 3.7. For PDM, Update Mode must be selected. In this application example, a 25ms power-down period has been used. V 0.1µF In this application, Alarm_High is used to turn on an LED in an open-drain configuration. The output must be low for the LED to be on, so the Alarm_High polarity bit is set to active low. The PDM clipping limits are set for 10% (666HEX) to 90% (3999HEX) output. 0.1µF Vcore ZSSC3122 SUPPLY (+1.8V to 5.5V) PDM_C Cap. Analog Output PDM_T Temp Analog Output VSS C0 LED CC Figure 7.2 Alarm_High Analog Output with Optional Alarms Example Example 2: Configuration Settings Configuration Register ZMDI_Config (Table 5.2) Cust_Config (Table 5.5) * cLite™ GND The AFE configuration registers show a resolution of 14 bits for capacitance; however, the PDM low pass filter may be set for a lower resolution with a faster settling time (See section 3.7). A capacitance range of 1.4pF to 8.6pF has been chosen. The internal temperature is set to 12-bit resolution. Table 7.2 VDD 15 0 0 † † † 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 1 1 0 0 0 X X 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 † † † † 0 0 1 1 0 1 0 † C_Config (Table 5.3) 0 T_Config (Table 5.4) 1 PDM_Clip_High 0 0 1 PDM_Clip_Low 0 0 0 † 0 0 † 0 0 † 0 1 1 0 1 0 0 1 1 0 0 0 1 0 † † 0 0 0 1* 1* 0* 0* 1* 0* 0* 1* 0* 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 The factory settings are set for a full span temperature range from -20°C to +125°C. Do not change this setting unless a different temperature range is needed. † Reserved setting – do not change factory settings. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 56 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 7.3 Bang-Bang Control System In this example, the only outputs are the alarm pins. They are programmed to control a high voltage bang-bang humidity control system. External devices are not needed if not using high voltage. Vsupply +1.8V to 5.5V cLite ™ If the humidity gets too high, the ZSSC3122 activates the dehumidifier using the Alarm_High pin. If the humidity gets too low, it activates the humidifier with the Alarm_Low pin. The alarm registers must be set to appropriate trip and hysteresis points (See section 3.8). The configuration settings are shown in Table 7.3. 2 The output selection bits should either be set to I C™ or SPI since depending on the PDM configuration, both 2 alarms are not supported. Additionally, I C™ and SPI are lower power than PDM. This application does not 2 use I C™ or SPI, so Update Mode must be used because Sleep Mode commands cannot be sent. The fastest update rate is used for this example. External devices are needed to control the outputs because a voltage source greater than VDD is used. VDD 0.1µF 12V ZSSC3122 12V Vcore 0.1µF Dehumidifier VSS Alarm_High GND Humidifier C0 GND Alarm_Low CC GND Figure 7.3 Bang-Bang Control System Example The alarm pins control NMOS devices so the alarm pins must be full push-pull and output high when the alarm is on, so the polarity bits are set to 0 and the open drain bits are set to 0. In this example application, a faster response time may be needed, so the AFE configuration settings show 10-bit resolution for both capacitance and internal temperature. C_Config settings have been selected for a capacitance range of 5.8pF to 7.2pF (see Table 2.1). Table 7.3 Example 3: Configuration Settings Configuration Register ZMDI_Config (Table 5.2) Cust_Config (Table 5.5) C_Config (Table 5.3) T_Config (Table 5.4) * 15 0 0 0 1 † † † † 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 † † † † 1 0 0 0 0 1 0* 1* 0* 0* 1* 0* 0 † 0 0 0 † † † 0 0 0 0 0 1 1 0 0 † 0 1* 0 1* 0 0* The factory settings are set for a full span temperature range from -20°C to +125°C. Do not change this setting unless a different temperature range is needed. † Reserved setting – do not change factory settings. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 57 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 7.4 Differential Input Capacitance This example shows that the full functionality of the ZSSC3122 including the applications illustrated in examples 1, 2, and 3, can be implemented with a differential input capacitance. The capacitor C CC allows a non-galvanic connection (e.g., to the moving part of a motion sensor as part of the sensor construction), but it is not needed for sensor types with existing galvanic connections. The configuration settings are shown in Table 7.4. The differential bit is set to select differential input capacitance. In this example, SPI has been selected in Update Mode at the fastest update rate. The SPI phase is set to 1 so that the master samples MISO on the negative edge of SCLK. The EEPROM has been locked. VSUPPLY (+1.8V to 5.5V) 0.1µF 0.1µF VDD cLite™ Vcore ZSSC3122 Ready The AFE configuration registers select 14-bit resolution for capacitance and 10-bit resolution for internal temperature. Because this is the differential configuration, both the internal reference and offset capacitors are set to zero. GND VSS SDA/MISO C0 SCL/SCLK SS CC Alarm_High Alarm_Low C1 Figure 7.4 Differential Input Capacitance Example Table 7.4 Example 4: Configuration Settings Configuration Register ZMDI_Config (Table 5.2) Cust_Config (Table 5.5) 15 0 0 C_Config (Table 5.3) 0 T_Config (Table 5.4) 1 † † † † 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 1 1 X X 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 † † † † 0 0 0 0 0 0 0* 1* 0* 0* 1* 0* 0 † 1 0 † 0 0 † 0 0 † 1 1 0 0 1 0 † 0 1* 0 1* 0 0* * The factory settings are set for a full span temperature range from -20°C to +125°C. Do not change this setting unless a different temperature range is needed. † Reserved setting – do not change factory settings. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 58 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 7.5 External Reference Capacitor This example demonstrates that the full functionality of the ZSSC3122, including the applications illustrated in examples 1, 2, and 3, can be implemented with an external reference capacitor in conjunction with a single-ended input capacitance. In this example, the digital output is used. The external reference is used. The configuration settings are shown in Table 7.5. VSUPPLY (+1.8V to 5.5V) 0.1µF 0.1µF cLite™ Vcore ZSSC3122 Ready 2 Example configuration settings show I C™ in Sleep Mode with the Comm_lock off so that the ZSSC3122 can res2 pond to any I C™ slave address. Also the Ready pin is configured for open drain so that multiple devices can have their Ready lines connected together. GND VSS SDA/MISO C0 SCL/SCLK SS CC Alarm_High Ref. Cap The AFE configuration registers select 12-bit resolution for capacitance and 12-bit resolution for internal temperature. This example also shows an offset setting of 4.3pF. Figure 7.5 Table 7.5 VDD Alarm_Low C1 Ext. Reference Input Capacitance Example Example 5: Configuration Settings Configuration Register 15 ZMDI_Config (Table 5.2) 0 Cust_Config (Table 5.5) 0 C_Config (Table 5.3) T_Config (Table 5.4) 0 1 † † † † 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 0 0 X X 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0* 1* 0* 0* 1* 0* 0 † 0 0 0 † 0 0 † 0 1 † 1 0 0 0 0 0 † † 0 0 † 1* 0 0 † 1* 0 † 0* * The factory settings are set for a full span temperature range from -20°C to +125°C. Do not change this setting unless a different temperature range is needed. † Reserved setting – do not change factory settings. 8 ESD/Latch-Up-Protection All external module pins have an ESD protection of >4000V and a latch-up protection of 100mA or (up to +8V / down to –4V) relative to VSS/VSSA. The internal module pin VCORE has an ESD protection of > 2000V. ESD protection referenced to the Human Body Model is tested with devices in TSSOP14 packages during product qualification. The ESD test follows the Human Body Model with 1.5kOhm/100pF based on MIL 883, Method 3015.7. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 59 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 9 Pin Configuration and Package The standard package for the ZSSC3122 is a TSSOP-14 (4.4±0.1mm body wide) with lead-pitch 0.65mm. See the notes in Table 9.2 regarding connection requirements. Table 9.1 Storage and Soldering Conditions Storage and Soldering TSSOP14 Maximum Storage Temperature Tmax_storage Less than 10hrs, before mounting Minimum Storage Temperature: Tmin_storage at original packing only Maximum Drybake Temperature Tdrybake Soldering Peak Temperature Figure 9.1 Tpeak 14 2 13 3 12 4 11 5 10 6 9 7 8 Name Less than100hrs in summary, before mounting 125 C Less than 30s (IPC/JEDEC-STD-020 Standard) 260 C Description 1 VCORE Core voltage 2 C0 Capacitor input 0 3 VSS Ground supply August 28, 2015 C -55 ZSSC3122 Pin Assignments for TSSOP-14 Pin Data Sheet C ZSSC3122 Pin-Out Diagram 1 Table 9.2 150 Notes Always connect to an external capacitor to Gnd that is within the specifications given in section 1.3 for CVCORE_SM and CVCORE_UM. This is the only internal module pin. Refer to section 8 for ESD details. Connecting to GND for shielding is strongly recommended. © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 60 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Pin Name Description Notes 4 CC Common capacitor input 5 VSS Ground supply Connecting to GND for shielding is strongly recommended. 6 C1 Capacitor input 1 If not used, must be unconnected. 7 VDD Supply voltage (1.8V to 5.5V) Must connect to Vsupply. 8 Alarm_Low/ Low alarm output PDM_T Temperature PDM If not used, must be unconnected. (see Table 3.8) 9 Alarm_High High alarm output If not used, must be unconnected. 10 Ready/ PDM_C If not used, must be unconnected. Ready signal (conversion complete output) Capacitance PDM (see Table 3.8) Must connect to GND. 11 VSS Ground supply 12 SDA/MISO I C™ data if in I C™ Mode 2 2 If not used, must connect to VDD. Master-In-Slave-Out if in SPI Mode (see Table 3.8) 13 SCL/SCLK 2 2 I C™ clock if in I C™ Mode If not used, must connect to VDD. Serial clock if in SPI Mode (see Table 3.8) 14 SS Slave Select (input) if in SPI Mode If not used, must be unconnected. (see Table 3.8) Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 61 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 10 Test The test program is based on this datasheet. The final parameters, which will be tested during production, are listed in the tables and graphs of section 1. 11 Reliability A reliability investigation according to the in-house non-automotive standard will be performed. 12 Customization For high-volume applications that require an upgraded or downgraded functionality compared to the ZSSC3122, ZMDI can customize the circuit design by adding or removing certain functional blocks. For this customization, ZMDI has a considerable library of sensor-dedicated circuitry blocks, which enable ZMDI to provide a custom solution quickly. Please contact ZMDI for further information. 13 Part Ordering Codes Please contact ZMDI Sales for additional information. Sales Code Description Package ZSSC3122AA1BN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on un-sawn wafer Wafer thickness: 370µm ZSSC3122AI1BN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on un-sawn wafer Wafer thickness: 370µm ZSSC3122AI3BN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on un-sawn wafer Wafer thickness: 725µm ZSSC3122AA3BN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on un-sawn wafer Wafer thickness: 725µm ZSSC3122AA1CN ZSSC3122 Die — Temperature range: -20°C to +125°C Tested dice on frame Wafer thickness: 370µm ZSSC3122AI1CN ZSSC3122 Die — Temperature range: -20°C to +85°C Tested dice on frame Wafer thickness: 370µm ZSSC3122AA2*N ZSSC3122 TSSOP14 — Temperature range: -20°C to +125°C – Lead-free package Tube: substitute “T” for * in code Reel: substitute “R” for * in code ZSSC3122AI2*N ZSSC3122 TSSOP14 — Temperature range: -20°C to +85°C – Lead-free package Tube: substitute “T” for * in code Reel: substitute “R” for * in code ZSSC3122KIT ZSSC3122 SSC Evaluation Kit: Communication Board, SSC Board, Sensor Replacement Board, USB Cable, 5 IC Samples (Software can be downloaded from www.zmdi.com/zssc3122) Kit Contact ZMDI Sales for support and sales of the ZSSC3122 Mass Calibration System. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 62 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 14 Related Documents Note: X_xy refers to the current revision of the document. Document File Name ZSSC3122 Feature Sheet ZSSC3122_cLite_Feature_Sheet_Rev_X_xy.pdf ZSSC3122/ZSSC3123 SSC Modular Evaluation Kit Description cLite_SSC_Eval_Kit_Description_Rev_X_xy.pdf ZMDI Wafer Dicing Guidelines ZMDI_Wafer_Dicing_Guidelines_Rev_X_xy.pdf Visit the ZSSC3122 product page www.zmdi.com/zssc3122 on ZMDI’s website www.zmdi.com or contact your nearest sales office for the latest version of these documents. 15 Glossary Term Description ADC Analog-to-Digital Converter CDC Capacitance-to-Digital Converter DAC Digital-to-Analog Converter ECC Error Checking and Correction SSC Sensor Signal Conditioner Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 63 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner 16 Document Revision History Revision Date Description 1.00 February 15, 2011 First release. 1.10 June 29, 2011 Added specification for “Excitation Frequency of External Capacitances C 0 and C1” in section 1.3 and 2.2.1. Added “PDM frequency” specification to table in section 1.3. In section 3.7, clarified that clipping limit default values must be adjusted for PDM output functionality. Revised PDM frequency in sections 1.3 and 3.7. Revised PDM ripple and settling time specifications in section 1.3. Revised related examples in Table 3.12 and corrected equation (14) for calculating ripple. Revisions to text explaining equation (16) and subsequent text recommending limits for PDM_Clip_High. Revised Table 5.1 for PDM_Clip_High and PDM_Clip_Low. Added new settings for PDM clipping limits to section 7.2 and revised related settings in Table 7.2. Revised section 1.6 for addition of specifications for “Voltage Dependency” for the temperature channel to section 1.3. Revised section 2.2.1.3 regarding total capacitance. Revised default value for EEPROM word 04HEX from 007THEX to 00FTHEX in Table 5.1. Minor edits for clarity in section 7.3. Revised notes for VCORE pin 1 in Table 9.2. Revisions to section 3.3.2.1. 1.20 August 16, 2011 Added specifications in section 1.3 for VPOR maximum, VREG typical and maximum, and PSRTEMP. Revisions to section 3.3.2.1 to explain preferred method for detecting valid data. Revised product ordering codes. 1.30 July 23, 2012 Added note for clarity to “Active Regulated Voltage” specification in section 1.3. Deleted redundant specification for fOSC in section 1.3. Revised specifications for CVCORE_SM and CVCORE_UM in specifications in section 1.2. Updated ZMDI contact information. 1.40 April 30, 2012 Update for part numbers. Update for contact information. 1.50 May 22, 2013 Revisions to section 3.3.2.1 to explain preferred method for detecting valid data. Revision to section 3.6.6 to update Ready pin behavior in Sleep Mode. Revision to Figure 3.7. 1.51 July 4, 2013 Update for part order codes. Data Sheet August 28, 2015 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 64 of 65 ZSSC3122 cLite™ Low Voltage Capacitive Sensor Signal Conditioner Revision Date Description 1.52 December 11, 2013 Update to kit description in the part order tables: software is no longer included in kit. Instead it is downloaded from the product page www.zmdi.com/zssc3122. Minor edits to refer to product by alphanumeric name ZSSC3122, rather than cLite™. 1.60 May 16, 2014 Revised specifications for lower temperature range of -20C to 125C in section 1.2 and in data sheet text. Revised specifications for upper internal clock frequency limit in section 1.3. Revised specification for PDM frequency in section 3.7. Revised part ordering codes. 1.61 June 13, 2014 Addition of ZSSC3122AA3BN part number in section 13 and on page 3. 1.62 August 28, 2014 Minor edit regarding die information on page 2. Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.306 Fax +49.351.8822.337 USA Phone 1.855.275.9634 Phone +1.408.883.6310 Fax +1.408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Data Sheet August 28, 2015 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2014 Zentrum Mikroelektronik Dresden AG — Rev.1.62 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 65 of 65