Application Note Rev. 2.10 / October 2013 ZSC31050 0-to-10V Analog Output Multi-Market Sensing Platforms Precise and Deliberate ZSC31050 0-to-10V Analog Output Contents 1 2 3 4 5 6 Introduction .................................................................................................................................................... 3 Application Configuration .............................................................................................................................. 4 2.1. Schematic Circuit .................................................................................................................................... 4 2.2. PCB Layout............................................................................................................................................. 5 2.3. Evaluation Software Configuration ......................................................................................................... 6 2.4. Output Voltage Adjustment VOUT ............................................................................................................ 7 2.5. Setup for the ZSC31050 Evaluation Board ............................................................................................ 8 External Components .................................................................................................................................... 9 Related Documents ..................................................................................................................................... 10 Glossary ...................................................................................................................................................... 10 Document Revision History ......................................................................................................................... 11 List of Figures Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 0V to 10V Analog Output / 4-20mA Current Loop Schematic ......................................................... 3 Three-Wire 0V to 10V Analog Output with ZACwire™ Interface ..................................................... 4 PCB Layout ...................................................................................................................................... 5 ZSC31050 SSC Evaluation Kit Software Configuration .................................................................. 6 Calibration Window .......................................................................................................................... 7 ZSC31050 Evaluation Board Settings ............................................................................................. 8 List of Tables Table 2.1 Table 3.1 Register Configuration ..................................................................................................................... 6 Parameters for External Parts ......................................................................................................... 9 For more information, contact ZMDI via [email protected]. Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 2 of 11 ZSC31050 0-to-10V Analog Output 1 Introduction In the circuit design described in this application note, the analog output voltage of the ZSC31050 is shifted into the range of 0 to 10 VDC by external circuitry creating a voltage-to-current-to-voltage converter consisting of four resistors (R5 to R7 and RC2), a capacitor (RC1), and two bipolar transistors (T2 and T3) as shown in Figure 1.1. T2 is a common NPN-type transistor (e.g., BC847); there are no special requirements to be considered. T3 is a PNP-type transistor; the type depends on the power dissipation at the maximum ambient temperature TAMB_max with the maximum supply voltage VSUPP_max, the maximum output load current IOUT_max, and the output voltage VOUT. The required power dissipation rating for T3 at TAMB_max can be calculated with equation (1). VOUT_max PT3_max TAMB _ max IOUT_max VSUPP_max VOUT_max R7 RC2 (1) Figure 1.1 provides the basic schematic for this application. VOUT_NR is the non-ratiometric output voltage. See section 3 for details on components. Note that component values vary depending on the output configuration. Figure 1.1 0V to 10V Analog Output / 4-20mA Current Loop Schematic With the current loop output, the analog 2-wire-interface is connected to V+ and V-. The ZACwire™ (one-wire; OWI) interface communicates via VOUT referenced to VSS using an isolated communication module with a pullup resistor at VOUT, which is supplied by a voltage equal to VDDA. For more details regarding current-loop applications and the ZACwire™ interface, see ZSC31050 Application Note–Two-Wire Current Loop Output (section 4). With all analog voltage output configurations, V- is shorted to VSS via R3 = 0 Ω. For protection against reverse polarity at low voltage drops, a PMOS-enhancement transistor with sufficient gateto-source voltage could be used instead of D1 or R1. Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 3 of 11 ZSC31050 0-to-10V Analog Output 2 Application Configuration The configuration is determined by the programming of the ZSC31050 and by the placement and value of the external parts given in the schematics in Figure 1.1 and Figure 2.1. For full details for programming and configuration of the ZSC31050 with the SSC Evaluation Kit, see the ZSC31050 Evaluation Kit Description. 2.1. Schematic Circuit A three-wire solution for 0V to 10V analog output using the ZACwire™ interface can be achieved by modifications implemented in the schematic in Figure 2.1. The logic will separate the analog and digital signal paths depending on the operational mode. In the resulting circuit, the reduction in the number of connection wires achieved by adding a few components to the schematic reduces installation and maintenance costs. Figure 2.1 Three-Wire 0V to 10V Analog Output with ZACwire™ Interface Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 4 of 11 ZSC31050 0-to-10V Analog Output Additional configuration of the ZSC31050 is needed to ensure proper triggering of the switch. See section 2.3 for the configuration settings using the ZSC31050 SSC Evaluation Kit Software. The IO2 port mode must be enabled as ALARM2 and active HIGH (EEPROM register 1BHEX), and the alarm threshold must be set to FFF9HEX (EEPROM register 13HEX). With these settings, the IO2 pin switches state from HIGH during the 20ms startup window to LOW when entering the Normal Operation Mode (NOM). This behavior can be used to trigger and open the communication channel for the ZACwire™ interface. Within the 20ms window, if a START_CM command is received, the communication channel stays open in Command Mode (CM); otherwise the ZSC31050 enters the Normal Operating Mode (NOM) and the analog output is active. The addition of the T4 MOSFET ensures there will not be a high voltage signal at pin 1 (B2) of IC1 before the T2 and T3 transistors conduct. A pull-up resistor must be connected to the IO2 pin in order to achieve the logic-high level during start-up window. When programming the device, an additional pull-up must be implemented on the Vout line from the programming microcontroller (D6 and R13). A temperature measurement can be implemented using the D3 diode. 2.2. PCB Layout Figure 2.2 PCB Layout An example Gerber file is available on the ZMDI website (see section 4). Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 5 of 11 ZSC31050 0-to-10V Analog Output 2.3. Evaluation Software Configuration Table 2.1 lists the register bits that must be configured to ensure proper triggering of the IC1 switch. Figure 2.3 shows the settings for these bits using the ZSC31050 SSC Evaluation Kit Software. Figure 2.3 ZSC31050 SSC Evaluation Kit Software Configuration Table 2.1 Register Configuration Settings Register Register Name Port Mode IO2 1BHEX CFGOUT 4 Port Mode IO2 1BHEX CFGOUT 5:6 Alarm high-active IO2 Alarm 13HEX - 0:15 Alarm 2 threshold Supply Voltage VDDA 18HEX CFGAPP 1:2 Coarse regulation Supply Voltage VDDA 1CHEX ADJREF 10:12 Application Note October 14, 2013 Bits Comment Enable Alarm 2 Fine regulation © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 6 of 11 ZSC31050 0-to-10V Analog Output 2.4. Output Voltage Adjustment VOUT The following procedures will compensate components’ parameter variations in order to achieve the desired output voltage of 0-10V. Calibration and coefficient calculation (initial targets: 10% and 90%) Analog output measurement Re-adjustment of target values (manual calculation via equation (2)) and limit values and calculation of the new coefficient VOUT VSET New_Target Initial_Target VSET_MAX VSET_MIN * (Target_max% Target_min%) (2) For example, re-calculation of the maximum target can be done based on the measured output 10.15V and initial calibration targets 10% and 90% as demonstrated in equation (3): 10.15V 10V New_Target 90% * (90% 10%) 88.8% 10V 0V (3) For adjustment of the minimum signal calibration target, the sensor signal must be set to a level that results in 10% output or 1.11V for the above example (considering that 10V equals 90% output). After raw data acquisition, the above formula for calculating the adjusted targets can be applied for fine-tuning the output. Figure 2.4 Calibration Window Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 7 of 11 ZSC31050 0-to-10V Analog Output 2.5. Setup for the ZSC31050 Evaluation Board Set the switches and jumpers on the SSC Evaluation Board according to Figure 2.5. Figure 2.5 ZSC31050 Evaluation Board Settings KL3 Screw Terminal Power Supply VDDA VINN VINN VSS VDDA VSS VSS VSS VDDA VINP VINP VSS Jumper K12 – VDDA Set to 12P (via external voltage or KS12V) VDDA VBR VBR VSS VDDA IRT IRT VSS VDDA FBP FBP VSS VDDA OUT OUT VSS VDDA FBN FBN VSS KL1/KL2 Screw Terminal Connect External Bridge Jumper K11 - Bridge Mode Voltage Supplied Jumper K17 – V+ ext Closed Jumper K19 – OUT Closed K2 Connector to SSC SRB Pin #1 of ZSC31050 K1 Connector to SSC CB Slide Switch S1 Voltage Resistors for Board Identification Jumper K15 Voltage Output (10V) Application Note October 14, 2013 Slide Switch S2 Communication via I²C ZMDI SSC Board ZSC31050 V3.0 VSS VDDA VDDA VDDA VSS IN3 IN3 VDDA LED Jumpers Open VSS VGATE VGATE VDDA VSS IO1 IO1 VDDA VSS IO2 IO2 VDDA VSS SCL SCL VDDA © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. VSS SDA SDA VDDA VSS VDD VDD VDDA 8 of 11 ZSC31050 0-to-10V Analog Output 3 External Components Table 3.1 Parameters for External Parts Part ID Ratiometric Output Non-ratiometric Output (VOUT_NR) Current Loop Output R1 Not placed 3 kΩ 0Ω R2 Not placed 6.8 kΩ 0Ω R3 0Ω 0Ω 50 Ω R4 Not placed 2.2 kΩ 2.2 kΩ R5 Not placed 1 kΩ 150 Ω R6 Not placed 390 Ω 0Ω R7 0Ω 2.2 kΩ Not placed R8 Not placed Typical 100 Ω (for current limitation) Not placed R9 Not placed 220 kΩ 220 kΩ R10 Not placed 10 kΩ 10 kΩ R11 Not placed 100 Ω 100 Ω R12 Not placed 10 kΩ 10 kΩ R13 Not placed 390 Ω 390 Ω R14 Not placed 4.7 Ω 4.7 Ω RC1 0Ω 100 nF Not placed RC2 15 nF 2 kΩ 0Ω C1 100 nF C2 100 nF C3 Not placed 220 pF 220 pF C4 Not placed 10 nF 10 nF D1 Not placed e.g. LL4148 e.g. LL4148 D2 Not placed BZV55C6V8 BZV55B7V5 D3 Not placed 1N4148 Not placed D4 LED 0603 LED 0603 LED 0603 D5 Not placed LED 0603 LED 0603 T1 Not placed DN3545N8 (SOT89) DN3545N8 (SOT89) T2 Not placed BC817-40 (SOT23) BC817-40 (SOT23) T3 Not placed BC807-40 (SOT23) Not placed T4 FDC6306P FDN5618P Not placed T5 Not placed BC817-40 (SOT23) BC817-40 (SOT23) T6 Not placed BC817-40 (SOT23) BC817-40 (SOT23) Application Note October 14, 2013 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 9 of 11 ZSC31050 0-to-10V Analog Output 4 Related Documents Note: X_xy refers to the current revision of the document. Document File Name ZSC31050 Data Sheet ZSC31050_DataSheet_Rev_X_xy.pdf ZSC31050 Functional Description ZSC31050_Functional_Description_Rev_X_xy.pdf ZSC31050 Application Note – Two-Wire Current Loop Output ZSC31050_AN_Current_Loop_Rev_X_xy.pdf ZSC31050 Evaluation Kit Description ZSC31050_Evaluation_Kit_Description_Rev_X_xy.pdf ZSC31050 Gerber Example Files ZSC31050 AN 0-10V_rev.X_x_Manufacturing_data.zip Visit the ZSC31050 product page (www.zmdi.com/zsc31050) on ZMDI’s web site at www.zmdi.com or contact your nearest sales office for the latest version of these documents. 5 Glossary Term Description OWI One-Wire Interface SSC Sensor Signal Conditioner Application Note © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. October 14, 2013 10 of 11 ZSC31050 0-to-10V Analog Output 6 Document Revision History Revision Date Description 1.00 September 21, 2009 First release. 1.01 April 8, 2010 Changed to ZMDI template. 1.10 April 5, 2011 Changed ZACwire™ description to OneWire, ZMDI template. Updated contact information. Renamed ZMD31050 to ZSC31050. 2.00 May 22, 2013 Schematic for three-wire operation added. Update for contact information, imagery for cover and headers. 2.10 October 14, 2013 Addition of sections 2.3, 2.4, and 2.5. Update to “Related Documents” section to add example Gerber files available on the ZMDI website. Update for Figure 2.3. Update for Table 3.1. Minor edits for clarity. Sales and Further Information www.zmdi.com [email protected] Zentrum Mikroelektronik Dresden AG Global Headquarters Grenzstrasse 28 01109 Dresden, Germany ZMD America, Inc. 1525 McCarthy Blvd., #212 Milpitas, CA 95035-7453 USA Central Office: Phone +49.351.8822.0 Fax +49.351.8822.600 USA Phone +855.275.9634 Phone +408.883.6310 Fax +408.883.6358 European Technical Support Phone +49.351.8822.7.772 Fax +49.351.8822.87.772 DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. European Sales (Stuttgart) Phone +49.711.674517.55 Fax +49.711.674517.87955 Application Note October 14, 2013 Zentrum Mikroelektronik Dresden AG, Japan Office 2nd Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan ZMD FAR EAST, Ltd. 3F, No. 51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +81.3.6895.7410 Fax +81.3.6895.7301 Phone +886.2.2377.8189 Fax +886.2.2377.8199 Zentrum Mikroelektronik Dresden AG, Korea Office U-space 1 Building 11th Floor, Unit JA-1102 670 Sampyeong-dong Bundang-gu, Seongnam-si Gyeonggi-do, 463-400 Korea Phone +82.31.950.7679 Fax +82.504.841.3026 © 2013 Zentrum Mikroelektronik Dresden AG — Rev. 2.10 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice. 11 of 11