Power Management

Data Sheet
Rev. 1.10 / August 2013
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Power Management
Power and Precision
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Brief Description
Benefits
The ZSPM9015 is ZMDI’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications.
The ZSPM9015 integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6mm package.

With an integrated approach, the complete switching
power stage is optimized with regard to driver and
MOSFET dynamic performance, system inductance,
and power MOSFET RDS(ON). The ZSPM9015 uses
innovative high-performance MOSFET technology,
which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck
converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
warning function indicates if a potential over-temperature situation (>150°C) has occurred. An automatic
thermal shutdown activates if an over-temperature
condition (>180°C) is detected. The ZSPM9015 also
incorporates a Zero Current Detection Mode (ZCD)
for improved light-load efficiency and provides a tristate 3.3V and 5V PWM input for compatibility with a
wide range of PWM controllers.





Improved efficiency with zero current detection
Clean switching waveforms with minimal ringing
Based on the Intel® 4.0 DrMOS standard
72% space-saving compared to conventional
discrete solutions
High current handling
Optimized for use with ZMDI’s ZSPM1000 true
digital PWM controller
Available Support

ZSPM8015-KIT: Evaluation Kit for ZSPM9015
Physical Characteristics





Operation temperature: 0°C to +150°C
VIN: 4.5V to 25V (typical 12V)
IOUT: up to 35A
Low-profile SMD package: 6mmx6mm QFN40
ZMDI green packaging and RoHS compliant
Typical Application
The ZSPM9015 DrMOS is compatible with ZMDI’s
ZSPM1000, a leading-edge configurable digital
power-management system controller designed for
non-isolated point-of-load (POL) supplies.
Features









High-current handling: up to 35A
PWM input capable of 3.3V and 5V
Optimized for switching frequencies up to 1MHz
Zero-current detection and under-voltage lockout
(UVLO)
Thermal shutdown and warning flag for overtemperature conditions
Driver output disable function (DISB# pin)
Integrated Schottky diode technology in the
low-side MOSFET
Integrated bootstrap Schottky diode
Adaptive gate drive timing for shoot-through
protection
For more information, contact ZMDI via [email protected]
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10 — August 5, 2013. All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated,
stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
ZSPM9015 Block Diagram
BOOT
Typical Applications

High-performance gaming
motherboards

Compact blade servers,
Vcore and non-Vcore
DC-DC converters





Desktop computers,
Vcore and Non-Vcore
DC-DC converters
VIN
DBoot
VCIN
UVLO
PWM
GH
Logic
GH
Level Shift
(Q1)
HS Power
MOSFET
GH
LOGIC
CGND
PHASE
Anti-Cross
Conduction
ZCD_EN#
VSWH
Workstations
VCIN
High-current DC-DC
point-of-load converters
Networking and telecom
microprocessor voltage
regulators
Small form-factor voltage
regulator modules
GL
GL
Logic
DISB#
(Q2)
LS Power
MOSFET
GL
Thermal Thermal
Warning Shutdown
THWN#
ZSPM9015
PGND
Ordering Information
Product Sales Code
Description
Package
ZSPM9015ZI1R
ZSPM9015 RoHS-Compliant QFN40 – Junction temperature range: 0°C to 150°C
Reel
ZSPM8015-KIT
Evaluation Kit for ZSPM9015
Kit
Sales and Further Information
www.zmdi.com
[email protected]
Zentrum Mikroelektronik
Dresden AG
Global Headquarters
Grenzstrasse 28
01109 Dresden, Germany
ZMD America, Inc.
1525 McCarthy Blvd., #212
Milpitas, CA 95035-7453
USA
Central Office:
Phone +49.351.8822.306
Fax
+49.351.8822.337
USA Phone 1.855.275.9634
Phone +1.408.883.6310
Fax
+1.408.883.6358
European Technical Support
Phone +49.351.8822.7.772
Fax
+49.351.8822.87.772
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The
information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer,
licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or
in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any
customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for
any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty,
tort (including negligence), strict liability, or otherwise.
European Sales (Stuttgart)
Phone +49.711.674517.55
Fax
+49.711.674517.87955
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Japan
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Phone +81.3.6895.7410
Fax
+81.3.6895.7301
Phone +886.2.2377.8189
Fax
+886.2.2377.8199
Zentrum Mikroelektronik
Dresden AG, Korea Office
U-space 1 Building
11th Floor, Unit JA-1102
670 Sampyeong-dong
Bundang-gu, Seongnam-si
Gyeonggi-do, 463-400
Korea
Phone +82.31.950.7679
Fax
+82.504.841.3026
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10 — August 5, 2013.
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Contents
1
2
3
4
5
6
7
8
9
IC Characteristics ............................................................................................................................................. 6
1.1. Absolute Maximum Ratings ....................................................................................................................... 6
1.2. Recommended Operating Conditions ....................................................................................................... 7
1.3. Electrical Parameters ................................................................................................................................ 7
1.4. Typical Performance Characteristics ......................................................................................................... 9
Functional Description .................................................................................................................................... 11
2.1. VCIN and Disable (DISB#) ...................................................................................................................... 11
2.2. Thermal Warning Flag (THWN#) and Thermal Shutdown ...................................................................... 12
2.3. Tri-state PWM Input ................................................................................................................................. 13
2.4. Adaptive Gate Drive Circuit ..................................................................................................................... 13
2.5. Zero Current Detection Mode (ZCD_EN#) .............................................................................................. 14
Application Design .......................................................................................................................................... 16
3.1. Supply Capacitor Selection ..................................................................................................................... 16
3.2. Bootstrap Circuit ...................................................................................................................................... 16
3.3. Power Loss and Efficiency Testing Procedures ...................................................................................... 17
Pin Configuration and Package ...................................................................................................................... 18
4.1. Available Packages ................................................................................................................................. 18
4.2. Pin Description......................................................................................................................................... 19
4.3. Package Dimensions ............................................................................................................................... 20
Circuit Board Layout Considerations .............................................................................................................. 21
Glossary ......................................................................................................................................................... 22
Ordering Information ...................................................................................................................................... 23
Related Documents ........................................................................................................................................ 23
Document Revision History ............................................................................................................................ 23
List of Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Figure 1.6
Figure 1.7
Figure 1.8
Figure 1.9
Figure 1.10
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Data Sheet
August 5, 2013
Power Loss vs. Output Current........................................................................................................... 9
Efficiency vs. Output Current .............................................................................................................. 9
Power Loss vs. Output Current........................................................................................................... 9
Efficiency vs. Output Current .............................................................................................................. 9
Power Loss vs. Switching Frequency ............................................................................................... 10
Power Loss vs. Input Voltage ........................................................................................................... 10
Power Loss vs. Control Input Voltage .............................................................................................. 10
Power Loss vs. Output Voltage ........................................................................................................ 10
Control Input Current vs. Switching Frequency ............................................................................... 10
Control Input Current vs. Control Input Voltage ............................................................................... 10
Block Diagram and Typical Application Circuit with PWM Control ................................................... 11
Thermal Warning Flag (THWN#) Operation ..................................................................................... 12
PWM and Tri-state Timing Diagram ................................................................................................. 13
ZCD_EN# Timing Diagram ............................................................................................................... 15
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
4 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Figure 3.1
Figure 4.1
Figure 4.2
Figure 5.1
Power Loss Measurement Block Diagram ....................................................................................... 16
Pin-out PQFN40 Package ................................................................................................................ 18
QFN40 Physical Dimensions and Recommended Footprint ............................................................ 20
PCB Layout Example ........................................................................................................................ 22
List of Tables
Table 2.1
Table 2.2
Data Sheet
August 5, 2013
UVLO and Disable Logic .................................................................................................................. 12
ZCD Mode Operation (ZCD_EN# = LOW) and Switch States ......................................................... 14
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
5 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
1
1.1.
IC Characteristics
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. The device might not function or be operable above the
recommended operating conditions. Stresses exceeding the absolute maximum ratings might also damage the
device. In addition, extended exposure to stresses above the recommended operating conditions might affect
device reliability. ZMDI does not recommend designing to the “Absolute Maximum Ratings.”
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Maximum Voltage – VCIN pin
-0.3
7.0
V
Maximum Voltage – PWM, DISB#,
THWN# and ZCD_EN# pins
-0.3
6.5
V
Maximum Voltage – VIN and VSHW
pins
-0.3
30
V
Maximum Voltage to BOOT pin –
VSWH pin
-0.3
7.0
V
35.0
V
40.0
V
ITHWN#
30
mA
Maximum Output Current
IOUT
35
A
Thermal Resistance, High-Side
MOSFET
θJPCB
13
°C/W
Thermal Resistance, Low-Side
MOSFET
θJPCB
5
°C/W
Maximum Voltage to BOOT pin –
PGND pin
Maximum Voltage to BOOT pin –
PGND pin
Maximum Sink Current – THWN# pin
< 50ns
Tj
0
+150
°C
Storage Temperature Range
TSTOR
-55
+150
°C
Electrostatic Discharge Protection
ESD
Operating Junction Temperature
Latch-Up Protection
LU
Moisture Sensitivity Level
Data Sheet
August 5, 2013
MSL
JEDEC
JESD22-A114
HBM Class 1B
JEDEC JESD78
Class 1 Level A
3
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
6 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
1.2.
Recommended Operating Conditions
The “Recommended Operating Conditions” table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ZMDI
does not recommend exceeding them or designing to the “Absolute Maximum Ratings.”
PARAMETER
SYMBOL
Control Input Voltage
Input Supply Voltage
1)
1.3.
1)
CONDITIONS
MIN
TYP
MAX
UNITS
VCIN
4.5
5.0
5.5
V
VIN
4.5
12.0
25
V
Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET
switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the "Absolute
Maximum Ratings" shown in the table above. Refer to sections 3 and 5 of this datasheet for additional information.
Electrical Parameters
Note: Performance is guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction
temperature as close to ambient as possible.
Typical values are VIN = 12V, VCIN = 5V, ambient temperature TAMB = -10ºC to +100°C unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
VCIN Current (Normal Mode)
DISB# = 5V, PWM = OSC,
FSW = 400kHz
14
20
mA
VCIN Current (Disabled Mode)
DISB# = GND
15
30
µA
3.8
4.35
4.5
V
0.150
0.2
0.250
V
Under-Voltage Lock-Out
UVLO Threshold
UVLO
UVLO Hysteresis
UVLO_Hyst
VCIN rising
PWM Input
PWM Input Resistance
63
kΩ
PWM Input Bias Voltage
1.7
V
PWM High-Level Voltage
VIH_PWM
2.65
PWM Tri-state Level Voltage
VTRI_PWM
1.4
PWM Low-Level Voltage
VIL_PWM
Tri-state Shutoff Time
Data Sheet
August 5, 2013
tD_HOLD-OFF
V
2.0
V
0.7
V
250
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
ns
7 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DISB# Input
High-Level Input Voltage
VIH_DISB#
Low-Level Input Voltage
VIL_DISB#
2.0
V
0.8
Hysteresis
500
Propagation Delay
tPD_DISB
20
V
mV
40
ns
Zero Current Detection
High-Level Input Voltage
VIH_ZCD_EN#
Low-Level Input Voltage
VIL_ZCD_EN#
2.0
V
0.8
ZCD Threshold
V
-6
mV
tZCD_DISB
250
ns
Activation Temperature
TACT
150
°C
Reset Temperature
TRST
135
°C
180
ºC
135
°C
ZCD Timer
Thermal Warning Flag
Thermal Shutdown
Activation Temperature
Reset Temperature
TRST_SD
Boot Diode
Forward-Voltage Drop
Data Sheet
August 5, 2013
VF
VCIN = 5V, forward bias
current = 2mA
0.1
0.4
0.6
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
V
8 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
1.4.
Typical Performance Characteristics
Test conditions: VIN=12V, VOUT=1.0V, VCIN=5V, LOUT=250nH, TAMB=25°C, and natural convection cooling, unless
otherwise specified.
Figure 1.1
Power Loss vs. Output Current
Figure 1.2
VIN = 12V, VCIN = 5V, VOUT = 1V
300kHz
500kHz
800kHz
1000kHz
7
90
Module Efficiency, η (%)
Module Power Loss, PMod (W)
8
6
5
4
3
85
80
75
70
2
300kHz
500kHz
800kHz
1000kHz
65
1
0
60
0
5
Figure 1.3
10
15
20
25
30
Module Output Current, IOUT (A)
35
40
Power Loss vs. Output Current
0
5
Figure 1.4
VIN = 12V, VCIN = 5V, VOUT = 1V
10
15
20
25
30
Module Output Current, IOUT (A)
35
40
Efficiency vs. Output Current
100%
0.9
VIN = 12V, VCIN= 5V, VOUT = 1V, FSW = 300kHz
0.8
90%
ZCD enabled
80%
0.7
Module Efficiency, η (%)
Module Power Loss, PLOSS (W)
Efficiency vs. Output Current
95
9
0.6
0.5
0.4
0.3
0.2
ZCD disabled
70%
60%
50%
40%
30%
20%
ZCD enabled
0.1
10%
ZCD disabled
VIN = 12V, VCIN= 5V, VOUT = 1V, FSW = 300kHz
0%
0
0
Data Sheet
August 5, 2013
2
4
6
Module Output Current, IOUT (A)
8
10
0
2
4
6
Module Output Current, IOUT (A)
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
8
10
9 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Figure 1.5
Power Loss vs. Switching Frequency
Figure 1.6
1.6
1.25
Normalized Module Power Loss
Normalized Module Power Loss
VCIN = 5V, VOUT = 1V, FSW = 300kHz, IOUT = 30A
VIN = 12V, VCIN = 5V, VOUT = 1V, IOUT = 30A
1.5
1.4
1.3
1.2
1.1
1.0
1.15
1.10
1.05
0.95
100
200
Figure 1.7
300 400 500 600 700 800 900 1000 1100
Module Switching Frequency, FSW (kHz)
Power Loss vs. Control Input Voltage
5
Figure 1.8
1.05
10
15
20
Module Input Voltage, VIN (V)
25
Power Loss vs. Output Voltage
2.2
VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 30A
1.04
VIN = 12V, VCIN = 5V, FSW = 300kHz, IOUT = 30A
2.0
Normalized Module Power Loss
Normalized Module Power Loss
1.20
1.00
0.9
1.03
1.02
1.01
1
0.99
0.98
1.8
1.6
1.4
1.2
1.0
0.97
0.8
0.96
4.50
4.75
5.00
5.25
Control Input Voltage, VCIN (V)
Figure 1.9
0.5
5.50
Control Input Current vs.
Switching Frequency
Figure 1.10
45
1.0
1.5
2.0
2.5
3.0
Module Output Voltage, VOUT (V)
3.5
4.0
Control Input Current vs.
Control Input Voltage
13.0
VIN = 12V, VCIN = 5V, VOUT = 1V, IOUT = 0A
40
VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 0A
Control Input Current, ICIN (mA)
Control Input Current, ICIN (mA)
Power Loss vs. Input Voltage
1.30
35
30
25
20
15
10
12.5
12.0
11.5
11.0
10.5
10.0
9.5
5
9.0
0
100
200
Data Sheet
August 5, 2013
300 400 500 600 700 800 900 1000 1100
Module Switching Frequency, FSW (kHz)
4.50
4.75
5.00
5.25
Control Input Voltage, VCIN (V)
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
5.50
10 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
2
Functional Description
The ZSPM9015 is a driver-plus-MOSFET module optimized for the synchronous buck converter topology. A
single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. It is
capable of driving speeds up to 1MHz.
Figure 2.1
Block Diagram and Typical Application Circuit with PWM Control
VIN = 4.5V to 25V
CVIN
VIN
V5V= 4.5V to 5.5V
DBoot
VCIN
BOOT
UVLO
CVCIN
PWM
GH
Logic
GH
Level Shift
RBOOT
(Q1)
HS Power
MOSFET
CBOOT
GH
LOUT
LOGIC
VOUT
PHASE
PWM
CONTROL
Enabled
ZCD_EN#
Anti-Cross
Conduction
COUT
VSWH
OFF
VCIN
Disabled
ON
GL
GL
Logic
DISB#
(Q2)
LS Power
MOSFET
GL
THWN#
Thermal Thermal
Warning Shutdown
ZSPM9015
Open Drain
Output
CGND
2.1.
PGND
VCIN and Disable (DISB#)
The VCIN pin is monitored by the under-voltage lockout (UVLO) circuit. When VCIN rises above ~4.35V, the driver
is enabled. When VCIN falls below ~4.1V, the driver is disabled (GH, GL= 0; see Table 2.1 and section 4.2).
The driver can also be disabled by pulling the DISB# pin LOW (DISB# < V IL_DISB#; see section 1.3), which holds
both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin
voltage HIGH (DISB# > VIH_DISB#). It is advisable not to leave the DISB# floating.
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
11 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Table 2.1
UVLO and Disable Logic
UVLO Circuit
DISB#
Driver State
ON
X
Disabled (GH=0, GL=0)
OFF
Low
Disabled (GH=0, GL=0)
OFF
High
Enabled
OFF
Open
Disabled (GH=0, GL=0)
ON = ULVO circuit is active and the driver output is disabled. The output will not respond to the PWM input under
any condition.
Off = ULVO is non-active and the output operates normally. The output will respond to the PWM input provided
the conditions are correct; e.g., not in thermal shutdown.
2.2.
Thermal Warning Flag (THWN#) and Thermal Shutdown
The ZSPM9015 provides a thermal warning flag (THWN#) to indicate over-temperature conditions. The thermal
warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached.
The THWN# output returns to the high-impedance state once the temperature falls to the reset temperature
(135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN.
Thermal Warning Flag (THWN#) Operation
VoltageatatTHWN#
THWN
Voltage
Figure 2.2
Reset
Temperature
Activation
Temperature
High
Normal
Operation
Thermal
Warning
Low
135°C
150°C
Driver
Temperature
Driver
Temperature
If the temperature exceeds 180ºC then the part will enter thermal shutdown and turn off both MOSFETs. Upon the
temperature falling below 155ºC, the part will resume operation.
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
12 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
2.3.
Tri-state PWM Input
The ZSPM9015 incorporates a tri-state PWM input gate drive design. The tri-state gate drive has both logic HIGH
and LOW levels, with a tri-state shutdown voltage window. When the PWM input signal enters and remains within
the tri-state voltage window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature
enables the gate drive to shut down both the high and low side MOSFETs using only one control signal. For
example, this can be used for phase shedding in multi-phase voltage regulators.
When exiting a valid tri-state condition, the ZSPM9015 follows the PWM input command. If the PWM input goes
from tri-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from tri-state to HIGH, the highside MOSFET is turned on, as illustrated in Figure 2.3. The ZSPM9015’s design allows for short propagation
delays when exiting the tri-state window.
Figure 2.3
PWM and Tri-state Timing Diagram
GH
0V
t
VDD
PWM
Tri-state
0V
t
GL
0V
t
tD_HOLDOFF
2.4.
tD_HOLDOFF
Adaptive Gate Drive Circuit
The low-side driver (GL) is designed to drive a ground-referenced low RDS(ON) N-channel MOSFET. The bias
voltage for GL is internally connected between VCIN and PGND. The GL output follows the inverse of the PWM
input with the exception that it is held LOW under any of the following conditions: a) the driver is disabled
(DISB#=0V); b) the PWM signal is held within the tri-state window for longer than the tri-state hold-off time,
tD_HOLDOFF; or c) specific circuit conditions that occur while in ZCD Mode (see section 2.5 for further details).
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
13 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit referenced to the switch node (VSWH) pin. This circuit consists of
an internal Schottky diode, an external bootstrap capacitor (CBOOT), and the optional RBOOT if used. During startup,
the VSWH pin is held at PGND, allowing CBOOT (see section 3.2) to charge to VCIN through the internal diode.
When the PWM input goes HIGH, GH begins to charge the gate of Q1, the high-side MOSFET. During this
transition, the charge is removed from C BOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN,
forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1.
To complete the switching cycle, Q1 is turned off by pulling GH to V SWH. CBOOT is then recharged to VCIN when
VSWH falls to PGND. The GH output follows the PWM input except that it is held LOW when either a) the driver is
disabled (DISB#=0V) or b) the PWM signal is held within the tri-state window for longer than the tri-state hold-off
time, tD_HOLDOFF.
The ZSPM9015 design ensures minimum MOSFET dead time while eliminating potential shoot-through (crossconduction) currents. It achieves this by monitoring the state of the MOSFETs and adjusts the gate drive
adaptively to prevent simultaneous conduction.
When the PWM input goes HIGH, the gate of the low side MOSFET (GL pin) will go low after a propagation delay.
The time it takes for the low side MOSFET to turn off is dependent on the gate charge on the low side MOSFET
gate. The ZSPM9015 monitors the gate voltage of both MOSFETs to determine the conduction status of the
MOSFETs. Once the low-side MOSFET is turned off, an internal timer will delay the turn on of the high-side
MOSFET. Similarly, when the PWM input pin goes low, the converse occurs.
2.5.
Zero Current Detection Mode (ZCD_EN#)
Zero Current Detection (ZCD) Mode allows higher converter efficiency under light-load conditions.
When the ZCD feature is disabled (ZCD_EN# is high), the ZSPM9015 will operate in the normal PWM Mode in
which the synchronous buck converter works in Synchronous Mode.
If the ZCD_EN# is set low, then the ZSPM9015 will operate in the ZCD Mode, and in this mode, the ZSPM9015
can prevent discharging of the output capacitors as the filter inductor current attempts reverse current flow. If the
PWM goes high, GH will go high after the non-overlap delay time. During this period, the ZCD timer is inactive
and thus reset. If the PWM goes low, GL will go high after the non-overlap delay time and stay high for the
duration of the ZCD timer (tZCD_DISB); see section 1.3. During this period ZCD operation is disabled. Once this timer
has expired, VSWH will be monitored for zero current detection and GL will go low if a zero-current condition is
detected. The ZCD threshold (see section 1.3) on VSWH to determine zero current undergoes an auto-calibration
cycle every time DISB# is brought from LOW to HIGH. This auto-calibration cycle takes 25µs to complete.
Table 2.2
ZCD Mode Operation (ZCD_EN# = LOW) and Switch States
PWM Input
ZCD Status
GH
GL
High
ZCD timer is reset (inactive)
High
Low
Low
Positive inductor current
Low
High
Low
Zero inductor current
Low
Low
Tri-state
X
Low
Low
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
14 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
Figure 2.4
ZCD_EN# Timing Diagram
See Figure 2.3 for the definitions of the timing parameters.
ZCD_EN#
0V
t
PWM
0V
t
GH
0V
t
GL
0V
t
ZCD
IL
Occurrence
0A
t
tZCD_DISB
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
15 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
3
3.1.
Application Design
Supply Capacitor Selection
For the supply input (VCIN), a local ceramic bypass capacitor (CCVIN) is required to reduce noise and is used to
supply the peak transient currents during gate drive switching action. Recommendation: use at a 1µF to 4.7µF
capacitor with an X7R or X5R dielectric. Keep this capacitor close to the VCIN pin, and connect it to the CGND
ground plane with vias.
3.2.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C BOOT), as shown in Figure 3.1. A bootstrap capacitance of
100nF using a X7R or X5R capacitor is typically adequate. A series bootstrap resistor might be needed for
specific applications to improve switching noise immunity. The boot resistor might be required when operating
with VIN above 15V, and it is effective at controlling the high-side MOSFET turn-on slew rate and VSWH overshoot.
Typically, RBOOT values from 0.5Ω to 3.0Ω are effective in reducing VSWH overshoot.
Figure 3.1
Power Loss Measurement Block Diagram
Open Drain Output
THWN#
V5V
A
VIN
CVIN
I5V
VIN
IIN
VCIN
A
BOOT
CVCIN
RBOOT
CBOOT
ZSPM9015
PWM Input
LOUT
PWM
VOUT
A
PHASE
OFF
IOUT
ZCD_EN#
ON
VSWH
COUT
DISB
DISB#
v
CGND
Data Sheet
August 5, 2013
VSW
PGND
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
16 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
3.3.
Power Loss and Efficiency Testing Procedures
The circuit in Figure 3.1 has been used to measure power losses in the following example. The efficiency has
been calculated based on the equations (1) through (7).
Power loss calculations in Watts:
PIN  VIN  IIN   V5 V  I5 V 
(1)
PSW  VSW  IOUT 
(2)
P OUT  VOUT  IOUT 
(3)
PLOSS _ MODULE  PIN  PSW 
(4)
PLOSS _ BOARD  PIN  POUT 
(5)
Efficiency calculations:

P
EFFMODULE   100  SW
PIN


 %


P
EFFBOARD   100  OUT
PIN


 %

Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
(6)
(7)
17 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
4
4.1.
Pin Configuration and Package
Available Packages
The ZSPM9015 is available in a 40-lead clip-bond QFN package. The pin-out is shown in Figure 4.1.
See Figure 4.2 for the mechanical drawing of the package.
Figure 4.1
Pin-out PQFN40 Package
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
18 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
4.2.
Pin Description
Pin
Name
1
ZCD_EN#
2
VCIN
3
NC
4
BOOT
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
5, 37 & pad 41
CGND
IC ground. Ground return for ZSPM9015.
6
GH
7
PHASE
8
NC
No connection.
9 - 14
& pad 42
VIN
Input power voltage (output stage supply voltage).
15, 29 - 35
& pad 43
VSWH
Switch node. Provides return for high-side bootstrapped driver and acts as a sense point for
the adaptive shoot-through protection.
16 – 28
PGND
Power ground (output stage ground). Source pin of the low-side MOSFET.
36
GL
38
THWN#
Thermal warning flag. When temperature exceeds the trip limit, the output is pulled LOW.
This pin has a maximum current capability of 30mA.
39
DISB#
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL
are held LOW). Advisable not to leave floating.
40
PWM
PWM signal input. This pin accepts a tri-state 3.3V or 5V PWM signal from the controller.
Data Sheet
August 5, 2013
Description
Enable Zero Current Detection Mode. Advisable not to leave floating.
IC bias supply. A 1µF (minimum) ceramic capacitor is recommended from this pin to CGND.
No connection.
Gate high. For manufacturing test only. This pin must float: it must not be connected.
Switch node pin for bootstrap capacitor routing; electrically shorted to VSWH pin.
Gate low. For manufacturing test only. This pin must float. It must not be connected.
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
19 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
4.3.
Package Dimensions
Figure 4.2
QFN40 Physical Dimensions and Recommended Footprint
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
20 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
5
Circuit Board Layout Considerations
Figure 5.1 provides an example of a proper layout for the ZSPM9015 and critical components. All of the highcurrent paths, such as the VIN, VSWH, VOUT, and GND copper traces, should be short and wide for low inductance
and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced
heat radiation and system performance.
The following guidelines are recommendations for the printed circuit board (PCB) designer:
1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the highcurrent power loop inductance and the input current ripple induced by the power MOSFET switching
operation.
2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the
DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS
package. The trace should be short and wide enough to present a low-impedance path for the highfrequency, high-current flow between the DrMOS and inductor to minimize losses and DrMOS temperature
rise. Note that the VSWH node is a high-voltage and high-frequency switching node with a high noise
potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a
heat sink for the lower MOSFET, the designer must balance using the largest area possible to improve
DrMOS cooling with maintaining acceptable noise emission.
3. Locate the output inductor close to the ZSPM9015 to minimize the power loss due to the VSWH copper trace.
Care should also be taken so that the inductor dissipation does not heat the DrMOS.
4. The power MOSFETs used in the output stage are effective for minimizing ringing due to fast switching. In
most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and
PGND pins. The resistor and capacitor must be the proper size for the power dissipation.
5. VCIN and BOOT capacitors should be placed as close as possible the VCIN-to-CGND and BOOT-to-PHASE
pin pairs to ensure clean and stable power. Routing width and length should be considered as well.
6. The layout should include a placeholder to insert a small-value series boot resistor (RBOOT) between the boot
capacitor (CBOOT) and the ZSPM9015 BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as
small as possible. The boot resistor may be required when operating with V IN above 15V. The boot resistor is
effective for controlling the high-side MOSFET turn-on slew rate and VSWH overshoot. RBOOT can improve the
operating noise margin in synchronous buck designs that might have noise issues due to ground bounce or
high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency.
Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5Ω to 3.0Ω are typically effective
in reducing VSWH overshoot.
7. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If
possible, these pins should be connected directly to the VIN and board GND planes. Important: the use of
thermal relief traces in series with these pins is discouraged since this adds inductance to the power path.
Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive
and negative VSWH ringing.
8. Connect the CGND pad and PGND pins to the GND plane copper with multiple vias for stable grounding.
Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead
to faulty operation of the gate driver and MOSFETs.
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
21 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add
an additional BOOT to PGND capacitor; this could lead to excess current flow through the BOOT diode.
10. It is advisable not to float the ZCD_EN# and DISB# pins.
11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current
flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical highfrequency components, such as RBOOT, CBOOT, RC snubber, and bypass capacitors, should be located as close
to the respective ZSPM9015 module pins as possible on the top layer of the PCB. If this is not feasible, they
can be connected from the backside through a network of low-inductance vias.
Figure 5.1
PCB Layout Example
Top View
6
Bottom View
Glossary
Term
Description
CCM
Continuous Conduction Mode
DCM
Discontinuous Conduction Mode
DISB
Driver Disable
HS
High Side
LS
Low Side
THWN#
Thermal Warning Flag
ZCD
Zero Current Detection
IL
Inductor Current
Data Sheet
August 5, 2013
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
22 of 23
ZSPM9015
Ultra-Compact, High-Performance, High-Frequency DrMOS Device
7
Ordering Information
Product Sales Code
Description
Package
ZSPM9015ZI1R
ZSPM9015 RoHS-Compliant QFN40 – Junction temperature range: 0°C to 150°C
Reel
ZSPM8015-KIT
Evaluation Kit for ZSPM9015
Kit
8
Related Documents
Document
File Name
ZSPM8015-KIT Evaluation Kit Description
ZSPM8015_Eval_Kit_revX_xy.pdf
Visit ZMDI’s website www.zmdi.com or contact your nearest sales office for the latest version of these documents.
9
Document Revision History
Revision
Date
Description
1.00
April 26, 2013
First release
1.10
August 5, 2013
Minor updates to 1.1. Maximum Absolute Rating: VSWH added; BOOT-PGND
values corrected.
Sales and Further Information
www.zmdi.com
[email protected]
Zentrum Mikroelektronik
Dresden AG
Global Headquarters
Grenzstrasse 28
01109 Dresden, Germany
ZMD America, Inc.
1525 McCarthy Blvd., #212
Milpitas, CA 95035-7453
USA
Central Office:
Phone +49.351.8822.306
Fax
+49.351.8822.337
USA Phone 1.855.275.9634
Phone +1.408.883.6310
Fax
+1.408.883.6358
European Technical Support
Phone +49.351.8822.7.772
Fax
+49.351.8822.87.772
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The
information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer,
licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or
in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any
customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for
any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty,
tort (including negligence), strict liability, or otherwise.
European Sales (Stuttgart)
Phone +49.711.674517.55
Fax
+49.711.674517.87955
Data Sheet
August 5, 2013
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Japan
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Phone +81.3.6895.7410
Fax
+81.3.6895.7301
Phone +886.2.2377.8189
Fax
+886.2.2377.8199
Zentrum Mikroelektronik
Dresden AG, Korea Office
U-space 1 Building
11th Floor, Unit JA-1102
670 Sampyeong-dong
Bundang-gu, Seongnam-si
Gyeonggi-do, 463-400
Korea
Phone +82.31.950.7679
Fax
+82.504.841.3026
© 2013 Zentrum Mikroelektronik Dresden AG — Rev. 1.10
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
23 of 23