Data Sheet

Data Sheet
Rev. 1.01 / July 2014
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Power Management
Power and Precision
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Brief Description
Benefits
The ZSPM4022-12 is a constant-frequency, synchronous DC/DC buck regulator featuring adaptive
on-time control architecture. The ZSPM4022-12
operates over a 4.5V to 19V supply range (12V typical). It has an internal linear regulator that provides a
regulated 5V to power the internal control circuitry.
The ZSPM4022-12 operates at a constant 600kHz
(typical) switching frequency in continuousconduction mode and can be used to provide up to
12A of output current. The output voltage is adjustable from 5.5V down to 0.8V.

Under medium to heavy loads, the ZSPM4022-12
provides high efficiency and ultra-fast transient response via its rapid-control architecture. Under light
load conditions, it maintains high efficiency and a
superior transient response by transitioning to
variable-frequency, discontinuous mode operation
with its ultra-light-load architecture.
The ZSPM4022-12 offers a full suite of protection
features to ensure protection of the IC during fault
conditions. These include under-voltage lockout to
ensure proper operation under power-sag conditions; thermal shutdown; internal soft-start to
reduce inrush current; foldback current limiting; and
“hiccup” mode short-circuit protection. The
ZSPM4022-12 includes a power good (PG) output to
allow simple sequencing.


Ultra-light load efficiency – up to 80% at 10mA
Up to 95% efficiency
Feedback reference accuracy as high as ±1%
Features






Rapid-control architecture enables operation with
a high input/output voltage ratio (e.g., VIN = 19V
and VOUT = 0.8V) and small output capacitance
Adjustable output voltage from 0.8V to 5.5V
Universally compatible with most output
capacitors—stable with zero to high ESR
Power good (PG) output
Foldback current limiting and “hiccup” mode
short-circuit protection
Safe start-up into pre-biased loads
Available Support


Evaluation Kit
Support documentation
Physical Characteristics





Input voltage range: 4.5V to 19V
Output current: up to 12A
Switching frequency: 600kHz
Junction temperature: –40C to +125C
28-pin 5mm  6mm QFN package
ZSPM4022-12 Typical Application
Efficiency (VIN = 12V)
vs. Output Current
100
95
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
EFFICIENCY (%)
90
85
80
75
70
65
60
55
VIN = 12V
50
0
3
6
9
12
15
OUTPUT CURRENT (A)
For more information, contact ZMDI via [email protected]
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01 — July 20, 2014. All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated,
stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
ZSPM4022-12
Functional Diagram
Typical Applications
 Servers, work stations
 Routers, switches, and telecom
equipment
 Base stations
Ordering Information
Product Sales Code
Description
Package
ZSPM4022AA1W12
ZSPM4022-12 QFN28 5mmx6mm — Temperature range: –40C to +125C
7” reel with 1000 ICs
ZSPM4022-12-KIT
Evaluation Kit for ZSPM4022-12, including ZSPM4022-12 Evaluation Board.
Kit
Sales and Further Information
www.zmdi.com
[email protected]
Zentrum Mikroelektronik
Dresden AG
Global Headquarters
Grenzstrasse 28
01109 Dresden, Germany
ZMD America, Inc.
1525 McCarthy Blvd., #212
Milpitas, CA 95035-7453
USA
Central Office:
Phone +49.351.8822.306
Fax
+49.351.8822.337
USA Phone 1.855.275.9634
Phone +1.408.883.6310
Fax
+1.408.883.6358
European Technical Support
Phone +49.351.8822.7.772
Fax
+49.351.8822.87.772
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The
information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer,
licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or
in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any
customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for
any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty,
tort (including negligence), strict liability, or otherwise.
European Sales (Stuttgart)
Phone +49.711.674517.55
Fax
+49.711.674517.87955
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Japan
ZMD FAR EAST, Ltd.
3F, No. 51, Sec. 2,
Keelung Road
11052 Taipei
Taiwan
Phone +81.3.6895.7410
Fax
+81.3.6895.7301
Phone +886.2.2377.8189
Fax
+886.2.2377.8199
Zentrum Mikroelektronik
Dresden AG, Korea Office
U-space 1 Building
11th Floor, Unit JA-1102
670 Sampyeong-dong
Bundang-gu, Seongnam-si
Gyeonggi-do, 463-400
Korea
Phone +82.31.950.7679
Fax
+82.504.841.3026
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01 — July 20, 2014.
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Contents
List of Figures .......................................................................................................................................................... 5
List of Tables ........................................................................................................................................................... 5
1 IC Characteristics ............................................................................................................................................. 6
1.1. Absolute Maximum Ratings ....................................................................................................................... 6
1.2. Operating Conditions ................................................................................................................................. 6
1.3. Electrical Parameters ................................................................................................................................ 7
1.4. Typical Characteristics .............................................................................................................................. 9
1.5. Functional Characteristics ....................................................................................................................... 13
2 Functional Description .................................................................................................................................... 16
2.1. Overview .................................................................................................................................................. 16
2.2. Pin Configuration and Description ........................................................................................................... 17
2.3. Theory of Operation ................................................................................................................................. 19
2.3.1. Continuous Mode .............................................................................................................................. 19
2.3.2. Discontinuous Mode ......................................................................................................................... 22
2.3.3. VDD Regulator .................................................................................................................................. 23
2.3.4. Soft–Start .......................................................................................................................................... 23
2.3.5. Current Limit...................................................................................................................................... 23
2.3.6. Power Good (PG).............................................................................................................................. 23
2.3.7. Internal MOSFET Gate Driver ........................................................................................................... 24
3 Application Information ................................................................................................................................... 25
3.1. External Component Selection ................................................................................................................ 25
3.1.1. Inductor Selection ............................................................................................................................. 25
3.1.2. Output Capacitor Selection ............................................................................................................... 26
3.1.3. Input Capacitor Selection .................................................................................................................. 27
3.1.4. Ripple Injection.................................................................................................................................. 28
3.1.5. Setting the Output Voltage ................................................................................................................ 30
3.2. Thermal Measurements ........................................................................................................................... 32
4 Mechanical Specifications .............................................................................................................................. 33
4.1. Package Dimensions ............................................................................................................................... 33
4.2. Recommended Land Pattern................................................................................................................... 34
5 PCB Layout Guidelines .................................................................................................................................. 34
5.1. ZSPM4022-12.......................................................................................................................................... 34
5.2. Input Capacitor ........................................................................................................................................ 35
5.3. Inductor .................................................................................................................................................... 35
5.4. Output Capacitor ..................................................................................................................................... 35
5.5. Optional RC Snubber .............................................................................................................................. 35
6 Ordering Information ...................................................................................................................................... 36
7 Related Documents ........................................................................................................................................ 36
8 Glossary ......................................................................................................................................................... 36
9 Document Revision History ............................................................................................................................ 37
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
4 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
List of Figures
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 4.1
Functional Diagram ........................................................................................................................... 16
Typical Application Circuit ................................................................................................................. 17
Pin Configuration 28-Pin 5mm  6mm QFN (JL)—Top View ........................................................... 17
ZSPM4022-12 Control Loop Timing –Continuous Mode ................................................................. 21
ZSPM4022-12 Load Transient Response ....................................................................................... 21
ZSPM4022-12 Control Loop Timing –Discontinuous Mode ............................................................ 22
ZSPM4022-12 Current–Limit Foldback Characteristic ..................................................................... 23
Feedback Circuit if Sufficient Ripple is Present at FB for Stable Operation ..................................... 29
Ripple Injection Circuit for Supplementing Inadequate Ripple at FB to Prevent Unstable
Operation .......................................................................................................................................... 29
Ripple Injection Circuit for Preventing Unstable Operation if No Ripple is Present at FB ................ 29
Voltage Divider Configuration ........................................................................................................... 30
Internal Ripple Injection .................................................................................................................... 31
Package Drawing—28-pin 5mm  6mm QFN (JL) Package ........................................................... 33
List of Tables
Table 2.1
Data Sheet
July 20, 2014
Pin Descriptions ................................................................................................................................ 18
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
5 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
1
IC Characteristics
The absolute maximum ratings are stress ratings only. The device might not function or be operable above the
operating conditions given in section 1.2. Stresses exceeding the absolute maximum ratings might also damage
the device. In addition, extended exposure to stresses above the recommended operating conditions might affect
device reliability. ZMDI does not recommend designing to the “Absolute Maximum Ratings.”
1.1.
Absolute Maximum Ratings
PARAMETER
SYMBOL
Voltage PVIN pin to PGND pin
Voltage VIN pin to PGND pin
Voltage PVDD or VDD pin to PGND pin
Voltage SW or CS pin to PGND pin
CONDITIONS
MIN
MAX
UNITS
VPVIN(max)
0.3
+29
V
VIN(max)
0.3
VPVIN
V
VPVDD(max)
VVDD(max)
0.3
+6V
V
VSW(max)
VCS(max)
0.3
(VPVIN +0.3V)
V
0.3
6
V
Voltage BST pin to SW pin
Voltage BST pin to PGND pin
VBST(max)
0.3
35
V
Voltage EN pin to PGND pin
VEN(max)
0.3
(VIN + 0.3V)
V
Voltage FB or PG pin to PGND pin
VFB(max)
VPG(max)
0.3
(VDD + 0.3V)
V
0.3
+0.3
V
+150
°C
+150
°C
260
°C
Voltage PGND pin to SGND pin
Junction Temperature
TJ
Storage Temperature
TS
65
Lead Temperature (soldering, 10s)
ESD Rating
1)
1.2.
1)
Human body model,
1.5kΩ in series with 100pF
V
Devices are ESD sensitive. Handling precautions are recommended.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage (PVIN, VIN pins)
VPVIN, VIN
Bias Voltage (PVDD, VDD pins)
Enable Input
Junction Temperature
1)
QFN28 Package Thermal
1)
Resistance
1)
1000
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
19
V
VPVDD, VDD
4.5
5.5
V
VEN
0
VIN
V
TJ
40
+125
C
JA
Junction to ambient
28
C/W
JC
Junction to case
2.5
C/W
Maximum Power Dissipation PD(MAX) = (TJ(MAX) – TA)/ JA, where JA depends upon the printed circuit layout and TA is the ambient temperature.
See section 3.2.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
6 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
1.3.
Electrical Parameters
Unless noted otherwise, test conditions for typical values are VPVIN = VIN = VEN = 12V; VBST – VSW = 5V; TA = 25°C.
Yellow shaded values indicate that 40°C ≤ TJ ≤ +125°C is a condition requirement.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
19
V
450
750
µA
5
10
µA
Power Supply Input
Input Voltage Range
4.5
VIN, VVPIN
Quiescent Supply Current
IVDD
VFB = 1.5V (non-switching)
Shutdown Supply Current
IVDD
VEN = 0V
VDD
VIN = 7V to 19V, IDD = 40mA
4.8
5
5.4
V
VDD rising
3.7
4.2
4.5
V
VDD Supply Voltage
VDD Output Voltage
VDD UVLO Threshold
VDD UVLO Hysteresis
400
Dropout Voltage (VIN – VDD)
mV
380
IDD = 25mA
600
mV
5.5
V
V
DC/DC Controller
Output-Voltage Adjustment
Range (VOUT)
0.8
Reference
Feedback (FB) Reference
Voltage
0°C ≤ TJ ≤ 85°C
0.792
0.8
0.808
40°C ≤ TJ ≤ 125°C
0.788
0.8
0.812
Load Regulation
IOUT = 3A to 12A (Continuous
Mode)
0.25
%
Line Regulation
VIN = 4.5 to 19V
0.25
%
FB Bias Current
VFB = 0.8V
50
500
nA
Enable Control
1.8
EN Logic Level High
V
0.6
V
6
30
µA
600
750
kHz
EN Logic Level Low
EN Bias Current
VEN = 12V
Oscillator
Switching Frequency
Maximum Duty Cycle
Minimum Duty Cycle
Minimum Off-time
450
fSW
1)
DMAX
VFB = 0V
82
%
DMIN
VFB = 1.0V
0
%
300
ns
3
ms
Soft-Start
Soft-Start time
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
7 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VFB = 0.8V, TJ = 25°C
18.75
21
38.5
A
VFB = 0.8V, TJ = 125°C
17.36
21
38.5
A
Short-Circuit Protection
Current–Limit Threshold
Short–Circuit Current Limit
VFB = 0V
12
A
Internal FETs
Top MOSFET
RDS (ON)
ISW = 3A
13
mΩ
Bottom MOSFET
RDS (ON)
ISW = 3A
5.3
mΩ
SW Leakage Current
VEN = 0V
60
µA
VIN Leakage Current
VEN = 0V
25
µA
95
%VOUT
Power Good
85
92
PG Threshold Voltage
Sweep VFB from Low to High
PG Hysteresis
Sweep VFB from High to Low
5.5
%VOUT
PG Delay Time
Sweep VFB from Low to High
100
µs
PG Low Voltage
Sweep VFB  0.9  VNOM,
IPG = 1mA
70
TJ rising
160
°C
15
°C
200
mV
Thermal Protection
Over-Temperature Shutdown
Over-Temperature Shutdown
Hysteresis
Notes:
1)
The maximum duty–cycle is limited by the fixed mandatory off-time (tOFF ) of 300ns (typical).
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
8 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
1.4.
Typical Characteristics
Note: For graphs marked with an asterisk (*), the die temperature measurement was taken at the hottest point on the
2
ZSPM4022-12 case mounted on a 5 in  0.62 in, four-layer FR-4 PCB with 2oz finish copper weight per layer; see section
3.2. Actual results will depend upon the size of the PCB, ambient temperature, and proximity to other heat emitting
components.
VDD Output Voltage
vs. Input Voltage
1.0
10
0.8
8
VDD VOLTAGE (V)
SUPPLY CURRENT (mA)
VIN Operating Supply Current
vs. Input Voltage
0.6
0.4
VOUT = 1.8V
IOUT = 0A
SWITCHING
0.2
6
4
2
VFB = 0.9V
IDD = 10mA
0
0.0
4
7
10
13
16
4
19
7
INPUT VOLTAGE (V)
0.800
0.796
VOUT = 1.8V
IOUT = 3A
0.792
25
CURRENT LIMIT (A)
TOTAL REGULATION (%)
FEEDBACK VOLTAGE (V)
0.804
0.5%
0.0%
-0.5%
13
INPUT VOLTAGE (V)
July 20, 2014
16
19
20
15
10
5
VOUT = 1.8V
IOUT = 3A to 12A
VOUT = 1.8V
0
-1.0%
Data Sheet
19
30
1.0%
10
16
Output Current Limit
vs. Input Voltage
Total Regulation
vs. Input Voltage
0.808
7
13
INPUT VOLTAGE (V)
Feedback Voltage
vs. Input Voltage
4
10
4
7
10
13
INPUT VOLTAGE (V)
16
19
4
7
10
13
16
INPUT VOLTAGE (V)
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
9 of 37
19
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Typical Characteristics (Continued)
Enable Input Current
vs. Input Voltage
Switching Frequency
vs. Input Voltage
16
650
600
550
VOUT = 1.8V
IOUT = 3A
100%
VPG THRESHOLD/VREF (%)
EN INPUT CURRENT (µA)
700
FREQUENCY (kHz)
PG/VREF Ratio
vs. Input Voltage
12
8
4
95%
90%
85%
VFB = 0.8V
VEN = VIN
0
500
4
7
10
13
16
80%
4
19
7
13
VIN Operating Supply Current
vs. Temperature
19
4
VDD UVLO Threshold
vs. Temperature
VDD THRESHOLD (V)
SUPPLY CURRENT (mA)
10
8
6
4
VIN = 12V
IOUT = 0A
VEN = 0V
50
75
100
-25
0.808
0
25
50
75
100
-50
125
VIN = 12V
VOUT = 1.8V
IOUT = 3A
0.792
50
75
TEMPERATURE (°C)
Data Sheet
July 20, 2014
100
125
25
50
75
100
125
0.4%
0.5%
0.0%
-0.5%
VIN = 12V
VOUT = 1.8V
IOUT =3A to 12A
0.3%
0.2%
0.1%
0.0%
VIN = 4.5V to 19V
VOUT = 1.8V
IOUT = 3A
-0.1%
-0.2%
-1.0%
25
0
Line Regulation
vs. Temperature
LINE REGULATION (%)
0.800
LOAD REGULATION (%)
0.804
0
-25
TEMPERATURE (°C)
1.0%
-25
1
Load Regulation
vs. Temperature
Feedback Voltage
vs. Temperature
-50
2
TEMPERATURE (°C)
TEMPERATURE (°C)
0.796
FALLING
3
0
-50
125
4
HYST
0
0.0
25
19
5
2
0
16
RISING
0.5
-25
13
12
1.0
-50
10
INPUT VOLTAGE (V)
14
VIN = 12V
VOUT = 1.8V
IOUT = 0A
SWITCHING
1.5
7
VIN Shutdown Current
vs. Temperature
2.0
FEEBACK VOLTAGE (V)
16
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
10
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
10 of 37
125
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Typical Characteristics (Continued)
Switching Frequency
vs. Temperature
VDD
vs. Temperature
6
30
VIN = 12V
VOUT = 1.8V
IOUT = 3A
25
CURRENT LIMIT (A)
650
5
VDD (V)
FREQUENCY (kHz)
700
Output Current Limit
vs. Temperature
600
550
4
3
VIN = 12V
VOUT = 1.8V
IOUT = 0A
500
-25
0
25
50
75
100
125
-25
0
TEMPERATURE (°C)
Feedback Voltage
vs. Output Current
VIN = 12V
VOUT = 1.8V
50
75
100
-50
125
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Output Voltage
vs. Output Current
Line Regulation
vs. Output Current
125
1.0%
0.804
0.800
0.796
VIN = 12V
VOUT = 1.8V
LINE REGULATION (%)
1.814
OUTPUT VOLTAGE (V)
1.810
1.805
1.800
1.796
1.791
1.787
2
4
6
8
10
0
12
2
OUTPUT CURRENT (A)
4
6
8
10
0
12
OUTPUT VOLTAGE (V)
650
600
550
VIN = 12V
VOUT = 1.8V
10.5
OUTPUT CURRENT (A)
Data Sheet
July 20, 2014
12
6
8
10
12
100
95
VIN = 5V
VFB < 0.8V
4.6
4.2
3.8
TA
25ºC
85ºC
125º
3.4
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
90
85
80
75
70
65
60
3.0
9
4
Efficiency (VIN = 5V)
vs. Output Current
55
500
7.5
2
OUTPUT CURRENT (A)
5.0
6
VIN = 4.5V to 19V
VOUT = 1.8V
Output Voltage (VIN = 5V)
vs. Output Current
700
4.5
-0.5%
OUTPUT CURRENT (A)
Switching Frequency
vs. Output Current
3
0.0%
-1.0%
1.782
0
0.5%
VIN = 12V
VOUT = 1.8V
EFFICIENCY (%)
FEEDBACK VOLTAGE (V)
25
1.819
0.792
FREQUENCY (kHz)
10
0
-50
0.808
15
5
2
-50
20
VIN = 5V
50
0
3
6
9
12
OUTPUT CURRENT (A)
15
0
3
6
9
12
OUTPUT CURRENT (A)
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
11 of 37
15
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Typical Characteristics (Continued)
IC Power Dissipation (VIN = 5V)
vs. Output Current
Die Temperature* (VIN = 5V)
vs. Output Current
4.0
Efficiency (VIN = 12V)
vs. Output Current
100
100
VIN = 5V
95
3.0
VOUT = 3.3V
2.5
2.0
1.5
VOUT = 0.8V
1.0
60
40
20
3
6
9
75
70
65
VIN = 12V
50
0
12
80
55
0
0
85
60
VIN = 5V
VOUT = 1.8V
0.5
0.0
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
90
80
EFFICIENCY (%)
DIE TEMPERATURE (°C)
POWER DISSIPATION (W)
3.5
2
4
6
8
10
12
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
IC Power Dissipation (VIN = 12V)
vs. Output Current
0
3
6
9
12
OUTPUT CURRENT (A)
Die Temperature* (VIN = 12V)
vs. Output Current
4.5
100
VIN = 12V
3.5
DIE TEMPERATURE (°C)
POWER DISSIPATION (W)
4.0
VOUT = 5V
3.0
2.5
2.0
1.5
VOUT = 0.8V
1.0
80
60
40
20
VIN = 12V
VOUT = 1.8V
0.5
0
0.0
0
3
6
9
OUTPUT CURRENT (A)
Data Sheet
July 20, 2014
12
0
2
4
6
8
10
12
OUTPUT CURRENT (A)
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
12 of 37
15
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
1.5.
Functional Characteristics
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
13 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Functional Characteristics (Continued)
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
14 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Functional Characteristics (Continued)
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
15 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
2
2.1.
Functional Description
Overview
The ZSPM4022-12 is an adaptive on-time synchronous step-down DC/DC regulator with an internal 5V linear regulator and a power good (PG) output. It is designed to operate over a wide input voltage range from 4.5V to 19V
and provides a regulated output voltage at up to 12A of output current. The output voltage is determined by a
resistor divider network as explained in section 3.1.5. An adaptive on-time control scheme is employed to obtain a
constant switching frequency and to simplify the control compensation. Over-current protection is implemented
without the use of an external sense resistor. The ZSPM4022-12 includes an internal soft-start function that
reduces the power supply input surge current at start-up by controlling the output voltage rise time.
Figure 2.1
Data Sheet
July 20, 2014
Functional Diagram
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
16 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Figure 2.2
2.2.
Typical Application Circuit
Pin Configuration and Description
The ZSPM4022-12 is available in a 28-pin 5mm  6mm QFN package. The pin-out is shown in Figure 2.3. The
mechanical drawing of the package is in Figure 4.1.
Figure 2.3
Data Sheet
July 20, 2014
Pin Configuration 28-Pin 5mm  6mm QFN (JL)—Top View
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
17 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Table 2.1
Pin Descriptions
Pin
Name
Description
1
PVDD
5V internal linear regulator output. The PVDD supply is the power MOSFET gate drive supply
voltage, and it is created from VIN by the internal LDO. When VIN  +5.5V, PVDD should be
tied to the PVIN pins. A 2.2µF ceramic capacitor from the PVDD pin to the PGND (pin 2) must
be placed next to the ZSPM4022-12.
2
PGND
3
NC
No connection.
4
SW
Switch node output. This is the internal connection for the high-side MOSFET source and lowside MOSFET drain. Due to the high-speed switching on this pin, the SW pin should be routed
away from sensitive nodes.
5
PGND
See pin 2.
6
PGND
See pin 2.
7
PGND
See pin 2.
8
PGND
See pin 2.
9
SW
See pin 4.
10
SW
See pin 4.
11
SW
See pin 4.
12
SW
See pin 4.
13
PVIN
High-side N-channel internal MOSFET drain connection input. The PVIN operating voltage
range is from 4.5V to 19V. Input capacitors between the PVIN pins and the power ground
(PGND) are required, and these connections must be kept short.
14
PVIN
See pin 13.
15
PVIN
See pin 13.
16
PVIN
See pin 13.
17
PVIN
See pin 13.
18
PVIN
See pin 13.
19
PVIN
See pin 13.
Data Sheet
July 20, 2014
Power ground. PGND is the ground path for the ZSPM4022-12 buck converter power stage.
The PGND pins connect to the ground for the low-side N-channel internal MOSFET gate drive
supply, the source of the low-side MOSFET, the negative terminals of input capacitors, and the
negative terminals of output capacitors. The loop for the power ground should be as small as
possible and separate from the signal ground (SGND) loop.
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
18 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Pin
Name
Description
20
BST
Boost output. This is the bootstrapped voltage to the high-side N-channel MOSFET driver. A
Schottky diode is connected between the PVDD pin and the BST pin. A boost capacitor of
0.1μF is connected between the BST pin and the SW pin. A small resistor can be added at the
BST pin in series with CBST to slow the turn-on time of the high-side N-channel MOSFET.
21
PGND
22
CS
23
SGND
24
FB
Feedback input. This is the input to the transconductance amplifier of the control loop. The FB
pin is regulated to 0.8V. A resistor divider connecting the feedback to the output is used to
adjust the desired output voltage.
25
PG
Power good output (open drain). The PG pin is externally tied to VDD through a 10kΩ pull-up
resistor. A high output is asserted when VOUT  92% of nominal.
26
EN
Enable input. This pin allows logic-level control of the output. This pin is CMOS-compatible.
Logic high = enable, logic low = shutdown. In the off state, the supply current of the device is
greatly reduced (typically 5µA). Do not allow the EN pin to float—either tie the pin high to
enable the ZSPM4022-12 or use a 10kΩ pull-up resistor to VIN for logic-level control.
27
VIN
Power supply voltage input. This pin requires a bypass capacitor to PGND.
28
VDD
5V internal linear regulator output. The VDD supply is the power MOSFET gate drive supply
voltage and the supply bus for the IC. VDD is created by internal LDO from VIN. When VIN 
+5.5V, VDD should be tied to the PVIN pins. A 2.2µF ceramic capacitor from the VDD pin to
SGND pins must be placed next to the ZSPM4022-12.
2.3.
See pin 2.
Current sense input. The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the off-time. The current sensing is required for short-circuit protection. In
order to sense the current accurately, use a Kelvin connection to connect the CS pin to the SW
pin, which is internally connected to the low-side MOSFET drain. The CS pin is also the highside MOSFET’s output driver return.
Signal ground. SGND must be connected directly to the ground planes. Do not route the
SGND pin to the PGND pad on the top layer (see section 5 for details).
Theory of Operation
The ZSPM4022-12 is able to operate in either continuous mode or discontinuous mode. The operating mode is
determined by the output of the zero-cross comparator (ZC) as shown in Figure 2.1.
2.3.1.
Continuous Mode
In continuous mode, the output voltage is sensed by the ZSPM4022-12 feedback pin FB via the voltage divider
R1 and R2, and compared to a 0.8V reference voltage V REF at the error comparator through a low gain
transconductance (gm) amplifier. If the feedback voltage decreases and the output of the g m amplifier is below
0.8V, then the error comparator will trigger the control logic and generate an on-time period.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
19 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
The on-time period length is predetermined by the “FIXED tON ESTIMATE” circuitry:
t ON(estimat ed) 
VOUT
VIN  600kHz
(1)
Where
VOUT = the output voltage
VIN = the power stage input voltage
At the end of the on-time period, the internal high-side driver turns off the high-side MOSFET and the low-side
driver turns on the low-side MOSFET. The off-time period length depends upon the feedback voltage in most
cases. When the feedback voltage decreases and the output of the g m amplifier is below 0.8V, the on-time period
is triggered and the off-time period ends. If the off-time period determined by the feedback voltage is less than the
minimum off-time tOFF(MIN), which is approximately 300ns, then the ZSPM4022-12 control logic will apply the
tOFF(MIN) instead. The tOFF(MIN) is required to maintain enough energy in the boost capacitor (C BST) to drive the highside MOSFET.
The maximum duty cycle is obtained from the 300ns tOFF(min):
Dmax 
t S - t OFF(min)
tS
 1-
300ns
tS
(2)
Where
tS 
1
f SW
For typical f SW  600kHz , t S  1.66ms
Recommendation: Do not use ZSPM4022-12 with an off-time close to tOFF(MIN) during steady-state operation. Also,
as VOUT increases, the internal ripple injection will increase and reduce the line regulation performance. Therefore,
the maximum output voltage of the ZSPM4022-12 should be limited to 5.5V and the maximum external ripple
injection should be limited to 200mV. See section 3.1.5 for more details.
The actual on-time and resulting switching frequency will vary with the part-to-part variation in the rise and fall
times of the internal MOSFETs, the output load current, and variations in the VDD voltage. Also, the minimum t ON
results in a lower switching frequency in applications with a high ratio for VIN to VOUT, such as 18V to 1.0V. For
comparison, the minimum tON measured on the ZSPM4022-12 Evaluation Board is approximately 100ns. During
load transients, the switching frequency is changed due to the varying off-time.
To illustrate the control loop operation, the steady-state and load-transient scenarios are analyzed below.
Figure 2.4 shows the ZSPM4022-12 control loop timing during steady-state operation. During the steady state,
the gm amplifier senses the feedback voltage ripple, which is proportional to the output voltage ripple and the
inductor current ripple, to trigger the on-time period. The on-time is predetermined by the tON estimator. The
termination of the off-time is controlled by the feedback voltage. At the valley of the feedback voltage ripple, which
occurs when VFB falls below VREF, the off-time period ends and the next on-time period is triggered through the
control logic circuitry.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
20 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Figure 2.4
ZSPM4022-12 Control Loop Timing –Continuous Mode
Figure 2.5 shows the operation of the ZSPM4022-12 during a load transient. The output voltage drops due to the
sudden load increase, which causes the VFB to be less than VREF. This will cause the error comparator to trigger
an on-time period. At the end of the on-time period, a minimum off-time tOFF(MIN) is generated to charge CBST since
the feedback voltage is still below VREF. Then, the next on-time period is triggered due to the low feedback
voltage. Therefore, the switching frequency changes during the load transient, but returns to the nominal fixed
frequency once the output has stabilized at the new load current level. With the varying duty cycle and switching
frequency, the output recovery time is fast and the output voltage deviation is small for the ZSPM4022-12
converter.
Figure 2.5
ZSPM4022-12 Load Transient Response
Unlike true current-mode control, the ZSPM4022-12 uses the output voltage ripple to trigger an on-time period.
The output voltage ripple is proportional to the inductor current ripple if the ESR of the output capacitor is large
enough. The ZSPM4022-12 control loop has the advantage of eliminating the need for slope compensation.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
21 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
In order to meet the stability requirements, the ZSPM4022-12 feedback voltage ripple should be in phase with the
inductor current ripple and large enough to be sensed by the g m amplifier and the error comparator. The
recommended feedback voltage ripple is 20mV to 100mV. If a low-ESR output capacitor is selected, then the
feedback voltage ripple might be too small to be sensed by the gm amplifier and the error comparator. Also, the
output voltage ripple and the feedback voltage ripple are not necessarily in phase with the inductor current ripple if
the ESR of the output capacitor is very low. In these cases, ripple injection is required to ensure proper operation.
Please refer to section 3.1.4 for more details about the ripple injection technique.
2.3.2.
Discontinuous Mode
In continuous mode, the inductor current is always greater than zero; however at light loads, the ZSPM4022-12 is
able to force the inductor current to operate in discontinuous mode. Discontinuous mode is where the inductor
current falls to zero, as indicated by trace (IL) shown in Figure 2.6. During this period, the efficiency is optimized
by shutting down all the non-essential circuits and minimizing the supply current. The ZSPM4022-12 wakes up
and turns on the high-side MOSFET when the feedback voltage VFB drops below 0.8V.
The ZSPM4022-12 has a zero crossing comparator that monitors the inductor current by sensing the voltage drop
across the low-side MOSFET during its ON-time. If the VFB > 0.8V and the inductor current goes slightly negative,
then the ZSPM4022-12 automatically powers down most of the IC circuitry and goes into a low-power mode.
Once the ZSPM4022-12 goes into discontinuous mode, both the low-side driver (LSD) and high-side driver (HSD)
are low, which turns off the high-side and low-side MOSFETs. The load current is supplied by the output
capacitors and VOUT drops. If the drop of VOUT causes VFB to go below VREF, then all the circuits will wake up into
normal continuous mode. First, the bias currents of most circuits that had been reduced during the discontinuous
mode are restored, and then a tON pulse is triggered before the drivers are turned on to avoid any possible
glitches. Finally, the high-side driver is turned on. Figure 2.6 shows the control loop timing in discontinuous mode.
Figure 2.6
ZSPM4022-12 Control Loop Timing –Discontinuous Mode
During discontinuous mode, the zero-crossing comparator and the current-limit comparator are turned off. The
bias current of most circuits are reduced. As a result, the total power supply current during discontinuous mode is
only about 450µA, allowing the ZSPM4022-12 to achieve high efficiency in light load applications.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
22 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
2.3.3.
VDD Regulator
The ZSPM4022-12 provides a 5V regulated output for input voltage VIN ranging from 5.5V to 19V. When VIN <
5.5V, VDD should be tied to the PVIN pins to bypass the internal linear regulator.
2.3.4.
Soft–Start
Soft-start reduces the power supply input surge current at startup by controlling the output voltage rise time. The
input surge appears while the output capacitor is charged up. A slower output rise time will draw a lower input
surge current.
The ZSPM4022-12 implements an internal digital soft-start by making the 0.8V reference voltage VREF ramp from
0 to 100% in about 3ms with 9.7mV steps. Therefore, the output voltage is controlled to increase slowly by a
staircase VFB ramp. Once the soft-start cycle ends, the related circuitry is disabled to reduce current consumption.
VDD must be powered up at the same time or after VIN to make the soft-start function correctly.
2.3.5.
Current Limit
The ZSPM4022-12 uses the RDS(ON) of the internal low–side power MOSFET to sense over-current conditions.
This method will avoid adding the cost, board space requirements, and power losses taken by a discrete currentsense resistor. The low-side MOSFET is used because it displays much lower parasitic oscillations during
switching than the high-side MOSFET.
In each switching cycle of the ZSPM4022-12 converter, the inductor current is sensed by monitoring the low-side
MOSFET in the off-time period. If the inductor current is greater than 21A, then the ZSPM4022-12 turns off the
high-side MOSFET and a soft-start sequence is triggered. This mode of operation is called “hiccup mode” and its
purpose is to protect the downstream load in case of a hard short. The load current-limit threshold has a foldback
characteristic related to the feedback voltage as shown in Figure 2.7.
Figure 2.7
2.3.6.
ZSPM4022-12 Current–Limit Foldback Characteristic
Power Good (PG)
The power good (PG) pin is an open drain output which indicates logic high when the output is nominally 92% of
its steady-state voltage. A pull-up resistor 10kΩ should be connected from PG to VDD.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
23 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
2.3.7.
Internal MOSFET Gate Driver
The block diagram (Figure 2.1) shows a bootstrap circuit, consisting of D1 (a Schottky diode is recommended)
and CBST. This circuit supplies energy to the high-side drive circuit. Capacitor CBST is charged while the low-side
MOSFET is on, and the voltage on the SW pin is approximately 0V. When the high-side MOSFET driver is turned
on, energy from CBST is used to turn the MOSFET on. As the high-side MOSFET turns on, the voltage on the SW
pin increases to approximately VIN. Diode D1 is reverse biased and CBST floats high while continuing to keep the
high-side MOSFET on. The bias current of the high-side driver is less than 10mA so a 0.1μF to 1μF is sufficient to
hold the gate voltage with minimal droop for the power stroke (high-side switching) cycle, i.e. ΔBST = 10mA x
1.67μs/0.1μF = 167mV. When the low-side MOSFET is turned back on, CBST is then recharged through D1. A
small resistor, RG, can be placed in series with CBST to slow the turn-on time of the high-side N-channel MOSFET.
The drive voltage is derived from the VDD supply voltage. The nominal low-side gate drive voltage is PVDD and
the nominal high-side gate drive voltage is approximately VDD – VDIODE, where VDIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both MOSFETs.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
24 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
3
Application Information
3.1.
External Component Selection
3.1.1.
Inductor Selection
Values for inductance, peak, and RMS currents are required in order to select the output inductor. The input and
output voltages and the inductance value determine the peak-to-peak inductor ripple current. Generally, higher
inductance values are used with higher input voltages. Larger peak-to-peak ripple currents will increase the power
dissipation in the inductor and MOSFETs. Larger output ripple currents will also require more output capacitance
to smooth out the larger ripple current. Smaller peak-to-peak ripple currents require a larger inductance value and
therefore a larger and more expensive inductor. A good compromise between size, loss, and cost is to set the
inductor ripple current to be equal to 20% of the maximum output current. The inductance value is calculated by
equation (3).
L
VOUT  (VIN(max)  VOUT )
VIN(max)  fsw  20% IOUT(max)
(3)
Where
fSW = switching frequency, 600kHz (nominal)
20% = ratio of AC ripple current to DC output current
VIN(max) = maximum power stage input voltage
The peak-to-peak inductor current ripple is
IL(pp) 
VOUT  (VIN(max)  VOUT )
VIN(max)  fsw  L
(4)
The peak inductor current is equal to the average output current plus one-half of the peak-to-peak inductor current
ripple.
IL(pk) = IOUT(max) + 0.5  ΔIL(pp)
(5)
2
The RMS inductor current is used to calculate the I R losses in the inductor.
IL(RMS)  IOUT(max) 
2
Data Sheet
July 20, 2014
ΔIL(PP)
2
(6)
12
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
25 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. The
high frequency operation of the ZSPM4022-12 requires the use of ferrite materials for all but the most costsensitive applications. Lower cost iron powder cores can be used but the increase in core loss will reduce the
efficiency of the power supply. This is especially noticeable at low output power. The winding resistance
decreases efficiency at the higher output current levels. The winding resistance must be minimized although this
usually comes at the expense of a larger inductor. The power dissipated in the inductor is equal to the sum of the
core and copper losses. At higher output loads, the core losses are usually insignificant and can be ignored. At
lower output currents, the core losses can be a significant contributor. Core loss information is usually available
from the magnetics vendor.
Copper loss in the inductor is calculated by equation (7):
2
PINDUCTOR(Cu) = IL(RMS) × RWINDING
(7)
The resistance of the copper wire, RWINDING, increases with the temperature. The value of the winding resistance
used should be at the operating temperature.
RWINDING(Ht) = RWINDING(20°C) × (1 + 0.0042 × (TH – T20°C))
(8)
Where
TH = temperature of wire under full load
T20°C = ambient temperature
RWINDING(20°C) = room temperature winding resistance (usually specified by the manufacturer)
3.1.2.
Output Capacitor Selection
The type of the output capacitor is usually determined by its equivalent series resistance (ESR). Its voltage and
RMS current capability are two other important factors for selecting the output capacitor. Recommended capacitor
types are ceramic, low–ESR aluminum electrolytic, OS–CON, and POSCAP. The output capacitor’s ESR is
usually the main cause of the output ripple. The output capacitor ESR also affects the control loop from a stability
point of view.
The maximum value of ESR is calculated with equation (9):
ESRCOUT 
ΔVOUT(pp)
(9)
ΔIL(PP)
Where
ΔVOUT(pp) = peak-to-peak output voltage ripple
ΔIL(PP) = peak-to-peak inductor current ripple
The total output ripple is a combination of the ESR and output capacitance. The total ripple is calculated in
equation (10):
2
ΔIL(PP)


  ΔIL(PP)  ESRCOUT
ΔVOUT(pp)  

 COUT  fSW  8 
Data Sheet
July 20, 2014


2
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
(10)
26 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Where
COUT = output capacitance value
fSW = switching frequency
As described in section 2.3, the ZSPM4022-12 requires at least 20mV peak-to-peak ripple at the FB pin to make
the gm amplifier and the error comparator function properly. Also, the output voltage ripple should be in phase with
the inductor current. Therefore, the output voltage ripple caused by the output capacitors value should be much
smaller than the ripple caused by the output capacitor ESR. If low-ESR capacitors, such as ceramic capacitors,
are selected as the output capacitors, a ripple injection method should be applied to provide the enough feedback
voltage ripple. See section 3.1.4 for more details.
The voltage rating of the capacitor should be twice the output voltage for a tantalum capacitor and 20% greater for
aluminum electrolytic or OS-CON capacitors. The output capacitor RMS current is calculated by equation (11):
ICOUT (RMS) 
ΔIL(PP)
(11)
12
The power dissipated in the output capacitor is
PDISS(COUT )  ICOUT (RMS)  ESRCOUT
2
3.1.3.
(12)
Input Capacitor Selection
The input capacitor for the power stage input VIN should be selected for ripple current rating and voltage rating.
Tantalum input capacitors might fail when subjected to high inrush currents caused by turning the input supply on.
A tantalum input capacitor’s voltage rating should be at least two times the maximum input voltage to maximize
reliability. Aluminum electrolytic, OS-CON, and multilayer polymer-film capacitors can handle the higher inrush
currents without voltage de-rating. The input voltage ripple will primarily depend on the input capacitor’s ESR. The
peak input current is equal to the peak inductor current; therefore
ΔVIN = IL(pk) × CESR
(13)
The input capacitor must be rated for the input current ripple. The RMS value of input capacitor current is
determined at the maximum output current. Assuming the peak-to-peak inductor current ripple is low, then
ICIN(RMS)  IOUT(MAX )  D  (1 D)
(14)
Where
D = duty cycle
The power dissipated in the input capacitor is
2
PDISS(CIN) = ICIN(RMS) × ESRCIN
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
(15)
27 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
3.1.4.
Ripple Injection
The VFB ripple required for proper operation of the gm amplifier and error comparator is 20mV to 100mV. However,
the output voltage ripple is generally designed as 1% to 2% of the output voltage. For a low output voltage, such
as a 1V, the output voltage ripple is only 10mV to 20mV, and the feedback voltage ripple is less than 20mV. If the
feedback voltage ripple is so small that the gm amplifier and error comparator cannot sense it, then the
ZSPM4022-12 will lose control and the output voltage is not regulated. In order to have some amount of VFB
ripple, a ripple injection method is applied for low output voltage ripple applications. (Also see section 3.1.5
regarding internal ripple injection.)
Applications are divided into three conditions according to the amount of the feedback voltage ripple:
1. When there is enough ripple at the feedback voltage due to a large ESR for the output capacitors, the
converter will be stable without any ripple injection. In this case, use the circuit shown in Figure 3.1. In this
circuit, the ESR of the output capacitor is shown as a series resistance. The feedback voltage ripple is
ΔVFB(pp) 
R2
 ESRCOUT  ΔIL (pp)
R1  R2
(16)
Where
ΔIL(pp) = the peak-to-peak value of the inductor current ripple
2. When there is inadequate ripple at the feedback voltage due to the small ESR of the output capacitors,
use the circuit shown in Figure 3.2. The output voltage ripple is fed into the FB pin through a feed-forward
capacitor CFF. In this circuit, the typical CFF value is between 1nF and 22nF. With the feed-forward
capacitor, the feedback voltage ripple is very close to the output voltage ripple:
ΔVFB(pp)  ESR  ΔIL (pp)
(17)
3. When there is virtually no ripple at the FB pin voltage due to the very-low ESR of the output capacitors,
use the circuit shown in Figure 3.3. In this situation, the output voltage ripple is less than 20mV; therefore
additional ripple must be injected into the FB pin from the switching node SW via a resistor R INJ and a
capacitor CINJ. The injected ripple is
ΔVFB(PP)  VIN  KDIV  D  (1 - D) 
KDIV 
1
fSW  τ
R1//R2
RINJ  R1//R2
(18)
(19)
Where
VIN = power stage input voltage
D = duty cycle
fSW = switching frequency
τ = (R1//R2//RINJ) × CFF where // indicates components are in parallel; therefore use
the equivalent resistance
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
28 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
Figure 3.1
Feedback Circuit if Sufficient Ripple is Present at FB for Stable Operation
SW
L1
ZSPM4022
R1
FB
COUT
R2
Figure 3.2
ESR
Ripple Injection Circuit for Supplementing Inadequate Ripple at FB to Prevent Unstable Operation
SW
L1
ZSPM4022
R1
FB
CFF
R2
Figure 3.3
COUT
ESR
Ripple Injection Circuit for Preventing Unstable Operation if No Ripple is Present at FB
L1
SW
R1
RINJ CINJ
ZSPM4022
CFF
COUT
FB
R2
ESR
In Equations 18 and 19, it is assumed that the time constant associated with C FF must be much greater than the
switching period tSW :
1
t
 SW  1
fSW  

(20)
If the voltage divider resistors R1 and R2 are in the kΩ range, a C FF of 1nF to 22nF can easily satisfy the large
time constant requirements. Also, a 100nF injection capacitor C INJ is used in order to be considered as short for a
wide range of the frequencies.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
29 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
The process of sizing the ripple injection resistor and capacitors in Figure 3.3 requires three steps:
Step 1
Select CFF to feed all output ripples into the feedback pin and ensure that the large time constant
assumption is satisfied. A typical choice for CFF is 1nF to 22nF if R1 and R2 are in the kΩ range.
Step 2
Select RINJ according to the expected feedback voltage ripple using equation (21):
KDIV 
ΔVFB(PP)
VIN

fSW  τ
D  (1  D)
(21)
Then the value of Rinj is obtained as
RINJ  (R1//R2)  (
Step 3
3.1.5.
1
KDIV
 1)
(22)
Select CINJ as 100nF, which could be considered as a short for a wide range of the frequencies.
Setting the Output Voltage
The ZSPM4022-12 requires two resistors to set the output voltage as shown in Figure 3.4.
Figure 3.4
Voltage Divider Configuration
The output voltage is determined by equation (23):
R1 

VO  VFB  1 

R2 

(23)
Where
VFB = 0.8V
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
30 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
A typical value of R1 can be between 3kΩ and 10kΩ. If R1 is too large, it may allow noise to be introduced into the
voltage feedback loop. If R1 is too small, it will decrease the efficiency of the power supply, especially at light
loads. Once R1 is selected, R2 can be calculated using equation (24):
R2 
VFB  R1
VOUT  VFB
(24)
In addition to the external ripple injection added at the FB pin, internal ripple injection is added at the inverting
input of the comparator inside the ZSPM4022-12, as shown in Figure 3.5. The inverting input voltage VINJ is
clamped to 1.2V. As VOUT is increased, the swing of VINJ will be clamped. The clamped VINJ reduces the line
regulation because it is reflected as a DC error on the FB terminal. Therefore, the maximum output voltage of the
ZSPM4022-12 should be limited to 5.5V to avoid this problem.
Figure 3.5
Data Sheet
July 20, 2014
Internal Ripple Injection
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
31 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
3.2.
Thermal Measurements
Measuring the ZSPM4022-12’s case temperature is recommended to ensure it is within its operating limits.
Although this might seem like a very elementary task, it is easy to get erroneous results. The most common
mistake is to use the standard thermal couple that comes with a thermal meter. This thermal couple wire gauge is
large, typically 22 gauge, and behaves like a heat sink, resulting in a lower case measurement.
The two methods of temperature measurement are using a smaller thermal couple wire or using an infrared
thermometer. If a thermal couple wire is used, it must be constructed of 36 gauge wire or higher (smaller wire
size) to minimize the wire heat-sinking effect. In addition, the thermal couple tip must be covered in either thermal
grease or thermal glue to make sure that the thermal couple junction is making good contact with the case of the
ZSPM4022-12. Omega®* brand thermal couple (5SC-TT-K-36-36) is adequate for most applications.
Wherever possible, an infrared thermometer is recommended. The measurement spot size of most infrared
thermometers is too large for an accurate reading on small form factor ICs. However, an IR thermometer from
†
Optris® has a 1mm spot size, which makes it a good choice for measuring the hottest point on the case. An
optional stand makes it easy to hold the beam on the ZSPM4022-12 for long periods of time.
In addition to the case temperature, ambient temperature, T A, is also of importance in the calculation of power
dissipation using the equation in Note 1 of section 1.2. TA should be measured 1 inch away from the package on
the printed circuit board. This can be measured using a thermocouple or an infrared thermometer.
* Omega® is a trademark of OMEGA Engineering, Inc.
†
Optris® is a trademark of Optris GmbH.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
32 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
4
4.1.
Mechanical Specifications
Package Dimensions
All dimensions are in millimeters.
Figure 4.1
Package Drawing—28-pin 5mm  6mm QFN (JL) Package
Notes:
1. Maximum package warpage is 0.05mm.
2. Maximum allowable burr is 0.076mm in all directions.
3. Pin 1 is on top and will be laser marked.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
33 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
4.2.
Recommended Land Pattern
Red circles in the land pattern represent thermal vias and must be connected to GND plane for maximum thermal
performance.
Green rectangle (with shaded area) indicates solder stencil opening on exposed pad area.
Blue and Magenta colored pads indicate different potentials. DO NOT connect to GND plane.
Thermal Via
5
Via Size/Pitch
Solder Stencil Opening/ Pitch
Red Circle/Black Pad
X
0.300  0.35mm/0.80mm
1.551.20mm/1.75mm
Blue Circle/Black Pad
X
0.300  0.35mm/0.80mm
0.801.11mm/1.31mm
Magenta Circle/Black Pad
X
0.300  0.35mm/0.80mm
0.501.11mm/1.31mm
PCB Layout Guidelines
IMPORTANT WARNING: To minimize EMI and output noise, follow these layout recommendations. PCB
layout is critical to achieve reliable, stable, and efficient performance. A ground plane is required to control EMI
and minimize the inductance in power, signal and return paths. The following guidelines should be followed to
ensure proper operation of the ZSPM4022-12 regulator.
5.1.



ZSPM4022-12
Place the ZSPM4022-12 close to the point-of-load (POL).
Use wide traces to route the input and output power lines.
Keep signal and power grounds separate and connected at only one location.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
34 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator


5.2.







5.3.






5.4.


5.5.
A 2.2µF ceramic capacitor that is connected to the PVDD pin must be located immediately next to the
ZSPM4022-12. The PVDD pin is very noise sensitive and placement of the capacitor is very critical. Use
wide traces to connect to the PVDD and PGND pins.
A 1µF ceramic capacitor must be placed immediately between VDD and the signal ground SGND. The
SGND must be connected directly to the ground planes. Do not route the SGND pin to the PGND Pad on
the top layer.
Input Capacitor
Place the input capacitors on the same side of the board and as close to the ZSPM4022-12 as possible.
Keep both the PVIN pin and PGND connections short.
Place several vias to the ground plane close to the input capacitor ground terminal.
Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors.
Do not substitute any other type of capacitor for the ceramic input capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
If a tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for
switching regulator applications and the operating voltage must be de-rated by 50%.
In “Hot-Plug” applications, a tantalum or electrolytic bypass capacitor must be used to limit the over-voltage
spike seen on the input supply if power is suddenly applied.
Inductor
Keep the connection short between the inductor and the switch node (SW).
Do not route any digital lines underneath or close to the inductor.
Keep the switch node (SW) away from the feedback (FB) pin.
Connect the CS pin directly to the SW pin to accurately sense the voltage across the low-side MOSFET.
To minimize noise, place a ground plane underneath the inductor.
The inductor can be placed on the opposite side of the board with respect to the ZSPM4022-12. It does not
matter whether the IC or inductor is on the top or bottom as long as there is enough airflow to keep the
power components within their temperature limits. The input and output capacitors must be placed on the
same side of the board as the IC.
Output Capacitor
Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal.
The phase margin will change as the output capacitor value and ESR changes. The feedback trace should
be separate from the power trace and connected as close as possible to the output capacitor. Sensing a
long high current load trace can degrade the DC load regulation.
Optional RC Snubber
Place the RC snubber on either side of the board and as close to the SW pin as possible. The intention is to damp
parasitic LC resonators that are responsible for the ringing in the waveform of the signal at the SW pin. This
provides damping by putting a resistor in “parallel” to the oscillating circuit.
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
35 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
6
Ordering Information
Product Sales Code
Description
Package
ZSPM4022AA1W12
ZSPM4022-12 QFN28 5mmx6mm — Temperature range: –40C to +125C
7” reel with 1000 ICs
ZSPM4022-12-KIT
Evaluation Kit for ZSPM4022-12, including ZSPM4022-12 Evaluation Board.
Kit
Visit ZMDI’s website www.zmdi.com or contact your nearest sales office for the latest version of these documents.
7
Related Documents
Note: X.y refers to the current revision of the document.
Document
File Name
ZSPM4022-06 Data Sheet
ZSPM4022-06_Data_Sheet-vX.y.pdf
ZSPM4022-09 Data Sheet
ZSPM4022-09_Data_Sheet-vX.y.pdf
ZSPM4023-06 Data Sheet
ZSPM4023-06_Data_Sheet-vX.y.pdf
ZSPM4023-09 Data Sheet
ZSPM4023-09_Data_Sheet-vX.y.pdf
ZSPM4023-12 Data Sheet
ZSPM4023-12_Data_Sheet-vX.y.pdf
ZSPM4022/4023-KIT Evaluation Kit Manual
ZSPM4022/4023-KIT_Manual.pdf
Visit ZMDI’s website www.zmdi.com or contact your nearest sales office for the latest version of these documents.
8
Glossary
Term
Description
HSD
High-Side Driver
LDO
Low-Dropout Regulator
LSD
Low-Side Driver
UVLO
Under-Voltage Lockout
ZC
Zero-Crossing
Data Sheet
July 20, 2014
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
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prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
36 of 37
ZSPM4022-12
12V/12A Synchronous DC/DC Buck Regulator
9
Document Revision History
Revision
Date
Description
1.00
September 17, 2013
First release of document.
1.01
July 20, 2014
Update for cover imagery.
Update for contact information.
Sales and Further Information
www.zmdi.com
[email protected]
Zentrum Mikroelektronik
Dresden AG
Global Headquarters
Grenzstrasse 28
01109 Dresden, Germany
ZMD America, Inc.
1525 McCarthy Blvd., #212
Milpitas, CA 95035-7453
USA
Central Office:
Phone +49.351.8822.306
Fax
+49.351.8822.337
USA Phone 1.855.275.9634
Phone +1.408.883.6310
Fax
+1.408.883.6358
European Technical Support
Phone +49.351.8822.7.772
Fax
+49.351.8822.87.772
DISCLAIMER: This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Zentrum Mikroelektronik Dresden AG (ZMD AG) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The
information furnished hereby is believed to be true and accurate. However, under no circumstances shall ZMD AG be liable to any customer,
licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or
in any way related to the furnishing, performance, or use of this technical data. ZMD AG hereby expressly disclaims any liability of ZMD AG to any
customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of ZMD AG for
any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty,
tort (including negligence), strict liability, or otherwise.
European Sales (Stuttgart)
Phone +49.711.674517.55
Fax
+49.711.674517.87955
Data Sheet
July 20, 2014
Zentrum Mikroelektronik
Dresden AG, Japan Office
2nd Floor, Shinbashi Tokyu Bldg.
4-21-3, Shinbashi, Minato-ku
Tokyo, 105-0004
Japan
ZMD FAR EAST, Ltd.
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Keelung Road
11052 Taipei
Taiwan
Phone +81.3.6895.7410
Fax
+81.3.6895.7301
Phone +886.2.2377.8189
Fax
+886.2.2377.8199
Zentrum Mikroelektronik
Dresden AG, Korea Office
U-space 1 Building
11th Floor, Unit JA-1102
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Bundang-gu, Seongnam-si
Gyeonggi-do, 463-400
Korea
Phone +82.31.950.7679
Fax
+82.504.841.3026
© 2014 Zentrum Mikroelektronik Dresden AG — Rev. 1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
37 of 37