1/4 STURUCTURE Type Silicon Monolithic Integrated Circuit 6 Channel Switching Regulator control system PRODUCUT SERIES BD９８３９MWV THYSICAL DIMENSIONS BLOCK DIAGRAM FEATURES Fig. 1 (Plastic Mold) Fig. 2 ● Step Down 5CH, Step Up 1CH total 6CH included. ● FET 4ch (CH1~CH4) for Synchronous Switching Regulator ● Short Circuit Protection (SCP) ● Under Voltage Lockout Function (UVLO) ● Thermal Shut Down Function (TSD) ● Independent ON/OFF Function Each Channel(Stand_by Current Is Under 5uA) ● UQFN056V7070 Package Absolute Maximum Ratings（Ta=25℃） Parameter Symbol Limits Units Power Supply Voltage VCC,PVCC1～6 12 V BOOT1～4 17.5 V Lx1～4,OUT5,6 12 V Input Voltage BOOT-Lx Voltage ΔBOOT1～4 6.5 V 420(*1) mW 930(*2) mW Power Dissipation Pd Operating Temperature Topr -30～+85 ℃ Storage Temperature Tstg -55～+125 ℃ Junction Temperature Tjmax 125 ℃ (*1) Without external heat sink, the power dissipation degrades by 4.2mW/℃ above 25℃. (*2)Power dissipation degrades by 9.3mW/℃ above 25℃, when mounted on a PCB (74.2mm×74.2mm×1.6mm). Recommended Operating Conditions（Ta=25℃） Parameter Symbol Spec. Units Min Typ Max VCC,PVCC1～56 4 7 11 V BOOT1～4 3.5 - 16 V BOOT-Lx Voltage ⊿BOOT1～4 3.5 - 5.0 V CH1～4 H NMOS Drain Current Idhnl - - 1.5(*3) A Power Supply Voltage CH1～4 L NMOS Drain Current Idlnl - - 1.5(*3) A Frequency Stability (*4) fosc 300 500 2000 kHz VREGA – GND Capacitor CVREGA 0.47 1.0 2.2 uF VCC – VREGD Capacitor CVREGD 0.47 1.0 2.2 uF BOOT – Lx Capacitor CBOOT 0.047 0.1 0.22 uF (*3) FET Drain Current Max value.Set the current value within Power dissipation in the application. (*4) Max 1MHz for Ch1 ~ Ch4. Status of this document The Japanese language version of this document shall be the official specification. Any translation of this document shall be for reference only. REV. C 2/4 ● Electrical Characteristics （Ta=25℃，VCC=7V，fosc=500kHz with no designation） Parameter Min. Limits Typ. Max. Ｉｓｔ Ｉｃｃ - 0.1 6.0 5 9.0 uA mA FB＝0V ＶＲＥＧＡ DVli ＤＶｌｏ Ｉｏｓ 2.475 -30 2.500 - 2.525 10 10 -5 V mV mV mA VREGA=-1mA VCC=4V～10V、VREGA=-1ｍA VREGA=-1ｍA～-5ｍA VREGA=0V ＶＲＥＧＤ 4.90 5.00 5.10 V ｆｏｓｃ Ｄｆ 450 - 500 0 550 2 kHz % Ｔｏｆｆｍｉｎ１ Ｔｏｆｆｍｉｎ２ Ｔｏｆｆｍｉｎ３ Ｔｏｆｆｍｉｎ４ ＶＳＥＬＨ ＶＳＥＬＬ 2 -0.3 - 100 100 100 100 VCC 0.8 nsec nsec nsec nsec V V Ｖｔ０ Ｖｔ１００ Ｄｍａｘ６ 1.00 81 1.10 1.60 90 1.70 99 V V % ＶＥＴＨ ＶＯＬ ＶＯＨ ＩＳＩＮＫ ＩＳＯＵＲＣＥ ＩＢＩＡＳ ＡＶ ＢＷ 0.790 2.2 1.8 -150 60 1 0.800 0.03 2.4 3.6 -100 -50 80 4 0.810 0.2 -50 - V V V mA uA nA dB MHz INV=0.9V INV=0.7V INV=0.9V、FB=1.25V INV=0.7V、FB=1.25V INV=0V Open loop ｇain ＶＥＴＨ ＶＯＬ ＶＯＨ ＩＳＩＮＫ ＩＳＯＵＲＣＥ ＩＢＩＡＳ ＡＶ ＢＷ 0.990 2.2 1.8 -150 60 1 1.000 0.03 2.4 3.6 -100 -50 80 4 1.010 0.2 -50 - V V V mA uA nA dB MHz INV=1.1V INV=0.9V INV=1.1V、FB=1.25V INV=0.9V、FB=1.25V INV=0V Open loop ｇain ＶＥＴＨ ＶＯＬ ＶＯＨ ＩＳＩＮＫ ＩＳＯＵＲＣＥ ＩＢＩＡＳ ＡＶ ＢＷ 0.285 2.2 1.8 -150 60 1 0.300 0.03 2.4 3.6 -100 -50 80 4 0.315 0.2 -50 - V V V mA uA nA dB MHz INV=0.4V INV=0.2V INV=0.4V、FB=1.25V INV=0.2V、FB=1.25V INV=0V Open loop ｇain ＲＬｘ ＴＵＰＰＥＲ ＴＬＯＷＥＲ ＲｏｎＨ１ ＲｏｎＬ１ ＲｏｎＨ２ ＲｏｎＬ２ ＲｏｎＨ３ ＲｏｎＬ３ ＲｏｎＨ４ ＲｏｎＬ４ ＲｏｎＨ５ ＲｏｎＬ５ ＲｏｎＨ６ ＲｏｎＬ６ 300 - 500 25 25 0.38 0.18 0.28 0.28 0.27 0.22 0.28 0.28 9 9 9 9 700 50 50 0.65 0.31 0.48 0.48 0.46 0.37 0.48 0.48 16 16 16 16 Ω ｎｓｅｃ ｎｓｅｃ Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω ＶＣＴＬＨ ＶＣＴＬＬ ＲＣＴＬ 2 -0.3 250 400 VCC 0.8 700 Ｖ Ｖ kΩ Ｖｓｔｓｃ ＩＳＯＦＴ -1.4 10 -1.0 100 -0.6 ｍV uA Ｖｔｉｍｅ Ｖｔｓｃ Ｉｓｃｐ Ｖｓｔｓｃ 2.1 0.9 -1.4 - 2.2 1.0 -1.0 10 2.3 1.1 -0.6 100 V V uA ｍV ＶＴＨ ＩＢＩＡＳ 0.95 -15 1.0 -10 1.05 -5 V uA SCP1=0V Ｖｓｔｄ１ ⊿Ｖｓｔ Ｖｓｔｄ２ Ｖｓｔｄ３ 3.3 25 1.8 2.8 3.4 100 2.0 3.0 3.5 200 2.2 3.2 V ｍV V V VCC voltage VCC voltage VREGA voltage VREGD voltage Symbol 【Whole Device】 Standby Current Circuit Current 【Reference Voltage】 Output Voltage Line regulation Load regulation Output current at VREGA PIN shorted 【Bias Voltage】 Output Voltage 【Oscillator】 Oscillator Frequency CH1～６ Oscillator Frequency coefficient 【Current Mode Circuit】 Minimum OFF time of H Nch（CH１） Minimum OFF time of H Nch（CH２） Minimum OFF time of H Nch（CH３） Minimum OFF time of H Nch（CH４） SEL control voltage 【PWM Comparator】 ０％Duty threshold（CH5,6） １００％Duty threshold（CH5） MAX Duty ｃｙｃｌｅ ＣＨ６ 【ERRORAMP１】（ＣＨ１） Threshold Voltage Output Voltage Ｌ Output Voltage Ｈ Output Sink Current Output Source Current Input Bias Current Voltage Gain Frequency Bandwidth 【ERRORAMP２】（ＣＨ２～５） Threshold Voltage Output Voltage Ｌ Output Voltage Ｈ Output Sink Current Output Source Current Input Bias Current Voltage Gain Frequency Bandwidth 【ERRORAMP３】（ＣＨ６） Threshold Voltage Output Voltage Ｌ Output Voltage Ｈ Output Sink Current Output Source Current Input Bias Current Voltage Gain Frequency Bandwidth 【Driver 部】 Ｌｘ Pull-down resistor（ＣＨ１～ＣＨ４） Simultaneous off time setting（ＣＨ１～ＣＨ４） H Nch resistor（ＣＨ１） L Nch resistor（ＣＨ１） H Nch resistor（ＣＨ２） L Nch resistor（ＣＨ２） H Nch resistor（ＣＨ３） L Nch resistor（ＣＨ３） H Nch resistor（ＣＨ４） L Nch resistor（ＣＨ４） Output ＯＮ resistor（ＣＨ５） Output ＯＮ resistor（ＣＨ６） Units Condition VREGD=-10ｍA RT=10kΩ、CT=220ｐF、SEL=”L” VCC=4V～10V （ｆｏｓｃ=ｆｏｓｃ/2）（CH1～4） CTL=0V Lx1=-50mA Lx1=50mA Lx2=-50mA Lx2=50mA Lx3=-50mA Lx3=50mA Lx4=-50mA Lx4=50mA IOUT5=-15mA IOUT5=15ｍA IOUT6=-15ｍA IOUT6=15ｍA 【Control Block】 ＣＴＬ vol ＣＴＬ１～６Pull-down resistor 【Soft Start Block】 Standby Voltage Input Charge Current 【Short Circuit Protection (SCP) Timer】 Timer Start Voltage Threshold Voltage Source Current Standby Volatge 【Short Circuit Detective Comparator】 Threshold Voltage Input Bias Current 【Under Volatge Lockout (UVLO)】 Threshold Voltage１ Hysteresis Voltage Threshold Voltage２ Threshold Voltage３ ON OFF REV. C SOFT1～6=0.1V FB1～6 voltage SCP=0.1V 3/4 ● Package BD9839MW LOT No. Fig－１ ● Block Diagram ● Pin Description BOOT1 SOFT1 － SS TIMER Pin No. Pin Name Pin Descriptions Pin No. Pin Name Pin Descriptions 1 SEL CH1～CH4 Oscillator Frequency Cotrol Pin 29 BOOT4 Input Supply Voltage Pin for CH4 Output 2 SOFT1 CH1 Soft Start Delay time Setting Pin with External Capacitor 30 PVCC4 Input Supply Voltage Pin for CH4 Output 3 INV1 CH1Error Amplifier Negative Input Pin 31 Lx4 Pin for Connecting to Inductor PVCC2 4 FB1 CH1 Error Amplifier Output Pin 32 PGND34 Ground Pin for CH3、4 Output Lx2 5 SOFT2 CH2 Soft Start Delay time Setting Pin with External Capacitor 33 PGND34 Ground Pin for CH3、4 Output 6 INV2 CH2 Error Amplifier Negative Input Pin 34 Lx3 Pin for Connecting to Inductor BOOT3 7 FB2 CH2 Error Amplifier Output Pin 35 Lx3 Pin for Connecting to Inductor 8 SOFT3 CH3 Soft Start Delay time Setting Pin with External Capacitor 36 PVCC3 Input Supply Voltage Pin for CH3 Output 9 INV3 CH3 Error Amplifier Negative Input Pin 37 BOOT3 Input Supply Voltage Pin for CH3 Output PVCC1 ERRORAMP1 INV1 CH1 Step Down DC/DC (Current mode) ＋ Lx1(2pin) PGND12(2pin) FB1 BOOT2 ERRORAMP2 － INV2 SOFT2 SS TIMER CH2 Step Down DC/DC (Current mode) ＋ FB2 INV3 SOFT3 PVCC3 ERRORAMP3 － SS TIMER CH3 Step Down DC/DC (Current mode) ＋ Lx3(2pin) PGND34(2pin) FB3 BOOT4 － SS TIMER FB3 CH3 Error Amplifier Output Pin 38 BOOT2 Input Supply Voltage Pin for CH2 Output 11 SOFT4 CH4 Soft Start Delay time Setting Pin with External Capacitor 39 PVCC2 Input Supply Voltage Pin for CH2 Output Pin for Connecting to Inductor PVCC4 ERRORAMP4 INV4 SOFT4 10 CH4 Step Down DC/DC (Current mode) ＋ 12 INV4 CH4 Error Amplifier Negative Input Pin 40 Lx2 13 FB4 CH4 Error Amplifier Output Pin 41 CTL3 CH3 ON/OFF Control Pin 14 SOFT5 CH5 Soft Start Delay time Setting Pin with External Capacitor 42 CTL2 CH2 ON/OFF Control Pin 15 INV5 CH5 Error Amplifier Negative Input Pin 43 CTL1 CH1 ON/OFF Control Pin 16 FB5 CH5 Error Amplifier Output Pin 44 PGND12 Ground Pin for CH1、2 Output 17 SOFT6 CH6 Soft Start Delay time Setting Pin with External Capacitor 45 PGND12 Ground Pin for CH1、2 Output 18 INV6 CH6 Error Amplifier Negative Input Pin 46 Lx1 Pin for Connecting to Inductor 19 FB6 CH6 Error Amplifier Output Pin 47 Lx1 Pin for Connecting to Inductor 20 SCP1 Short Detective Comparator Negative Input Pin 48 PVCC1 Input Supply Voltage Pin for CH1Output 21 SCP Short Circuit Protection Delay time Setting Pin with External Capacitor 49 BOOT1 Input Supply Voltage Pin for CH1Output 22 OUT6 CH6 NchFET Driver Output Pin 50 VREGD Bias Output Voltage Pin 23 PGND56 Ground Pin for CH5、6 Driver 51 VCC Input Supply Voltage Pin Lx4 FB4 ERRORAMP5 INV5 SOFT5 － SS TIMER PVCC56 CH5 Step Down DC/DC (Voltage mode) ＋ OUT5 PGND56 FB5 ERRORAMP6 － INV6 SOFT6 SS TIMER CH6 Step Up DC/DC (Voltage mode) ＋ OUT6 FB6 PROTECTION SCP1 SCP SCP TIMER － － － － － － ＋ 2.2V CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 VREGA VCC 24 OUT5 Output Pin for CH5 PchFET Driver 52 VREGA Reference Output Voltage Pin 25 PVCC56 Input Supply Voltage Pin for CH5、6 Driver 53 GND Ground Pin Slope Setting Pin with external Resistor 26 CTL6 CH6 ON/OFF Control Pin 54 SLOPE 27 CTL5 CH5 ON/OFF Control Pin 55 RT Oscillator Frequency Adjustment Pin with external Resistor CT Oscillator Frequency Adjustment Pin with external Capacitor UVLO SHUT DOWN 28 VREGD OSC CTL4 GND RT CT SLOPE SEL VREGA VREGD Fig－２ REV. C CH4 ON/OFF Control Pin 56 4/4 ● Operation Notes １.) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. ２.) GND potential Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. ３.) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. ４.) Inter-pin shorts and mounting errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC. ５.) Operation in a strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. ６.) Common impedance Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance). ７.) Voltage of CTL pin The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V. The region between 0.8V and 2.0V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. ８.) Thermal shutdown circuit (TSD circuit) This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed. ９.) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. It is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and each pin. 10.) Relationship between PVCC - VCC Because diode was connecting between PVCC (Anode) – VCC (Cathode) for prevent electrostatic breakdown, it must be set PVCC – VCC < 0.3V voltage relationship. 11.) Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentaly rush current at the time of power supply injection. Because there exists inside logic uncertainty state. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. 12.) Please use it so that VCC and PVCC terminal should not exceed the absolute maximum ratings. Ringing might be caused by L element of the pattern according to the position of the input capacitor, and ratings be exceeded. Please will assume the example of the reference ,the distance of IC and capacitor, use it by 5.0mm or less when thickness of print pattern are 35um, pattern width are 1.0mm. 13.) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 14.) IC pin input This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart, the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins. Resistance Transistor ( NPN) (PinA) Ｅ Ｃ Ｎ Ｐ Ｎ Ｐ ＋ Ｐ Ｎ Ｐ ＋ Ｎ P substrate Ｎ ＋ Parasitic diode ＧＮＤ Ｐ Ｐ Ｎ ＧＮＤ (PinB) ＋ Ｎ P substrate ＧＮＤ Parasitic diode (PinA) Ｂ (PinB) Ｂ Ｃ Ｅ ＧＮＤ Parasitic elementals Other adiacent components REV. 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