1/4 Structure Silicon Monolithic Integrated Circuit Product Name Power supply for CCD camera of mobile phone Type BD6029GU Features A system power supply for the CCD camera module o ○Absolute Maximum Ratings (Ta=25 C ) Parameter Symbol Rating Unit Maximum Applied Voltage 1 VMAX1 20(*1) V Maximum Applied Voltage 2 VMAX2 18(*2) V Maximum Applied Voltage 3 VMAX3 -13.5(*3) V Maximum Applied Voltage 4 VMAX4 6(*4) V Power Dissipation Pd 1925(*5) mW o Operating Temperature Range Topr -30 to 85 C o Storage Temperature Range Tstg -55 to 150 C (* 1) SW，VPLUS1，VPLUS2 pin (* 2) VDD3 pin (* 3) VDD4 pin (* 4) Except *1~*3 pin (* 5) Power dissipation deleting is 15.4mW/ oC, when it’s used in over 25 oC. (It’s deleting is on the board that is ROHM’s standard) Condition o ○Operating conditions (VBAT≥VIO, Ta=-30 to 85 C) Rating Min. Typ. Max. VBAT power supply voltage VBAT 2.7 3.6 5.5 VIO power supply voltage VIO 1.62 3.0 3.3 This product isn’t designed to protect itself against radioactive rays. Parameter Symbol REV. A Unit V V Condition 2/4 ○Electrical Characteristics Unless otherwise specified, Ta=25 oC, VBAT=3.6V, VIO=1.8V/3.0V Parameter Symbol Min. Spec Typ. Max. Unit Condition Circuit Current VBAT Circuit current 1 VBAT Circuit current 2 VBAT Circuit current 3 VBAT Circuit current 4 VBAT Circuit current 5 VBAT Circuit current 6 VBAT Circuit current 7 IBAT1 IBAT2 IBAT3 IBAT4 IBAT5 IBAT6 IBAT7 - 0.1 0.5 90 90 90 90 90 3.0 3.0 135 135 135 135 135 μA μA μA μA μA μA μA VBAT Circuit current 8 IBAT8 - 9 14 mA -8.4 -7.9 -7.4 -8.0 -7.5 -7.0 -7.6 -7.1 -6.6 V V V Io=100mA Io=100mA Io=100mA 1.140 1.746 1.20 1.80 1.260 1.854 V V Io=150mA Io=150mA 2.619 2.910 3.201 2.70 3.00 3.30 2.781 3.090 3.399 V V V Io=150mA Io=150mA Io=150mA 14.05 14.55 12.55 14.5 15.0 13.0 14.95 15.45 13.45 V V V Io=60mA Io=60mA Io=60mA 1.746 2.910 1.80 3.00 1.854 3.090 V V Io=150mA Io=150mA 2.910 3.007 3.104 3.201 3.00 3.10 3.20 3.30 3.090 3.193 3.296 3.399 V V V V Io=200mA Io=200mA Io=200mA Io=200mA 1.746 2.910 3.201 1.80 3.00 3.30 1.854 3.090 3.399 V V V Io=150mA Io=150mA Io=150mA SWREG4（Inverted DC/DC） Output voltage 1 VoND1 Output voltage 2 VoND2 Output voltage 3 VoND3 REG1 （1.2V/1.8V LDO） Output voltage 1 Vo11 Output voltage 2 Vo12 REG2 （2.7V/3.0V/3.3V LDO） Output voltage 1 Vo21 Output voltage 2 Vo22 Output voltage 3 Vo23 REG3 （15V/14.5V/13V LDO） Output voltage 1 Vo31 Output voltage 2 Vo32 Output voltage 3 Vo33 REG5 （1.8V/3.0V LDO） Output voltage 1 Vo51 Output voltage 2 Vo52 REG6 （3.0V/3.1V/3.2V/3.3V LDO） Output voltage 1 Vo61 Output voltage 2 Vo62 Output voltage 3 Vo63 Output voltage 4 Vo64 REGA （1.8V/3.0V/3.3V LDO） Output voltage 1 VoA1 Output voltage 2 VoA2 Output voltage 3 VoA3 REV. A RST=0V, VIO=0V RST=0V REG1:ON, Io=0mA REG2:ON, Io=0mA REG5:ON, Io=0mA REG6:ON, Io=0mA REGA:ON, Io=0mA SWREG3:ON,REG3:ON, SWREG4:ON, Io=0mA 3/4 ○External dimensions ○Terminals Type PIN PIN Name A1 BD6029 LOT No. VCSP85H4 (48PIN) PIN T1 PIN Name D1 VDD2 GND1 D2 SCL H2 VDD3 VBATN2 D7 VBAT3 H3 VPLUS1 A4 SENSN1 D8 VDD1 H4 GNDP A5 TRSW E1 GND7 H5 MONR2 A6 GND2 E2 SDA H6 SW A7 VDD4 E7 VREF H7 GND6 A8 T2 E8 GND5 H8 T3 B1 MVDD2 F1 RST B2 MVDD1 F2 VIO B3 VBATN1 F7 VBAT4 B4 SENSN2 F8 VDD5 B5 VBAT1 G1 TESTI1 B6 GND3 G2 TESTI2 B7 TESTO1 G3 VPLUS2 GNDPS B8 GND4 G4 C1 VBAT6 G5 MONR1 C2 VBAT7 G6 VBAT5 C7 VBAT2 G7 TESTO2 C8 VDD6 G8 AVDD VPLUS2 VPLUS1 GNDPS MONR1 GNDP MONR2 SW VBAT1 0.08Ω VBAT3 Current Sense REG3 VBAT7 - REG1 1.2V / 1.8V Iomax=150mA + Control VDD3 15V / 14.5V / 13V Iomax=60mA Over Voltage Limit S Q R VBAT6 - + Driver VBAT5 VDD1 T2 REG2 2.7V / 3.0V / 3.3V Iomax=150mA OSC T3 + - T1 - VDD2 Feed Back REG5 + VDD5 1.8V / 3.0V Iomax=150mA T4 SWREG3 REGA 1.8V / 3.0V / 3.3V Iomax=150mA VREF VREF AVDD REG6 3.0V /3.1V / 3.2V / 3.3V Iomax=200mA VDD6 VIO MVDD1 MVDD2 RST CONT SDA 2 IC SWREG4 VBATN2 Current Sense - SCL VBATN1 0.08Ω + SENSN1 OSC SENSN2 TESTO1 + TESTO2 - R Control Q Driver TRSW S Over Voltage Limit TESTI1 + TESTI2 - GND7 + GND6 GND5 GND4 GND3 GND2 GND1 TSD REV. A PIN Name T4 A3 ○Block diagram VBAT4 H1 A2 (Unit : mm) VBAT2 PIN VDD4 4/4 ○Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and GND line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and GND lines. Especially, when there are GND pattern for small signal and GND pattern for large current included the external circuits, please separate each GND pattern. Furthermore, for all power supply terminals to LSI, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. ( except for VDD4 terminal ) (4) Short circuit between terminals and erroneous mounting In order to mount LSI on a set PCB, pay thorough attention to the direction and offset of the LSI. Erroneous mounting can break down the LSI. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the LSI can break down. (5) Operation in strong electromagnetic field Be noted that using LSI in the strong electromagnetic field can malfunction them. (6) Input terminals In terms of the construction of LSI, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the LSI. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (8) Thermal shutdown circuit (TSD) This LSI builds in a thermal shutdown (TSD) circuit. When junction temperatures become detection temperature or higher, the thermal shutdown circuit operates and turns a switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (9) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. (10) LDO Use each output of LDO by the independence. Don’t use under the condition that each output is short-circuited because it has the possibility that a operation becomes unstable. (11) DC/DC converter Please select the low DCR inductors to decrease power loss for DC/DC converter. (12) About the pin for the test, the un-use pin Prevent a problem from being in the pin for the test and the un-use pin under the state of actual use. Please refer to a function manual and an application notebook. And, as for the pin that doesn't specially have an explanation, ask our company person in charge. (13) About the rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of wiring. (14) About the function description or application note or more. The function description and the application notebook are the design materials to design a set. So, the contents of the materials aren't always guaranteed. Please design application by having fully examination and evaluation include the external elements. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. 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