HM64YLB36514 Series
16M Synchronous Late Write Fast Static RAM
(512-kword × 36-bit, Register-Latch Mode)
REJ03C0039-0001Z
Preliminary
Rev.0.10
May.15.2003
Description
The HM64YLB36514 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized
high speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
• 2.5 V ± 5% operation and 1.5 V (VDDQ)
• 16M bit density
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• Differential pseudo-HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single differential clock register-latch mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology's Sales Dept. regarding specifications.
Rev.0.10, May.15.2003, page 1 of 22
HM64YLB36514 Series
Ordering Information
Type No.
Organization
Access time
Cycle time Package
HM64YLB36514BP-6H
512k × 36
5.5 ns
6.5 ns
119-bump 1.27 mm
14 mm × 22 mm BGA (BP-119E)
Pin Arrangement
1
2
3
4
A
VDDQ
SA14
SA13
NC
B
NC
SA15
SA12
NC
5
6
7
SA6
SA7
VDDQ
SA5
SA9
NC
C
NC
SA16
SA11
VDD
SA4
SA8
NC
D
DQc7
DQc8
VSS
ZQ
VSS
DQb8
DQb7
E
DQc5
DQc6
VSS
SS
VSS
DQb6
DQb5
F
VDDQ
DQc4
VSS
G
VSS
DQb4
VDDQ
G
DQc3
DQc2
SWEc
NC
SWEb
DQb2
DQb3
H
DQc1
DQc0
VSS
NC
VSS
DQb0
DQb1
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd1
DQd0
VSS
K
VSS
DQa0
DQa1
L
DQd3
DQd2
SWEd
K
SWEa
DQa2
DQa3
M
VDDQ
DQd4
VSS
SWE
VSS
DQa4
VDDQ
N
DQd5
DQd6
VSS
SA17
VSS
DQa6
DQa5
P
DQd7
DQd8
VSS
SA0
VSS
DQa8
DQa7
R
NC
SA10
M1
VDD
M2
SA1
NC
T
NC
NC
SA18
SA3
SA2
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
(Top view)
Rev.0.10, May.15.2003, page 2 of 22
Rev.0.10, May.15.2003, page 3 of 22
ZQ
G
K
SWE
SS
(x: a to d)
SWEx
SA0 to SA18
SWE
reg.
SS
reg.
SWEx
1st reg.
Read
add. reg.
SWEx
2nd reg.
SA0 to SA18
compare
Write
add. reg.
Impedance
control
Byte write
control
0
1
Output
latch
0 1
Output enable
Match0
Memory array
(way0)
512k × 36
DQxn
(x: a to d,
n: 0 to 8)
Din
reg.
HM64YLB36514 Series
Block Diagram
HM64YLB36514 Series
Pin Descriptions
Name
I/O type
Descriptions
VDD
Supply
Core power supply
VSS
Supply
Ground
VDDQ
Supply
Output power supply
VREF
Supply
Input reference, provides input reference voltage
K
Input
Clock input, active high
K
Input
Clock input, active low
SS
Input
Synchronous chip select
SWE
Input
Synchronous write enable
Notes
SAn
Input
Synchronous address input
n: 0 to 18
SWEx
Input
Synchronous byte write enables
x: a to d
G
Input
Asynchronous output enable
ZZ
Input
Power down mode select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous data input/output
x: a to d
n: 0 to 8
M1, M2
Input
Output protocol mode select
TMS
Input
Boundary scan test mode select
TCK
Input
Boundary scan test clock
TDI
Input
Boundary scan test data input
TDO
Output
Boundary scan test data output
NC
No connection
M1
M2
Protocol
Notes
VDD
VSS
Synchronous register to latch operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or
open, output buffer impedance will be maximum.
2. There is 1 protocol with mode control input pins (M1, M2). These mode pins are to be tied either
VDD or VSS respectively.
These mode pins are set at power-up and will not change the states during the SRAM operates.
This SRAM is tested only in the synchronous register to latch operation.
Rev.0.10, May.15.2003, page 4 of 22
HM64YLB36514 Series
Truth Table
ZZ
SS
G
SWE
SWEa
SWEb
SWEc
SWEd
K
K
Operation
DQ (n)
DQ (n+1)
H
×
×
×
×
×
×
×
×
×
Sleep
mode
High-Z
High-Z
L
H
×
×
×
×
×
×
L-H
H-L
Dead
(not
selected)
High-Z
×
L
×
H
H
×
×
×
×
×
×
Dead
(dummy
read)
High-Z
High-Z
L
L
L
H
×
×
×
×
L-H
H-L
Read
DOUT
(a, b,
c, d)
0 to 8
×
L
L
×
L
L
L
L
L
L-H
H-L
Write
a, b, c, d
byte
High-Z
DIN
(a, b, c, d)
0 to 8
L
L
×
L
H
L
L
L
L-H
H-L
Write
b, c, d
byte
High-Z
DIN
(b, c, d)
0 to 8
L
L
×
L
L
H
L
L
L-H
H-L
Write
a, c, d
byte
High-Z
DIN
(a, c, d)
0 to 8
L
L
×
L
L
L
H
L
L-H
H-L
Write
a, b, d
byte
High-Z
DIN
(a, b, d)
0 to 8
L
L
×
L
L
L
L
H
L-H
H-L
Write
a, b, c
byte
High-Z
DIN
(a, b, c)
0 to 8
L
L
×
L
H
H
L
L
L-H
H-L
Write
c, d byte
High-Z
DIN (c, d)
0 to 8
L
L
×
L
L
H
H
L
L-H
H-L
Write
a, d byte
High-Z
DIN (a, d)
0 to 8
L
L
×
L
L
L
H
H
L-H
H-L
Write
a, b byte
High-Z
DIN (a, b)
0 to 8
L
L
×
L
H
L
L
H
L-H
H-L
Write
b, c byte
High-Z
DIN (b, c)
0 to 8
L
L
×
L
H
H
H
L
L-H
H-L
Write
d byte
High-Z
DIN (d)
0 to 8
L
L
×
L
H
H
L
H
L-H
H-L
Write
c byte
High-Z
DIN (c)
0 to 8
L
L
×
L
H
L
H
H
L-H
H-L
Write
b byte
High-Z
DIN (b)
0 to 8
L
L
×
L
L
H
H
H
L-H
H-L
Write
a byte
High-Z
DIN (a)
0 to 8
Notes: 1. H: VIH, L: VIL, ×: VIH or VIL
2. SWE, SS, SWEa to SWEd, and SA are sampled at the rising edge of K clock.
Rev.0.10, May.15.2003, page 5 of 22
HM64YLB36514 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable value of RQ to
guarantee impedance matching with a tolerance of 15% is 250 Ω. If the status of ZQ pin is open, output
impedance is maximum value. Maximum impedance also occurs with ZQ connected to VDDQ. The
impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations
will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. The user
may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock, to
guarantee the proper update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the
impedance to be completely updated.
Rev.0.10, May.15.2003, page 6 of 22
HM64YLB36514 Series
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
Input voltage on any pin
VIN
−0.5 to VDDQ + 0.5
V
1, 4
Core supply voltage
VDD
−0.5 to +3.13
V
1
Output supply voltage
VDDQ
−0.5 to +2.1
V
1, 4
Operating temperature
TOPR
0 to +85
°C
Storage temperature
TSTG
−55 to +125
°C
Output short-circuit current
IOUT
25
mA
Latch up current
ILI
200
mA
Package junction to top thermal resistance
θJ-top
6.5
°C/W
5
Package junction to board thermal resistance
θJ-board
12
°C/W
5
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional
operation should be restricted the operation conditions. Exposure to higher voltages than
recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V,
whatever the instantaneous value of VDDQ.
5. See figure below.
θJ-top
θJ-board
Thermocouple
Thermo grease
Water
Teflon block
Water
Cold plate
Thermocouple
SRAM
SRAM
Water
Teflon block
JEDEC/2S2P BGA
Thermal board
Rev.0.10, May.15.2003, page 7 of 22
Thermo grease
Water
Cold plate
JEDEC/2S2P
Thermal board
BGA
HM64YLB36514 Series
Note: The following DC and AC specifications shown in the tables, this device is tested under the
minimum transverse air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions (Ta = 0 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Power supply voltage: core
VDD
2.38
2.50
2.63
V
Power supply voltage: I/O
VDDQ
1.40
1.50
1.60
V
Input reference voltage: I/O
VREF
0.70
0.75
0.80
V
1
Input high voltage
VIH
VREF + 0.15
VDDQ + 0.50
V
4
Input low voltage
VIL
−0.50
VREF − 0.15
V
4
Clock differential voltage
VDIF
0.10
VDDQ + 0.30
V
2, 3
Clock common mode voltage
VCM
0.90
1.30
V
3
Notes: 1.
2.
3.
4.
Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
Minimum differential input voltage required for differential input clock operation.
See figure below.
VREF = 0.75 V (typ).
Differential Voltage / Common Mode Voltage
VDDQ
VDIF
VCM
VSS
Rev.0.10, May.15.2003, page 8 of 22
HM64YLB36514 Series
DC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Parameter
Symbol
Min
Max
Unit
Notes
Input leakage current
ILI
2
µA
1
Output leakage current
ILO
5
µA
2
Standby current
ISBZZ
150
mA
3
VDD operating current, excluding output drivers
IDD
350
mA
4
Quiescent active power supply current
IDD2
200
mA
5
Maximum power dissipation, including output drivers
P
2.3
W
6
Parameter
Symbol
Min
Typ
Max
Output low voltage
VOL
VSS
VSS + 0.4
V
7
Output high voltage
VOH
VDDQ − 0.4
VDDQ
V
8
ZQ pin connect resistance
RQ
250
Ω
Output “Low” current
IOL
(VDDQ/2)/{(RQ/5) − 15%}
(VDDQ/2)/{(RQ/5) + 15%} mA 9, 11
Output “High” current
IOH
(VDDQ/2)/{(RQ/5) + 15%}
(VDDQ/2)/{(RQ/5) − 15%} mA 10, 11
Unit Notes
Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin)
2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z
3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification
is guaranteed at +75°C junction temperature.
4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle
5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz
6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the
SRAM designer to determine electrical and package requirements for the SRAM device.
7. RQ = 250 Ω, IOL = 6.8 mA
8. RQ = 250 Ω, IOH = −6.8 mA
9. Measured at VOL = 1/2 VDDQ
10. Measured at VOH = 1/2 VDDQ
11. The total external capacitance of ZQ pin must be less than 7.5 pF.
Rev.0.10, May.15.2003, page 9 of 22
HM64YLB36514 Series
AC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Single Differential Clock Register-Latch Mode
HM64YLB36514BP
-6H
Parameter
Symbol
Min
Max
Unit
CK clock cycle time
tKHKH
6.5
ns
CK clock high width
tKHKL
1.2
ns
CK clock low width
tKLKH
1.2
ns
Address setup time
tAVKH
0.4
ns
2
Data setup time
tDVKH
0.4
ns
2
Address hold time
tKHAX
1.0
ns
Data hold time
tKHDX
1.0
ns
Clock high to output valid
tKHQV
1.7
5.5
ns
Clock low to output valid
tKLQV
0.5
2.3
ns
Clock low to output hold
tKLQX
0.5
ns
Clock low to output low-Z (SS control)
tKLQX2
0.5
ns
1, 4, 6
Clock high to output high-Z
tKHQZ
0.5
2.3
ns
1, 3, 6
Output enable low to output low-Z
tGLQX
0.1
ns
1, 4, 6
Output enable low to output valid
tGLQV
2.3
ns
1, 4
Output enable high to output high-Z
tGHQZ
2.3
ns
1, 3
Sleep mode recovery time
tZZR
20.0
ns
5
Sleep mode enable time
tZZE
15.0
ns
1, 3, 5
Notes: 1.
2.
3.
4.
5.
6.
Notes
1
See figure in ”AC Test Conditions”.
Parameters may be guaranteed by design, i.e., without tester guardband.
Transitions are measured ±50 mV of output high impedance from output low impedance.
Transitions are measured ±50 mV from steady state voltage.
When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
Minimum value is verified by design and tested without guardband.
Rev.0.10, May.15.2003, page 10 of 22
HM64YLB36514 Series
Timing Waveforms
Read Cycle-1
tKHKH
K,
tKHKL
tKLKH
K
tAVKH
SA
A1
tKHAX
A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
A4
SS
SWE
SWEx
tKHQV
DQ
Q0
Q1
tKLQX
Q2
Q3
tKLQV
Note: ZZ = VIL
Read Cycle-2 (SS Controlled)
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A4
A3
tAVKH tKHAX
SS
tAVKH tKHAX
SWE
SWEx
DQ
tKHQV
tKHQZ
Q0
Q1
Note: ZZ = VIL
Rev.0.10, May.15.2003, page 11 of 22
tKLQX2
Q3
HM64YLB36514 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
A4
SS
SWE
SWEx
G
tGHQZ
DQ
Q0
Q1
tGLQX
Q2
Q3
tGLQV
Note: ZZ = VIL
Write Cycle
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A2
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
tDVKH
tKHDX
A3
A4
D2
D3
SS
SWE
SWEx
G
DQ
D0
Note: ZZ = VIL
Rev.0.10, May.15.2003, page 12 of 22
D1
HM64YLB36514 Series
Read-Write Cycle-1
READ
tKHKH
WRITE
READ
DEAD
WRITE
(SS control)
READ
tKHKL tKLKH
K, K
tAVKH
SA
A2
A1
tKHAX
A3
A4
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
A6
A7
SS
SWE
SWEx
G
tGHQZ tDVKH tKHDX tGLQV
tKHQV
DQ
Q0
tKLQX
tKLQV
Q1
Q2
D3
D6
Q4
tGLQX tKHQZ
Note: ZZ = VIL
Read-Write Cycle-2
READ
tKHKH
WRITE
READ
READ
tKHKL tKLKH
DEAD
WRITE
(SS control)
K, K
tAVKH
SA
A2
A1
tKHAX
A3
A4
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
A5
A6
A7
SS
SWE
SWEx
G
DQ
Low fixed
tKHQZ tDVKH tKHDX
tKHQV
Q0
tKLQX
tKLQV
Q1
Q2
D3
Q4
D6
tKLQV tKHQZ
Note: G, ZZ = VIL
During this period DQ pins are in the output state so that the input signal of opposite phase to the
outputs must not be applied.
Rev.0.10, May.15.2003, page 13 of 22
HM64YLB36514 Series
ZZ Control
tKHKH
tKHKL tKLKH
tAVKH
tKHAX
K, K
SA
A1
tAVKH
tKHAX
tAVKH
tKHAX
SS
SWE
SWEx
ZZ Sleep active
Sleep off
Sleep active
Q1
DQ
tZZR
Rev.0.10, May.15.2003, page 14 of 22
tZZE
HM64YLB36514 Series
Input Capacitance (VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Min Max Unit Pin name
Notes
Input capacitance
CIN
4
pF
SAn, SS, SWE, SWEx
1, 3
Clock input capacitance
CCLK
5
pF
K, K
1, 2, 3
I/O capacitance
CIO
5
pF
DQxn
1, 3
Notes: 1. This parameter is sampled and not 100% tested.
2. Exclude G
3. Connect pins to GND, except VDD, VDDQ, and the measured pin.
AC Test Conditions
Parameter
Symbol
Conditions
Unit
Input and output timing reference levels
VREF
0.75
V
Input signal amplitude
VIL, VIH
0.25 to 1.25
V
Input rise / fall time
tr, tf
0.5 (10% to 90%)
ns
Clock input timing reference level
Differential cross point
VDIF to clock
0.75
V
VCM to clock
1.10
V
Output loading conditions
See figure below
Note
Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V.
Output Loading Conditions
16.7 Ω
0.75 V
16.7 Ω
DQ
50 Ω
50 Ω
5 pF
16.7 Ω
50 Ω
50 Ω
0.75 V
5 pF
0.75 V
Rev.0.10, May.15.2003, page 15 of 22
HM64YLB36514 Series
Boundary Scan Test Access Port Operations
Overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 1990. But does not implement all of the functions required for 1149.1 compliance the HM64YLB series
contains a TAP controller. Instruction register, boundary scans register, bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
Test clock
TMS
Test mode select
TDI
Test data in
TDO
Test data out
Note: This device does not have a TRST (TAP reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected.
To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V.
TAP DC Operating Characteristics (Ta = 0 to +85°C)
Parameter
Symbol
Min
Max
Boundary scan input high voltage
VIH
1.4 V
3.6 V
Boundary scan input low voltage
VIL
−0.3 V
0.8 V
Boundary scan input leakage current
ILI
−10 µA
+10 µA
1
Boundary scan output low voltage
VOL
0.2 V
2
Boundary scan output high voltage
VOH
2.1 V
3
Boundary scan output leakage current
ILO
−5 µA
+5 µA
4
Notes: 1.
2.
3.
4.
0 ≤ VIN ≤ 3.6 V for all logic input pins
IOL = 2 mA at VDD = 2.5 V.
IOH = −2 mA at VDD = 2.5 V.
0 ≤ VOUT ≤ VDD, TDO in high-Z
Rev.0.10, May.15.2003, page 16 of 22
Notes
HM64YLB36514 Series
TAP AC Operating Characteristics (Ta = 0 to +85°C)
Parameter
Symbol
Min
Max
Unit
Test clock cycle time
tTHTH
67
ns
Test clock high pulse width
tTHTL
30
ns
Test clock low pulse width
tTLTH
30
ns
Test mode select setup
tMVTH
10
ns
Test mode select hold
tTHMX
10
ns
Capture setup
tCS
10
ns
1
Capture hold
tCH
10
ns
1
TDI valid to TCK high
tDVTH
10
ns
TCK high to TDI don’t care
tTHDX
10
ns
TCK low to TDO unknown
tTLQX
0
ns
TCK low to TDO valid
tTLQV
20
ns
Note:
Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions (VDD = 2.5 V)
Temperature
0°C ≤ Ta ≤ +85°C
Input timing measurement reference level
1.1 V
Input pulse levels
0 to 2.5 V
Input rise/fall time
1.5 ns typical (10% to 90%)
Output timing measurement reference level
1.25 V
Test load termination supply voltage (VT)
1.25 V
Output load
See figure below
Boundary Scan AC Test Load
VT
DUT
50 Ω
Z0 = 50 Ω
TDO
Rev.0.10, May.15.2003, page 17 of 22
HM64YLB36514 Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
TDO
tTLQX
tCS tCH
RAM
ADDRESS
Test Access Port Registers
Register name
Length
Symbol
Instruction register
3 bits
IR [2:0]
Bypass register
1 bit
BP
ID register
32 bits
ID [31:0]
Boundary scan register
70 bits
BS [70:1]
Note
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
Operation
0
0
0
SAMPLE-Z
Tristate all data drivers and capture the pad value
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0
1
1
BYPASS
1
0
0
SAMPLE
1
0
1
BYPASS
1
1
0
PRIVATE
1
1
1
BYPASS
Tristate all data drivers and capture the pad value
Do not use. They are reserved for vendor use only
Note: This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command
in IEEE 1149.1.
Rev.0.10, May.15.2003, page 18 of 22
HM64YLB36514 Series
Boundary Scan Order (HM64YLB36514)
Bit #
Bump ID
Signal name
Bit #
Bump ID
Signal name
1
5R
M2
36
3B
SA12
2
4P
SA0
37
2B
SA15
3
4T
SA3
38
3A
SA13
4
6R
SA1
39
3C
SA11
5
5T
SA2
40
2C
SA16
6
7T
ZZ
41
2A
SA14
7
6P
DQa8
42
2D
DQc8
8
7P
DQa7
43
1D
DQc7
9
6N
DQa6
44
2E
DQc6
10
7N
DQa5
45
1E
DQc5
11
6M
DQa4
46
2F
DQc4
12
6L
DQa2
47
2G
DQc2
13
7L
DQa3
48
1G
DQc3
14
6K
DQa0
49
2H
DQc0
15
7K
DQa1
50
1H
DQc1
16
5L
SWEa
51
3G
SWEc
17
4L
K
52
4D
ZQ
18
4K
K
53
4E
SS
19
4F
G
54
4G
NC
20
5G
SWEb
55
4H
NC
21
7H
DQb1
56
4M
SWE
22
6H
DQb0
57
3L
SWEd
23
7G
DQb3
58
1K
DQd1
24
6G
DQb2
59
2K
DQd0
25
6F
DQb4
60
1L
DQd3
26
7E
DQb5
61
2L
DQd2
27
6E
DQb6
62
2M
DQd4
28
7D
DQb7
63
1N
DQd5
29
6D
DQb8
64
2N
DQd6
30
6A
SA7
65
1P
DQd7
31
6C
SA8
66
2P
DQd8
32
5C
SA4
67
3T
SA18
33
5A
SA6
68
2R
SA10
34
6B
SA9
69
4N
SA17
35
5B
SA5
70
3R
M1
Rev.0.10, May.15.2003, page 19 of 22
HM64YLB36514 Series
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. The NC pads listed in this table are indeed no connects, but are represented in the boundary
scan register by a “Place Holder”. Place holder registers are internally connected to VSS.
3. In boundary scan mode, differential input K and K are referenced to each other and must be at
the opposite logic levels for the reliable operation.
4. ZZ must remain VIL during boundary scan.
5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results.
6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.
ID Register
Part
Revision
number
(31:28)
Device density
and configuration
(27:18)
Vendor
definition
(17:12)
Vendor JEDEC
code (11:1)
Start
bit (0)
HM64YLB36514
0000
0011100100
000000
00000000111
1
TAP Controller State Diagram
1
Test-logicreset
0
0
Run-test/
idle
1
1
SelectDR-scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
1
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
1
Exit1-DR
0
1
SelectIR-scan
Update-IR
0
1
0
Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the
time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held
high for at least five rising edges of TCK.
Rev.0.10, May.15.2003, page 20 of 22
HM64YLB36514 Series
Package Dimensions
HM64YLB36514BP Series (BP-119E)
Preliminary
0.20
Unit: mm
A
0.20 C
Y
7654321
0.35 C
4×
C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1.27
18.04
22.00
14.00
11.08
1.27
2.02 ± 0.22
0.69 ± 0.08
(0.15)
B
119 × φ 0.88 ± 0.06
φ 0.30 M C A B
φ 0.15 M C
Details of the part Y
Rev.0.10, May.15.2003, page 21 of 22
Package Code
JEDEC
JEITA
Mass (reference value)
BP-119E
—
—
1.1 g
HM64YLB36514 Series
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Rev.0.10, May.15.2003, page 22 of 22