XC6127 Series ETR0217-007 Ultra Small Voltage Detector with High Precision Delay Circuit and Manual Reset Function ■GENERAL DESCRIPTION XC6127 series is ultra small highly accurate voltage detector with delay circuit built-in. The device includes a highly accurate reference voltage source, manufactured using CMOS process technology and laser trimming technologies, it maintains high accuracy, low power consumption, and accurate releases delay time over the full operation temperature range. The release delay time periods are internally set in a range from 50ms to 800ms. Moreover, with the manual reset function, reset can be asserted at any time. The device is available in both CMOS and N-channel open drain output configurations. Also detect logic is available in both RESETB (Active Low) and RESET (Active High). Ultra small package USPN-4 is ideally suited for small design of portable devices and high densely mounting applications. The conventional packages SSOT-24,SOT-25 is also available for upper compatible replacements. ■FEATURES ■APPLICATIONS ● Microprocessor logic reset circuitry ● System battery life and charge voltage monitors ● Memory battery back-up circuits ● Power-on reset circuits ● Power failure Detection High Accuracy : ±0.8％ (25℃) Temperature Characteristics : ±50ppm/℃ Low Power Consumption : 0.6μA TYP. (Detect: VDF=1.8V, VIN=1.62V) Operating Voltage Range : 0.7V～6.0V Detect Voltage Range : 1.5V～5.5V (0.1V increments) Manual Reset Input : MRB Pin (Built-in Pull-up resistance) Output Configuration : N-channel open drain or CMOS Output Logic : RESETB (Active Low) Release Delay Time : 50ms/100ms/200ms/400ms/800ms±15% Operating Ambient Temperature : -40℃ ~ +85℃ Packages : USPN-4, SSOT-24, SOT-25 Environmentally Friendly : EU RoHS Compliant, Pb Free 0.7μA TYP. (Release: VDF=1.8V, VIN=1.98V) ● Delay circuit RESET (Active High) ■TYPICAL APPLICATION CIRCUIT ■ TYPICAL PERFORMANCE CHARACTERISTICS VCC MRB VIN RESETB/RESET INPUT RESETB RESET VSS VSS RESET SW CMOS output Vpull-Up VCC XC6127 series VIN MRB VIN RESETB RESET Rpull μP RESETB/RESET INPUT Release Delay Time: tDR (ms) VIN XC6127x27Bｘ μP XC6127 series VIN=VDFL×0.9→VDFL×1.1 , MRB=OPEN 115 110 105 100 95 90 85 -50 -25 0 25 50 75 100 Ambient Temperature: Ta (℃) VSS VSS RESET SW N-ch open drain output 1/24 XC6127 Series ■PIN CONFIGURATION VIN 4 RESETB 1 RESET VSS 3 2 MRB RESETB RESET MRB 4 3 1 2 VIN VSS USPN-4 (BOTTOM VIEW) SSOT-24 (TOP VIEW) VIN RESETB RESET 5 4 1 2 3 MRB VSS NC SOT-25 (TOP VIEW) ■PIN ASSIGNMENT USPN-4 PIN NUMBER SSOT-24 SOT-25 1 1 2 3 4 4 4 3 2 1 PIN NAME FUNCTIONS RESETB RESET MRB VSS VIN Signal Output (Active Low) (*1) Signal Output (Active High) (*2) Manual Reset Input Ground Power Input 4 4 1 2 5 (*1) Type A～E (Refer to the ④ in Ordering Information table) (*2) Type F～K (Refer to the ④ in Ordering Information table) ■FUNCTION CHART PIN NAME SIGNAL STATUS MRB L H OPEN Forced Reset Normal Operation Normal Operation 2/24 XC6127 Series ■PRODUCT CLASSIFICATION ●Ordering Information XC6127①②③④⑤⑥-⑦(*1) DESIGNATOR ITEM ① Output Configuration ②③ Detect Voltage ④ Type ⑤⑥-⑦ (*1) (*1) Packages (Order Unit) SYMBOL C N 15～55 A B C D E F G H J K 7R-G MR-G NR-G DESCRIPTION CMOS output N-ch open drain output e.g. 2.7V → ②=2, ③=7 Reset Active Low, Release Delay Time: 50ms Reset Active Low, Release Delay Time: 100ms Reset Active Low, Release Delay Time: 200ms Reset Active Low, Release Delay Time: 400ms Reset Active Low, Release Delay Time: 800ms Reset Active High, Release Delay Time: 50ms Reset Active High, Release Delay Time: 100ms Reset Active High, Release Delay Time: 200ms Reset Active High, Release Delay Time: 400ms Reset Active High, Release Delay Time: 800ms USPN-4 (5,000/Reel) SOT-25 (3,000/Reel) SSOT-24 (3,000/Reel) The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant. 3/24 XC6127 Series ■BLOCK DIAGRAMS 1) XC6127 Series, Type CxxA/CxxB/CxxC/CxxD/CxxE (CMOS Output, Output Logic: Active Low) * Diodes inside the circuits are ESD protection diodes and parasitic diodes. 2) XC6127 Series, Type NxxA/NxxB/NxxC/NxxD/NxxE (N-ch Open Drain Output, Output Logic: Active Low) * Diodes inside the circuits are ESD protection diodes 4/24 XC6127 Series ■BLOCK DIAGRAMS (Continued) 3) XC6127 Series, Type CxxF/CxxG/CxxH/CxxJ/CxxK (CMOS Output, Output Logic: Active High) * Diodes inside the circuits are ESD protection diodes and parasitic diodes. 4) XC6127 Series, Type NxxF/NxxG/NxxH/NxxJ/NxxK (N-ch Open Drain Output, Output Logic: Active High) * Diodes inside the circuits are ESD protection diodes. 5/24 XC6127 Series ■ABSOLUTE MAXIMUM RATINGS Ta=25℃ PARAMETER SYMBOL RATINGS UNITS Input Voltage VIN VSS-0.3～VSS+6.5 V MRB Input Voltage VMRB VSS～VSS+6.5 V Output Current (*1) 20 mA Output Voltage Power Dissipation XC6127C (*2) XC6127N (*4) (*3) USPN-4 SOT-25 VSS-0.3～VIN+0.3≦VSS+6.5 VSS-0.3～VSS+6.5 Pd SSOT-24 100 250 V mW 150 Operating Ambient Temperature Topr -40～+85 ℃ Storage Temperature Tstg -55～+125 ℃ Note: (*1) SYMBOL is different for each product. IRBOUT: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE IROUT: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (*2) CMOS Output (*3) N-ch Open Drain Output (*4) SYMBOL is different for each product. VRESETB: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE VRESET: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK 6/24 XC6127 Series ■ELECTRICAL CHARACTERISTICS ●XC6127CxxA/CxxB/CxxC/CxxD/CxxE, XC6127NxxA/NxxB/NxxC/NxxD/NxxE (Output Logic: Active Low) PARAMETER SYMBOL CONDITIONS Operating Voltage VIN VDF(T) =1.5～5.5V, MRB=OPEN Detect Voltage VDFL VDF(T)=1.5～5.5V, MRB=OPEN (*1) MIN. (*2) 0.7 TYP. (*3) VDF(T)×0.992 VDF(T) E-1 Hysteresis Width VHYS Ta=25℃ CIRCUI MAX. UNITS 6.0 V - V ① V ① μA ② μA ② mA ③ ③ VDF(T)×1.008 (*4) VDFL×0.02 VDFL×0.05 VDFL×0.08 VDF(T)=1.5～1.8V - 0.6 1.4 VDF(T)=1.9～3.0V - 0.7 1.6 VDF(T)=3.1～5.5V - 1.0 1.9 VDF(T)=1.5～1.8V - 0.7 1.6 VDF(T)=1.9～3.0V - 0.8 1.9 VDF(T)=3.1～5.5V - 1.1 2.35 VIN=0.7V, VRESETB=0.5V(Nch) , MRB=OPEN 0.014 0.2 - VIN=1.0V, VRESETB=0.5V(Nch) , MRB=OPEN VIN=VDFL×0.9 , MRB=OPEN Supply Current 1 ISS1 VIN=VDFL×1.1 Supply Current 2 ISS2 (*5) , MRB=OPEN 0.5 1.6 - (*6) 4.4 7.0 - (*7) 7.0 9.0 - (*8) 8.5 11.0 - (*9) 9.0 12.0 - VIN=6.0V, VRESETB=5.5V(Pch) , MRB=OPEN - -4.5 -3.0 mA VIN=VDFL×0.9, VRESETB=0V , MRB=OPEN - -0.01 - μA VIN=6.0V, VRESETB=6.0V , MRB=OPEN - 0.01 0.15 μA ΔVDFL/ (ΔTopr・VDFL) -40℃≦Topr≦85℃ - ±50 - ppm/℃ ① tDF VIN=VDFL×1.1→VDFL×0.9 - - 100 μs ④ tDR VIN=VDFL×0.9→VDFL×1.1 ms ④ IRBOUT1 RESETB Output Current VIN=2.0V , VRESETB=0.5V(Nch) , MRB=OPEN VIN=3.0V , VRESETB=0.5V(Nch) , MRB=OPEN VIN=4.0V , VRESETB=0.5V(Nch) , MRB=OPEN VIN=5.0V , VRESETB=0.5V(Nch) , MRB=OPEN I RESETB Leakage Current CMOS Output(Pch) Nch Open Drain Output Temperature Characteristics (*11) Detect Delay Time (*12) Release Delay Time MRB “Low” Level Voltage (*10) RBOUT2 ILEAK ③ (*11) , MRB=OPEN (*12) , MRB=OPEN E-2 (*13) (*14) VMRL VDFL×1.1≦VIN≦6.0V VSS - 0.3 V ⑤ (*14) VMRH VDFL×1.1≦VIN≦6.0V 1.0 - 6.0 V ⑤ 0.4 0.8 3.0 MΩ ⑥ 150 - - ns ⑦ MRB “High” Level Voltage MRB pull-up Resistance RMRB Minimum MRB Pulse Width TMRB VIN=6.0V, Applied pulse to MRB pin, Note: (*1) VDF(T) : Nominal detect voltage (*2) For the N-ch Open Drain, Rpull=100kΩ, Vpull-Up=VIN Rpull: An External Pull-up resistor Vpull-Up: Pull-up Voltage (*3) VIN voltage for VOUT≦0.3V is under detect state. (*4) For the detail value, please refer to “Voltage Table” in P10. (*5) VDF(T)= 5.5V where VIN=6.0V (*6) For VDF(T)＞2.0V products. (*7) For VDF(T)＞3.0V products. (*8) For VDF(T)＞4.0V products. (*9) For VDF(T)＞5.0V products. (*10) For the XC6127C (CMOS output) (*11) A time between VIN=VDFL and VRESETB=VDFL×0.45 when VIN falls. (*12) A time between VIN=VDFL+VHYS and VRESETB=VDFL×0.55 when VIN rises. (*13) For the detail value, please refer to “Release Delay Time” in P11. (*14) For MRB pin, please do not apply the voltage below VSS. 7/24 XC6127 Series ■ELECTRICAL CHARACTERISTICS (Continued) Ta=25℃ ●XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (Output Logic: Active High) PARAMETER SYMBOL Operating Voltage VIN Detect Voltage VDFH CONDITIONS (*1) MIN. (*2) VDF(T) =1.5～5.5V, MRB=OPEN VDF(T)=1.5～5.5V, MRB=OPEN 0.7 TYP. (*3) VDF(T)×0.992 VDF(T) E-1 Hysteresis Width VHYS MAX. UNITS CIRCUIT 6.0 V - V ① V ① μA ② μA ② mA ③ mA ③ VDF(T)×1.008 (*4) VDFH×0.02 VDFH×0.05 VDFH×0.08 VDF(T)=1.5～1.8V - 0.6 1.4 VDF(T)=1.9～3.0V - 0.7 1.6 VDF(T)=3.1～5.5V - 1.0 1.9 VDF(T)=1.5～1.8V - 0.7 1.6 VDF(T)=1.9～3.0V - 0.8 1.9 VDF(T)=3.1～5.5V - 1.1 2.35 VIN=VDFH×0.9 , MRB=OPEN Supply Current 1 ISS1 VIN=VDFH×1.1 Supply Current 2 ISS2 (*5) , MRB=OPEN (*6) VIN=1.65V , VRESET=0.5V(Nch) , MRB=OPEN 0.5 1.6 - (*7) 4.4 7.0 - (*8) 7.0 9.0 - (*9) 8.5 11.0 - 9.0 12.0 - VIN=6.0V, VRESET=0.5V(Nch) , MRB=OPEN 9.0 12.0 - VIN=0.7V, VRESET=0.2V(Pch) , MRB=OPEN - -0.07 -0.001 VIN=1.0V, VRESET=0.5V(Pch) , MRB=OPEN - -0.4 -0.09 VIN=2.0V , VRESET=0.5V(Nch) , MRB=OPEN IROUT1 VIN=3.0V , VRESET=0.5V(Nch) , MRB=OPEN VIN=4.0V , VRESET=0.5V(Nch) , MRB=OPEN VIN=5.0V RESET Output Current IROUT2 (*11) RESET Leakage Current CMOS Output (P-ch) N-ch Open Drain Output Temperature ΔVDFH/ (ΔTopr・VDFH) (*16) Release Delay Time VIN=2.0V (*12) , VRESET=1.5V(Pch) , MRB=OPEN - -2.0 -1.3 VIN=3.0V (*13) , VRESET=2.5V(Pch) , MRB=OPEN - -3.0 -1.8 VIN=4.0V (*14), VRESET=3.5V(Pch) , MRB=OPEN - -4.0 -2.5 VIN=5.0V (*15) , VRESET=4.5V(Pch) , MRB=OPEN - -4.5 -3.0 VIN=6.0V, VRESET=0V, MRB=OPEN - -0.01 - μA VIN=VDFH×0.9, VRESET=6.0V, MRB=OPEN - 0.01 0.15 μA -40℃≦Topr≦85℃ - ±50 - ppm/℃ ① - - μs ④ ms ④ ③ (*16) , MRB=OPEN (*18) , MRB=OPEN VIN=VDFH×1.1→VDFH×0.9 (*18) tDR VIN=VDFH×0.9→VDFH×1.1 (*20) VMRL VDFH×1.1≦VIN≦6.0V VSS - 0.3 V ⑤ (*20) VMRH VDFH×1.1≦VIN≦6.0V 1.0 - 6.0 V ⑤ 0.4 0.8 3.0 MΩ ⑥ 150 - - ns ⑦ MRB “High” Level Voltage MRB pull-up Resistance RMRB Minimum MRB Pulse Width TMRB VIN=6.0V, Applied pulse to MRB pin, 6.0V→0V E-2 E-3 (*17) tDF MRB “Low” Level Voltage 8/24 , VRESET=0.5V(Nch) , MRB=OPEN ILEAK Characteristics Detect Delay Time (*10) (*19) XC6127 Series ■ELECTRICAL CHARACTERISTICS (Continued) (*1) VDF(T): Nominal detect voltage (*2) For the N-ch Open Drain, Rpull=100kΩ, Vpull-Up=VIN Rpull: An External Pull-up resistor Vpull-Up: Pull-up Voltage (*3) VIN voltage for VOUT≧0.4V is under detect state. (*4) For the detail value, please refer to “Voltage Table” in P10. (*5) VDF(T)= 5.5V where VIN=6.0V (*6) For VDF(T)=1.5V products. (*7) For VDF(T)≦1.8V products. (*8) For VDF(T)≦2.7V products. (*9) For VDF(T)≦3.6V products. (*10) For VDF(T)≦4.6V products. (*11) For the XC6127C (CMOS output) (*12) For VDF(T)＞2.0V products. (*13) For VDF(T)＞3.0V products. (*14) For VDF(T)＞4.0V products. (*15) For VDF(T)＞5.0V products. (*16) A time between VIN=VDFH and VRESET=VDFH×0.45 when VIN falls. (*17) For the detail value, please refer to “Detect Delay Time” in P11. (*18) A time between VIN=VDFH+VHYS and VRESET=VDFH×0.55 when VIN rises. (*19) For the detail value, please refer to “Release Delay Time” in P11. (*20) For MRB pin, please do not apply the voltage below VSS. 9/24 XC6127 Series ■ELECTRICAL CHARACTERISTICS (Continued) Voltage Table 1 NOMINAL DETECT VOLTAGE (V) VDF(T) Voltage Table 2 DETECT VOLTAGE (V) E-1 VDFL or VDFH MIN. MAX. 1.50 1.4880 1.5120 1.60 1.5872 1.6128 1.70 1.6864 1.80 NOMINAL DETECT VOLTAGE (V) VDF(T) DETECT VOLTAGE (V) E-1 VDFL or VDFH MIN. MAX. 4.10 4.0672 4.1328 4.20 4.1664 4.2336 1.7136 4.30 4.2656 4.3344 1.7856 1.8144 4.40 4.3648 4.4352 1.90 1.8848 1.9152 4.50 4.4640 4.5360 2.00 1.9840 2.0160 4.60 4.5632 4.6368 2.10 2.0832 2.1168 4.70 4.6624 4.7376 2.20 2.1824 2.2176 4.80 4.7616 4.8384 2.30 2.2816 2.3184 4.90 4.8608 4.9392 2.40 2.3808 2.4192 5.00 4.9600 5.0400 2.50 2.4800 2.5200 5.10 5.0592 5.1408 2.60 2.5792 2.6208 5.20 5.1584 5.2416 2.70 2.6784 2.7216 5.30 5.2576 5.3424 2.80 2.7776 2.8224 5.40 5.3568 5.4432 2.90 2.8768 2.9232 5.50 5.4560 5.5440 3.00 2.9760 3.0240 3.10 3.0752 3.1248 3.20 3.1744 3.2256 3.30 3.2736 3.3264 3.40 3.3728 3.4272 3.50 3.4720 3.5280 3.60 3.5712 3.6288 3.70 3.6704 3.7296 3.80 3.7696 3.8304 3.90 3.8688 3.9312 4.00 3.9680 4.0320 10/24 XC6127 Series ■ELECTRICAL CHARACTERISTICS (Continued) Release Delay Time Table RELEASE DELAY TIME (ms) TYPE E-2 tDR MIN. TYP. MAX. XC6127CxxA / XC6127NxxA 42.5 50 57.5 XC6127CxxB / XC6127NxxB 85 100 115 XC6127CxxC / XC6127NxxC 170 200 230 XC6127CxxD / XC6127NxxD 340 400 460 XC6127CxxE / XC6127NxxE 680 800 920 XC6127CxxF / XC6127NxxF 42.5 50 57.5 XC6127CxxG / XC6127NxxG 85 100 115 XC6127CxxH / XC6127NxxH 170 200 230 XC6127CxxJ / XC6127NxxJ 340 400 460 XC6127CxxK / XC6127NxxK 680 800 920 Detect Delay Time Table DETECT DELAY TIME (μs) TYPE E-3 tDF MAX. XC6127CxxF/CxxG/CxxH/CxxJ/CxxK 100 XC6127NxxF/NxxG/NxxH/NxxJ/NxxK 200 11/24 XC6127 Series ■OPERATIONAL EXPLANATION 1. Detect / Release operation using XC6127CxxA/CxxB/CxxC/CxxD/CxxE, XC6127NxxA/NxxB/NxxC/NxxD/NxxE (Output Logic: Active Low) ●Typical Application Circuit ●Timing Chart A timing chart is used to explain the operation of the typical application circuit when MRB is open. ①In the initial state, an input voltage (VIN) higher than the release voltage (VDR) is applied, and then VIN gradually falls. While the input voltage (VIN) is higher than the detect voltage (VDFL), an output voltage (VRESETB) equal to the input voltage (VIN) goes out. *In the case of an N-ch open drain output product, the RESETB pin is in a high-impedance state, and if the output is pulled up, the output voltage (VRESETB) is equal to the pull-up voltage. ②③After the elapse of the detect delay time (tDF) that starts when the input voltage (VIN) falls below the detect voltage (VDFL), an output voltage (VRESETB) equal to the ground voltage (VSS) goes out (detection state). *This is the same on the N-ch open drain output product. ④The input voltage (VIN) drops further, and if it falls below the minimum operating voltage (0.7V), the output becomes undefined state. *When an N-ch open drain output product is used and the output pin is pulled up, an output voltage (VRESETB) equal to the pull-up voltage may be output. ⑤The input voltage (VIN) rises past the minimum operating voltage (0.7V), and until it reaches the release voltage (VDR), the output voltage (VRESETB) is equal to the ground voltage. ⑥ From the time that the input voltage (VIN) becomes higher than the release voltage (VDR) until the release delay time （tDR) elapses, the output voltage (VRESETB) remains at the ground voltage due to the delay circuit. ⑦ After the release delay time (tDR) elapses, the output voltage (VRESETB) is equal to the input voltage (VIN) (release state). *In the case of an N-ch open drain output product, the RESETB pin will be in a high impedance state like ①. If the output is pulled up, an output voltage (VRESETB) equal to the pull-up voltage will be output. ⑧The difference between the release voltage (VDR) and the detect voltage (VDFL) is the hysteresis width (VHYS). 12/24 XC6127 Series ■OPERATIONAL EXPLANATION (Continued) 2. XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (Output Logic: Active High) ●Typical Application Circuit ●Timing Chart A timing chart is used above to explain the operation of the typical application circuit when MRB is open. ① In the initial state, an input voltage (VIN) higher than the release voltage (VDR) is applied, and then VIN gradually falls. While the input voltage (VIN) is higher than the detect voltage (VDFH), an output voltage (VRESET) equal to the ground voltage (VSS) goes out. *This is the same on the N-ch open drain output product. ②③After the elapse of the detect delay time (tDF) that starts when the input voltage (VIN) falls below the detect voltage (VDFH), the output voltage (VRESET) is equal to the input voltage (VIN) (detection state). *In the case of an N-ch open drain output product, the RESET pin is in a high-impedance state, and if the output is pulled up, the output voltage (VRESET) is equal to the pull-up voltage. ④ The input voltage (VIN) drops further, and if it falls below the minimum operating voltage (0.7V), the output becomes undefined state. ⑤The input voltage (VIN) rises past the minimum operating voltage (0.7V), and until it reaches the release voltage (VDR), the output voltage (VRESET) is equal to the VIN voltage. *In the case of an N-ch open drain output product, the RESET pin is in a high-impedance state, and if the output is pulled up, the output voltage (VRESET) is equal to the pull-up voltage. ⑥From the time that the input voltage (VIN) becomes higher than the release voltage (VDR) until the release delay time （tDR) elapses, the output voltage (VRESET) remains equal to the VIN voltage due to the delay circuit. ⑦After the release delay time (tDR) elapses, the output voltage (VRESET) is equal to the ground voltage (VSS) (release state). ⑧The difference between the release voltage (VDR) and the detect voltage (VDFH) is the hysteresis width (VHYS). 13/24 XC6127 Series ■OPERATIONAL EXPLANATION (Continued) 3. MRB Pin The output pin signal can be forcibly changed to the detect state by an input signal to the MRB pin. The operation of the circuit at MRB signal input is explained using a timing chart. When an H level (VMRH) signal and then an L (or less) level (VMRL) signal are input to the MRB input voltage (VMRB) with a voltage equal to or higher than VDR applied to the input voltage (VIN), the output pin outputs release state (*1) and then detect state (*2) signals. During the release delay time (tDR) after the MRB input voltage (VMRB) changes from the L level (VMRL) to the H level (VMRH), the output pin maintains the detection state. After the release delay time (tDR) elapses, the output pin outputs the release state signal. (*1) The output voltage in the release state is indicated below by product type. XC6127CxxA/CxxB/CxxC/CxxD/CxxE types, XC6127NxxA/NxxB/NxxC/NxxD/NxxE types (output logic: Active Low) : Input voltage (VIN) (*3) XC6127CxxF/CxxG/CxxH/CxxJ/CxxK types, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK types (output logic: Active High) : Ground voltage (VSS) (*2) The output voltage in the detect state is indicated below by product type. XC6127CxxA/CxxB/CxxC/CxxD/CxxE types, XC6127NxxA/NxxB/NxxC/NxxD/NxxE types (output logic: Active Low) : Ground voltage (VSS) XC6127CxxF/CxxG/CxxH/CxxJ/CxxK types, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK types (output logic: Active High) : Input voltage (VIN) (*3) (*3) On an N-ch open drain output product, if the output is pulled up, the output voltage is the pull-up voltage. (*4) A pull-up resistance (RMRB) is built-in between the MRB pin and the VIN pin, and thus if a voltage is applied to the MRB pin, current will flow from the VIN pin to the MRB pin. (*5) The voltage input to the MRB pin should be within the range VSS to 6.0 V. ●Timing Chart Input Voltage: VIN Release Voltage: VDR Detect Voltage: VDFL or VDFH Ground Voltage：VSS MRB Input Voltage: VMRB MRB “High” Level Voltage: VMRH MRB “Low” Level Voltage: VMRL Ground Voltage：VSS Output Voltage: VRESETB Release Delay Time: ｔDR Ground Voltage：VSS Output Voltage: VRESET Release Delay Time: ｔDR Ground Voltage：VSS 14/24 XC6127 Series ■NOTE ON USE 1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded. 2. Note that there is a possibility of malfunctioning if the input voltage changes sharply or undergoes repeated, cyclical changes. 3. If the resistance RIN is connected between the VIN pin and the power supply VDD, the voltage drop due to the flow through current in the internal circuit and RIN may cause oscillation when release takes place. When using the CMOS output product, oscillation due to RIN and the flow through current may occur without relation to release and detection, and thus RIN should not be connected. 4. When N-ch open drain output is used, the output voltage at detection is determined by the pull-up resistance connected to the output pin. Select the resistance based on the following considerations: Using a XC6127CxxA/CxxB/CxxC/CxxD/CxxE or XC6127NxxA/NxxB/NxxC/NxxD/NxxE (output logic: Active Low) At detection: VRESETB=(Vpull-Up)/(1+Rpull/RON) Vpull-Up: Voltage after pull-up RON (*1) : ON resistance of N-ch driver （calculated from VRESETB/IRBOUT1 in electrical characteristics） (*3) Example calculation: When VIN=2.0V (*2) , RON=0.5/4.4×10-3≒114Ω（MAX.）. If you wish to make the VRESETB voltage at detection 0.1V or lower with Vpull-Up=3.0V, Rpull=(Vpull-Up /VRESETB-1)×RON=(3/0.1-1)×114≒3.3kΩ, and thus to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 3.3kΩ or higher. (*1) The smaller VIN is, the larger RON becomes. (*2) When selecting VIN, calculate using the lowest value of the input voltage range you will use. (*3) IRBOUT1 specified in the electrical characteristics is the value at Ta=25℃. IRBOUT1 varies depending on the ambient temperature. To select the pull-up resistance taking ambient temperature into account, please consult us. At release: VRESETB = (Vpull-Up)/(1+Rpull/ROFF) Vpull-Up: Voltage after pull-up ROFF: Resistance value 40MΩ（MIN.）when N-ch driver is OFF (calculated from VRESETB/ILEAK in electrical characteristics) Calculation example: If you wish to make VRESETB 5.99V or higher with Vpull-Up=6.0V Rpull=(Vpull-Up/VRESETB-1)×ROFF=(6/5.99-1)×40×106≒66kΩ, and thus to make the output voltage 5.99V or higher at release under the above conditions, the pull-up resistance must be 66kΩ or less. Using the XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, or XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (output logic: Active High) At detection：VRESET=(Vpull-Up)/(1+Rpull/ROFF) Vpull-Up: Voltage after pull-up （calculated from VRESET/ILEAK in the electrical characteristics） ROFF: When the N-ch driver is OFF, the resistance is 40MΩ（MIN.） Calculation example: If you wish to make VRESET 5.99V or higher with Vpull-Up = 6.0V Rpull=(Vpull-Up/VRESET-1)×ROFF=(6/5.99-1)×40×106≒66kΩ and thus to make the output voltage 5.99V or higher at detection under the above conditions, the pull-up resistance must be 66kΩ or less. At release：VRESET=(Vpull-Up)/(1+Rpull/RON) Vpull-Up：Voltage after pull-up RON (*1) ：ON resistance of N-ch driver (calculated from VRESET/IROUT1 in the electrical characteristics） (*3) Calculation example: When VIN=2.0V (*2) , RON=0.5/4.4×10-3≒114Ω (MAX.). If you wish to make the VRESET voltage 0.1V or lower at detection with Vpull-Up=3.0 V, Rpull=(Vpull-Up /VRESET-1)×RON=(3/0.1-1)×114≒3.3kΩ and thus to make the output voltage 0.1V or lower at release under the above conditions, the pull-up resistance must be 3.3kΩ or higher. (*1) The smaller VIN is the larger RON becomes. (*2) When selecting VIN, calculate using the lowest value of the input voltage range you will be using. (*3) IROUT1 specified in the electrical characteristics is the value at Ta=25℃. IROUT1 varies depending on the ambient temperature. To select the pull-up resistance taking ambient temperature into account, please consult us. 5. We work hard to improve our products and increase reliability. Nevertheless, to allow for the unexpected, please employ a design such as a failsafe design that is sufficiently safe in terms of both devices and the system, and conduct aging or other testing. 15/24 XC6127 Series ■TEST CIRCUITS Circuit 1 Circuit 2 Circuit 3 Circuit 4 16/24 XC6127 Series ■TEST CIRCUITS (Continued) Circuit 5 Circuit 6 Circuit 7 17/24 XC6127 Series ■PACKAGING INFORMATION Unit:mm ●USPN-4 ●USPN-4 Reference Pattern Layout 0.25 4 3 0.2 0.2 4 3 0.45 0.25 ●USPN-4 Reference Metal Mask Design 18/24 1 0.55 2 0.125 0.1 0.4 5 .0 C0 0.125 1 0.55 2 0.1 XC6127 Series ■PACKAGING INFORMATION (Continued) Unit:mm ●SSOT-24 ●SOT-25 19/24 XC6127 Series ■MARKING RULE ●USPN-4 ① represents product series and output configuration. MARK OUTPUT CONFIGURATION PRODUCT SERIES F CMOS XC6127C*****-G H Nch XC6127N*****-G ② represents detect voltage. MARK OUTPUT VOLTAGE(V) A 1.5 1.6 B 1.7 MARK OUTPUT VOLTAGE(V) MARK OUTPUT VOLTAGE(V) K 2.9 3.0 T 4.3 4.4 1.8 L 3.1 3.2 U 4.5 4.6 3.3 3.4 V 4.7 4.8 3.5 3.6 X 4.9 5.0 C 1.9 2.0 M D 2.1 2.2 N E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2 F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4 H 2.7 2.8 S 4.1 4.2 0 5.5 - ③ represents detect voltage range and release delay time / detect logic. MARK DETECT RELEASE DELAY TIME/ VOLTAGE [V] DETECT LOGIC PRODUCT SERIES A 50ms/Low XC6127*15A**-G ～ XC6127*55A**-G B 100ms/Low XC6127*15B**-G ～ XC6127*55B**-G C 200ms/Low XC6127*15C**-G ～ XC6127*55C**-G D 400ms/Low XC6127*15D**-G ～ XC6127*55D**-G E Odd 800ms/Low XC6127*15E**-G ～ XC6127*55E**-G F number 50ms/High XC6127*15F**-G ～ XC6127*55F**-G H 100ms/High XC6127*15G**-G ～ XC6127*55G**-G K 200ms/High XC6127*15H**-G ～ XC6127*55H**-G L 400ms/High XC6127*15J**-G ～ XC6127*55J**-G M 800ms/High XC6127*15K**-G ～ XC6127*55K**-G N 50ms/Low XC6127*16A**-G ～ XC6127*54A**-G P 100ms/Low XC6127*16B**-G ～ XC6127*54B**-G R 200ms/Low XC6127*16C**-G ～ XC6127*54C**-G S 400ms/Low XC6127*16D**-G ～ XC6127*54D**-G T Even 800ms/Low XC6127*16E**-G ～ XC6127*54E**-G U number 50ms/High XC6127*16F**-G ～ XC6127*54F**-G V 100ms/High XC6127*16G**-G ～ XC6127*54G**-G X 200ms/High XC6127*16H**-G ～ XC6127*54H**-G Y 400ms/High XC6127*16J**-G ～ XC6127*54J**-G Z 800ms/High XC6127*16K**-G ～ XC6127*54K**-G ④ represents production lot number 0 to 9, A to Z, and inverted 0 to 9, A to Z repeated. (G, I, J, O, Q, W excepted.) * No character inversion used. 20/24 XC6127 Series ■MARKING RULE (Continued) ●SSOT-24 SSOT-24 SSOT-24 SSOT24(方向上バー付きタイプ) (With the orientation bar at the top) (With the orientation bar at the bottom) 1 1 2 ④ 3 ③ ④ ③ 4 ② ② ① 3 ① 4 SSOT24(方向下バー付きタイプ) 2 ①-1 represents product series and detect voltage range, output configuration. MARK OUTPUT DETECT RELEASE DELAY TIME/ CONFIGURATION VOLTAGE [V] DETECT LOGIC PRODUCT SERIES 5 50ms/Low XC6127C15A**-G ～ XC6127C55A**-G 6 100ms/Low XC6127C15B**-G ～ XC6127C55B**-G 7 200ms/Low XC6127C15C**-G ～ XC6127C55C**-G 8 400ms/Low XC6127C15D**-G ～ XC6127C55D**-G 9 Odd 800ms/Low XC6127C15E**-G ～ XC6127C55E**-G A number 50ms/High XC6127C15F**-G ～ XC6127C55F**-G B 100ms/High XC6127C15G**-G ～ XC6127C55G**-G C 200ms/High XC6127C15H**-G ～ XC6127C55H**-G D 400ms/High XC6127C15J**-G ～ XC6127C55J**-G 800ms/High XC6127C15K**-G ～ XC6127C55K**-G E F CMOS 50ms/Low XC6127C16A**-G ～ XC6127C54A**-G H 100ms/Low XC6127C16B**-G ～ XC6127C54B**-G K 200ms/Low XC6127C16C**-G ～ XC6127C54C**-G N 400ms/Low XC6127C16D**-G ～ XC6127C54D**-G P Even 800ms/Low XC6127C16E**-G ～ XC6127C54E**-G R number 50ms/High XC6127C16F**-G ～ XC6127C54F**-G S 100ms/High XC6127C16G**-G ～ XC6127C54G**-G T 200ms/High XC6127C16H**-G ～ XC6127C54H**-G U 400ms/High XC6127C16J**-G ～ XC6127C54J**-G V 800ms/High XC6127C16K**-G ～ XC6127C54K**-G * The products of CMOS output configuration are shipped in the package having the orientation bar marked in the top. 21/24 XC6127 Series ■MARKING RULE (Continued) ①-2 represents product series and detect voltage range, output configuration. MARK OUTPUT DETECT RELEASE DELAY TIME/ CONFIGURATION VOLTAGE [V] DETECT LOGIC PRODUCT SERIES 0 50ms/Low XC6127N15A**-G ～ XC6127N55A**-G 1 100ms/Low XC6127N15B**-G ～ XC6127N55B**-G 2 200ms/Low XC6127N15C**-G ～ XC6127N55C**-G 3 400ms/Low XC6127N15D**-G ～ XC6127N55D**-G 4 Odd 800ms/Low XC6127N15E**-G ～ XC6127N55E**-G 5 number 50ms/High XC6127N15F**-G ～ XC6127N55F**-G 6 100ms/High XC6127N15G**-G ～ XC6127N55G**-G 7 200ms/High XC6127N15H**-G ～ XC6127N55H**-G 8 400ms/High XC6127N15J**-G ～ XC6127N55J**-G 800ms/High XC6127N15K**-G ～ XC6127N55K**-G 50ms/Low XC6127N16A**-G ～ XC6127N54A**-G B 100ms/Low XC6127N16B**-G ～ XC6127N54B**-G C 200ms/Low XC6127N16C**-G ～ XC6127N54C**-G D 400ms/Low XC6127N16D**-G ～ XC6127N54D**-G 9 Nch A E Even 800ms/Low XC6127N16E**-G ～ XC6127N54E**-G F number 50ms/High XC6127N16F**-G ～ XC6127N54F**-G H 100ms/High XC6127N16G**-G ～ XC6127N54G**-G K 200ms/High XC6127N16H**-G ～ XC6127N54H**-G L 400ms/High XC6127N16J**-G ～ XC6127N54J**-G M 800ms/High XC6127N16K**-G ～ XC6127N54K**-G * The products of Nch output configuration are shipped in the package having the orientation bar marked in the bottom. ② represents detect voltage. MARK OUTPUT VOLTAGE(V) MARK OUTPUT VOLTAGE(V) MARK OUTPUT VOLTAGE(V) A 1.5 1.6 K 2.9 3.0 T 4.3 4.4 B 1.7 1.8 L 3.1 3.2 U 4.5 4.6 C 1.9 2.0 M 3.3 3.4 V 4.7 4.8 D 2.1 2.2 N 3.5 3.6 X 4.9 5.0 E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2 F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4 2.8 S 4.1 4.2 0 5.5 - H 2.7 ③④ represents production lot number. 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ、B1～ZZ repeated. (G, I, J, O, Q, W excluded.) * No character inversion used. 22/24 XC6127 Series ■MARKING RULE (Continued) SOT-25(Under dot) 5 ●SOT-25 ① ① represents product series and output configuration. 4 ② 1 MARK OUTPUT CONFIGURATION PRODUCT SERIES 5 CMOS XC6127C*****-G 6 Nch XC6127N*****-G ③ ④ 2 ⑤ 3 Magnified 拡大 * SOT-25 with the under-dot marking is used. ② represents detect voltage. MARK A OUTPUT VOLTAGE(V) 1.5 1.6 MARK OUTPUT VOLTAGE(V) K MARK 2.9 3.0 T OUTPUT VOLTAGE(V) 4.3 4.4 B 1.7 1.8 L 3.1 3.2 U 4.5 4.6 C 1.9 2.0 M 3.3 3.4 V 4.7 4.8 D 2.1 2.2 N 3.5 3.6 X 4.9 5.0 E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2 F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4 H 2.7 2.8 S 4.1 4.2 0 5.5 - ③ represents detect voltage range and release delay time / detect logic. MARK DETECT RELEASE DELAY TIME/ VOLTAGE [V] DETECT LOGIC PRODUCT SERIES A 50ms/Low XC6127*15A**-G ～ XC6127*55A**-G B 100ms/Low XC6127*15B**-G ～ XC6127*55B**-G C 200ms/Low XC6127*15C**-G ～ XC6127*55C**-G D 400ms/Low XC6127*15D**-G ～ XC6127*55D**-G E Odd 800ms/Low XC6127*15E**-G ～ XC6127*55E**-G F number 50ms/High XC6127*15F**-G ～ XC6127*55F**-G H 100ms/High XC6127*15G**-G ～ XC6127*55G**-G K 200ms/High XC6127*15H**-G ～ XC6127*55H**-G L 400ms/High XC6127*15J**-G ～ XC6127*55J**-G M 800ms/High XC6127*15K**-G ～ XC6127*55K**-G N 50ms/Low XC6127*16A**-G ～ XC6127*54A**-G P 100ms/Low XC6127*16B**-G ～ XC6127*54B**-G R 200ms/Low XC6127*16C**-G ～ XC6127*54C**-G S 400ms/Low XC6127*16D**-G ～ XC6127*54D**-G T Even 800ms/Low XC6127*16E**-G ～ XC6127*54E**-G U number 50ms/High XC6127*16F**-G ～ XC6127*54F**-G V 100ms/High XC6127*16G**-G ～ XC6127*54G**-G X 200ms/High XC6127*16H**-G ～ XC6127*54H**-G Y 400ms/High XC6127*16J**-G ～ XC6127*54J**-G Z 800ms/High XC6127*16K**-G ～ XC6127*54K**-G ③④ represents production lot number. 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ、B1～ZZ repeated. (G, I, J, O, Q, W excluded.) * No character inversion used. 23/24 XC6127 Series 1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this datasheet may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD. 24/24