RENESAS HD151TS305RPEL

HD151TS305RP
Spread Spectrum Clock for EMI Solution
REJ03D0021–0900Z
Rev.9.00
Jul. 07, 2004
Description
The HD151TS305 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution.
Features
•
•
•
•
Supports 60 MHz to 160 MHz operation. (Designed @ SSCCLKOUT = 72 MHz)
1 copy of finx4 clock out with Spread Spectrum Modulation @3.3 V
1 copy of reference clock @3.3 V
Programmable Spread Spectrum Modulation (±0.25%, ±0.5%, ±1.5% Central Spread Modulation and Spread
Spectrum disable mode)
• SOP-8pin
Key Specifications
•
•
•
•
•
Supply Voltages: VDD = 3.3 V ±0.165 V
0 to 70°C (Ta) Operating Range
50 ± 5% Outputs Clock Duty Cycle
Cycle to Cycle jitter = ±250ps typ.
Ordering Information
Part Name
Package Type
HD151TS305RPEL
SOP-8 pin (JEDEC)
Package Code
FP-8DC
Package
Abbreviation
RP
Taping Abbreviation
(Quantity)
EL (2,500 pcs / Reel)
Note: Please consult the sales office for the above package availability.
Block Diagram
VDD
GND
CLKOUT (12MHz typ.)
XIN
OSC
1/m
Synthesizer
XOUT R=1 MΩ
1/n
SSC Modulator
R=100 kΩ
SEL0
R=100 kΩ
SEL1
Rev.9.00 Jul. 07, 2004 page 1 of 9
Mode Control
SSCCLKOUT (48MHz typ.)
HD151TS305RP
Pin Arrangement
SSCCLKOUT
1
8
SEL1
VDD
2
7
CLKOUT
GND
3
6
SEL0
XIN
4
5
XOUT
(Top view)
SSC Function Table
SEL1 :0
Spread Percentage
00
±0.5%
01
±1.5%
10
SSC OFF
11
±0.25%
Note: ±0.25% SSC is selected for default by internal pull-up resistors.
Clock Frequency Table
XIN(MHz)
SSCCLKOUT(MHz)
*1
15
60
15
*1
40
CLKOUT(MHz)
*2
40*2
160
Notes: 1. With spread spectrum modulation.
2. Without spread spectrum modulation.
Pin Descriptions
Pin name
No.
Type
Description
GND
3
Ground
GND pin
VDD
2
Power
Power supplies pin. Normally 3.3 V.
CLKOUT
7
Output
Normally 3.3 V reference clock output.
SSCCLKOUT
1
Output
Spread spectrum modulated clock output.
XIN
4
Input
Oscillator input.
XOUT
5
Output
Oscillator output.
SEL0
6
Input
SSC mode select pin. LVCMOS level input.
Pull-up by internal resistor (100 kΩ).
SEL1
8
Input
SSC mode select pin. LVCMOS level input.
Pull–up by internal resistor (100 kΩ).
Rev.9.00 Jul. 07, 2004 page 2 of 9
HD151TS305RP
Absolute Maximum Ratings
Item
Symbol
Supply voltage
Ratings
Unit
Conditions
VDD
–0.5 to 4.6
Input voltage
VI
–0.5 to 4.6
V
Output voltage *1
VO
–0.5 to VDD+0.5
V
Input clamp current
IIK
–50
mA
Output clamp current
IOK
–50
mA
VO < 0
Continuous output current
IO
±50
mA
VO = 0 to VDD
0.7
W
–65 to +150
°C
Maximum power dissipation
at Ta = 55°C (in still air)
Storage temperature
Tstg
V
VI < 0
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Symbol
Supply voltage
VDD
DC input signal voltage
Min
Typ
Max
Unit
3.135
3.3
3.465
–0.3
—
VDD+0.3 V
V
High level input voltage
VIH
2.0
—
VDD+0.3 V
Low level input voltage
VIL
–0.3
—
0.8
V
Operating temperature
Ta
0
—
70
°C
45
50
55
%
Input clock duty cycle
Conditions
DC Electrical Characteristics
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Symbol
Min
Typ
*1
Max
Unit
Test Conditions
Input low voltage
VIL
—
—
0.8
V
Input high voltage
VIH
2.0
—
—
V
Input current
II
—
—
±10
µA
—
—
±100
1
—
4
V / ns
20% – 80%
—
—
4
pF
SEL0, SEL1
—
20
—
mA
XIN = 18 MHz, CL = 0 pF, VDD = 3.3 V
Input slew rate
Input capacitance
CI
Operating current
Note:
VI = 0 V or 3.465 V,
VDD = 3.465 V, XIN pin
VI = 0 V or 3.465 V, VDD = 3.465 V,
SEL0, SEL1 pins
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating
conditions.
Rev.9.00 Jul. 07, 2004 page 3 of 9
HD151TS305RP
DC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Symbol
Output voltage
Output current *1
Note:
Min
Typ
Max
Unit
Test Conditions
VOH
3.1
—
—
V
IOH = –1 mA, VDD = 3.3 V
VOL
—
—
50
mV
IOL = 1 mA, VDD = 3.3 V
IOH
—
–40
—
mA
VOH = 1.5 V
IOL
—
40
—
VOL = 1.5 V
1. Parameters are target of design. Not 100% tested in production.
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item
Symbol
Cycle to cycle jitter
Output frequency
*1, 2
*1, 2
Slew rate*1
Clock duty cycle
tCCS
tSL
*1
Min
Typ
Max
—
| 250 |
| 300 |
—
| 250 |
—
Unit
ps
SSC = 0%
SEL1:0 = 10
Fig1
| 300 |
SSCCLKOUT = 72MHz,
XIN = 18 MHz
SSC = ±0.25%
SEL1:0 = 11
Fig1
| 250 |
| 300 |
CLKOUT=18MHz
Fig1
70.4
—
73.6
SSCCLKOUT = 72MHz,
XIN = 18 MHz
SSC = 0%
SEL1:0 = 10
70.3
—
73.7
SSCCLKOUT = 72MHz,
XIN = 18 MHz
SSC= ±0.25%
SEL1:0 = 11
0.8
—
—
V/ns
XIN = 18 MHz CLKOUT
0.4 V to 2.4 V
45
50
55
%
MHz
—
40
—
Ω
—
33
—
KHz
Input clock frequency
15
—
40
MHz
—
—
2
ms
Stabilization time
Note:
*1,3
Notes
SSCCLKOUT = 72MHz,
XIN = 18 MHz
Spread spectrum
modulation frequency *1
Output impedance
*1
Test Conditions
SSCCLKOUT = 96MHz,
XIN = 24 MHz
1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.9.00 Jul. 07, 2004 page 4 of 9
HD151TS305RP
Application Information
1. Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed, as close to the VDD pin as possible, otherwise the increased trace
inductance will negate its decoupling capability.
The C2 decoupling capacitor shown should be a tantalum type.
R1
SSCCLKOUT
1
8
VDD
2
7
SEL1
R2
CLKOUT
C1
C2
3
6
SEL0
TS300 Series
GND GND
4
5
GND
Notes:
XIN
XOUT
(Crystal or
Reference input)
(Crystal or
Not connection)
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF tantalum type recommended)
R1, R2 = Match value to line impedance.
(22 Ω Reference value)
Figure 2 Recommended circuit configuration
Rev.9.00 Jul. 07, 2004 page 5 of 9
HD151TS305RP
2. Example Board Layout Configuration
VDD
(+3.3 V Supply)
P
22 µF
FB
G
R1
1
SSCCLKOUT
8
0.1 µF
R2
7
G
G
3
6
4
5
Crystal connection
or Reference input
Note:
Crystal connection
or Not connection
G Via to GND plane
R1, R2 = Match value to line impedance.
(22 Ω Reference value)
FB = Ferrite bead.
Figure 3 Example Board Layout
Rev.9.00 Jul. 07, 2004 page 6 of 9
CLKOUT
HD151TS305RP
3. Example of TS300 EMI Solution IC’s Application
Spread Spectrum
Modulated Clock
XTAL
XOUT
TS30X
CPU & ASIC
SSC
CLKOUT
Memory
System BUS
XIN
Graphics
System Cont.
Ref.
Clock
3.3 V CMOS level ref. Clock
Fig 4 Ref. Clock Input Example
XIN
XTAL
XOUT
TS30X
CPU & ASIC
SSC
CLKOUT
System BUS
Spread Spectrum
Modulated Clock
Memory
Graphics
System Cont.
Fig 5 XTAL Ref. Clock Input Example
Rev.9.00 Jul. 07, 2004 page 7 of 9
HD151TS305RP
4. Recommendation of Power–ON Sequence
We recommend usage as power–on sequence Vdd starting profile.
At the time of power–on starting, there is possibility for SSCCKOUT to fix Hi/Low level. Please refer Fig6–1 and
Fig6–2.
VDD
Power
ON
Upper 2.8V
delay
XIN
XIN
XOUT
Ref. Clock
Input Timing of XIN
(XIN should be applied after Vdd ≥ 2.8V)
Fig 6–1 In case of reference clock input
VDD
Power
ON
2.8V
Over 3.5V/msec
XIN
XIN
Minimal Rising Time
XOUT
X' tal
(Vdd rising time should be applied over 3.5V/msec)
Fig 6–2 In case of X’tal reference input
5. Cycle to Cycle Jitter
We have guaranteed that cycle to cycle jitter will be less than |300ps| at XIN=18MHz, Vdd=3.3V. In case of using XIN
will be less than 15MHz, the cycle to cycle jitter may be over |300ps|. Please notice to consider this point.
Rev.9.00 Jul. 07, 2004 page 8 of 9
HD151TS305RP
Package Dimensions
As of January, 2003
Unit: mm
3.95
4.90
5.3 Max
5
8
*0.22 ± 0.03
0.20 ± 0.03
4
1.75 Max
1
0.75 Max
+ 0.10
6.10 – 0.30
1.08
*0.42 ± 0.08
0.40 ± 0.06
0.14 – 0.04
1.27
+ 0.11
0˚ – 8˚
+ 0.67
0.60 – 0.20
0.15
0.25 M
*Dimension including the plating thickness
Base material dimension
Rev.9.00 Jul. 07, 2004 page 9 of 9
Package Code
JEDEC
JEITA
Mass (reference value)
FP-8DC
Conforms
—
0.085 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0