PRELIMINARY DATA SHEET 4G bits DDR2 Mobile RAM™ PoP (12mm × 12mm, 216-ball FBGA) EDB4432BAPC Specifications Features • Density: 4G bits • Organization — 16M words × 32 bits × 8 banks • Data rate: 1066Mbps (max.) • Package: 216-ball FBGA — Package size: 12.0mm × 12.0mm — Ball pitch: 0.4mm — Lead-free (RoHS compliant) and Halogen-free • Power supply — VDD1 = 1.70V to 1.95V — VDD2, VDDQ = 1.14V to 1.30V • Interface: HSUL_12 • Operating case temperature range — TC = -30°C to +85°C • JEDEC LPDDR2-S4B compliance • DLL is not implemented • Low power consumption • Mobile RAM functions — Partial Array Self-Refresh (PASR) — Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor — Deep power-down mode — Per Bank Refresh • This FBGA is suitable for Package on Package (PoP) Block Diagram CKE /CS VDD1 VDD2 VDDQ CK, /CK CA0 to CA9 VREFCA VREFDQ VSS 4G bits (128M x 32) DQS0 to DQS3 /DQS0 to /DQS3 DQ0 to DQ31 DM0 to DM3 ZQ Document No. E1891E10 (Ver. 1.0) Date Published February 2012 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2012 EDB4432BAPC Ordering Information Part number Organization (words x bits) Clock frequency Data rate Read latency Package EDB4432BAPC-1D-F 128M x 32 533MHz 1066Mbps 8 216-ball FBGA Part Number E D B 44 32 B A PC - 1D - F Elpida Memory Environment Code F: Lead Free (RoHS compliant) and Halogen Free Type D: Packaged Device Product Family B: DDR2 Mobile RAM Speed 1D: 1066Mbps Density/Chip select 44: 4Gb/1-CS Package PC: BGA for PoP Organization 32: x32 Power Supply, Interface B: VDD1 = 1.8V, VDD2 = VDDQ = 1.2V, S4B device, HSUL Revision Preliminary Data Sheet E1891E10 (Ver. 1.0) 2 EDB4432BAPC CONTENTS Specifications ........................................................................................................................................ 1 Block Diagram ....................................................................................................................................... 1 Features ................................................................................................................................................ 1 Ordering Information ............................................................................................................................. 2 Part Number .......................................................................................................................................... 2 Pin Configurations ................................................................................................................................. 4 Pin Descriptions .................................................................................................................................... 5 Pin Capacitance .................................................................................................................................... 6 Package Drawing .................................................................................................................................. 7 Mode Register Specification ................................................................................................................. 8 1. Electrical Conditions ...................................................................................................................... 9 1.1 Absolute Maximum Ratings .............................................................................................. 9 1.2 Recommended DC Operating Conditions ........................................................................ 9 2. Electrical Specifications ............................................................................................................... 10 2.1 DC Characteristics 1 ....................................................................................................... 10 2.2 DC Characteristics 2 ....................................................................................................... 12 2.3 AC Characteristics .......................................................................................................... 13 Preliminary Data Sheet E1891E10 (Ver. 1.0) 3 EDB4432BAPC Pin Configurations /xxx indicate active low signal. * !"# %&'() Preliminary Data Sheet E1891E10 (Ver. 1.0) 4 EDB4432BAPC Pin Descriptions Pin name Function CK, /CK Clock CKE Clock enable /CS Chip select CA0 to CA9 DDR command/address inputs DM0 to DM3 Input data mask DQ0 to DQ31 Data input/output DQS0 to DQS3, /DQS0 to /DQS3 Data strobe VDD1 Core power supply 1 VDD2 Core power supply 2 and input receiver power supply VDDQ I/O power supply VREFCA Reference voltage for CA input receiver VREFDQ Reference voltage for DQ input receiver VSS Ground ZQ Reference pin for output drive strength calibration NC *1 Note: 1. No connection Not internally connected. Preliminary Data Sheet E1891E10 (Ver. 1.0) 5 (Address configurations: Row:R0-R13, Column:C0-C9, Bank:BA0-BA2) EDB4432BAPC Pin Capacitance Parameter Symbol Pins min. max. Unit Note Input capacitance CI1 CK, /CK 1.5 3.5 pF 1, 2 CI2 All other DDR2 Mobile RAM input only pins 1.5 3.5 pF 1, 2 CI/O DQ, DM, DQS, /DQS 2.0 5.0 pF 1, 2, 3 CZQ ZQ 1.5 3.5 pF 1, 2, 3 Data input/output capacitance Notes: 1. This parameter is not subject to production test. It is verified by design and characterization. 2. These parameters are measured on f = 100MHz, VOUT = VDDQ/2, TA = +25°C. 3. DOUT circuits are disabled. Preliminary Data Sheet E1891E10 (Ver. 1.0) 6 EDB4432BAPC Package Drawing 216-ball FBGA Solder ball: Lead free 12.00 ± 0.10 Unit: mm 0.15 S B 12.00 ± 0.10 INDEX MARK 0.15 S A 0.10 S 0.66 ± 0.065 S 0.08 S 0.18 ± 0.05 216−φ0.25 ± 0.05 φ0.06 M S AB 0.4 B 11.20 A INDEX MARK 0.4 11.20 ECA-TS2-0465-01 Preliminary Data Sheet E1891E10 (Ver. 1.0) 7 EDB4432BAPC Mode Register Specification The following table shows the specifications of mode register values (MR5, 6, 7, 8) for the manufacturer ID and the device descriptions such as DRAM type, density, I/O and die revision. MR# MA <7:0> 5 05h OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Manufacturer ID : ELPIDA 0 6 0 0 0 0 06h Die Revision : Revision A 7 0 0 0 0 0 0 0 0 07h RFU : Default value 8 08h Note: 1. 1 I/O : ×32 1 Density of Die : 4Gbit Type : S4 The register values specify monolithic die information in a package. Therefore, please refer to the block diagram for understanding whole memory configuration of the product containing multiple dice in a package. Preliminary Data Sheet E1891E10 (Ver. 1.0) 8 EDB4432BAPC 1. Electrical Conditions • All voltages are referenced to VSS (GND) • Execute power-up and Initialization sequence before proper device operation is achieved. • Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DDR2 Mobile RAM Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. 1.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings Parameter Symbol min. max. Unit Note VDD1 supply voltage relative to VSS VDD1 -0.4 2.3 V 2 VDD2 supply voltage relative to VSS VDD2 -0.4 1.6 V 2 VDDQ supply voltage relative to VSSQ VDDQ -0.4 1.6 V 2, 3 Voltage on any ball relative to VSS VIN, VOUT -0.4 1.6 V Storage Temperature TSTG -55 125 °C Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. See Power-Ramp section “Power-up, initialization and Power-Off” in the individual DDR2 Mobile RAM data sheet for relationship between power supplies. 3. VREF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV. 4. Storage Temperature is the case surface temperature on the center/top side of the DDR2 Mobile RAM Device. For the measurement conditions, please refer to JESD51-2 standard. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 1.2 Recommended DC Operating Conditions Table 2 Recommended DC Operating Conditions(TC = -30°C to +85°C) Parameter Symbol min. typ. max. Unit Core Power1 VDD1 1.70 1.80 1.95 V Core Power2, Input Buffer Power VDD2 1.14 1.20 1.30 V I/O Buffer Power VDDQ 1.14 1.20 1.30 V Preliminary Data Sheet E1891E10 (Ver. 1.0) 9 EDB4432BAPC 2. Electrical Specifications 2.1 DC Characteristics 1 (TC = -30°C to +85°C, VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V) Table 3 IDD Specification Parameters and Operating Conditions Symbol Power Supply 1066 Unit Parameter/Condition Operating one bank active-pecharge current: tCK = tCK(avg)min; tRC = tRCmin; CKE is HIGH; /CS is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE max. IDD0_1 VDD1 11 mA IDD0_2 VDD2 55 mA IDD0_IN VDDQ 1.0 mA IDD2P_1 VDD1 0.4 mA IDD2P_2 VDD2 0.9 mA IDD2P_IN VDDQ 0.1 mA IDD2PS_1 VDD1 0.4 mA IDD2PS_2 VDD2 0.9 mA IDD2PS_IN VDDQ 0.1 mA IDD2N_1 VDD1 0.6 mA IDD2N_2 VDD2 15 mA IDD2N_IN VDDQ 1.0 mA IDD2NS_1 VDD1 0.6 mA IDD2NS_2 VDD2 7.0 mA IDD2NS_IN VDDQ 1.0 mA IDD3P_1 VDD1 0.7 mA IDD3P_2 VDD2 5.5 mA IDD3P_IN VDDQ 0.1 mA IDD3PS_1 VDD1 0.7 mA IDD3PS_2 VDD2 5.5 mA IDD3PS_IN VDDQ 0.1 mA IDD3N_1 VDD1 1.0 mA IDD3N_2 VDD2 22 mA IDD3N_IN VDDQ 1.0 mA IDD3NS_1 VDD1 1.0 mA IDD3NS_2 VDD2 15 mA IDD3NS_IN VDDQ 1.0 mA IDD4R_1 VDD1 2.0 mA IDD4R_2 VDD2 190 mA Idle power-down standby current: tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle power-down standby current with clock stop: CK = LOW, /CK = HIGH; CKE is LOW; /CS is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE Idle non power-down standby current: tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle non power-down standby current with clock stop: CK = LOW, /CK = HIGH; CKE is HIGH; /CS is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE Active power-down standby current: tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active power-down standby current with clock stop: CK = LOW, /CK = HIGH; CKE is LOW; /CS is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE Active non power-down standby current: tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active non power-down standby current with clock stop: CK = LOW, /CK = HIGH; CKE is HIGH; /CS is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE Operating burst read current: tCK = tCK(avg)min; /CS is HIGH between valid commands; One bank active; BL = 4; RL = RLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer; Preliminary Data Sheet E1891E10 (Ver. 1.0) 10 EDB4432BAPC Table 3 IDD Specification Parameters and Operating Conditions (cont’d) Symbol Power Supply 1066 Unit Parameter/Condition Operating burst write current: tCK = tCK(avg)min; /CS is HIGH between valid commands; One bank active; BL = 4; WL = WLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer; max. IDD4W_1 VDD1 2.0 mA IDD4W_2 VDD2 220 mA IDD4W_IN VDDQ 1.0 mA IDD5_1 VDD1 40 mA IDD5_2 VDD2 150 mA IDD5_IN VDDQ 1.0 mA IDD5AB_1 VDD1 2.0 mA IDD5AB_2 VDD2 16 mA IDD5AB_IN VDDQ 1.0 mA IDD5PB_1 VDD1 2.0 mA IDD5PB_2 VDD2 16 mA IDD5PB_IN VDDQ 1.0 mA IDD8_1 VDD1 16 µA IDD8_2 VDD2 6.0 µA IDD8_IN VDDQ 12 µA Notes: 1. 2. All Bank Auto Refresh Burst current: tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are SWITCHING; Data bus inputs are STABLE; All Bank Auto Refresh Average current: tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are SWITCHING; Data bus inputs are STABLE; Per Bank Auto Refresh Average current: tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are SWITCHING; Data bus inputs are STABLE; Deep Power-Down current: CK = LOW, /CK = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; IDD values published are the maximum of the distribution of the arithmetic mean. IDD current specifications are tested after the device is properly initialized. Preliminary Data Sheet E1891E10 (Ver. 1.0) 11 EDB4432BAPC Table 4 IDD6 Full and Partial Array Self-Refresh Current Parameter Self-Refresh Current +45°C Full Array 1/2 Array 1/4 Array 1/8 Array Self-Refresh Current +85°C Full Array 1/2 Array 1/4 Array 1/8 Array Note: 1. 2.2 Symbol Value Unit Condition IDD6_1 300 µA IDD6_2 850 µA CK = LOW, /CK = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; IDD6_IN 10 µA IDD6_1 200 µA IDD6_2 500 µA IDD6_IN 10 µA IDD6_1 150 µA IDD6_2 300 µA IDD6_IN 10 µA IDD6_1 120 µA IDD6_2 200 µA IDD6_IN 10 µA IDD6_1 900 µA IDD6_2 3200 µA IDD6_IN 12 µA IDD6_1 550 µA IDD6_2 2400 µA IDD6_IN 12 µA IDD6_1 400 µA IDD6_2 2000 µA IDD6_IN 12 µA IDD6_1 320 µA IDD6_2 1800 µA IDD6_IN 12 µA IDD6 85°C is the maximum and IDD6 45°C is typical of the distribution of the arithmetic mean. DC Characteristics 2 (TC = -30°C to +85°C, VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V) Table 5 Electrical Characteristics and Operating Conditions Symbol min. max. Unit Parameter/Condition IL -2 +2 µA Input leakage current: For CA, CKE, /CS, CK, /CK Any input 0V ≤ VIN ≤ VDD2 (All other pins not under test = 0V) IVREF -1 +1 µA VREF supply leakage current: VREFDQ = VDDQ/2 or VREFCA = VDD2/2 (All other pins not under test = 0V) Notes: 1. 2. Note 2 1 The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. Although DM is for input only, the DM leakage shall match the DQ and DQS, /DQS output leakage specification. Preliminary Data Sheet E1891E10 (Ver. 1.0) 12 EDB4432BAPC 2.3 AC Characteristics (TC = -30°C to +85°C, VDD1 = 1.70V to 1.95V, VDD2, VDDQ = 1.14V to 1.30V) Table 6 AC Characteristics Table*6 Parameter Symbol min. min. max. tCK*9 Max. Frequency*4 1066 Unit — 533 MHz min. — 1.875 ns max. — 100 ns min. — 0.45 max. — 0.55 min. — 0.45 max. — 0.55 Clock Timing Average Clock Period Average high pulse width Average low pulse width tCK(avg) tCH(avg) tCK(avg) tCL(avg) tCK(avg) Absolute Clock Period tCK(abs) min. — tCK(avg)(min.) + tJIT(per)(min.) Absolute clock HIGH pulse width (with allowed jitter) tCH(abs), allowed min. — 0.43 max. — 0.57 Absolute clock LOW pulse width (with allowed jitter) tCL(abs), allowed min. — 0.43 max. — 0.57 tJIT(per), allowed min. — -90 Clock Period Jitter (with allowed jitter) max. — 90 max. — 180 min. — min((tCH(abs),min tCH(avg),min), (tCL(abs),min tCL(avg),min)) × tCK(avg) max. — max((tCH(abs),max tCH(avg),max), (tCL(abs),max tCL(avg),max)) × tCK(avg) tERR(2per), allowed min. — -132 max. — 132 tERR(3per), allowed min. — -157 max. — 157 min. — -175 max. — 175 Maximum Clock Jitter between two consecutive clock cycles (with allowed jitter) Duty cycle Jitter (with allowed jitter) Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles tJIT(cc), allowed tCK(avg) tCK(avg) ps tJIT(duty), allowed tERR(4per), allowed ps ps ps min. — -188 — 188 tERR(6per), allowed min. — -200 max. — 200 tERR(7per), allowed min. — -209 max. — 209 Preliminary Data Sheet E1891E10 (Ver. 1.0) 13 ps ps max. tERR(5per), allowed ps ps ps ps EDB4432BAPC Table 6 AC Characteristics Table*6 (cont’d) Parameter Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 . . . 49, 50 cycles min. min. max. tCK*9 1066 tERR(8per), allowed min. — -217 max. — 217 tERR(9per), allowed min. — -224 max. — 224 tERR(10per), min. allowed max. — -231 — 231 tERR(11per), min. allowed max. — -237 — 237 tERR(12per), min. allowed max. — -242 — 242 min. — tERR(nper),allowed,min. = (1 + 0.68ln(n)) × tJIT(per),allowed,min. max. — tERR(nper),allowed,max. = (1 + 0.68ln(n)) × tJIT(per),allowed,max. min. — 2500 max. — 5500 Symbol Unit ps ps ps ps ps tERR(nper), allowed ps Read Parameters DQS output access time from CK, /CK tDQSCK ps DQSCK Delta Short*15 tDQSCKDS max. — 330 ps DQSCK Delta Medium*16 tDQSCKDM max. — 680 ps DQSCK Delta Long*17 tDQSCKDL max. — 920 ps DQS – DQ skew tDQSQ max. — 200 ps Data hold skew factor tQHS max. — 230 ps DQS Output High Pulse Width tQSH min. — tCH(abs) - 0.05 tCK(avg) DQS Output Low Pulse Width tQSL min. — tCL(abs) - 0.05 tCK(avg) Data Half Period tQHP min. — min(tQSH, tQSL) tCK(avg) DQ / DQS output hold time from DQS tQH min. — tQHP - tQHS Read preamble*12,*13 tRPRE min. — 0.9 tCK(avg) Read postamble*12,*14 tRPST min. — tCL(abs) - 0.05 tCK(avg) DQS low-Z from clock*12 tLZ(DQS) min. — tDQSCK(min.) - 300 ps DQ low-Z from clock*12 tLZ(DQ) min. — tDQSCK(min.) (1.4 × tQHS(max.)) ps DQS high-Z from clock*12 tHZ(DQS) max. — tDQSCK(max.) - 100 ps DQ high-Z from clock*12 tHZ(DQ) max. — tDQSCK(max.) + (1.4 × tDQSQ(max.)) ps Preliminary Data Sheet E1891E10 (Ver. 1.0) 14 ps EDB4432BAPC Table 6 AC Characteristics Table*6 (cont’d) Parameter Symbol min. min. max. tCK*9 1066 Unit Write Parameters*11 DQ and DM input hold time (VREF based) tDH min. — 210 ps DQ and DM input setup time (VREF based) tDS min. — 210 ps DQ and DM input pulse width tDIPW min. — 0.35 tCK(avg) min. — 0.75 Write command to 1st DQS latching transition tDQSS max. — 1.25 tCK(avg) DQS input high-level width tDQSH min. — 0.4 tCK(avg) DQS input low-level width tDQSL min. — 0.4 tCK(avg) DQS falling edge to CK setup time tDSS min. — 0.2 tCK(avg) DQS falling edge hold time from CK tDSH min. — 0.2 tCK(avg) Write postamble tWPST min. — 0.4 tCK(avg) Write preamble tWPRE min. — 0.35 tCK(avg) CKE min. pulse width (high and low pulse width) tCKE min. 3 3 tCK(avg) CKE input setup time tISCKE*2 min. — 0.25 tCK(avg) CKE input hold time tIHCKE*3 min. — 0.25 tCK(avg) Address and control input setup time (VREF based) tIS*1 min. — 220 ps Address and control input hold time (VREF based) tIH*1 min. — 220 ps Address and control input pulse width tIPW min. — 0.40 tCK(avg) max. — 100 min. — 18 CKE Input Parameters Command Address Input Parameters*11 Boot Parameters (10 MHz – 55 MHz)*5,*7,*8 Clock Cycle Time tCKb ns CKE Input Setup Time tISCKEb min. — 2.5 ns CKE Input Hold Time tIHCKEb min. — 2.5 ns Address & Control Input Setup Time tISb min. — 1150 ps Address & Control Input Hold Time tIHb min. — 1150 ps DQS Output Data Access Time from CK, /CK min. — 2.0 tDQSCKb max. — 10.0 Data Strobe Edge to Ouput Data Edge tDQSQb - 1.2 tDQSQb max. — 1.2 ns Data Hold Skew Factor tQHSb max. — 1.2 ns Mode Register Write command period tMRW min. 5 5 tCK(avg) Mode Register Read command period tMRR min. 2 2 tCK(avg) ns Mode Register Parameters Preliminary Data Sheet E1891E10 (Ver. 1.0) 15 EDB4432BAPC Table 6 AC Characteristics Table*6 (cont’d) Parameter Symbol min. min. max. tCK*9 1066 Unit DDR2 Mobile RAM Core Parameters*9 Read Latency RL min. 3 8 tCK(avg) Write Latency WL min. 1 4 tCK(avg) ACTIVE to ACTIVE command period tRC min. — tRAS + tRPab (with all-bank Precharge) tRAS + tRPpb (with per-bank Precharge) ns CKE min. pulse width during Self-Refresh (low pulse width during Self-Refresh) tCKESR min. 3 15 ns Self-refresh exit to next valid command delay tXSR min. 2 tRFCab + 10 ns Exit power down to next valid command delay tXP min. 2 7.5 ns CAS to CAS delay tCCD min. 2 2 tCK(avg) Internal Read to Precharge command delay tRTP min. 2 7.5 ns RAS to CAS Delay tRCD min. 3 18 ns Row Precharge Time (single bank) tRPpb min. 3 18 ns Row Precharge Time (all banks) tRPab min. 3 21 ns min. 3 42 ns Row Active Time tRAS max. — 70 µs Write Recovery Time tWR min. 3 15 ns Internal Write to Read Command Delay tWTR min. 2 7.5 ns Active bank A to Active bank B tRRD min. 2 10 ns Four Bank Activate Window tFAW min. 8 50 ns Minimum Deep Power Down Time tDPD min. — 500 µs Refresh Window tREFW max. — 32 ms Required number of REFRESH commands R min. — 8192 Average time between REFRESH commands (for reference only) tREFI max. — 3.9 µs tREFIpb max. — 0.4875 µs Refresh Cycle time tRFCab min. — 130 ns Per Bank Refresh Cycle time tRFCpb min. — 60 ns Burst Refresh Window = 4 × 8 × tRFCab tREFBW min. — 4.16 µs Initialization Calibration Time tZQINIT min. — 1 µs Long Calibration Time tZQCL min. 6 360 ns Short Calibration Time tZQCS min. 6 90 ns Calibration Reset Time tZQRESET min. 3 50 ns DDR2 Mobile RAM Refresh Requirement Parameters ZQ Calibration Parameters*9 Preliminary Data Sheet E1891E10 (Ver. 1.0) 16 EDB4432BAPC Notes: 1. Input set-up/hold time for signal(CA0 – CA9, /CS). 2. CKE input setup time is measured from CKE reaching high/low voltage level to CK, /CK crossing. 3. CKE input hold time is measured from CK, /CK crossing to CKE reaching high/low voltage level. 4. Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities. 5. To guarantee device operation before the DDR2 Mobile RAM Device is configured a number of AC boot timing parameters are defined in the Table 6 on page 13. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb. 6. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities. 7. The DDR2 Mobile RAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in “Mode Register Definition” in the individual DDR2 Mobile RAM data sheet. 8. The output skew parameters are measured with Ron default settings into the reference load. 9. These parameters should be satisfied with both specification, analog (ns) value and min. tCK. 10. All AC timings assume an input slew rate of 1V/ns. 11. Read, Write, and Input Setup and Hold values are referenced to VREF. 12. For low-to-high and high-to-low transitions the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Figure 1 shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. VOH X VOH - X mV 2x X VTT + 2x Y mV VTT + Y mV VOH - 2x X mV tLZ(DQS), tLZ(DQ) VTT VTT Y actual waveform 2x Y VTT - Y mV tHZ(DQS), tHZ(DQ) VOL + 2x X mV VTT - 2x Y mV VOL + X mV T1 T2 VOL T1 T2 stop driving point = 2 x T1 - T2 begin driving point = 2 x T1 - T2 Figure 1 — tLZ and tHZ Method for Calculating Transition and Endpoints The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS-/DQS. 13. Measured from the start driving of DQS – /DQS to the start driving the first rising strobe edge. 14. Measured from the from start driving the last falling strobe edge to the stop driving DQS – /DQS. 15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. 16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1.6µs rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. 17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10°C/s. Values do not include clock jitter. Preliminary Data Sheet E1891E10 (Ver. 1.0) 17 EDB4432BAPC 2.3.1 HSUL_12 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VREF 0.5 x VDDQ DDR2 Mobile RAM RTT = 50 Ω Output VTT = 0.5 x VDDQ Cload = 5pF Figure 2 — HSUL_12 Driver Output Reference Load for Timing and Slew Rate Note: 1. All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc) are reported with respect to this reference load. This reference load is also used to report slew rate. Preliminary Data Sheet E1891E10 (Ver. 1.0) 18 EDB4432BAPC NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E1891E10 (Ver. 1.0) 19 EDB4432BAPC Mobile RAM is a trademark of Elpida Memory, Inc. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to contact Elpida Memory's sales office before using this product for such applications. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E1007 Preliminary Data Sheet E1891E10 (Ver. 1.0) 20