CSN-18: Bare Die SiPs and MCMs Introduction Customer Service Note Design Considerations for Bare Die SiPs and MCMs Introduction Due to the growth in small form factor solutions, bare die has become an excellent choice for designers who wish to make the most out of their board space. The following questionnaire is provided to help guide potential customers through the various details that need to be taken into account when considering a bare die solution. Customers are encouraged to use this guide to define their system needs and thereby enable Micron to recommend an optimal memory solution. 1. Desired Memory Type a. SDRAM Mobile SDRAM DDR SDRAM Mobile DDR SDRAM DDR2 SDRAM NAND Flash DDR3 SDRAM PSRAM b. Density: _________________________________________________________________ c. Configuration: ___________________________________________________________ d. Bus widths: ______________________________________________________________ e. Voltage: Core _____________________________________________________________________ I/O _____________________________________________________________________ f. Clock speed: _____________________________________________________________ g. Is low power required? ____________________________________________________ 1. Active current target ____________________________________________________ 2. Power-down target _____________________________________________________ 3. Power-down current target ______________________________________________ 4. Self refresh current target @45°C ______________ @70°C ______________ @85°C ______________ 5. Deep power-down current ______________________________________________ 2. Application a. System application: _______________________________________________________ b. Processor(s) and/or memory controller used: ________________________________ c. Operating voltage of the system: ____________________________________________ d. Operating temperature range of the system: _________________________________ e. Bond pad requirements of the memory: If edge, single- or dual-sided? PDF: 09005aef80f55803/Source: 09005aef80f557e2 CSN18.fm - Rev. 4/09 EN.L 1 Edge Single-Sided Center Dual-Sided Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. THIS QUESTIONNAIRE IS NOT A CONTRACT OR AGREEMENT, DOES NOT IMPOSE OBLIGATIONS ON BEHALF OF MICRON, AND IS FOR INFORMATIONAL PURPOSES ONLY. CSN-18: Bare Die SiPs and MCMs Introduction f. Expected time frame for: Customer samples ________________________________________________________ Proto builds ______________________________________________________________ Production _______________________________________________________________ 3. Package and Assembly Considerations a. Internal assembly or sub contracted assembly? ______________________________ Who may be selected as the subcontractor? __________________________________ Will any post processing, such as RDL be performed?__________________________ b. Expected die thickness: ____________________________________________________ Will a stress relief process be used? __________________________________________ If so, which process? _______________________________________________________ c. Will there be complete access to the Micron® memory at the final package? _____ If no direct access, will there be a bypass mode to the memory?_________________ d. Overall size of the final package: Width _____________ Length _____________ Height _____________ e. If there are multiple memories in this package, will they be sharing a bus? _______ f. Expected number of die per SiP/MCM: ______________________________________ g. If this is an SiP, what is the maximum measured junction temperature of the system? __________________________________________________________________ h. Die size requirement of the memory (X, Y aspect ratio): _______________________ i. Where does the Micron memory reside in the stack (that is, bottom, top, etc.)?__________________________________________________ j. Is an interposer used? _____________________________________________________ k. What other die will be included? DSPs CPUs NOR PSRAM LPSDRAM NAND Other 4. Test Methodology a. Will the final package be tested for quality? __________________________________ 1. Type of tester used______________________________________________________ 2. Who will be developing the test code?_____________________________________ 3. Will a BIST engine be employed? _________________________________________ Note: Micron memory does not include on-chip BIST circuitry. 4. Minimum and maximum temperatures package will be tested at ____________ 5. Will the memories be tested separately? ___________________________________ b. Will the final package be stressed for reliability? ______________________________ 1. If so, how? _____________________________________________________________ Voltage range __________________________________________________________ Temperature range _____________________________________________________ Duration of stress ______________________________________________________ PDF: 09005aef80f55803/Source: 09005aef80f557e2 CSN18.fm - Rev. 4/09 EN.L 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. THIS QUESTIONNAIRE IS NOT A CONTRACT OR AGREEMENT, DOES NOT IMPOSE OBLIGATIONS ON BEHALF OF MICRON, AND IS FOR INFORMATIONAL PURPOSES ONLY. CSN-18: Bare Die SiPs and MCMs Introduction 5. Quality and Reliability Requirements (refer to Micron technical note TN-00-14) a. What are your initial “time zero” quality (DPM) expectations? __________________ 1. How will quality be measured in the final package? _________________________ b. What are your reliability expectations (extrinsic and intrinsic failure rates? _____________________________________________________________ 1. For NAND, please list any bit error rate requirements or expectations _________ _______________________________________________________________________ 2. How will reliability be measured? _________________________________________ 7. Your Company Name:______________________________________________________________________ Title: _______________________________________________________________________ Division: ___________________________________________________________________ 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef80f55803/Source: 09005aef80f557e2 CSN18.fm - Rev. 4/09 EN.L 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. THIS QUESTIONNAIRE IS NOT A CONTRACT OR AGREEMENT, DOES NOT IMPOSE OBLIGATIONS ON BEHALF OF MICRON, AND IS FOR INFORMATIONAL PURPOSES ONLY. CSN-18: Bare Die SiPs and MCMs Revision History Revision History Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/09 • Updated form • Updated template Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/03 • Initial release PDF: 09005aef80f55803/Source: 09005aef80f557e2 CSN18.fm - Rev. 4/09 EN.L 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.