DDR333 Design Guide for Two-DIMM Unbuffered Systems

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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
TECHNICAL
NOTE
DDR333 MEMORY DESIGN GUIDE
FOR TWO-DIMM UNBUFFERED
SYSTEMS
DDR memory busses vary depending on the intended
market for the finished product. Some products must
support four or more registered DIMMs, some are pointto-point topologies. This document focuses on solutions
requiring two unbuffered DIMMs operating at a data
rate of 333 MHz and is intended to assist board designers with the development and implementation of their
products.
The document is split into two sections. The first section uses data gathered from a chipset and motherboard designed by Micron to provide a set of board
design rules. These rules are meant to be a starting point
for a board design. The second section details the process of determining the portion of the total timing budget allotted to the board interconnect. The intent is that
board designers will use the first section to develop a set
of general rules and then, through simulation, verify the
design in their particular environment.
of the address and command bus, so the system can
have one or two DIMMs per copy. Further, the address
bus can be clocked using 1T or 2T clocking. With 1T, a
new command can be issued on every clock cycle. 2T
timing will hold the address and command bus valid
for two clock cycles. This reduces the efficiency of the
bus to one command per two clocks, but it doubles the
amount of setup and hold time. The data bus remains
the same for all of the variations in the address bus.
This design guide covers a DDR system using two
unbuffered DIMMs, operating at a 333 MHz data rate
and two variations of the address and command bus.
The first variation covered is a system with two DIMMs
on the address and command bus using 1T clocking. A
block diagram of this topology is shown in Figure 1.
The second variation is a system with two DIMMs on
the address and command bus using 2T clocking. This
topology is shown in Figure 2. Please note that the
guidelines provided in this section are intended to provide a set of rules for board designers to follow. It is
always advisable to simulate the final implementation
to ensure proper functionality.
Introduction
Systems using unbuffered DIMMs can implement
the address and command bus using various configurations. For example, some controllers have two copies
Figure 1:
Two-DIMM Unbuffered DDR333 MHz
Topology 1T Address and Command Bus
Figure 2:
Two-DIMM Unbuffered DDR333 MHz
Topology 2T Address and Command Bus
VREF
VREF
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CLK5, CLK5#
Data
1
VTT
Regulator
DDR DIMM
Parallel Termination Resistors
CLK4, CLK4#
Series
Resistors
VTT
Regulator
DDR DIMM
CLK1, CLK1#
CLK2, CLK2#
CLK3, CLK3#
Series
Resistors
Data
CLK0, CLK0#
DDR
Memory
Controller
Series
Resistors
CLK5, CLK5#
Parallel Termination Resistors
CLK4, CLK4#
DDR DIMM
CLK1, CLK1#
CLK2, CLK2#
CLK3, CLK3#
Series
Resistors
CLK0, CLK0#
DDR
Memory
Controller
DDR DIMM
Command/Address
Command/Address
Series
Resistors
Capacitor to ground
on each Address and
Command signal.
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©2002, Micron Technology Inc.
TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR Signal Grouping
The signals that compose a DDR memory bus can
be broken into three unique groupings, each with their
own configuration and routing rules.
bus runs at a clock rate of 167 MHz. The address and
command signals are captured at the DRAM using the
memory clocks. For a system with two unbuffered
DIMMs on a single address and command bus, the
loading on these signals will differ greatly depending
on the type and number of DIMMs installed. A twoDIMM channel loaded with two double-sided DIMMs
has 36 loads on the address and command signals.
Under this heavy loading, the slew rate on the address
bus is slow. The reduced slew rate makes it difficult, if
not impossible, to meet the setup and hold times at the
DRAM. To address this issue, the controller can use 2T
address timing—increasing the time available for the
address command bus by one clock period. Note that
CS and CKE timing are not changed between 1T and
2T addressing.
Data Group: Data Strobe DQS[8:0], Data Mask
DQM[8:0], Data DQ[63:0], and Check Bits CB[7:0]
Address and Control Group: Bank Address
BA[1:0], Address A[13:0], and Command Inputs
RAS#, CAS#, and WE#. Note that Clock Enable
CKE[3:0], and Chip Select S[3:0]# are also part of
the command signals but they have different
loading and timing.
Clock Group: Differential Clocks CK[5:0] and
CK#[5:0]
Board Stackup
A two-DIMM DDR channel can be routed on a
four-layer board. The layout should be done using
controlled impedance traces of Zo = 60 ohm (±10%)
characteristic impedance. The example stackup is
shown in Figure 3. The trace impedance is based on a
5-mil-wide trace and 1/2 oz. copper.
Routing Rules
It is important that the address and command lines
be referenced to a solid ground or power plane. On a
four-layer board, the address and command would
typically be routed on the second signal layer referenced to a solid power plane. The system address and
command signals should be ground or power referenced over the entire bus to provide a low-impedance
current return path. The address and command signals should be kept from the data group signals, from
the controller to the first DIMM. Address and command signals are captured at the DIMM using the
clock signals, so they must maintain a length relationship to the clock signals at the DIMM.
Figure 3:
Sample Board Stackup
Component Side - Signal Layer 1
(0.5 oz. cu.)
5.5 mil Pregreg
Ground Plane
(1 oz. cu.)
Figure 4:
DDR Address and Command Signal
Group Routing Topology
~42 mil Core
Pad on Die
Pin on Package
Address and
Control
5.5 mil Pregreg
Power Plane
(1 oz. cu.)
A
Solder Side - Signal Layer 2
(0.5 oz. cu.)
DDR
Memory
Controller
B
DIMM1
DIMM2
VTT
Rs
Rp
C
D
E
Address and Command Signals 2T Clocking
On a DDR memory bus, the address and command
signals are unidirectional signals driven by the memory controller. For DDR333, the address and command
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Table 1:
Address and Command Signals 1T Clocking
Address and Command
Group Routing Rules
On a DDR memory bus, the address and command
signals are unidirectional signals always driven by the
memory controller. For DDR333, the address runs at a
clock rate of 167 MHz. The address and command signals are captured at the DRAM using the memory
clocks. For a system with two unbuffered DIMMs on a
single address and command bus, the loading on these
signals will differ greatly depending on the type and
number of DIMMs installed. A two-DIMM channel
loaded with two double-sided DIMMs has 36 loads on
the address and command signals. The heavy capacitive load causes a significant reduction in signal slew
rate and voltage margin at the DRAM. The reduced
voltage margin causes a reduction in timing margin. As
a result, setup and hold times at the DRAM may not be
met.
To address the poor margin, Micron has developed
a compensated bus topology. This topology uses a
capacitor to ground in place of the series damping
resistor. A block diagram of this topology is shown in
Figure 7.
Figure 5 and Figure 6 are scope captures taken off
two address signals on the same system. The boxes
drawn in the center of the address eye show the setup
and hold times at VIH and VIL DC. Both signals are captured in a system populated with two double-sided
DIMMs. This is the worst-case address loading situation in this type of system. All measurements are taken
at room temperature and nominal voltage. The
address signal in Figure 5 is using a series and parallel
resistor topology. As one can see, the address signal
has a slow slew rate and a low maximum VIH. The combined result is a severe reduction in address setup and
hold times. Under corner conditions, it is possible for
this architecture to violate the DRAM setup and hold
times, resulting in unstable system operation. In
Figure 6, the address line is using the compensated
capacitor architecture. The scope capture clearly
shows the improved signal quality and larger address
valid window.
LENGTH
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the
ASIC package.)
B = 1.5in.–2.8in.
C = 0.4in.–0.6in.
D = 0.425in.
E = 0.2in.–0.55in.
Total: A + B + C = 2.4in.–3.2in.
LENGTH MATCHING
±100 mils of memory clock length at the DIMM*
TRACE
Trace Width = 5 mils
Trace Space = 15 mils reducing to 11.5 mils going
between the pins of the DIMM.
Trace Space from DIMM pins = 7 mils
Trace Space to other signal groups = 20 mils
*This value is controller-dependent; see Routing Rules on
page 8.
Series Resistors (Rs)
Location: The series resistors should be located
near the first DIMM for ease of routing.
Value: The value of Rs can vary depending on the
bus topology.
Range: 10 ohms–25 ohms*
Recommended: 20 ohms*
Parallel/Pull-up Resistor (Rp) Termination
Resistor
Location: The parallel termination resistors
should be placed behind the last DIMM slot and
attached to the VTT power island.
Value: The value of the parallel resistor can vary
depending on the bus topology.
Range: 25 ohms–56 ohms*
Recommended: 36 ohms*
*A recommended value. A range of values is provided
for simulation when there is a need to deviate from the
recommendation.
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 5:
Uncompensated Address Line
Figure 7:
DDR Address and Command Signal
Group Routing Topology
Pad on Die
Pin on Package
DIMM1
DIMM2
Address and
Control
A
B
C
D
E
CCOMP
DDR
Memory
Controller
Table 2:
VTT
Rp
Address and Command
Group Routing Rules
LENGTH
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the
ASIC package.)
B = 0.4in.–1.4in.
C = 1.6in.–2.2in.
D = 0.425in.
E = 0.2in.–0.55in.
Figure 6:
Compensated Address Line
Total: A + B + C = 2.4in.–3.2in.
LENGTH MATCHING
±100 mils of memory clock length at the DIMM*
TRACE
Trace Space = 15 mils reducing to 11.5 mils going
between the pins of the DIMM.
Trace Space from DIMM pins = 7 mils
Trace Space to other signal groups = 20 mils
*This value is controller-dependent; see Routing Rules
on page 8.
Routing Rules
mand signals are captured at the DIMM using the
clock signals, so they must maintain a length relationship to the clock signals at the DIMM.
It is important that the address and command lines
be referenced to a solid ground or power plane. On a
four-layer board, the address and command would
typically be routed on the second signal layer referenced to a solid power plane. The system address and
command signals should be ground or power referenced over the entire bus to provide a low-impedance
current return path. The address and command signals should be kept from the data group signals, from
the controller to the first DIMM. Address and com-
Compensation Capacitor (CCOMP)
Location: CCOMP should be located such that
lengths B and C are close to equal.
Value: The value of CCOMP can vary depending
on the bus topology.
Range: 45pF–82pF*
Recommended: 82pF*
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Parallel/Pull-Up Resistor (Rp)
Termination Resistor
Table 3:
Location: The parallel termination resistors
should be placed behind the last DIMM slot and
attached to the VTT power island.
Value: The value of the parallel resistor can vary
depending on the bus topology.
Range: 25 ohms–56 ohms*
Recommended: 36 ohms*
*A recommended value. A range of values is provided
for simulation when there is a need to deviate from the
recommendation.
Data to Data Strobe
Grouping
DATA
DATA STROBE
DATA MASK
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
CB[7:0]
DQS 0
DQS 1
DQS 2
DQS 3
DQS 4
DQS 5
DQS 6
DQS 7
DQS 8
DM 0
DM 1
DM 2
DM 3
DM 4
DM 5
DM 6
DM 7
DM 8
Figure 8:
DDR Data Byte Lane Routing Topology
Data Signals
In a DDR system, the data is captured by the memory and the controller using the data strobe rather than
the clock. To achieve the double data rate, data is captured on the rising and falling edges of the data strobe.
Each eight bits of data has an associated data strobe
(DQS) and a data mask bit (DM). Since the data is captured off the strobe, the data bits associated with the
strobe must be length matched closely to their strobe
bit. This group of data and data strobe is referred to as
a byte lane. The length matching between byte lanes is
not as tight as it is within the byte lane. Table 3 shows
the data and data strobe byte lane groups. Figure 8
shows the signals in a single-byte lane and the bus
topology for the data signals.
Pad on Die
Pin on Package
DQ Byte Group X
A
DIMM1
DIMM2
VTT
Rs
B
Rp
C
D
E
C
D
E
C
D
E
DQS[X]
A
B
DM[X]
A
B
DDR
Memory
Controller
Table 4:
Data Group Routing Rules
Routing Rules
LENGTH
It is important that the data lines be referenced to a
solid ground plane because they are operating at twice
the frequency of the address and command signals.
These high-speed data signals require a good ground
return path to avoid degradation of signal quality due
to inductance in the signal return path. The system
memory signals should be ground referenced from the
memory controller to the DIMM connectors and from
DIMM connector to DIMM connector to provide a
low-impedance current return path.
This is accomplished by routing the data signals on
the top layer for the entire length of the signal. The
data signals should not have any vias. To help reduce
cross talk noise, the data strobe signals are shielded on
each side by a 5-mil ground trace.
We recommend stitching shield track to ground
every inch to reduce transient currents.
A = Obtain from DRAM controller vendor. (A is the
length from the die pad to the ball on the ASIC
package.)
B = 1.5in.–2.8in.
C = 0.4in.–0.6in.
D = 0.425in.
E = 0.2in.–0.55in.
Total: A + B + C = 2.4in.–3.2in.
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LENGTH MATCHING IN DATA/STROBE BYTE LANE
±100 mils from data strobe
LENGTH MATCHING BYTE LANE TO BYTE LANE
±0.5in. of memory clock length
TRACE
Trace Width = 5 mils
Trace Space = 15 mils reducing to 11.5 mils going
between the pins of the DIMM.
Trace Space from DIMM pins = 7 mils
Trace Space to other signal groups = 20 mils
5
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Clock Signals
Figure 9:
DDR Clock Signal Group Routing
Topology
The memory clocks CK[5:0] and CK#[5:0] are used
by the DRAM on a DDR bus to capture the address and
command data. Unbuffered DIMMs require three
clock pairs per DIMM. Some DDR memory controllers
will drive all of these clocks, and others will require an
external clock driver to generate these signals. In this
example, it is assumed that the memory controller will
drive the six clock pairs required for a two-DIMM
unbuffered system. Clocks are differential signals, so
they do not get connected to VTT like the other signals
of a DDR bus. The clocks are differential pairs and
must be routed as a differential pair. Each clock pair is
differentially terminated on the DIMM by a 120 ohm
resistor. Figure 9 shows the routing topology used for
the clocks. In this figure, only one of the three clock
pairs required by each DIMM is shown.
Pad on Die
CK[2:0]
A
A
DIMM1
DIMM2
Rs
B
CK#[2:0]
B
C
C
CK[5:3]
A
A
B
CK#[5:3]
B
C2
C2
DDR
Memory
Controller
Routing Rules
Series Resistors (Rs)
The clocks are routed as a differential pair from the
controller to the DIMM. The clocks are used to capture
the address signals at the DIMM, so they must maintain a length relationship to the address signals at the
DIMM they are connected to. Different controllers
handle the address clock relationship differently—
some controllers have the ability to adjust the address
to clock delay and others use a fixed delay. Memory
controllers with a variable delay can better center the
clock in the address valid eye over varying load conditions. Controllers with a fixed delay may require different routing of the clocks to compensate for different
loading on the clock versus the address. The rules in
this section are based on a controller that has variable
clock delay.
Location: The series resistors should be located
near the first DIMM for ease of routing.
Value: The value of the series resistor can vary
depending on the bus topology.
Range: 10 ohms–25 ohms*
Recommended: 20 ohms*
Parallel/Pull-Up Resistor (Rp)
Termination Resistor
Location: The parallel termination resistors
should be placed behind the last DIMM slot and
attached to the VTT power island.
Value: The value of the parallel resistor can vary
depending on the bus lengths used.
DDR Memory Power Supply
Requirements
Range: 25 ohms–56 ohms*
A DDR bus implementation requires three separate
power supplies. The DRAM and the memory portion of
the controller require a 2.5-volt supply. The 2.5-volt
supply provides power for the DRAM core and I/O as
well as at least the I/O of the DRAM controller. The
second power supply is VREF, which is used as a reference voltage by the DRAM and the controller. The
third supply is VTT, which is the termination supply of
the bus. Table 6 lists the tolerances of each of these
supplies.
Recommended: 36 ohms*
*A recommended value. A range of values is provided
for simulation when there is a need to deviate from the
recommendation.
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Pin on Package
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Table 5:
MVTT Layout Recommendations
Clock Group Routing Rules
• Place the MVTT island on the component-side
signals layer at the end of the bus behind the last
DIMM slot.
• Use a wide-island trace for current capacity.
• Place VTT generator as close to termination
resistors as possible to minimize impedance
(inductance).
• Place one or two 0.1µf decoupling caps by each
termination RPACK on the MVTT island to minimize the noise on VTT. Other bulk (10µf–22µf )
decoupling is also recommended to be placed on
the MVTT island.
LENGTH
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the
ASIC package.)
B = 1.5in.–2.8in.
C = 0.4in.–0.6in.
C2 =0.825in.–1.025in.
LENGTH MATCHING
±30 mils for CKE to CKE#
±30 mils clock pair to clock pair at the DIMM
TRACE
Trace Width = 10 mils
Trace Space = 5 mils
Trace Space to other signal groups = 20 mils
MVREF Voltage
The memory reference voltage, MVREF, requires
approximately 3mA of current at a voltage level of 1/2
VDD with a tolerance shown in Table 6. VREF can be
generated using a simple resistor divider with one percent or better accuracy. VREF must track 1/2 of VDD
over voltage, noise, and temperature changes.
• Peak-to-peak AC noise on VREF may not exceed
±2 percent VREF (DC).
Series Resistor (Rs)
Location: The series resistor is located near the
driver.
Value: The value of the series resistor can vary
depending on the bus topology.
Range: 22 ohms–25 ohms
MVREF Layout Recommendations
Recommended: 22 ohms
• Use 30-mil trace between decoupling cap and
destination.
• Maintain a 25-mil clearance from other nets.
• Simplify implementation by routing VREF on the
top signal trace layer.
• Isolate VREF and/or shield with ground.
• Decouple using distributed 0.01µf and 0.1µf
capacitors by the regulator, controller, and DIMM
slots. Place one 0.01µf and 0.1µf near pin one of
each DIMM. Place one 0.1µf near the source of
VREF, one near the VREF pin on the controller, and
two between the controller and the first DIMM.
MVTT Voltage
The memory termination voltage, MVTT, requires
current at a voltage level of 1.25 VDC. See Figure 6 for
the VTT tolerance. VTT must be generated by a regulator that is able to sink and source current while still
maintaining the tight voltage regulation.
• VREF and VTT must track variations in VDD over
voltage, temperature, and noise ranges.
• VTT of the transmitting device must track VREF of
the receiving device.
Table 6:
SYMBOL
VDD (V25)
VREF
VTT
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Required Voltages
PARAMETER
Device Supply Voltage
Memory Reference Voltage
Memory Termination Voltage
MIN
TYPICAL
MAX
UNIT
2.3
(0.5 × VDD) - 25mV
VREF - 640mV
2.5
0.5 × VDD
VREF
2.7
(0.5 × VDD) + 25mV
VREF + 40mV
V
V
V
7
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Timing Budget
DDR Data Write Budget
The previous section is useful for getting an idea of
how the DDR memory bus functions and the general
relationship between the signals on the bus. However,
if a design should deviate from the given example, the
routing rules for the design can change. Since it is
unlikely that every design will follow the given example exactly, it is important to simulate the design. One
of the objectives of simulation is to determine if the
design will meet the signal timing requirements of the
DRAM and DDR controller. To meet this objective, a
timing budget must be generated. This section shows
how to use the data provided in the DDR DRAM and
DDR controller data sheets to determine the amount
of the total timing budget that the board interconnect
can consume.
Table 7 gives a breakdown of the timing budget for
DDR WRITEs at 333 MHz. The portion of the budget
consumed by the DRAM device and by the DDR controller is fixed and cannot be influenced by the board
designer. The amount of the total budget remaining
after subtracting the portion consumed by the DRAM
and the controller is what remains for the board interconnect. This is the portion that is used to determine
the bus routing rules. The different components of the
board interconnect are outlined. The board designer
can make trade-offs with trace spacing, length matching, resistor tolerance, etc., to determine the best interconnect solution.
Table 7:
DDR Write Budget
ELEMENT
SKEW COMPONENT
Transmitter
DRAM device
(from spec)
Interconnect
Total Interconnect
Total Budget
Total Budget
Consumed by
Controller and DRAM
Interconnect Budget
SETUP
HOLD
UNITS
Total Skew at Transmitter
DH/tDS
Total Device
XTK (cross talk) - DQ
550
450
450
100
550
450
450
100
ps
ps
ps
ps
XTK (cross talk) - DQS
30
30
ps
ISI - DQ
ISI - DQS
Path Matching
15
5
15
15
5
15
ps
ps
ps
Input Capacitance Matching
95
95
ps
RTERM VOH/VOL Skew (1%)
Input Eye Reduction (VREF)
20
100
20
100
ps
ps
Strobe-to-Data Skew
10
+10
ps
Interconnect Skew
3000/2 @ 333 MHz
Transmitter + DRAM
390
1500
1000
390
1500
1000
ps
ps
ps
Total - (transmitter + DRAM)
500
500
ps
t
COMMENTS
From data sheet
From data sheet
4 aggressors (a pair on each
side of the victim)
1 shielded victim, 2 aggressors
(PRBS)
Within byte lane:
165 ps/in. × 0.1in.;
motherboard routes account
for memory controller package
skew
4.0pF and 5.0pF loads, strobe
and data shift differently
±75mV included in DRAM
skew; additional =
(±25mV)/(.5 V/ns); this includes
DQ and DQS
Strobe shifts relative to data
(1010 pattern vs. PRBS)
From simulation
Must be greater than amount
consumed by board
interconnect
NOTE:
These are worst-case slow numbers (100C, 2.375V, slow process).
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Determining DRAM Write Budget
Consumption
Determining DDR Controller Write Budget Consumption
The amount of the write budget consumed by the
DRAM is easily obtained from the data sheets. The
DRAM data sheet provides the data input hold time
relative to strobe (tDH) and the data input setup time
relative to strobe (tDS). These numbers are entered
directly into the timing budgets for setup and hold.
They account for all of the write timing budget consumed by the DRAM.
To calculate the amount of the setup timing budget
consumed by the DDR controller on a DRAM WRITE,
find the value for tDQSU minimum. This is the minimum amount of time all data will be valid before the
data strobe transitions shown in Figure 10. tDQSU
should take clock asymmetry into account. In an ideal
situation, tDQSU would be equal to 1/4 × tCK. The difference between 1/4 × tCK and tDQSU is the amount of
the write timing budget consumed by the controller
for setup. From this, the following equation is derived.
Controller setup data valid reduction = 1/4 × tCK t
DQSU.
To calculate the hold time, use the same equation,
but use tDQHD in place of tDQSU.
Figure 10:
Memory Write and ADDR/CMD Timing
T0
T1
T2
T3
T4
T5
T6
tDQSS
tADSU
tADHD
CK
ADDR/
CK
tDSH
tDSS
tWPST
DQS
DQ
tDQSU
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A
A
A
A
tDQHD
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR Data Read Budget
Table 8 gives a breakdown of the timing budget for
DDR reads at 333 MHz. The portion of the budget consumed by the DRAM device and by the DDR controller
is fixed and cannot be influenced by the board
Table 8:
designer. The amount of the total budget remaining
after subtracting the portion consumed by the DRAM
and the controller is what remains for the board
interconnect.
DDR Read Budget
ELEMENT
SKEW COMPONENT
SETUP
HOLD
UNITS
DRAM device
(from spec)
t
6
2.70
6
2.70
ns
ns
t
350
350
ps
t
500
500
ps
t
2.20
2.20
ns
t
1.85
1.85
ns
(tCK/2 - tDV)/2
Total DRAM Data Valid
Reduction
Total Skew at Receiver
575
575
ps
575
575
ps
From data sheet
550
550
ps
From data sheet
XTK (cross talk) - DQ
70
70
ps
XTK (cross talk) - DQS
35
35
ps
ISI - DQ
ISI - DQS
Path Matching
50
15
20
50
15
20
ps
ps
ps
4 aggressors (a pair on each
side of the victim)
1 shielded victim, 2 aggressors
(PRBS)
Spice-generated eye diagram
Rterm VOH/VOL Skew (1%)
Input Eye Reduction (VREF)
20
100
20
100
ps
ps
Total Skew at Interconnect
3000/2 @ 333 MHz
Receiver + DRAM
310
1500
1125
310
1500
1125
ps
ps
ps
Total - (transmitter + DRAM)
375
375
ps
Clock
t
t
HP ( CL/ CH[MIN] at 45/55)
DQSQ
QHS
QH (tHP - tQHS)
DV (tHP - tDQSQ - tQHS, or
QH - tDQSQ)
COMMENTS
t
DRAM Total
Receiver
(controller)
Interconnect
Total Interconnect
Total Budget
Total Budget
Consumed by
Controller and DRAM
Interconnect Budget
Within byte lane:
165 ps/in. × 0.1in.; MB routes
acct. for MC pkg. skew
±75mV included in DRAM
skew; additional =
(±25 mV)/(.5 V/ns); this includes
DQ and DQS
From simulation
Must be greater than amount
consumed by board
interconnect
NOTE:
These are worst-case slow numbers (100C, 2.375V, slow process).
TN-46-07
TN4607.fm - Rev 12/02
10
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 11:
DRAM Read Data Valid
tCK/2
tHP
= 3.0ns
= 2.7ns ([email protected]/55) Clock Duty Cyle = 45/55%
tQH
tDQSQ = 350ps
tQHS
= 2.2ns
= 500ps
DVW = 1.85ns
DQS
DQ (last data valid)
DQ (first data no longer valid)
All DQs and DQS, collectively
Data Valid Window
Figure 12:
Read Data Timing
T1
T0
T2
T3
T4
CK
tHP
tHP
tHP
tDQSQ
tHP
tDQSQ
tHP
tDQSQ
tHP
tHP
tDQSQ
DQS
D
DQ (last data valid)
D
D
D
D
D
D
DQ (byte), collectively
tDV
D
tQH
tDV
tQH
tDV
Using the DRAM data sheet and filling in numbers for
the timing parameters in Figure 11, the total data valid
window at the DRAM can be calculated using the following equation:
Figure 11 shows how the information from the
DRAM data sheet affects the total data valid window as
the data is driven from the DRAM device. This information is used in the timing budget to determine the
amount of the total data timing budget that is consumed by the DRAM device. The total budget for the
data is half the clock period. This time is halved again
to determine the time allowed for setup and hold.
TN-46-07
TN4607.fm - Rev 12/02
D
tQH
tDV
D
D
D
Determining DRAM Read Budget
Consumption
D
D
D
tQH
D
D
D
D
D
D
D
D
D
D
D
D
D
DQ (first data no
longer valid)
D
D
D
D
DVW = tHP - tDQSQ - tQHS
t
CK/2 - DVW/2 = DRAM data valid reduction.
The DRAM data valid reduction is used in the timing
budget for setup and hold.
11
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Determining DDR Controller Read
Budget Consumption
Determining DRAM Address Budget
Consumption
When read data is received at the controller from
the DRAM, the strobe is edge aligned with the data. It
is the responsibility of the controller to delay the
strobe and then use the delayed strobe to capture the
read data. The controller will have some minimum
value it can accept for a data valid window. Internally,
the controller has a minimum setup and hold time that
the data must maintain from the internally delayed
strobe. Half the data valid window is the setup or hold
time required by the controller plus any controllerintroduced signal skew and strobe centering uncertainty. The timing diagram example in Figure 12 shows
the timing parameters required for calculating the data
valid window. tDQSQ is the maximum delay from the
last data signal to go valid after the strobe transitions.
t
QH is the minimum time all data must remain valid
after strobe transitions. Use the following equation to
obtain tDV:
The portion of the address budget consumed by the
DRAM is obtained by getting the value of tIS for setup
and tIH for hold. tIH and tIS are the setup and hold
times required by the DRAM inputs. For systems with
heavy loading on the address and command lines, the
value in the data sheet must be derated depending on
the slew rate. For Micron DDR DRAM, the setup time is
raised by 50ps for each 100 mV/ns that the slew rate
drops below 0.5 V/ns. The hold time is not changed.
t
t
Determining Controller Address Budget
Consumption
The DRAM controller will provide a minimum setup
and hold time for the address and command signals
with respect to clock. This is the amount of the setup
and hold budget consumed by the controller.
Clock to Data Strobe Relationship
t
DV = QH - DQSQ.
The DDR DRAM and the DDR controller must move
the data from the data strobe clocking domain into the
DDR clock domain when the data is latched internally.
Due to this requirement, the data strobe must maintain a relationship to the DDR clock. For the DDR
DRAM, this relationship is specified by tDQSS. This
timing parameter states that after a WRITE command,
the data strobe must transition 0.75 to 1.25 × tCK.
Figure 10 shows the DDR controller also specifies a
t
DQSS timing parameter. This is the time after the
WRITE command that the data strobe will transition.
For the controller in this example, tDQSS = ±0.06 × tCK.
The following equation is used to calculate the amount
of clock to data strobe skew that is left for consumption by the board interconnect:
t
Assuming DV is split evenly between setup and
hold, the portion of the timing budget consumed by
the controller for setup and hold is 1/2 tDV. For the
controller used in this example, an even split between
setup and hold can be assumed because the controller
determining the center of the data eye during the
bootup routine and the DLL maintains this relationship over temperature and voltage variations.
Address Timing Budget
Table 9 gives a breakdown of the timing budget for
1T address and command at a 167 MHz clock rate. The
portion of the budget consumed by the DRAM device
and the DDR controller is fixed and cannot be influenced by the board designer. The amount of the total
budget remaining after subtracting the portion consumed by the DRAM and the controller is what
remains for the board interconnect.
TN-46-07
TN4607.fm - Rev 12/02
Interconnect budget = DRAM tDQSS - Controller
DQSS
t
Using this equation, it is apparent that this is not
one of the strict timing requirements of a DDR channel. If the clocks are routed so they are between the
shortest and longest strobe lengths, the designer gains
some leeway in the data strobe to data strobe byte lane
routing restrictions.
12
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Table 9:
Address Timing Budget
ELEMENT
SKEW COMPONENT
Transmitter
SETUP
HOLD
UNITS
550
550
ps
Chipset
Receiver
Memory Controller
Transmitter
DRAM Skew
850
750
ps
t
Interconnect
Cross Talk: Address
640
640
ps
ISI: Address
Cross Talk: Clock
VREF: Reduction
690
25
50
690
25
50
ps
ps
ps
Path Matching
15
15
ps
Input Capacitance Matching
105
105
ps
Compensating Capacitor
Skew (5%)
Rterm VOH/VOL Skew (1%)
Total Skew at Interconnect
6000 @ 333 MHz
Transmitter + DRAM
60
60
ps
10
1595
3000
1400
10
1595
3000
1300
ps
ps
ps
ps
Total - (Transmitter + DRAM)
1600
1700
ps
Total Interconnect
Total Budget
Total Budget
Consumed by
Controller and DRAM
Interconnect Budget
COMMENTS
IS, tIH from DRAM spec (slow
edge). tIS: additional 50ps for
every 0.1 V/ns below 0.5 V/ns
(0.3 V/ns)
1 victim (1010...), 4 aggressors
(PRBS)
(PRBS)
Spec.
±75mV included in DRAM
skew; additional =
(±25mV)/(.5 V/ns)
Within byte lane: 165 ps/in. ×
0.1in.; MB routes acct. for MC
pkg. skew
1.5pF for 5 device, 2.5pF for 18
device (1610-1400) = 210 total
Compensating capacitor
5% tolerance
Estimator tool
333 MHz bit width
NOTE:
These are worst-case slow numbers (100C, 2.375V, slow process).
Appendix: Simulation Result Data
Data Bus Simulation Conditions
STANDARD TERMINATION
Rs = 20
Controller Ron = 15
DRAM Ron = 15
Rp = 36 ohms
B = 2,200 mils
C = 400 mils
D = 425 mils
E = 400 mils
Rise Time = 750ps
Data Rate = 333 MHz
TN-46-07
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 13:
SSTL READs Rs = 20 Rstub = 22 Rp = 36 Pitch = 0.425”
Slot 1
ISI1 = 9
Apert21 = 2.496
DD
SlewR1 = 1.42
DS
ISI3 = 23
Apert23 = 2.493
SlewR3 = 1.43
ISI4 = 11
Apert24 = 2.404
SlewR4 = 1.19
ISI9 = 25
Apert29 = 2.551
SlewR9 = 1.64
ISI10 = 30
Apert210 = 2.556
SlewR10 = 1.69
SD
ISI5 = 13
Apert25 = 2.471
SlewR5 = 1.33
ISI6 = 24
Apert26 = 2.464
SlewR61 = 1.37
Slot 2
ISI2 = 11
Apert22 = 2.434
DD
SlewR2 = 1.27
DS
SD
Slot 1
ISI7 = 29
Apert27 = 2.477
SlewR7 = 1.37
SS
D–
ISI11 = 28
S–
Apert211 = 2.559
SlewR11 = 1.67
ISI12 = 31
Apert212 = 2.556
SlewR12 = 1.75
Slot 2
ISI8 = 26
Apert28 = 2.446
TN-46-07
TN4607.fm - Rev. 12/02
SlewR8 = 1.31
SS
–D
14
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 14:
SSTL Writes Rs = 20 Rstub = 22 Rp = 36 Pitch = 0.425”
Slot 1
ISI1 = 37
Apert21 = 2.033
DD
SlewR1 = 0.79
DS
ISI3 = 21
Apert23 = 2.210
SlewR3 = 0.93
ISI4 = 20
Apert24 = 2.358
SlewR4 = 1.17
ISI9 = 3
Apert29 = 2.431
SlewR9 = 1.26
SD
ISI5 = 23
Apert25 = 2.476
SlewR5 = 1.40
ISI6 = 26
Apert26 = 2.243
SlewR61 = 0.97
Slot 2
ISI2 = 38
Apert22 = 2.076
DD
SlewR2 = 0.80
DS
SD
Slot 1
ISI7 = 4
Apert27 = 2.516
SlewR7 = 1.46
SS
D–
ISI11 = 3
S–
Apert211 = 2.589
SlewR11 = 1.71
ISI12 = 3
Apert212 = 2.590
SlewR12 = 1.72
Slot 2
ISI8 = 5
Apert28 = 2.470
TN-46-07
TN4607.fm - Rev. 12/02
SlewR8 = 1.34
SS
–D
ISI10 = 8
Apert210 = 2.428
SlewR10 = 1.26
15
–S
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address Bus Simulation Conditions
STANDARD TERMINATION
COMPENSATED
Rs = 10
Controller Ron = 15
Rp = 33 ohms
B = 2,750 mils
C = 250 mils
D = 425 mils
E = 400 mils
Rise Time = 700ps
2T Cycle @ 83 MHz
A1 address line is simulated.
Waveforms shown are @ U1 memory device for
both the slots
Fcap = 82pF
Controller Ron = 15
(Except last slide, where it is 25)
Rp = 33 ohms
B = 1,500 mils
C = 1,500 mils
D = 425 mils
E = 400 mils
Rise Time = 700ps
1T Cycle @ 166 MHz
A1 address line is simulated.
Waveforms shown are @ U1 memory device for
both the slots
TN-46-07
TN4607p16.fm - Rev 12/02
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 15:
Standard Termination, 2T Cycle Slot 1
5,0
5,5
5,9
5,18
TN-46-07
TN4607.fm - Rev. 12/02
ISI1 = 29
Apert21 = 11.036
SlewR1 = 0.72
ISI1 = 22
Apert21 = 10.670
SlewR1 = 0.52
ISI1 = 47
Apert21 = 10.403
SlewR1 = 0.43
ISI1 = 38
Apert21 = 10.115
SlewR1 = 0.36
9,0
9,5
9,9
9,18
ISI1 = 31
Apert21 = 10.634
SlewR1 = 0.49
ISI1 = 13
Apert21 = 10.389
SlewR1 = 0.42
ISI1 = 25
Apert21 = 10.165
SlewR1 = 0.38
ISI1 = 85
Apert21 = 9.831
SlewR1 = 0.32
17
18,0
18,5
18,9
18,18
ISI1 = 79
Apert21 = 10.279
SlewR1 = 0.41
ISI1 = 15
Apert21 = 9.961
SlewR1 = 0.34
ISI1 = 6
Apert21 = 9.743
SlewR1 = 0.31
ISI1 = 77
Apert21 = 9.392
SlewR1 = 0.27
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 16:
Standard Termination, 2T Cycle Slot 2
0,5
5,5
5,9
5,18
ISI1 = 22
Apert21 = 10.982
SlewR1 = 0.68
ISI1 = 14
Apert25 = 10.578
SlewR5 = 0.48
ISI5 = 9
Apert251 = 10.255
SlewR51 = 0.39
ISI5 = 17
Apert25 = 9.866
SlewR5 = 0.32
TN-46-07
TN4607.fm - Rev. 12/02
0,9
9,5
9,9
9,18
ISI1 = 40
Apert21 = 10.608
SlewR1 = 0.49
ISI10 = 62
Apert210 = 10.249
SlewR10 = 0.39
ISI10 = 41
Apert210 = 10.025
SlewR10 = 0.35
ISI10 = 39
Apert210 = 9.596
SlewR10 = 0.29
18
0,18
18,5
18,9
18,18
ISI1 = 77
Apert21 = 10.244
SlewR1 = 0.40
ISI2 = 74
Apert22 = 9.974
Slew2 = 0.33
ISI2 = 6
Apert22 = 9.734
SlewR2 = 0.31
ISI2 = 22
Apert22 = 9.326
SlewR2 = 0.26
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 17:
Compensated, 1T Cycle Slot 1
5,0
5,5
5,9
5,18
ISI1 = 311
Apert21 = 4.925
SlewR1 = 0.77
ISI1 = 124
Apert21 = 4.955
SlewR1 = 0.70
ISI1 = 226
Apert21 = 4.643
SlewR1 = 0.58
ISI1 = 418
Apert21 = 4.221
SlewR1 = 0.43
TN-46-07
TN4607.fm - Rev. 12/02
9,0
9,5
9,9
9,18
ISI1 = 145
Apert21 = 4.998
SlewR1 = 0.71
ISI1 = 19
Apert21 = 4.921
SlewR1 = 0.64
ISI1 = 126
Apert21 = 4.742
SlewR1 = 0.60
ISI1 = 283
Apert21 = 4.476
SlewR1 = 0.46
19
18,0
18,5
18,9
18,18
ISI1 = 117
Apert21 = 4.848
SlewR1 = 0.62
ISI1 = 160
Apert21 = 4.653
SlewR1 = 0.55
ISI1 = 133
Apert21 = 4.576
SlewR1 = 0.53
ISI1 = 65
Apert21 = 4.422
SlewR1 = 0.44
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DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 18:
Compensated, 1T Cycle Slot 2
0,5
5,5
5,9
5,18
ISI1 = 326
Apert21 = 4.907
SlewR1 = 0.76
ISI5 = 45
Apert25 = 4.971
SlewR5 = 0.67
ISI5 = 127
Apert251 = 4.747
SlewR51 = 0.59
ISI5 = 291
Apert25 = 4.503
SlewR5 = 0.51
TN-46-07
TN4607.fm - Rev. 12/02
0,9
9,5
9,9
9,18
ISI1 = 148
Apert21 = 4.955
SlewR1 = 0.69
ISI10 = 199
Apert210 = 4.723
SlewR10 = 0.61
ISI10 = 186
Apert210 = 4.666
SlewR10 = 0.56
ISI10 = 369
Apert210 = 4.320
SlewR10 = 0.47
20
0,18
18,5
18,9
18,18
ISI1 = 133
Apert21 = 4.809
SlewR1 = 0.60
ISI2 = 333
Apert22 = 4.397
Slew2 = 0.51
ISI2 = 174
Apert22 = 4.531
SlewR2 = 0.54
ISI2 = 274
Apert22 = 4.217
SlewR2 = 0.45
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TN-46-07
DDR333 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Figure 19:
Compensated, 1T Cycle, Slot 1
(Ron = 25, to reduce excessive overshoot in lightly loaded cases)
Slot 1
5,0
ISI1 = 414
Apert21 = 4.547
SlewR1 = 0.59
ISI1 = 453
Apert21 = 4.519
SlewR1 = 0.54
9,0
ISI1 = 328
Apert23 = 4.505
SlewR1 = 0.53
ISI1 = 361
Apert21 = 4.433
SlewR1 = 0.48
18,0
ISI1 = 264
Apert21 = 4.426
SlewR1 = 0.46
ISI1 = 204
Apert21 = 4.247
SlewR 1 = 0.42
Slot 2
0,5
0,9
0, 18
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TN-46-07
TN4607.fm - Rev. 12/02
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