4Gb: x4, x8 TwinDie DDR3 SDRAM Functionality TwinDieTM DDR3 SDRAM MT41J1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks MT41J512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks For component data sheets, refer to Micron’s Web site: www.micron.com Functionality Options The 4Gb TwinDie™ DDR3 SDRAM uses Micron’s 2Gb DDR3 die and has similar functionality. This data sheet includes key timing parameters, ball assignments, a functional description, functional block diagrams, IDD specifications, and package dimensions. Refer to Micron’s 2Gb DDR3 SDRAM data sheet for complete specifications. (Specifications for base part number MT41J512M4 correlate to TwinDie manufacturing part number MT41J1G4; specifications for base part number MT41J256M8 correlate to TwinDie manufacturing part number MT41J512M8.) Features • Uses 2Gb Micron die • Two ranks (includes dual CS#, ODT, CKE, and ZQ balls) • Each rank has 8 internal banks • VDD = VDDQ = +1.5V ±0.075V • 1.5V center-terminated push/pull I/O • JEDEC-standard ball-out • Low-profile package • TC of 0°C to 95°C – 0°C to 85°C: 8192 refresh cycles in 64ms – 85°C to 95°C: 8192 refresh cycles in 32ms Table 1: Marking • Configuration – 64 Meg x 4 x 8 banks x 2 ranks – 32 Meg x 8 x 8 banks x 2 ranks • FBGA package (lead-free) – 82-ball FBGA (12.5 x 15 x 1.35mm) Rev. A – 78-ball FBGA (9 x 11.5 x 1.2mm) Rev. D • Timing – cycle time1 – 1.5ns @ CL = 10 (DDR3-1333) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 8 (DDR3-1066) – 1.87ns @ CL = 7 (DDR3-1066) – 2.5ns @ CL = 6 (DDR3-800) – 2.5ns @ CL = 5 (DDR3-800) • Self refresh – Standard • Operating temperature – Commercial (0°C ≤ TC ≤ 95°C) • Revision (82-ball FBGA) • Revision (78-ball FBGA) 1G4 512M8 THU THD -15 -15E -187 -187E -25 -25E None None :A :D Notes: 1. CL = CAS (READ) latency. Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -15 -15E -187 -187E -25 -25E 1333 1333 1066 1066 800 800 10-10-10 9-9-9 8-8-8 7-7-7 6-6-6 5-5-5 PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 1 t RCD (ns) 15 13.5 15 13.1 15 12.5 t RP (ns) CL (ns) 15 13.5 15 13.1 15 12.5 15 13.5 15 13.1 15 12.5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb: x4, x8 TwinDie DDR3 SDRAM Features Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 1024 Meg x 4 512 Meg x 8 64 Meg x 4 x 8 banks x 2 ranks 8K 32K A[14:0] 8 BA[2:0] 2K A[11, 9:0] 32 Meg x 8 x 8 banks x 2 ranks 8K 32K A[14:0] 8 BA[2:0] 1K A[9:0] 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 1: 82-Ball FBGA Ball Assignments – Rev. A (Top View) 1 2 3 4 9 10 11 NC VSS VDD NC 5 6 7 NF, NF/TDQS# VSS 8 VDD NC VSS VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ VSSQ NF, DQ6 DQS# VDD VSS VSSQ VREFDQ VDDQ NF, DQ4 ODT1 VSS RAS# CK VSS CKE1 ODT0 VDD CAS# CK# VDD CKE0 CS1# CS0# WE# A10/AP ZQ0 ZQ1 VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS A B C D NF, DQ7 NF, DQ5 VDDQ E F G H J K L M NC NC N Notes: 1. Balls with black dots are incremental to balls on the monolithic die. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions Figure 2: 78-Ball FBGA Ball Assignments – Rev. D (Top View) 1 2 3 VSS VDD NC 4 5 6 NF, NF/TDQS# VSS 7 8 VDD 9 VSS VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ VSSQ NF, DQ6 DQS# VDD VSS VSSQ VREFDQ VDDQ NF, DQ4 ODT1 VSS RAS# CK VSS CKE1 ODT0 VDD CAS# CK# VDD CKE0 CS1# CS0# WE# A10/AP ZQ0 ZQ1 VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS A B C D NF, DQ7 NF, DQ5 VDDQ E F G H J K L M N PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions Table 3: 82-Ball and 78-Ball FBGA Ball Descriptions Symbol Type Description A14, A13, A12/BC#, A11, A10/AP, A[9:0] Input BA[2:0] Input CK, CK# Input CKE[1:0] Input CS#[1:0] Input DM Input ODT[1:0] Input RAS#, CAS#, WE# Input RESET# Input DQ[3:0] I/O DQ[7:0] I/O DQS, DQS# I/O TDQS, TDQS# Output VDD Supply Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = burst length (BL) of 8 or no burst chop, LOW = burst chop (BC) of 4, burst chop). Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with the input data, during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edgealigned with read data. Input with write data. Center-aligned with write data. Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Power supply: 1.5V ±0.075V. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Ball Assignments and Descriptions Table 3: 82-Ball and 78-Ball FBGA Ball Descriptions (continued) Symbol Type VDDQ VREFCA Supply Supply VREFDQ VSS VSSQ ZQ[1:0] NC NF Description DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. Supply Ground. Supply DQ ground: Isolated on the device for improved noise immunity. Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Functional Description Functional Description The 4Gb (TwinDie) DDR3 SDRAM is a high-speed, CMOS dynamic random access memory device containing 4,294,967,296 bits and is internally configured as two 8-bank 2Gb DDR3 SDRAM. Although each die is tested individually within the dual-die package, some TwinDie test results may vary from a like-die tested within a monolithic die package. The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. The differential data strobes (DQS, DQS#) are transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. Read and write accesses to the DDR3 SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits (including CSn#, BAn, and An) registered coincident with the READ or WRITE command are used to select the rank, bank, and starting column location for the burst access. This data sheet provides a general description, package dimensions, and the package ballout. Refer to the Micron 2Gb DDR3 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Functional Block Diagrams Functional Block Diagrams Figure 3: Functional Block Diagram (64 Meg x 4 x 8 Banks x 2 Ranks) Rank 1 (64 Meg x 4 x 8 banks) Rank 0 (64 Meg x 4 x 8 banks) CS0# CS1# CKE1 CAS# RAS# ODT1 ZQ1 WE# RESET# CK CK# CKE0 A[14:0], BA[2:0] ODT0 ZQ0 DQS, DQS# DQ[3:0] DM Figure 4: Functional Block Diagram (32 Meg x 8 x 8 Banks x 2 Ranks) Rank 1 (32 Meg x 8 x 8 banks) Rank 0 (32 Meg x 8 x 8 banks) CS1# RAS# CKE1 CAS# ODT1 WE# RESET# ZQ1 CK CK# CS0# CKE0 A[14:0], BA[2:0] ODT0 ZQ0 DQS, DQS# DQ[7:0] DM/TDQS TDQS# PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 4: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDDQ VIN, VOUT II VDD supply voltage relative to VSS VDD supply voltage relative to VSSQ Voltage on any ball relative to VSS Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Operating case temperature Storage temperature –0.4 –0.4 –0.4 –4 1.975 1.975 1.975 +4 V V V µA 1 –2 +2 µA 2 0 –55 95 150 °C °C 3, 4 IVREF TC TSTG Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV. 2. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. 3. MAX operating case temperature. TC is measured in the center of the package (see Figure 5 on page 10). 4. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. Temperature and Thermal Impedance It is imperative that the DDR3 SDRAM device’s temperature specifications, shown in Table 5 on page 10, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. Thermal impedances listed in Table 6 on page 10 apply to the current die revision and packages. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08: “Thermal Applications,” prior to using the thermal impedances in Table 6. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the reduction in die size. The DDR3 SDRAM device’s safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications Table 5: Thermal Characteristics Parameter/Condition Symbol Value Units Notes TC 0 to 85 0 to 95 °C °C 1, 2, 3 1, 2, 3, 4 Operating case temperature Notes: 1. MAX operating case temperature. TC is measured in the center of the package (see Figure 5). 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if available, must be enabled. Table 6: Thermal Impedance Die Rev Package Substrate θJA (°C/W) Airflow = 0m/s A 82-ball D 78-ball 2-layer 4-layer 2-layer 4-layer 46.0 34.2 61.0 44.5 θJA (°C/W) Airflow = 1m/s θJA (°C/W) Airflow = 2m/s θJB (°C/W) θJC (°C/W) Notes 33.9 27.1 43.7 35.3 28.1 23.6 37.3 31.5 25.6 23.2 27.1 23.2 1.73 1 2.8 1 Notes: 1. Thermal resistance data is based upon a number of samples from multiple lots and should be viewed as a typical number. Figure 5: Temperature Test Point Location Test point Length (L) 0.5 (L) 0.5 (W) Width (W) PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications IDD Specifications and Conditions Table 7: DDR3 ICDD Specifications and Conditions – Rev. A Note 1 applies to the entire table. Combined Symbol Individual Die Status Width -25/ -25E -187/ -187E -15/ -15E Units ICDD0 ICDD0 = IDD0 + IDD2P0 + 5 ICDD1 ICDD1 = IDD1 + IDD2P0 + 5 ICDD2P0 (slow exit) ICDD2P1 (fast exit) ICDD2Q ICDD2N ICDD2NT ICDD3P ICDD3N ICDD4W ICDD2P0 = IDD2P0 + IDD2P0 x4 x8 x4 x8 x4/x8 92 117 117 132 24 107 137 132 152 24 117 147 147 172 24 mA mA mA mA mA 42 47 52 mA ICDD2Q = IDD2Q + IDD2P0 ICDD2N = IDD2N + IDD2P0 ICDD2NT = IDD2NT + IDD2P0 ICDD3P = IDD3P + IDD2P0 ICDD3N = IDD3N + IDD2P0 ICDD4W = IDD4W + IDD2P0 + 5 ICDD4R ICDD4R = IDD4R + IDD2P0 + 5 ICDD5B ICDD6 ICDD6ET ICDD7 ICDD5B = IDD5B + IDD2P0 ICDD6 = IDD6 + IDD6 ICDD6ET = IDD6ET + IDD6ET ICDD7 = IDD7 + IDD2P0 + 5 ICDD8 ICDD8 = 2 × IDD2P0 + 4 67 72 77 62 82 212 277 192 212 287 20 28 337 417 28 77 82 87 67 92 242 312 217 242 302 20 28 362 447 28 87 92 97 77 107 272 347 247 272 317 20 28 432 477 28 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ICDD2P1 = IDD2P1 + IDD2P0 x4/x8 x4/x8 x4/x8 x4/x8 x4 x8 x4 x8 x4/x8 x4/x8 x4/x8 x4 x8 All Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individual die valueS. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Electrical Specifications Table 8: DDR3 ICDD Specifications and Conditions – Rev. D Note 1 applies to the entire table. Combined Symbol Individual Die Status Width -187/ -187E -15/ -15E Units ICDD0 ICDD0 = IDD0 + IDD2P0 + 5 ICDD1 ICDD1 = IDD1 + IDD2P0 + 5 ICDD2P0 (slow exit) ICDD2P1 (fast exit) ICDD2Q ICDD2N ICDD2NT ICDD3P ICDD3N ICDD4W ICDD2P0 = IDD2P0 + IDD2P0 x4 x8 x4 x8 x4/x8 82 82 102 102 24 87 87 107 107 24 mA mA mA mA mA 32 37 mA ICDD2Q = IDD2Q + IDD2P0 ICDD2N = IDD2N + IDD2P0 ICDD2NT = IDD2NT + IDD2P0 ICDD3P = IDD3P + IDD2P0 ICDD3N = IDD3N + IDD2P0 ICDD4W = IDD4W + IDD2P0 + 5 ICDD4R ICDD4R = IDD4R + IDD2P0 + 5 ICDD5B ICDD6 ICDD6ET ICDD7 ICDD5B = IDD5B + IDD2P0 ICDD6 = IDD6 + IDD6 ICDD6ET = IDD6ET + IDD6ET ICDD7 = IDD7 + IDD2P0 + 5 ICDD8 ICDD8 = 2 × IDD2P0 + 4 42 44 52 42 47 147 147 142 142 202 24 30 287 287 28 47 49 57 47 52 167 167 162 162 217 24 30 337 337 28 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ICDD2P1 = IDD2P1 + IDD2P0 x4/x8 x4/x8 x4/x8 x4/x8 x4 x8 x4 x8 x4/x8 x4/x8 x4/x8 x4 x8 All Notes: 1. ICDD values reflect the combined current of both individual die. IDDx represents individual die valueS. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Package Dimensions Package Dimensions Figure 6: 82-Ball FBGA Package Dimensions – Rev. A 1 ±0.05 Seating plane 0.1 A Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu A Substrate material: plastic laminate Mold compound: epoxy novolac 12.5 ±0.1 82X Ø0.45 Dimensions apply to solder balls post-reflow. Prereflow ball is Ø0.42 on a Ø0.33 NSMD ball pad. 6.25 ±0.05 11 10 9 8 4 3 2 Ball A1 ID Ball A1 ID 1 A B C 7.5 ±0.05 D 0.8 TYP E 15 ±0.1 F G 9.6 H J K 4.8 L M N 4 0.8 TYP 8 Note: PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 1.35 MAX All dimensions are in millimeters. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 4Gb: x4, x8 TwinDie DDR3 SDRAM Package Dimensions Figure 7: 78-Ball FBGA Package Dimensions – Rev. D 0.8 ±0.1 Seating plane 0.12 A A 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F 9.6 CTR G 11.5 ±0.15 H J K L M 0.8 TYP N 0.8 TYP 1.2 MAX 0.25 MIN 6.4 CTR 9 ±0.15 Note: All dimensions are in millimeters. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the Micron logo, and TwinDie are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved.