4Gb: x4, x8 TwinDie DDR2 SDRAM

4Gb: x4, x8 TwinDie DDR2 SDRAM
Features
TwinDie™ DDR2 SDRAM
MT47H1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks
MT47H512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks
Features
Options
Marking
• Configuration
– 64 Meg x 4 x 8 banks x 2 ranks
– 32 Meg x 8 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 63-ball FBGA (9mm x 11.5mm) Rev.
C
• Timing – cycle time1
– 2.5ns @ CL = 5 (DDR2-800)
– 2.5ns @ CL = 6 (DDR2-800)
– 3.0ns @ CL = 5 (DDR2-667)
– 3.75ns @ CL = 4 (DDR2-533)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C ≤ T C ≤ 85°C)
• Revision
• Uses 2Gb Micron die
• Two ranks (includes dual CS#, ODT, and CKE balls)
• Each rank has 8 internal banks for concurrent operation
• VDD = V DDQ = +1.8V ±0.1V
• JEDEC-standard 63-ball FBGA
• Low-profile package – 1.35mm MAX thickness
Functionality
The 4Gb (TwinDie™) DDR2 SDRAM uses Micron’s
2Gb DDR2 monolithic die and has similar functionality. This TwinDie data sheet is intended to provide a
general description, package dimensions, and the
ballout only. Refer to Micron's 2Gb DDR2 data sheet
for complete information or for specifications not included in this document.
Note:
1G4
512M8
WTR
-25E
-25
-3
-37E
None
None
:C
1. CL = CAS (READ) latency.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
CL = 3
CL = 4
CL = 5
CL = 6
-25E
400
533
800
800
12.5
12.5
55
197.5
-25
400
533
667
800
15
15
55
197.5
-3
400
533
667
n/a
15
15
55
197.5
-37E
400
533
n/a
n/a
15
15
55
197.5
tRCD
(ns)
tRP
(ns)
tRC
(ns)
tRFC
(ns)
Table 2: Addressing
Parameter
1 Gig x 4
512 Meg x 8
Configuration
64 Meg x 4 x 8 banks x 2 ranks
32 Meg x 8 x 8 banks x 2 ranks
Refresh count
8K
8K
A[14:0] (32K)
A[14:0] (32K)
Row address
Bank address
Column address
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BA[2:0] (8)
BA[2:0] (8)
A[11, 9:0] (2K)
A[9:0] (1K)
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 63-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
A
VDD NF, NU/RDQS# VSS
B
DQS#/NU VDDQ
VSSQ DM, RDQS
DQS
VSSQ
NF, DQ7
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
NF, DQ4
VSSQ
DQ3
DQ2
VSSQ
NF, DQ5
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE0
WE#
RAS#
CK#
ODT0
BA2
BA0
BA1
CAS#
CS0#
CS1#
CKE1
A10
A1
A2
A0
VDD
VSS
A3
A5
A6
A4
ODT1
A7
A9
A11
A8
VSS
A12
A14
RFU
A13
NF, DQ6
C
D
VSSQ
E
F
G
H
J
K
L
VDD
Note:
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1. Dark balls (with ring) designate balls that differ from the monolithic versions.
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 63-Ball Descriptions
Symbol
Type
Description
A[14:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
BA[2:0]
Input
Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0]
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-down (row active in any bank). CKE is synchronous for power-down entry, powerdown exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, VREF must be maintained.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple ranks. CS# is considered part of the command code.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls.
ODT[1:0]
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[7:0], DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
DQ[3:0]
I/O
Data input/output: Bidirectional data bus for x4 configuration.
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for x8 configuration.
DQS, DQS#
I/O
Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
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© 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 63-Ball Descriptions (Continued)
Symbol
Type
RDQS, RDQS#
I/O
VDD
Supply
Power supply: 1.8V ±0.1V.
VDDQ
Supply
DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
VDDL
Supply
DLL power supply: 1.8V ±0.1V.
VREF
Supply
SSTL_18 reference voltage (VDDQ/2).
VSS
Supply
Ground.
VSSDL
Supply
DLL ground: Isolated on the device from VSS and VSSQ.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
NF
–
No function: These balls are no function on the x4 configuration.
NU
–
Not used: For the x8 configuration only. If EMR(E10) = 0, A2 = RDQS# and A8 = DQS#. If
EMR(E10) = 1, A2 and A8 are not used.
RFU
–
Reserved for future use.
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Description
Redundant data strobe: For the x8 configuration only. RDQS is enabled/disabled via
the load mode command to the extended mode register (EMR). When RDQS is enabled,
RDQS is output with read data only and is ignored during write data. When RDQS is disabled, ball B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
4
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© 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Functional Description
Functional Description
The 4Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access
memory device containing 4,294,967,296 bits and internally configured as two 8-bank
2Gb DDR2 SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
Addressing of the TwinDie is identical to the monolithic device. Additionally, multiple
chip selects select the desired rank.
This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to the Micron 2Gb DDR2 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation.
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: 64 Meg x 4 x 8 Banks x 2 Ranks
Rank 1
(64 Meg x 4 x 8 banks)
Rank 0
(64 Meg x 4 x 8 banks)
CS1#
RAS#
CKE1
CAS#
ODT1
WE#
CK
CK#
CS0#
CKE0
A[14:0]
BA[2:0]
ODT0
DQS, DQS#
DQ[3:0]
DM
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© 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Functional Block Diagrams
Figure 3: 32 Meg x 8 x 8 Banks x 2 Ranks
Rank 1
(32 Meg x 8 x 8 banks)
Rank 0
(32 Meg x 8 x 8 banks)
CS1#
RAS#
CKE1
CAS#
ODT1
WE#
CK
CK#
CS0#
CKE0
A[14:0]
BA[2:0]
ODT0
DQS, DQS#, RDQS, RDQS#
DQ[7:0]
DM
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© 2006 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications – Absolute Ratings
Electrical Specifications – Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions oustide those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 4: Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
VDD supply voltage relative to VSS
VDD
1.0
2.3
V
1
VDDQ supply voltage relative to VSSQ
VDDQ
0.5
2.3
V
1, 2
VDDL supply voltage relative to VSSL
VDDL
0.5
2.3
V
1
Voltage on any ball relative to VSS
VIN, VOUT
0.5
2.3
V
3
II
10
10
µA
IOZ
10
10
µA
IVREF
4
4
µA
Input leakage current; any input 0V ≤ VIN ≤ VDD;
all other balls not under test = 0V
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ
and ODT disabled
VREF leakage current; VREF= valid VREF level
Notes:
1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times; this is not required when power is ramping down.
2. VREF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed in Table 6 (page 9)for the applicable and
available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedances listed below. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather
than existing values) to account for increased thermal impedances from the die size reduction.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications.
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications – Absolute Ratings
Table 5: Temperature Limits
Parameter
Symbol
Min
Max
Units
Notes
TSTG
–55
150
°C
1
TC
0
85
°C
2, 3
Storage temperature
Operating temperature: commercial
Notes:
1. MAX storage case temperature TSTG is measured in the center of the package, as shown
in the figure below. This case temperature limit is allowed to be exceeded briefly during
package reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering
Parameters.”
2. MAX operating case temperature TC is measured in the center of the package, as shown
below.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
Figure 4: Example Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
Lmm x Wmm FGBA
Table 6: Thermal Impedance
Die
Revision
Package
C
63-ball
Substrate
Θ JA (°C/W)
Airflow =
0m/s
Θ JA (°C/W)
Airflow =
1m/s
Θ JA (°C/W)
Airflow =
2m/s
Θ JB (°C/W)
Θ JC (°C/W)
Notes
2-layer
62.6
45.3
39.2
28.5
3.5
1
4-layer
45.8
36.5
32.9
28.1
Note:
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1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
9
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications – ICDD Parameters
Electrical Specifications – ICDD Parameters
Table 7: DDR2 IDD Specifications and Conditions (Die Revision C)
Notes: 1–8 apply to the entire table
Combined
Symbol
Parameter/Condition
tCK
Individual
Die Status
Bus
Width
-25E/
-25
-3E/-3 Units
tCK
Operating one bank active-precharge current:
=
(IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS#
is HIGH between valid commands; address bus inputs are
switching; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
ICDD0
ICDD0 =
IDD0 + ICDD2P
x4, x8
92
87
mA
Operating one bank active-read-precharge current: IOUT
= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH,
CS# is HIGH between valid commands; address bus inputs are
switching; Data pattern is same as IDD4W (inactive die is in
IDD2P condition, but with inputs switching)
ICDD1
ICDD1 =
IDD1 + ICDD2P
x4, x8
107
102
mA
Precharge power-down current: All banks idle; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
ICDD2P
ICDD2P =
IDD2P + IDD2P
x4, x8
24
24
mA
Precharge quiet standby current: All banks idle; tCK = tCK
(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P
x4, x8
47
42
mA
Precharge standby current: All banks idle; tCK = tCK (IDD);
CKE is HIGH, CS# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching (inactive
die is in IDD2P condition, but with inputs switching)
ICDD2N
ICDD2N =
IDD2N + ICDD2P
x4, x8
52
47
mA
Active power-down current: All banks open;
tCK = tCK (I ); CKE is LOW; Other control and address bus inDD
puts are stable; Data bus inputs are floating (individual die
status: ICDD3P = IDD3P + IDD2P)
ICDD3P
Fast PDN exit
MR[12] = 0
x4, x8
42
37
mA
Slow PDN exit
MR[12] = 1
x4, x8
26
26
Active power-down current: All banks open;
tCK = tCK (I ); CKE is LOW; Other control and address bus inDD
puts are stable; Data bus inputs are floating (individual die
status: ICDD3P = IDD3P + IDD2P)
ICDD3N
ICDD3N =
IDD3N + ICDD2P
x4, x8
62
57
mA
Active standby current: All banks open; tCK = tCK (IDD),
= tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is
HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching)
ICDD4W
ICDD4W =
IDD4W + ICDD2P
x4, x8
162
142
mA
Operating burst read current: All banks open, continuous
burst reads, Iout = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK =
tCK (I ), tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH,
DD
DD
DD
CS# is HIGH between valid commands; address bus inputs are
switching; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
ICDD4R
ICDD4R =
IDD4R + ICDD2P
x4, x8
162
142
mA
tRAS
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications – ICDD Parameters
Table 7: DDR2 IDD Specifications and Conditions (Die Revision C) (Continued)
Notes: 1–8 apply to the entire table
Combined
Symbol
Parameter/Condition
current:tCK
tCK
Individual
Die Status
Bus
Width
-25E/
-25
-3E/-3 Units
Burst refresh
=
(IDD); refresh command at
every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
ICDD5
ICDD5 =
IDD5 + ICDD2P
x4, x8
197
177
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
ICDD6
ICDD6 =
IDD6 + IDD6
x4, x8
24
24
mA
Operating bank interleave read current: All bank interleaving reads, Iout = 0mA; BL = 4, CL = CL (IDD), AL = tRCD
(IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD =
tRRD (I ), tRCD = tRCD (Idd); CKE is HIGH, CS# is HIGH beDD
tween valid commands; address bus inputs are stable during
deselects; Data bus inputs are switching (inactive die is in
IDD2P condition, but with inputs switching)
ICDD7
ICDD7 =
IDD7 + ICDD2P
x4, x8
262
237
mA
Notes:
1. ICDD/IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
VDD = VDDQ = +1.8V ±0.1V; VDDL = +1.8V ±0.1V; VREF = VDDQ/2.
2. ICDD/IDD parameters are specified with ODT disabled.
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. Idd values must be met
with all combinations of EMR bits 10 and 11.
4. ICDD/IDDvalues must be met with all combinations of EMR bits 10 and 11.
5. Definitions for ICDD/IDD conditions:
LOW
HIGH
Stable
Floating
Switching
VIN(AC) ≤ VIL(AC)max
VIN ≥ VIH(AC)min
Inputs stable at a HIGH or LOW level
Inputs at VREF = VDDQ/2
Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. ICDD values reflect the combined current of both individual die. IDDx represents individual
die values.
8. The following IDD values must be derated (IDD limits increase) on IT-option or on AT-option devices when operated outside of the range 0°C ≤ TC ≤ 85°C:
When
TC ≤ 0°C
When
TC ≥ 85°C
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IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%
IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
11
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4Gb: x4, x8 TwinDie DDR2 SDRAM
Package Dimensions
Package Dimensions
Figure 5: 63-Ball FBGA (9mm x 11.5mm) (WTR)
Seating
plane
0.12 A
0.8 ±0.1
A
63X Ø0.45
Solder ball
material: SAC305.
Dimensions apply
to solder balls
post-reflow on
Ø0.33 NSMD
ball pads.
9
8
7
3
2
Ball A1 ID
1
Ball A1 ID
A
B
C
D
E
8 CTR
F
11.5 ±0.15
G
H
J
K
0.8 TYP
L
0.8 TYP
1.2 MAX
6.4 CTR
0.25 MIN
9 ±0.15
Note:
1. All dimensions are in millimeters.
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
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