AN309018 Application note How to migrate from S29GL256P to M29W256G Flash memories Introduction The objective of this application note is to explain how to migrate an application based on the S29GL256P Flash memory to an M29W256GH/L Flash memory. The purpose of this document is not to provide detailed information on the devices, but to highlight the similarities and differences between them. The comparison takes into consideration the signal descriptions, packages, architecture, software command set, performance, and block protections. The S29GL256P and M29W256GH/L are 256 Mbit (16 Mb x 16 or 32 Mb x 8) Flash memories that can be read, erased and reprogrammed using a single low supply voltage. Both memories are divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Program and erase commands are written to the command interface of the memory. An onchip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. Groups of blocks can be protected to prevent accidental program or erase commands from modifying the memory. On both devices, the highest or lowest memory block can also be protected by using a hardware method. All devices have an extra block, the extended block, of 128 words (256 bytes). It can be accessed using a dedicated command. The extended block can be protected and so is useful for storing security information. However the protection is not reversible, once protected the protection cannot be undone. In this document, the S29GL256P, highest and lowest block protected (01 and 02 model), will be referred to as S29GL256P, and the M29W256GH (highest block protected) and the M29W256GL (lowest block protected) will be referred to as M29W256G unless otherwise specified. Please refer to the S29GL256P and M29W256G datasheets for additional information on devices. July 2009 Rev 1 1/22 www.numonyx.com Contents AN309018 Contents 1 Memory architecture and protection groups . . . . . . . . . . . . . . . . . . . . . 5 2 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 2.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Program operation fails detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Device codes and auto select codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Difference in CFI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Performance and characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Temporary block unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Power-up waiting timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/22 AN309018 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Signal Description for the S29GL256P and M29W256G Devices . . . . . . . . . . . . . . . . . . . . 6 Command Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M29W256G, Write to Buffer Commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 S29GL256P, Write to Buffer Command (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M29W256G Enhanced Buffered Program Commands, 16-bit mode . . . . . . . . . . . . . . . . . 11 M29W256G, Write to Buffer Commands, 8-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 S29GL256P, Write to Buffer Command (8-bit Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus Operations for Accessing the Auto Select Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Auto Select Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CFI Exit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program/erase Times and Program/erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . 16 Comparison between S29GL256P and M29W256G Performance and Characteristics. . . 17 Block Protection Techniques, M29W256G / S29GL256P Memory Devices. . . . . . . . . . . . 18 Commands Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-up Waiting Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3/22 List of figures AN309018 List of figures Figure 1. Figure 2. Figure 3. Figure 4. 4/22 S29GL256P TSOP56 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M29W256G TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 S29GL256P FBGA64 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M29W256G FBGA64 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AN30918 1 Memory architecture and protection groups Memory architecture and protection groups The S29GL256P and the M29W256G memory arrays are divided into uniform blocks. In particular, they have 256 blocks of 64 Kwords (128 Kbytes) each. Both devices have an extended memory block of 128 words in x 16 mode or of 256 bytes in x 8 mode. See Section 3: Software command set for a description of the extended memory block commands. On the S29GL256P and M29W256G, all blocks are protected individually. The protection granularity is always 64 Kwords or 128 Kbytes. 5/22 Hardware migration 2 AN30918 Hardware migration This section provides a detailed comparison between S29GL256P and M29W256G signals and package pin-out. 2.1 Signal description Table 1 gives a comparison between the S29GL256P and M29W256G signals. On both devices, the VPP function allows the memory to use an external high voltage power supply to reduce the time required for fast program operations. The Write Protect (WP) function provides a hardware method of protecting the outermost memory block: When (VPP/WP) is Low, VIL, the highest or lowest block is protected on both the M29W256G and S29GL256P devices. When VPP/WP is High, VIH, the memory reverts to the previous protection status of the outermost block. Upon customer request, on the M29W256G devices, applying 12 V to the VPP/WP pin will temporarily unprotect any block previously protected (including the two outermost blocks). In addition, the VPP/WP pin can be left floating or unconnected due to an internal pull-up. In both devices, VCCQ provides the power supply to the I/O pins and enable all outputs to be powered independently from VCC. Table 1. Signal Description for the S29GL256P and M29W256G Devices Name Description S29GL256P Direction M29W256G A0-A23 Address inputs Inputs DQ0-DQ7 Data inputs/outputs I/O DQ8-DQ14 Data inputs/outputs I/O DQ15A–1 (or DQ15) Data input/output or address input (or data input/output) I/O CE# E Chip Enable Input OE# G Output Enable Input WE# W Write Enable Input RESET# RP Reset/Block Temporary Unprotect Input RY/BY# RB Ready/Busy output BYTE# Byte/word organization select VCC VPP/WP WP#/ACC 6/22 Supply voltage Supply voltage for fast program (optional) or write protect Output Input Supply Input VSS Ground – NC Not connected internally – AN30918 2.2 Hardware migration Packages The S29GL256P and M29W256G are both delivered in TSOP56 - 14 x 20 mm and FBGA64 11x 13 mm. The M29W256G is also offered in the TBGA64 - 10 x 13 mm, 1 mm pitch packages. Compared with FBGA, the TBGA64 is smaller and it has different ball size, the TBGA ball size ranges from 0.35mm to 0.5mm while the FBGA ball size ranges from 0.5mm to 0.7mm. The M29W256G is fully pin-to-pin compatible with the S29GL256P. See Figure 1 and Figure 2, in conjunction with Table 1. Refer to the S29GL256P and M29W256G datasheets for details on the packages. Figure 1. A23 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC S29GL256P TSOP56 Connections 1 56 14 15 43 42 28 29 NC NC A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 NC VIO(1) Pinout_S29GL_256P Figure 2. A23 A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC M29W256G TSOP56 Connections 1 56 14 15 43 42 28 29 NC NC A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC VCCQ (2) Pinout_M29W256G 1. VIO = 1.65 V to VCC. 2. VCCQ = 1.65 V to VCC. 7/22 Hardware migration Figure 3. AN30918 S29GL256P FBGA64 Connections 1 2 3 4 5 6 7 8 A NC A3 A7 RY/BY# WE# A9 A13 NC B NC A4 A17 WP#/ ACC RESET A8 A12 A22 C NC A2 A6 A18 A21 A10 A14 A23 D NC A1 A5 A20 A19 A11 A15 VIO(1) E NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS F VIO CE# DQ8 DQ10 DQ12 DQ14 BYTE# NC G NC OE# DQ9 DQ11 VCC DQ13 DQ15 A–1 NC H NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC Pin_Connections_FBGA64 8/22 AN30918 Figure 4. Hardware migration M29W256G FBGA64 Connections 1 2 3 4 5 6 7 8 A NC A3 A7 RB W A9 A13 NC B NC A4 A17 VPP/WP RP A8 A12 A22 C NC A2 A6 A18 A21 A10 A14 A23 D NC A1 A5 A20 A19 A11 A15 VCCQ E NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS F VCCQ E DQ8 DQ10 DQ12 DQ14 BYTE# NC G NC G DQ9 DQ11 VCC DQ13 DQ15 A-1 NC H NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC Pin_Connections_M29W_256G 9/22 Software command set 3 AN30918 Software command set The S29GL256P and M29W256G feature an identical set of standard commands. The commands are compliant with the JEDEC standard. Table 2. Command Set Command 3.1 S29GL256P M29W256G Read/Reset X X Auto Select X X Program X X Write Buffer X X Unlock Bypass X X Unlock Bypass Program X X Unlock Bypass Reset X X Chip Erase X X Block Erase X X Program/Erase Suspend X X Program/Erase Resume X X Read CFI Query X X Enter Extended Block X X Exit Extended Block X X Enhanced Buffered Program - X Fast program commands The S29GL256P and the M29W256G devices both feature fast program commands. Since the write to buffer program is available on both devices, it is recommended to use this command if a minimum number of changes is required for the migration. On the other side, to reach the best programming speed with M29W256G devices, it is recommended to use enhanced buffered program with VPP=VPPH (see Table 3: M29W256G, Write to Buffer Commands, 16-bit mode and Table 6: M29W256G, Write to Buffer Commands, 8-bit Mode). The Enhanced Buffered Program command is only available on M29W256G devices. It is valid in x 16 mode only and makes use of the device’s 256-word write buffer to speed up programming. To use the Enhanced Buffered Program command, all the 256 words must be loaded into the write buffer in an increasing address order. Each write buffer has the same A23-A8 addresses. The Enhanced Buffered Program command dramatically reduces system programming time. 10/22 AN30918 M29W256G, Write to Buffer Commands, 16-bit mode Bus write operations (1) Length Table 3. Software command set Command 1st 2nd 3rd 4th 5th 6th Add Data Add Data Add Data Add Data Add Data Add Data PA (3) PD WBL(4) PD Write to Buffer Program N+5 555 AA 2AA 55 BAd 25 BAd N(2) Unlock Bypass Write to Buffer Program N+3 BAd 25 BAd N(2) PA(3) PD WBL (6) PD Write to Buffer Program Confirm 1 BAd(5) 29 Buffered Program Abort Reset 3 555 AA 2AA 55 555 F0 1. X don’t care, PA program address, PD program data, BAd any address in the block, WBL write buffer location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the write to buffer program operation. 3. Each buffer has the same A23-A5 addresses. A0-A4 are used to select a word within the N+1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BAd must be identical to the address loaded during the write to buffer program 3rd and 4th cycles. 6. The 4th cycle has to be issued N time. WBL scans the word inside the page. Table 4. S29GL256P, Write to Buffer Command (16-bit mode) Bus write cycles Command Cycles 1st Add Write to Buffer (1) WC + 5 2nd 3rd Data Add Data 555 AA 2AA 55 4th Add Data BA(2) 25 Add 5th 6th Data Add Data Add Data BA (2) WC(2) PA(2) PD(2) WBL(2) PD(2) 1. The total number of cycles in the command sequence is determined by the number of words to be written to the write buffer. The maximum number of cycles is 20. 2. BA Block Address, WC Number of words to be programmed - 1, PA Program Address, PD Program Data, WBL Write Buffer Location (address must be within the same write buffer page as PA). Table 5. M29W256G Enhanced Buffered Program Commands, 16-bit mode Command Length Bus write operations 1st 2nd 3rd ... Add Data Add Data Add Data 3 555 AA 2AA 55 555 38 258 BAd 33 BAd (00) Data BAd (01) Data Exit Enhanced Buffered Program Command Set 2 X 90 X 00 Enhanced Buffered Program Abort Reset 3 555 AA 2AA 55 555 F0 Enter Enhanced Buffered Program Command Set Enhanced Buffered Program 256th 257th 258th Add Data Add Data Add Data Add Data ... ... BAd (FE) Data BAd (FF) Data BAd (00) 29 11/22 Software command set M29W256G, Write to Buffer Commands, 8-bit Mode Bus write operations(1) Length Table 6. AN30918 Command 1st 2nd 3rd 4th 5th 6th Add Data Add Data Add Data Add Data Add Data Add Data PA(3) PD WBL(4) PD Write to Buffer Program N+5 AAA AA 555 55 BAd 25 BAd N(2) Unlock Bypass Write to Buffer Program N+3 BAd 25 BAd N(2) PA(3) PD WBL(6) PD Write to Buffer Program Confirm 1 BAd(5) 29 Buffered Program Abort Reset 3 AAA AA 555 55 AAA F0 1. X don’t care, PA program address, PD program data, BAd any address in the block, WBL write buffer location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the write to buffer program operation. 3. Each buffer has the same A23-A5 addresses. A0-A4 and A-1 are used to select a byte within the N+1 byte page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BAd must be identical to the address loaded during the write to buffer program 3rd and 4th cycles. 6. The 4th cycle has to be issued N time. WBL scans the word inside the page. Table 7. S29GL256P, Write to Buffer Command (8-bit Mode) Command Write to Buffer(1) Cycles Bus write cycles BC+5 1st 2nd 3rd Add Data Add Data Add AAA 555 55 BA(2) AA 4th Data Add 25 BA 5th 6th Data Add Data Add Data BC(2) PA(2) PD(2) WBL(2) PD 1. The total number of cycles in the command sequence is determined by the number of bytes to be written to the write buffer. The maximum number of cycles is 30. 2. BA Block Address, WC Number of bytes to be programmed - 1, PA Program Address, PD Program Data, WBL Write Buffer Location (address must be within the same write buffer page as PA). 12/22 AN30918 3.2 Software command set Program operation fails detection In M29W256G devices, it is possible to detect program operation fails, even during a write to buffer or enhanced buffered program, when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. In S29GL256P devices, this functionality is not available. 3.3 Device codes and auto select codes The auto select codes are composed of the manufacturer code, the device code, the block protection status, and the extended memory block verify code. The S29GL256P and M29W256G devices have different manufacturer code, device code, and extended memory block verify code. The S29GL256P and M29W256G devices use identical commands and address inputs to read the auto select codes. Two methods are available to access the auto select codes: Table 8. in the first method, an Auto Select command is issued (see Table 2: Command Set) to place the device in auto select mode. The auto select codes can then be read by using a bus read operation with addresses and control signals set as shown in Table 8: Bus Operations for Accessing the Auto Select Codes. in the high voltage method, the same sequence of bus read operations as in the first method is issued, except that A9 is set at VID. Bus Operations for Accessing the Auto Select Codes Address inputs Operation E G W x 8 mode x 16 mode DQ15A-1, A0-A23 A0-A23 Read manufacturer code A0-A3 = VIL , A6 = VIL, A9 = VID, others VIL or VIH Read device code A0 = VIH, A1-A3 = VIL, A6 = VIL, A9 = VID , others VIL or VIH VIL VIL VIH Block protection status A0,A2,A3, A6= VIL, A1= VIH, A9 = VID, A12-A21 = Block address, others VIL or VIH Extended memory block verify code A0-A1 = VIH, A2-A3 = VIL, A6 = VIL, A9 = VID , others VIL or VIH Data inputs/outputs x 8 mode DQ14-DQ8 Hi-Z x 16 mode DQ7-DQ0 DQ15A-1, DQ14-DQ0 see Table 9 13/22 Software command set Table 9. AN30918 Auto Select Codes Spansion Auto select code S29GL256P (01 model)(1) Numonyx S29GL256P (02 model)(2) M29W256GH M29W256GL Spansion S29GL256P (01 model)(1) Numonyx S29GL256P (02 model)(2) x 16 mode 0001h Device code 227Eh 2222h 2201h 227Eh+2222h+2201h Block protection status 01h (protected) 00h (unprotected)(3) 0001h (protected) 0000h (unprotected) XX99h (factory locked) XX19h (not factory locked)(3) 0020h XX89h (factory locked) XX09h (not factory locked)(3) 0099h (factory locked) 0019h (not factory locked) 1. Highest block protected by driving V PP/WP High. 2. Lowest block protected by driving VPP/WP High. 3. DQ8 to DQ15 are ‘don’t care’. 3.4 M29W256GL x 8 mode Manufacturer code Extended memory block verify indicator M29W256GH 0020h 0089h (factory locked) 0009h (not factory locked) 01h 20h 7Eh+22h+01h 7Eh+22h+01h 01h (protected) 00h (unprotected) 99h (factory locked) 19h (not factory locked) (3) 89h (factory locked) 09h (not factory locked)(3) 99h (factory 89h (factory locked) locked) 19h (not 09h (not factory locked) factory locked) Difference in CFI operation When exiting CFI mode on M29W256G device, Read/Reset command (0xF0h) is used to return the device to the previous mode (Main Array Read or Auto Select Mode). Table 10: CFI Exit Sequence shows the detail exiting command sequence on M29W256G device. Table 10. CFI Exit Sequence Exiting from CFI to main array read command sequence Entering CFI Sequence S29GL256P M29W256G Main Array Read --> CFI 0xF0h 0xF0h Main Array Read --> Auto Select Mode --> CFI 0xF0h 0xF0h --> 0xF0h (twice command) S29GL256P will enter main array read mode when it is issued Read/Reset command (0xF0h). 14/22 AN30918 4 Performance and characteristics Performance and characteristics The S29GL256P and the M29W256G have almost compatible DC and AC characteristics (see the respective datasheets for details). The M29W256G memory devices offer better performance in terms of access, programming, and erase times than the S29GL256P devices. 4.1 Access time The M29W256G has a random access time of 70 ns or 90 ns, depending on the VCCQ supply voltage, whereas the S29GL256P has an access time of 90 ns, 100 ns or 110 ns. 4.2 Page read mode The page mode is available on the S29GL256P and M29W256G to speed up read operations. The data is internally read and stored in a 8-word (or 16-byte) page buffer. Using page read, the access time for subsequent read operations is reduced to 25 ns for both devices with VCCQ = VCC, while it is reduced to 30 ns for the M29W256G with VCCQ = 1.65 V. 15/22 Performance and characteristics 4.3 AN30918 Program and erase times The time required to program or erase the whole memory is lower on the M29W256G compared to the S29GL256P. The memory can be programmed using a Fast Program, an Enhanced Buffered Program command, or the word by word program command. Refer to Section 3.1 for details. Table 11. Program/erase Times and Program/erase Endurance Cycles Parameter Min Chip Erase Typ(1)(2) Max(2) Unit 145(3) 400(4) s 125 400(4) s 0.5 2 s 25 35 μs VPP /WP = VPPH Chip Erase Block Erase (128 kbytes) (5) Erase Suspend latency time Block Erase timeout 50 Single Byte Program Byte Program 16 Write to Buffer Program (64 bytes at-a-time) VPP /WP = VPPH 50 VPP /WP = VIH 70 Single Word Program Word Program μs μs 200(4) μs μs 16 Write to Buffer Program (32 words at-a-time) VPP /WP = VPPH 50 VPP /WP = VIH 70 200(4) μs 540 800(4) s Chip Program (word by word) 270 400(4) s Chip Program (Write to Buffer Program)(6) 25 200(4) s Chip Program (byte by byte) Chip Program (Write to Buffer Program with VPP /WP = VPPH) Chip Program (Enhanced Buffered Program) (6) 13 (6) (4) 50 s 15 60 s Chip Program (Enhanced Buffered Program with VPP /WP = VPP ) 10 40 s Program Suspend latency time 5 15 μs (6) Program/Erase cycles (per block) Data retention 100,000 Cycles 20 Years 1. Typical values measured at room temperature and nominal voltages and for not cycled devices. 2. Sampled, but not 100% tested. 3. Time needed to program the whole array at 0 is included. 4. Maximum value measured at worst case conditions for both temperature and V CC after 100,000 program/erase cycles. 5. Block erase polling cycle time. 6. Intrinsic program timing, that means without the time required to execute the bus cycles to load the program commands. 16/22 AN30918 Table 12. Performance and characteristics Comparison between S29GL256P and M29W256G Performance and Characteristics Parameter S29GL256P M29W256G Access time 90, 100, 110 ns 60 ns, 70 and 80 ns with VCCQ= 3 V (1) Page Read 25 ns (8-word page) Write to Buffer Program (32 Words/64 Bytes) Fast Program — Enhanced Buffered Program (256 Words) Chip Program time 246 s (using the Write to Buffer Program) Supply voltage 2.7 to 3.6 V 25 s (VPP /WP = VIH) 13 s (V PP/WP = VPPH) (using the Write to Buffer Program) 15 s (VPP /WP = VIH) 10 s (VPP/WP = VPPH) (using the Enhanced Buffered Program) 2.7 to 3.6 V Temperature range –40 to 85 °C VCCQ or VIO input/output supply 1.65 V to VCC Chip Erase time 128 s (typical), except all 0000h programmed prior to erasing 145 s (typical) 1. 60 ns available upon customer request. 17/22 Block protection 5 AN30918 Block protection The M29W256G memories, as the S29GL256P devices, feature three techniques to control block protection. The table below shows how the three techniques are called in the M29W256G and S29GL256P devices, respectively. Table 13. Block Protection Techniques, M29W256G / S29GL256P Memory Devices M29W256G(1) S29GL256P Hardware method (VPP /WP) Hardware Data Protection (WP/ACC) Volatile/non-volatile protection Advanced protection/unprotection Password protection method Password protection method 1. Please refer to the M29W256G datasheet for further details. The S29GL256P and M29W256G both feature hardware protection. In particular in the M29W256G memories, when: VPP/WP = VIL, the highest or lowest blocks are protected VPP/WP = VIH, the highest or lowest blocks are unprotected. Advanced protection/unprotection in S29GL256P corresponds to volatile/non-volatile protection in M29W256G: In the volatile protection mode, each block can be protected/unprotected with powerdown or by a command In the non-volatile protection mode, each block can be protected/unprotected by a command. Power-down or hardware reset do not change the protection status. The password protection method is available in both S29GL256P and M29W256G devices. It is a high level security protection mode that requires a 64-bit password to unlock the device. Read, program or erase operations are not allowed if the password is not correct. The password protection method is a non-volatile protection. The S29GL256P and M29W256G devices feature the same commands with the same functions (see Table 14: Commands Cross Reference), so protection commands are fully compatible. Table 14. Commands Cross Reference M29W256G 18/22 S29GL256P Protection commands Protection commands Lock register Lock register Password protection Password protection Non-volatile protection Global non-volatile NVPB lock bit Global volatile freeze (PPB Lock) Volatile protection Volatile Exit protection command set Command set exit AN30918 5.1 Power-up waiting timing Temporary block unprotect In the M29W256G, when held at VID, the RP or VPP/WP pin, temporarily unprotects all the blocks previously protected using a volatile/non-volatile protection with the NVPB lock bit not set. To unprotect blocks with a temporary block unprotect mode and a password mode, it is necessary to provide the password and then put the RP or VPP/WP pin at VID. In the M29W256G, this functionality is only available upon customer request, while it is not available at all in S29GL256P devices. 6 Power-up waiting timing The time needed to power up the M29W256G devices is different from the one needed by S29GL256P devices. In particular, M29W256G needs 500 μs to accept commands (program, erase, read CFI, etc.) and 50 μs to read content in memory cells after power-up. The power-up waiting timing differences are shown in Table 15. Table 15. Power-up Waiting Timings Waiting timing M29W256G S29GL256P Unit Time to accept commands after power-up Min 500 Min 35 μs Time to read memory cells after power-up Min 50 Min 35 μs Please refer to the M29W256G and S29GL256P datasheets for further details. 7 Conclusion Applications can be easily migrated from an S29GL256P to an M29W256G Flash memory. In addition, the M29W256G features better performance with respect to the S29GL256P devices. 19/22 Revision history 8 AN30918 Revision history Table 16. 20/22 Document Revision History Date Version June 2009 1 Changes Initial release. AN309018 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. 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Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2009, Numonyx, B.V., All Rights Reserved. 21/22