(x64, SR) PC3200 200-Pin DDR SDRAM SODIMMs

128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
DDR SDRAM SMALLOUTLINE DIMM
MT4VDDT1664H – 128MB
MT4VDDT3264H – 256MB
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/modules
Features
Figure 1: 200-Pin SODIMM (MO-224)
• 200-pin, small-outline dual in-line memory module
(DDR SODIMM)
• Fast data transfer rates: PC3200
• Utilizes 400 MT/s DDR SDRAM components
• 128MB (16 Meg x 64 ) and 256MB (32 Meg x 64)
• VDD= VDDQ= +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs;
centeraligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes: 7.8125µs
maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
Table 1:
1.25in. (31.75mm)
OPTIONS
MARKING
• Package
200-pin SODIMM (Standard)
200-pin SODIMM (Lead-free)1
• Memory Clock/Speed/CAS Latency2
5ns (200 MHz), 400 MT/s, CL = 3
• PCB
1.25in. (31.75mm)
NOTE:
G
Y
-40B
1. Consult factory for product availability.
2. CL = Device CAS (READ) Latency.
Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
1
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 2:
Part Numbers and Timing Parameters
PARTNUMBER
MT4VDDT1664HG-40B__
MT4VDDT1664HY-40B__
MT4VDDT3264HG-40B__
MT4VDDT3264HY-40B__
MODULE
DENSITY
CONFIGURATION
MODULE
BANDWIDTH
MEMORY CLOCK/
DATA RATE
CLOCK LATENCY
(CL - tRCD - tRP)
128MB
128MB
256MB
256MB
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
5ns/ 400 MT/s
5ns/ 400 MT/s
5ns/ 400 MT/s
5ns/ 400 MT/s
3-3-3
3-3-3
3-3-3
3-3-3
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT4VDDT1664HG-40BA1.
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
Table 4:
Pin Assignment
(200-Pin SODIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
DNU
DNU
VSS
DNU
DNU
VDD
DNU
NC
VSS
DNU
DNU
VDD
NC
NC
A12
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A9
VSS
A7
A5
A3
A1
VDD
A10
BA0
WE#
S0#
NC
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
151 DQ42
153 DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163 DQ48
165 DQ49
167
VDD
169 DQS6
171 DQ50
173
VSS
175 DQ51
177 DQ56
179
VDD
181 DQ57
183 DQS7
185
VSS
187 DQ58
189 DQ59
191
VDD
193
SDA
195
SCL
197 VDDSPD
199
NC
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
DNU
DNU
VSS
DNU
DNU
VDD
DNU
NC
VSS
VSS
VDD
VDD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
NC
NC
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
NC
Figure 2: 200-Pin SODIMM Module Layout
Front View
U1
Back View
U4
U2
U5
No Components This Side of Module
U3
PIN 1
(all odd pins)
PIN 199
PIN 200
Indicates a VDD or VDDQ pin
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3
(all even pins)
PIN 2
Indicates a VSS pin
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
SYMBOL
118, 119, 120
WE#, CAS#, RAS#
35, 37, 158, 160
CK0, CK0#,
CK1, CK1#
96
CKE0
121
S0#
116, 117
BA0, BA1
99, 100, 101, 102, 105,
106, 107, 108, 109, 110,
111, 112, 115
A0–A12
11, 25, 47, 61, 133, 147,
169, 183
DQS0–DQS7
12, 26, 48, 62, 134, 148,
170, 184
DM0–DM7
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TYPE
DESCRIPTION
Input Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWERDOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied and until CKE is first brought HIGH. After
CKE is brought HIGH, it becomes an SSTL_2 input only.
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
SYMBOL
5, 6, 7, 8, 13, 14, 17, 18,
19, 20, 23, 24, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 65,
66, 67, 68, 127, 128, 129,
130, 135, 136, 139, 140,
141, 142, 145, 146, 151,
152, 153, 154, 163, 164,
165, 166, 171, 172, 175,
176, 177, 178, 181, 182,
187, 188, 189, 190
195
DQ0–DQ63
194, 196, 198
SA0–SA2
193
SDA
1, 2
9, 10, 21, 22, 33, 34, 36,
45, 46, 57, 58, 69, 70, 81,
82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,
180, 191, 192
3, 4, 15, 16, 27, 28, 38, 39,
40, 51, 52, 63, 64, 75, 76,
87, 88, 90, 103, 104, 125,
126, 137, 138, 149, 150,
159, 161, 162, 173, 174,
185, 186
197
71, 72, 73, 74, 77, 78, 79,
80, 83, 84
85, 95, 97, 98, 99, 122,
123, 128, 199, 200
VREF
VDD
Input Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presencedetect portion of the module.
Supply SSTL_2 reference voltage.
Supply Power Supply: +2.6V ±0.1V.
VSS
Supply Ground.
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SCL
VDDSPD
DNU
NC
TYPE
DESCRIPTION
Input/ Data I/Os: Data bus.
Output
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
—
Do Not Use: These pins are not connected on these modules,
but are assigned pins on other modules in this product family.
—
No Connect: These pins should be left unconnected.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Figure 3: Functional Block Diagram
S0#
CS#
DQS0
DM0
DQS4
DM4
UDQS
UDM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS1
DM1
DQS2
DM2
UDQS
UDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS3
DM3
BA0-BA1
DDR SDRAMs
DDR SDRAMs
A0-A12
RAS#
DDR SDRAMs
U1
CS#
UDQS
UDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS7
DM7
SCL
WP
SERIAL PD
U3
A0
A1
CS#
U4
CS#
U5
LDQS
LDM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VDDSPD
SDA
SA0 SA1 SA2
SPD
VDD
DDR SDRAMs
VREF
DDR SDRAMs
VSS
DDR SDRAMs
120
CK1
CK1#
DDR SDRAMs U1, U2
DDR SDRAMs U3, U4
2pF
2pF
NOTE:
Standard modules use the following DDR SDRAM devices:
MT46V16M16TG (128MB); MT46V32M16TG (256MB)
Unless otherwise stated, all resistors are 22Ω..
Per industry standard, Micron utilizes various component speed
grades as referenced in the Module Part Numbering Guide at
www.micron.com/numberguide.
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DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
120
1.
2.
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6
DM6
U2
DDR SDRAMs
DDR SDRAMs
CK0
CK0#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DDR SDRAMs
CAS#
WE#
CKE0
UDQS
UDM
Lead-free modules use the following DDR SDRAM devices:
MT46V16M16P (128MB); MT46V32M16P (256MB)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
General Description
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 256Mb or 512Mb DDR SDRAM component data
sheets.
The MT4VDDT1664H and MT4VDDT3264H are
high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAMs.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-pre-fetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select device bank; A0–A12 select
device row). The address bits registered coincident
with the READ or WRITE command are used to select
the device bank and the starting device column location for the burst access.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
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Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 4, Mode Register Definition Diagram, on
page 8. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and or A7–A12
specify the operating mode.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Burst Length
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Read and write accesses to DDR SDRAM devices are
burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 for Figure 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both READ and WRITE bursts.
Figure 4: Mode Register Definition
Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13 12 11 10 9 8
Operating Mode
0* 0*
7
6 5 4 3 2 1 0
CAS Latency BT Burst Length
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
Burst Type
M3
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst
Definition Table, on page 9.
0
Sequential
1
Interleaved
CAS Latency
M6 M5 M4
Read Latency
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Mode Register (Mx)
Burst Length
Burst Type
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,
CAS Latency Diagram.
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
M12 M11 M10 M9 M8 M7
8
Address Bus
M6-M0
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 6:
BURST
LENGTH
STARTING
COLUMN
ADDRESS
4
8
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
2.
3.
4.
5.
COMMAND
TYPE =
INTERLEAVED
T2
READ
NOP
NOP
T2n
T3
T3n
NOP
CL = 2
DQS
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
DQ
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK
COMMAND
NOP
CL = 2.5
DQS
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
DQ
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
NOP
CL = 3
DQS
DQ
For a burst length of two, A1–Ai select the two-dataelement block; A0 selects the first access within the
block.
For a burst length of four, A2–Ai select the four-dataelement block; A0–A1 select the first access within the
block.
For a burst length of eight, A3–Ai select the eightdata-element block; A0–A2 select the first access
within the block.
Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
i = 8 (128MB);
i = 9 (256MB)
Table 7:
T1
CK
NOTE:
1.
T0
CK#
ORDER OF ACCESSES
WITHIN A BURST
TYPE =
SEQUENTIAL
2
Figure 5: CAS Latency Diagram
Burst Definition Table
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operating mode.
All other combinations of values for A7–A12 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future versions may result.
CAS Latency (CL) Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
CL = 3
-40B
75 ≤ f ≤ 133
75 ≤ f ≤ 167
133 ≤ f ≤ 200
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
DON’T CARE
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Extended Mode Register
disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE HIGH must occur before a
READ command can be issued.
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and output drive strength. These functions are controlled via
the bits shown in Figure 4, Mode Register Definition
Diagram, on page 8. The extended mode register is
programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified operation.
Figure 6: Extended Mode Register
Definition Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13 12 11 10 9 8 7 6 5
Operating Mode
01 11
4
3
2
1
0
DS DLL
E1
Address Bus
Extended Mode
Register (Ex)
E0
DLL
0
Enable
1
Disable
Drive Strength
Output Drive Strength
0
Normal
The normal full drive strength for all outputs is
specified to be SSTL2, Class II. The x16 DDR SDRAM
devices used in these modules support an option for
reduced drive. The reduced drive option is intended
for lighter load and point-to-point environments. For
detailed information on output drive strength options,
refer to 256Mb or 512Mb DDR SDRAM component
data sheets.
1
Reduced
E11 E10 E9 E8 E7 E6 E5 E4 E3 E22
E1, E0
0
0
0
0
0
0
0
0
0
0
Valid
–
–
–
–
–
–
–
–
–
–
–
Operating Mode
Normal Operation
All other states reserved
NOTE:
1.
2.
DLL Enable/Disable
BA1 and BA0 (E14 and E13) must be “0, 1” to select
the Extended Mode Register (vs. the base Mode Register).
QFC# is not supported.
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Commands
Figure 8, Commands Truth Table, and Figure 9, DM
Operation Truth Table, below, provide a general reference of available commands. For a more detailed
Table 8:
description of commands and operations, refer to the
256Mb or 512Mb DDR SDRAM component data sheet.
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select device bank and activate row)
READ (Select device bank and column, and start READ burst)
WRITE (Select device bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in device bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
CS#
RAS#
H
L
L
L
L
L
L
L
L
X
H
L
H
H
H
L
L
L
CAS# WE#
X
H
H
L
L
H
H
L
L
X
H
H
H
L
L
L
H
L
ADDR
NOTES
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
1
1
2
3
3
4
5
6, 7
8
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
DESELECT and NOP are functionally interchangeable.
BA0–BA1 provide device bank address and A0–A12 provide row address.
BA0–BA1 provide device bank address; A0–A8 (128MB) or A0–A9 (256MB), provide column address; A10 HIGH enables
the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
READ bursts with auto precharge enabled and for WRITE bursts.
A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
Table 9:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
11
DM
DQS
L
H
Valid
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Operating Temperature,
TA (ambient) . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C
Storage Temperature (plastic) . . . . . . -55°C to +150°C
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
I/O Supply Voltage
VDD
VDDQ
2.5
2.5
2.7
2.7
V
V
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT Any input
0V ≤ VIN ≤ VDD, Vref pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
VREF
VTT
VIH(DC)
VIL(DC)
V
V
V
V
32, 37, 49
32, 37, 40,
49
6, 40
7, 40
25
25
Command/
Address, RAS#,
CAS#, WE#,
CKE, S#
CK, CK#
DM
DQ, DQS
OUTPUT LEAKAGE CURRENT
(DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ)
OUTPUT LEVELS
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
OUTPUT LEVELS (Reduced drive option)
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
0.49 × VDDQ 0.51 × VDDQ
VREF - 0.04 VREF + 0.04
VREF + 0.15
VDD + 0.3
-0.3
VREF - 0.15
-8
8
µA
47
IOZ
-4
-2
-5
4
2
5
µA
47
IOH
IOL
-16.8
16.8
–
–
mA
mA
33, 35
IOH
IOL
-9
9
–
–
mA
mA
34, 35
II
Table 11: AC Input Operating Conditions
Notes: 1–5, 14; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
PARAMETER/CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
SYMBOL
MIN
MAX
UNITS
NOTES
VIH(AC)
VIL(AC)
VREF(AC)
VREF + 0.310
–
0.49 × VDDQ
–
VREF - 0.310
0.51 × VDDQ
V
V
V
12, 25, 36
12, 25, 36
6
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 12: IDD Specifications and Conditions – 128MB Module
DDR SDRAM component values only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
t
t
OPERATING CURRENT: One device bank; Active-Precharge; RC = RC (MIN);
t
CK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle;
Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge; Burst =
4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK
MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with
auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control
inputs change only during Active READ or WRITE commands
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13
SYM
-40B
UNITS
NOTES
IDD0
540
mA
20, 42
IDD1
740
mA
20, 42
IDD2P
16
mA
IDD2F
240
mA
21, 28,
44
45
IDD3P
160
mA
IDD3N
280
mA
21, 28,
44
20
IDD4R
1,040
mA
20, 42
IDD4W
860
mA
20
IDD5
IDD5A
IDD6
IDD7
1,040
24
16
2,040
mA
mA
mA
mA
24, 44
24, 44
9
20, 43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 13: IDD Specifications and Conditions – 256MB Module
DDR SDRAM component values only
Notes: 1–5, 8, 10, 14, 48; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
t
t
OPERATING CURRENT: One device bank; Active-Precharge; RC = RC (MIN);
t
CK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle;
Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge; Burst =
4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK
MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with
auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control
inputs change only during Active READ or WRITE commands
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
14
SYM
-40B
UNITS
NOTES
IDD0
620
mA
20, 42
IDD1
780
mA
20, 42
IDD2P
20
mA
IDD2F
220
mA
21, 28,
44
45
IDD3P
180
mA
IDD3N
240
mA
21, 28,
44
20
IDD4R
840
mA
20, 42
IDD4W
860
mA
20
IDD5
IDD5A
IDD6
IDD7
1,380
44
24
1,920
mA
mA
mA
mA
24, 44
24, 44
9
20, 43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 14: Capacitance
Note: 11; notes appearon pages 17–20
PARAMETER
SYMBOL
MIN
MAX
UNITS
CIO
CI1
CI2
4.0
8.0
6.0
5.0
12.0
8.0
pF
pF
pF
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions
Notes: 1–5, 12-15, 29; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
AC CHARACTERISTICS
-40B
PARAMETER
UNITS
NOTES
SYMBOL
MIN
MAX
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
ns
CK high-level width
tCH
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
tCK
26
5
7.5
ns
41, 46
6
13
ns
41, 46
7.5
13
Clock cycle time
CL = 3
CL = 2.5
CL = 2
tCK
tCK
(3)
(2.5)
tCK
(2)
0.45
DQ and DM input hold time relative to DQS
tDH
0.40
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
0.40
ns
23, 27
tDIPW
1.75
ns
27
tDQSCK
-0.60
+0.60
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
Write command to first DQS latching transition
tDQSS
DQS falling edge to CK rising - setup time
t
DQS falling edge from CK rising - hold time
t
DSS
DSH
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
Data-out low-impedance window from CK/CK#
tLZ
Address and control input hold time (fast slew rate)
tIH
Address and control input setup time (fast slew rate)
tIS
Address and control input hold time (slow slew rate)
tIH
Address and control input setup time (slow slew rate)
tIS
0.72
0.40
ns
1.28
tCK
0.20
0.20
t
CK
t
CK
ns
30
ns
16, 38
-0.70
ns
16, 38
0.6
ns
12
0.6
ns
12
S
0.6
ns
12
S
0.6
ns
12
F
F
tCH,tCL
+0.70
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP -tQHS
ns
Data hold skew factor
tQHS
ACTIVE to READ with Auto Precharge command
tRAP
15
ACTIVE to PRECHARGE command
tRAS
40
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
15
22, 23
0.50
22, 23
ns
ns
70,000
ns
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (Continued)
Notes: 1–5, 12-15, 29; notes appear on pages 17–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
AC CHARACTERISTICS
-40B
PARAMETER
SYMBOL
MIN
UNITS
NOTES
MAX
tRC
55
ns
AUTO REFRESH command period
tRFC
70
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
tRP
15
ns
0.9
1.1
tCK
39
0.6
tCK
39
ACTIVE to ACTIVE/AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
tRPRE
DQS read postamble
tRPST
0.4
ACTIVE bank a to ACTIVE bank b command
tRRD
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
10
ns
tWPRE
0.25
tCK
tWPRES
0
ns
18, 19
tWPST
0.4
tCK
17
tWR
15
ns
2
tCK
tWTR
Internal WRITE to READ command delay
na
Data valid output window
44
tQH
0.6
- tDQSQ
ns
22
REFRESH to REFRESH command interval
tREFC
70.3
µs
21
Average periodic refresh interval
tREFI
7.8
µs
21
Terminating voltage delay to VDD
tVTD
0
Exit SELF REFRESH to non-READ command
tXSNR
70
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
16
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
12.
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
13.
14.
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL (ACV)
and VIH (AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time at CL = 3 for -40B with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. VDD = +2.5V ±0.2V,
VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =
25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) =
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15.
16.
17.
18.
19.
20.
21.
17
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew
rate is < 0.5V/ns, timing must be derated: tIS has
an additional 50ps per each 100 mV/ns reduction
in slew rate from 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -40B, slew rates must be ≥
0.5 V/ns.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF
stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.
The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
VTT.
t
HZ and tLZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. If DQS transitions to HIGH above VIH (DC) MIN, then it must
not transition to LOW below VIH (DC) MIN prior
to tDQSH (MIN).
This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
The refresh period is 64ms. This equates to an
average refresh rate of 7.8125µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or postMicron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics, on page 19.
b. The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 7, Pull-Down Characteristics,
on page 19.
c. The full variation in driver pull-up current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics, on page 19.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 8, Pull-Up Characteristics, on page 19.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
34. Reduced Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Reduced Output Pull-Down Characteristics,
on page 19.
b. The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Reduced Output Pull-Down
Characteristics, on page 19.
c. The full variation in driver pull-up current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Reduced Output Pull-Up Characteristics, on
page 19.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 10, Reduced Output Pull-Up Characteristics, on page 19.
ing by the DRAM controller greater than eight
refresh cycles is not allowed.
The valid data window is derived by achieving
other specifications: tHP (tCK/2), tDQSQ, and tQH
(tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock has a maximum duty cycle variation of
45/55, beyond which functionality is uncertain.
Each byte lane has a corresponding DQS.
This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is
LOW (i.e., during standby).
To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL (AC)
or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL (DC)
or VIH (DC).
JEDEC specifies CK and CK# input slew rate must
be ≥ 1 V/ns (2 V/ns differentially).
DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to tDS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4 V/ns, functionality is uncertain. For -40B, slew rates must be ≥ 0.5 V/ns.
VDD must not vary more than 4 percent if CKE is
not active while any device bank is active.
The clock is allowed up to ±150ps of jitter. Each
timing parameter may vary by the same amount.
t
HP min is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during device bank active.
READs and WRITEs with auto precharge may be
issued after tRAS(MIN) has been satisfied prior to
the internal precharge command is issued.
Any positive glitch in the nominal voltage must be
less than 1/3 of the clock and not more than
+300mV or 2.9V maximum, whichever is less. Any
negative glitch must be less than 1/3 of the clock
cycle and not exceed either -200mV or 2.4V minimum, whichever is more positive. The average
cannot be below the +2.6V minimum.
Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
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18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Figure 7: Pull-Down Characteristics
Figure 8: Pull-Up Characteristics
160
0
-20
um
140
Maxim
Maximum
-40
120
IOUT (mA)
IOUT (mA)
80
Nominal low
60
-80
-100
Nom
-120
inal
-140
Minimum
40
Nominal high
-60
high
Nominal
100
-160
20
-180
-200
0
0.0
0.5
1.0
1.5
2.0
0.0
2.5
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
VOUT (V)
Figure 9: Reduced Output Pull-Down
Characteristics
Figure 10: Reduced Output Pull-Up
Characteristics
0
80
-10
um
70
im
Max
60
40
IOUT (mA)
Nominal high
50
IOUT (mA)
low
Min
imu
m
Nominal low
-20
Minimum
-30
Nominal low
-40
-50
30
Minimum
20
-60
M
No
ax
im
-70
mi
um
10
na
lh
igh
-80
0.0
0
0.0
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
2.5
VOUT (V)
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
35. The voltage levels used are derived from a minimum VDD level and the referenced test load. In
practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.
36. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
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37.
38.
39.
40.
19
VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
VDD and VDDQ must track each other.
tHZ (MAX) will prevail over tDQSCK (MAX) +
tRPST (MAX) condition. tLZ (MIN) will prevail
over tDQSCK (MIN) + tRPRE (MAX) condition.
tRPST end point and tRPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
During initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/VDDQ are 0V, provided a minimum of
42Ω of series resistance is used between the VTT
supply and the input pin.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
41. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
42. Random addressing changing and 50 percent of
data changing at every transfer.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
tREF later.
45. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
46.
47.
48.
49.
20
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
When an input signal is HIGH or LOW, it is
defined as a steady state logic high or logic low.
This is the DC voltage supplied at the DRAM and
is inclusive of all noise up to 20MHz. Any noise
above 20MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±100mV.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Initialization
Figure 11: Initialization Flow Diagram
To ensure device operation the DRAM must be initialized as described below:
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic low.
4. Provide stable CLOCK signals.
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or
DESELECT command. At this point the CKE input
changes from a LVCMOS input to a SSTL2 input
only and will remain a SSTL_2 input unless a
power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time, during this time NOPs or
DESELECT commands must be given.
9. Using the LMR command program the Extended
Mode Register (E0 = 0 to enable the DLL and E1 =
0 for normal drive or E1 = 1 for reduced drive, E2
through En must be set to 0; where n = most significant bit).
10. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
11. Using the LMR command program the Mode Register to set operating parameters and to reset the
DLL. Note at least 200 clock cycles are required
between a DLL reset and any READ command.
12. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time, only NOPs or DESELECT
commands are allowed.
15. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
16. Wait at least tRFC time, only NOPs or DESELECT
commands are allowed.
17. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
18. Wait at least tRFC time, only NOPs or DESELECT
commands are allowed.
19. Although not required by the Micron device,
JEDEC requires a LMR command to clear the DLL
bit (set M8 = 0). If a LMR command is issued the
same operating parameters should be utilized as
in step 11.
20. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between
step 11 (DLL Reset) and any READ command.
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
Step
21
1
VDD and VDDQ Ramp
2
Apply VREF and VTT
3
CKE must be LVCMOS Low
4
Apply stable CLOCKs
5
Wait at least 200us
6
Bring CKE High with a NOP command
7
PRECHARGE ALL
8
Assert NOP or DESELECT for tRP time
9
Configure Extended Mode Register
10
Assert NOP or DESELECT for tMRD time
11
Configure Load Mode Register and reset DLL
12
Assert NOP or DESELECT for tMRD time
13
PRECHARGE ALL
14
Assert NOP or DESELECT for tRP time
15
Issue AUTO REFRESH command
16
Assert NOP or DESELECT commands for tRFC
17
Issue AUTO REFRESH command
18
Assert NOP or DESELECT for tRFC time
19
Optional LMR command to clear DLL bit
20
Assert NOP or DESELECT for tMRD time
21
DRAM is ready for any valid command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
SPD Clock and Data Conventions
SPD Acknowledge
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 12, Data Validity, and Figure 13, Definition of Start and Stop).
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 14, Acknowledge Response from Receiver).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Figure 12: Data Validity
Figure 13: Definition of Start and Stop
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
START
BIT
STOP
BIT
Figure 14: Acknowledge Response from Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
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DDA4C16_32x64HG.fm - Rev. D 9/04 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 16: EEPROM Device Select Code
Most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
SELECT CODE
Memory Area Select Code (two arrays)
Protection Register Select Code
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Table 17: EEPROM Operating Modes
MODE
RW BIT
WC
BYTES
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
≥1
1
≤ 16
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
INITIAL SEQUENCE
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
Figure 15: SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
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23
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©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
SYMBOL
MIN
MAX
UNITS
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
2.3
VDDSPD × 0.7
-1
–
–
–
–
–
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
10
10
30
2
V
V
V
V
µA
µA
µA
mA
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
MIN
MAX
UNITS
NOTES
tAA
0.2
1.3
200
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
300
0
0.6
0.6
tI
tLOW
50
1.3
tR
0.3
400
fSCL
tSU:DAT
tSU:STA
t
SU:STO
tWRC
100
0.6
0.6
10
2
2
3
4
NOTE:
1.
2.
3.
4.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge
of SDA.
This parameter is sampled.
For a reSTART condition, or following a WRITE cycle.
The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the
EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 20: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
DESCRIPTION
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used by Micron
Total Number of Bytes in SPD Device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
10
SDRAM Access from Clock, tAC (CAS Latency = 3)
Module Configuration Type
Refresh Rate/type
SDRAM Device Width (Primary DDR SDRAM)
Error-checking DDR SDRAM Data Width
Minimum Clock Delay, Back-to-Back Random
Column Access
Burst Lengths Supported
Number of Banks on DDR SDRAM Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ENTRY (VERSION)
MT4VDDT1664H
MT4VDDT3264H
128
256
DDR SDRAM
13
9, 10
1
64
0
SSTL 2.5V
5ns (-40B)
80
08
07
0D
09
01
40
00
04
50
80
08
07
0D
0A
01
40
00
04
50
0.7ns (-40B)
70
70
None
7.8µs/SELF
16
None
1 clock
00
82
10
00
01
00
82
10
00
01
0E
04
1C
01
02
20
C1
0E
04
1C
01
02
20
C1
60
60
70
70
75
75
75
75
3C
3C
10ns (-40B)
28
28
15ns (-40B)
3C
3C
SDRAM Cycle Time, tCK (CAS Latency = 3)
2, 4, 8
4
3, 2.5 and 2
0
1
Unbuffered/Diff. Clock
Fast/Concurrent Auto
Precharge
6ns (Set for PC2700
SDRAM Cycle Time, tCK (CAS Latency = 2.5)
Compatibility)
SDRAM Access From Clock, tAC (CAS Latency = 2.5) 0.7ns (Set for PC2700
Compatibility)
7.5ns (Set for PC2100/
SDRAM Cycle Time, tCK (CAS Latency = 2)
PC1600 Compatibility)
0.75ns (Set for PC2100/
SDRAM Access From CK, tAC (CAS Latency = 2)
PC1600 Compatibility)
15ns (-40B)
Minimum Row Precharge Time, tRP
Minimum Row Active to Row Active,
tRRD
t
Minimum RAS# to CAS# Delay, RCD
40ns (-40B)
28
28
Address and Command Setup Time, tIS
128MB, 256MB
0.6ns (-40B)
20
60
40
60
33
Address and Command Hold Time, tIH
0.6ns (-40B)
60
60
34
tDS
0.40ns (-40B)
40
40
tDH
0.40ns (-40B)
40
40
00
00
31
32
Minimum RAS# Pulse Width,
Module Rank Density
tRAS
Data/Data Mask Input Setup Time,
35
Data/Data Mask Input Hold Time,
36-40 Reserved
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Table 20: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
41
DESCRIPTION
ENTRY (VERSION)
MT4VDDT1664H
MT4VDDT3264H
55ns (-40B)
37
37
42
Min Active Auto Refresh Time, tRC
Minimum Auto Refresh to Active/Auto Refresh
Command Period, tRFC
70ns (-40B)
46
46
43
SDRAM Device Max Cycle Time, tCKMAX
12ns (-40B)
30
30
0.40ns (-40B)
28
28
0.5ns (-40B)
50
50
00
01
00
11
68
2C
00
01 - 0C
Variable Data
01 - 09
00
Variable Data
Variable Data
Variable Data
Variable Data
00
01
00
11
89
2C
00
01 - 0C
Variable Data
01 - 09
00
Variable Data
Variable Data
Variable Data
Variable Data
44
45
46-61
47
48–61
62
63
64
65-71
72
73-90
91
92
93
94
95-98
99127
t
SDRAM Device Max DQS-DQ Skew Time, DQSQ
SDRAM Device Max Read Data Hold Skew Factor,
t
QHS
Reserved
DIMM Height
Reserved
SPD Revision
Checksum for Bytes 0-62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC IDCode
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Identification Code (Continued)
Year of Manufacture in BCD
Week of Manufacturein BCD
Module Serial Number
Manufacturer-Specific Data (RSVD)
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
Release 1.1
-40B
MICRON
(Continued)
01–12
1-9
0
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x64, SR) PC3200
200-PIN DDR SDRAM SODIMM
Figure 16: 200-Pin SODIMM Dimensions
FRONT VIEW
0.075 (1.90)
MAX
2.667 (67.75)
2.656 (67.45)
0.079 (2.00) R
(2X)
U1
U2
U4
0.071 (1.80)
(2X)
U5
1.256 (31.90)
1.244 (31.60)
U3
0.787 (20.00)
TYP
0.236 (6.00)
0.096 (2.44)
0.079 (2.00)
0.043 (1.10)
0.035 (0.90)
0.039 (.99)
TYP
0.018 (0.46)
TYP
0.024 (0.61)
TYP
PIN 199
PIN 1
2.504 (63.60)
TYP
BACK VIEW
No Components This Side of Module
PIN 200
PIN 2
NOTE:
MAX
All dimensions are in inches (millimeters); MIN or typical where noted.
Data Sheet Designation
Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete
power supply and temrperature range for production
devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
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E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
pdf: 09005aef80b56d1b, source: 09005aef8086ea0b
DDA4C16_32x64HG.fm - Rev. D 9/04 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2004 Micron Technology, Inc