56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Features Parallel NOR and PSRAM 56-Ball MCP Combination Memory MT38L3031AA03JVZZI.X7A Features Figure 1: MCP Block Diagram • Micron® Parallel NOR Flash and PSRAM components • RoHS-compliant, “green” package • Multiplexed address/data bus NOR Flash and PSRAM interfaces • Space-saving multichip package (MCP) • Low-voltage operation (1.70–1.95V) • Industrial temperature range: –40°C to +85°C NOR Flash Device NOR Flash Power NOR Flash-Specific Features • Multiple-bank, Parallel NOR Flash memory • Synchronous/asynchronous read – Synchronous burst read mode: 66 MHz – Random access times: 70ns – Asynchronous page mode read: 20ns • Programming times – 2.5μs typical word program time using buffer enhanced factory program command – Fast program with 9V V PP • Memory blocks – Multiple bank memory array: 8Mb banks – Top or bottom location parameter blocks1 • Synchronous burst read suspend • Dual operations – Program erase in 1 bank, read in others – No delay between READ and WRITE operations • Block locking – All blocks locked at power-up – Any combination of blocks can be locked – WP# for block lock-down • Security – 2112-bit user programmable OTP cells – 64-bit unique device number • Common Flash interface • 100,000 PROGRAM/ERASE cycles per block • Electronic signature – Manufacturer code: 20h – 128Mb Flash code: 882Eh (top boot) PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN PSRAM Power PSRAM Device PSRAM-Specific Features • Synchronous/asynchronous read – Synchronous burst read mode: 83 MHz – Random access: 70ns – Asynchronous page mode: 20ns • Partial-array self refresh (PAR) • Deep power-down (DPD) mode • Automatic temperature-compensated self-refresh (TCR) Notes: 1 1. Contact factory for availability of version. 2. For physical part markings, see Part Numbering Information (page 2). Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Features Part Numbering Information Micron NOR Flash and PSRAM devices are available in different configurations and densities. The MCP/PoP part numbering guide is available at www.micron.com/numbering. Figure 2: Part Number Chart MT 38X XXX X X X X X XXX X X . XXX -XX Micron Technology Production Status Product Family Die Revision Code Density Operating Temperature Range Voltage Range (Core I/O) Special Option Die Count Package Code NOR Configuration xPSRAM Description xNAND Description Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/ Label,” at www.micron.com/csn. PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM MCP General Description MCP General Description Micron MCP products combine NOR Flash and PSRAM devices in a single MCP. Operational characteristics for the NOR Flash and PSRAM devices are found in the standard data sheets for each of the discrete devices. Recommended operating conditions do not allow more than one device to be active at a time. A common example of this scenario is running simultaneous READ operations on the NOR device and on the PSRAM device. Doing this results in data bus contention. To prevent this, one device must be High-Z when reading the selected device. The NOR Flash device is M58LR128KC70. For device specifications and complete Micron NOR Flash features documentation, contact your local Micron sales office. The PSRAM ADM device is W956D6H. For device specifications and complete PSRAM features documentation, contact your local Micron sales office. PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 56-Ball TFBGA (NOR x16; PSRAM x16) Ball Assignments (Top View Through Package) 1 2 NC NC WAIT A21 VSS VDDQ A16 A20 ADV# A B C D VSS E 3 4 CLK 5 6 7 LB# UB# VDD WE# VPP NC RP# WP# 8 9 10 NC NC A19 A17 A22 A18 CE# VSSQ ADQ7 ADQ6 ADQ13 ADQ12 ADQ3 ADQ2 ADQ9 ADQ8 OE# ADQ15 ADQ14 VSSQ ADQ5 ADQ4 ADQ11 ADQ10 VDDQ ADQ1 ADQ0 F NC NC CRE CE# NC NC PSRAM Flash Table 1: x16 NOR Ball Descriptions Symbol Alternate Symbol Type CE# E# Input Chip enable: Activates the memory control logics, input buffers, decoders, and sense amplifiers. When CE# is LOW and RESET is HIGH, the device is in active mode. When HIGH, the NOR device is deselected, the outputs are High-Z, and the power consumption is reduced to the standby level. WP# – Input Write protect: Provides additional hardware protection for each block. When WP# is LOW, lock-down is enabled and the protection status of the locked-down blocks cannot be changed. When WP# is HIGH, lock-down is disabled and the locked-down blocks can be locked or unlocked. PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN Description 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Ball Assignments and Descriptions Table 1: x16 NOR Ball Descriptions (Continued) Symbol Alternate Symbol Type Description RP# – Input Reset: Provides a hardware reset of the memory. When RP# is LOW, the device is in reset mode; the outputs are High-Z and the current consumption is reduced to IDD2. After RP#, all blocks are in the locked state and the configuration register is reset. When RP# is HIGH, the device is in normal operation. Upon exiting reset mode, the device enters asynchronous read mode, but a negative transition of CE# or ADV# is required to ensure valid data outputs. VPP – Supply Both a NOR control input and power supply pin. The two functions are selected by the voltage range applied to the pin. When VPP = 0V - VDDQ, it functions as a control input. In this case, a voltage lower than VPPLKF provides absolute protection against program or erase, while VPP > VPP1F enables these functions. VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect, and PROGRAM or ERASE operations continue. When VPP is in the range of VPPH, it acts as a power supply pin. In this condition, VPP must be stable until the program/erase algorithm is completed. Table 2: x16 PSRAM Ball Descriptions Symbol Alternate Symbol Type CE# E# Input Chip enable: When LOW, CE# activates the memory state machine, address buffers and decoders, enabling READ and WRITE operations. When HIGH, all other pins are ignored and the device is automatically put in low-power standby mode. CRE CR Input Configuration register enable: When HIGH, bus READ or WRITE operations access either the value of the refresh configuration register or the bus configuration register, according to the value of A19. UB# – Input Upper byte enable: Gates the data on the upper byte data I/Os (DQ[15:8]) to or from the upper part of the selected address during a WRITE or READ operation. LB# – Input Lower byte enable: Gates the data on the lower byte data I/Os (DQ[7:0]) to or from the lower part of the selected address during a WRITE or READ operation. PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN Description 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Ball Assignments and Descriptions Table 3: NOR/PSRAM Shared Ball Descriptions Symbol Type Description A[MAX:16] Input Shared address: Select the cells in the memory array to access during bus READ operations. During bus WRITE operations they control the commands sent to the command interface of NOR memory program/erase controller, and they select the cells to access in the PSRAM. ADQ[15:0] Input/ Output Shared data inputs/outputs: The bidirectional I/Os output the data stored at the selected address during a NOR bus READ operation or inputs a command or the data to be programmed during a bus WRITE operation. For both NOR and PSRAM, the ADQ[15:0], in conjunction with A[23:16] address lines, select the cells in the memory array to access during bus READ operations. The upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a PSRAM WRITE or READ operation, when UB# is driven LOW. Likewise, the lower byte data I/Os carry the data to or from the lower part of the selected address during a WRITE or READ operation, when LB# is driven LOW. CLK Input Shared clock. WE# Input Common to Flash memory and PSRAM components. Refer to the respective memory component data sheets for details. OE# Input Shared output enable. ADV# Input Shared latch enable input. WAIT Output Shared WAIT data in burst mode. VSS Supply Shared ground. VDD Supply Shared power supply. VDDQ Supply Shared I/O power supply. NC – Note: PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN Not connected. 1. Each device in a system should have VDD, VDDQ , and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high-frequency, inherently low inductance capacitors should be as close as possible to the package). The PCB track widths should be sufficient to carry the required VPP program and erase currents. 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 4: Absolute Maximum Ratings Parameters/Conditions Symbol Min Max Unit TA –40 85 °C TBIAS –40 85 °C TSTG –55 125 °C Input voltage VIN –0.2 2.45 V Core supply voltage VDD –0.2 2.45 V I/O supply voltage VDDQ –0.2 2.45 V VPP –0.2 10 V Ambient operating temperature Storage temperature range Flash VPP program voltage Output short circuit current Time for VPP at VPPH IO 100 mA tVPPH 100 hours Table 5: Recommended Operating Conditions Symbol Min Max Unit Core supply voltage Parameters VDD 1.70 1.95 V I/O supply voltage VDDQ 1.70 1.95 V Flash VPP supply voltage (application environment) VPP –0.4 VDDQ + 0.4 V Flash VPP supply voltage (factory environment) VPP 8.5 9.5 V – –40 +85 °C Operating temperature range PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Electrical Specifications Table 6: Operating Modes – Standard Asynchronous Operation X = "Don't Care" Operation RP# CE# OE# WE# ADV# CLK1 UB# LB# CRE CE# ADQ[15:0] WAIT2 READ VIH VIL VIL VIH VIH VIL X X X VIH Address in/ data out Low-Z WRITE VIH VIL VIH VIL VIH VIL X X X VIH Address in/ data in Low-Z ADDRESS LATCH VIH VIL VIH X VIL VIL X X X VIH Data out or High-Z3 Low-Z OUTPUT DISABLE VIH VIL VIH VIH VIH VIL X X X VIH High-Z Low-Z STANDBY VIH VIH X X X VIL High-Z High-Z RESET VIL X X X X VIL High-Z High-Z READ X VIH VIL VIH \_/ VIL VIL VIL VIL VIL Address in/ data out Low-Z WRITE X VIH VIH VIL \_/ VIL VIL VIL VIL VIL Address in/ data in High-Z READ CONFIGURATION REGISTER X VIH VIL VIH \_/ VIL VIL VIL VIH VIL Address in/ BCR, RCR, or DIDR content Low-Z SET CONFIGURATION REGISTER X VIH VIH VIL \_/ VIL X X VIH VIL BCR/RCR data Low-Z OUTPUT DISABLE (No operation) X VIH VIH X X X X X VIL VIL High-Z Low-Z DEEP POWER DOWN5 Any Flash mode allowed X X X VIL X X X VIH High-Z High-Z X X X VIL X X X VIH High-Z High-Z FLASH Any PSRAM mode allowed PSRAM 4 STANDBY Notes: PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 1. CLK must remain LOW when the PSRAM device is operating in asynchronous mode. 2. For the Flash device, WAIT polarity is configured using the SET CONFIGURATION REGISTER command. 3. See the NOR data sheet for more information. 4. BCR and RCR only. 5. The device enters deep power-down mode by driving the CE# from LOW to HIGH, with bit 4 of the RCR set to 0. The device remains in deep power-down mode until CE# goes LOW again and is held LOW for tDPDX. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Device Diagrams Device Diagrams Figure 4: Functional Block Diagram (NOR with PSRAM) VPP CE# NOR Flash RP# WP# WE# A[MAX:16] OE# ADV# VDD VDDQ CLK VSS ADQ[15:0] WAIT VSSQ CE# PSRAM CRE UB# LB# Note: PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 1. The devices share the same power supplies and the same ground. They are distinguished by two CE# inputs. Recommended operating conditions do not allow more than one device to be active at a time, which would result in a data bus contention. One device should be placed in High-Z when the selected device is operating. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Package Dimensions Package Dimensions Figure 5: 56-Ball TFBGA (Package Code: JVZ) Seating plane A 0.08 A 56X Ø0.3±0.05 6 ±0.1 Ball A1 ID Ball A1 ID 2.5 CTR 4.5 CTR 0.5 TYP 0.5 TYP 4.5 CTR 1.2 MAX 0.15 MIN 6.5 CTR 8 ±0.1 Note: PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 1. All dimensions are in millimeters. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. 56-Ball MCP: 128Mb Parallel NOR and 64Mb PSRAM Revision History Revision History Rev. C – 11/14 • Production Rev. B – 09/14 • Removed references to VSSQ since this node is connected to VSS inside the package. Rev. A – 08/14 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef85ddc5b5 56ball_nor_psram_jx7a.pdf - Rev. C 11/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.