TN-25-09: Layout Guidelines – Serial NOR Flash Introduction Technical Note PCB Layout Design Guidelines Introduction This technical note provides PCB designers basic guidelines for optimizing signal layout and power supply lines in Micron's Serial NOR Flash device to prevent signal integrity problems. The standard data sheet provides a complete description of functionality, operating modes, and specifications. IBIS models for simulating signal integrity issues are available at micron.com. Figure 1: Serial NOR Flash Recommended Schematic VCC C2 VCC U1 SPI NOR controller C1 U2 N25Qxxx and MT25Qxxx R1 R3 R4 R5 VCC S# S# C C DQ0 DQ0 DQ1 DQ1 W#/VPP/DQ2 W#/VPP/DQ2 HOLD#/DQ3 HOLD#/DQ3 RESET# RESET# VSS R2 Notes: 1. VPP is available only with N25Qxxx products. 2. MT25Q devices already include a RESET# pull‐up resistor. 3. When HOLD# is disabled, a pull‐up resistor for it is unnecessary.The HOLD# functionality can be disabled using bit 4 of the NVCR as described in device datasheet.. 4. When the controller drives input signals at proper VIL/VIH levels, pull-up and pull-down resistors are unnecessary. PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. TN-25-09: Layout Guidelines – Serial NOR Flash Resistor Terminations Resistor Terminations Table 1: Recommended Resistor Terminations Parameter Symbol Min Max Recommended Unit S# pull-up resistor R1 4.7 50 10 KΩ Prevents bus floating – CLK pull-down resistor R2 47 500 100 KΩ Ensures that S# and CLK are not HIGH simultaneously and that tSHCH is met. – W# pull-up resistor R3 4.7 50 10 KΩ Prevents bus floating – HOLD# pull-up resistor R4 4.7 50 10 KΩ Prevents bus floating – RESET# pull-up resistor R5 4.7 50 10 KΩ Prevents bus floating – CLK/ Control/DAT impedance – 45 55 50 Ω Impedance match: Final manufacturing value 1 VCC capacitor value C1, C2 3.3 + 0.01 10 + 0.22 4.7 + 0.1 µF Decoupling capacitor should be connected as closely as possible to VCC and VSS – Note: PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN Description Notes 1. All signals should be routed with controlled impedance. When trace impedance is outside the specified range, simulation with IBIS models is strongly recommended to determine serial resistor terminations for data lines. 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. TN-25-09: Layout Guidelines – Serial NOR Flash PCB Design Recommendations PCB Design Recommendations VCC Power Supply Decoupling For decoupling power supply V CC, two ceramic capacitors are recommended, one 4.7µF 0805 and one 0.1µF 0603. Decoupling Capacitor Routing Lengths Reducing decoupling capacitor routing lengths helps minimize total loop inductance. The measure includes the following: • • • • Reduced V CC and V SS decoupling capacitor pad fan out trace length Fan out trace width equal to or less than the capacitor pad width Power and ground planes Decoupling capacitor placement relative to device Figure 2: Connecting Capacitor Pads Unacceptable 1 Good 3 Acceptable 2 Better 4 Best 5 (Solid via within pad) Figure 3: Routing Decoupling Capacitor Cap IC Power Via Total loop inductance Ground PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. TN-25-09: Layout Guidelines – Serial NOR Flash PCB Design Recommendations Decoupling Capacitor Placement Decoupling capacitors should be as close as possible to V CC and V SS pads with priority as follows: Closest is 0.1μF followed by 4.7μF. CLK Signal Routing The following clock trace guidelines help minimize impedance variation: • To minimize impedance variation, maintain a straight clock trace, as much as possible, by using arc-shaped bends instead of right-angle bends. Figure 4: Trace Shape Not recommended Recommended Recommended • Maintain a short clock trace, as much as possible, and match lengths between clock and data signals. • Use one signal layer to ensure constant transmission line impedance for the clock signal. • Place a ground plane next to the outer layer to minimize noise from other signals. • If an inner layer is used to route the clock trace, sandwich the inner layer between reference planes. • To minimize reflection, terminate clock signals or set up an appropriate driver strength, and keep the clock trace with controlled impedance (typically 50 ohm trace impedance). • To ensure signal quality, use point-to-point clock trace as much as possible. • To reduce crosstalk from other, nearby signals, maintain space between the clock signal line and other signal lines as wide as possible. Moreover, take care to have dielectric height more than three times the distance among two adjacent lines, as showed in the below drawing: PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. TN-25-09: Layout Guidelines – Serial NOR Flash PCB Design Recommendations Figure 5: Trace Width Example G W active signal W active signal S S P E, F GN GND t H Source 1. Dielectric height = H, trace to trace separation = G. For optional crosstalk performance G/H ≥ 3. Note: • The clock signal should not be over the split plane. Figure 6: Avoiding Breaks and Voids Return current Return current Slot in image plane Slot in image plane Unacceptable Acceptable Data Signal Routing • • • • PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN Data signals should not be over the split plane. Data signals should not be routed over via-anti pads. Maintain a continuous reference plane for each data signal over its entire path. If the signal reference plane changes from ground plane to power plane, add capacitors near the via transition site to help support a good return path. 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. TN-25-09: Layout Guidelines – Serial NOR Flash PCB Design Recommendations • If the signal reference plane changes from one ground plane to another, ground vias should surround all signals (Two ground vias per clock via; one ground via per highspeed signal via). • Keep stubs short to avoid reflections. Keep stub propagation delay to <20% of the signal rise time. Figure 7: Typical Stub Case Branch PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. TN-25-09: Layout Guidelines – Serial NOR Flash Revision History Revision History Rev. A – 7/15 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef863f2a7e tn2509_layout_guidelines_spi_nor - Rev. A 07/15 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.